Timer based on FPGA
By combining Block RAM and DDR storage mechanisms in FPGA, a high-precision timer design was achieved, solving the resource consumption and accuracy problems of traditional FPGA timers and improving the performance and resource utilization efficiency of the timer.
Patent Information
- Application Number
- CN202411436401.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-15
- Publication Date
- 2026-04-17
AI Technical Summary
Traditional FPGA-based timers have issues with resource consumption and accuracy, especially when the number of tasks is large, the timing accuracy decreases, and frequent access to DDR leads to excessive bus bandwidth consumption.
An on-chip and off-chip shared storage mechanism is adopted. The timeout task insertion, detection and timing module is implemented through FPGA. Block RAM is used to store time slices and DDR to store task information. The timing is performed in an upward counting mode to reduce access to DDR and save bus bandwidth and storage resources.
It achieves high-precision timing regardless of the number of tasks, saves FPGA storage and logic resources, reduces reliance on DDR, and improves the overall performance of the timer.
Smart Images
Figure CN121879918A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the fields of FPGA and networking and communication, and in particular to an FPGA-based timer. Background Technology
[0002] Timers originated in early computer systems to manage and control program execution time. With the development of computer technology, timers have evolved into more complex and powerful components, playing a crucial role in various applications. In traditional systems, timers are often used to achieve precise time measurement and event triggering, such as task scheduling and clock management in real-time operating systems (RTOS). In the field of communications, timers are widely used in data transmission and network protocols to ensure timely data transmission and reception.
[0003] However, software-based implementations can lead to issues with the performance, accuracy, or flexibility of the timer and overall functionality. To address these problems, a transition to hardware timers needs to be considered. FPGA (Field-Programmable Gate Array)-based timer technology plays a crucial role in today's rapidly evolving digital design landscape, but the resource consumption and accuracy issues of traditional FPGA-based timers still require further resolution and optimization.
[0004] Among the relevant patents, Chinese patent application CN111831605A, "A Precise Data Packet Delay Method and System Based on FPGA," timestamps data packets, allocates data packets and timestamps according to link status, and stores them on DDR. A judgment module continuously accesses the timestamps to continuously determine whether the data packets meet the delay standard. This method frequently reads off-chip memory, requires significant channel bus bandwidth, and is prone to conflicts with other modules using DDR. Chinese patent application CN114280977A, "A Large-Scale Timing Method and Apparatus Based on FPGA," utilizes multiple RAMs, determines the effective address range of the RAMs, and stores task information, timing times, and judgment signals on different RAMs. It counts the number of times an address is read by polling RAM addresses to determine if the timeout period is met. This method consumes more on-chip Block RAM, and its timing accuracy has a linear negative relationship with the number of tasks; the more tasks, the lower the timing accuracy. It may not be usable when the number of tasks is large and high precision requirements are high. Summary of the Invention
[0005] The purpose of this invention is to overcome the shortcomings of the prior art and to propose an FPGA-based timer.
[0006] To achieve the above objectives, this invention proposes an FPGA-based timer, comprising: a timeout task insertion module, a timeout task detection module, and a timing module, wherein...
[0007] The timeout task insertion module is used to receive timeout task information and timeout time, calculate the target time slice for task insertion based on the timeout time, update the number of tasks in the corresponding time slice in the time slice storage space on Block RAM, calculate the storage address of task information, and store the timeout task information in the corresponding location in the task information storage space on DDR.
[0008] The timeout task detection module is used to detect the number of tasks stored in the time slice pointed to by the index according to the time slice index maintained by the timing module, retrieve the corresponding task information, and clear the number of tasks corresponding to the current time slice to zero.
[0009] The timing module is used to time in an upward counting mode and maintain a time slice index.
[0010] Preferably, the time slice storage space is divided into n time slices, each time slice represents a certain time slot T, and the upper limit of the number of tasks that meet the timeout triggering conditions stored on each time slice is a set value m.
[0011] Preferably, the task information storage space is divided into n subspaces, each subspace corresponding one-to-one with a time slice of the time slice storage space; each subspace is divided into m slots, and each slot stores one task information in the order of task insertion.
[0012] Preferably, the maximum task timing trigger time provided by the timer is T*(n-1).
[0013] Preferably, the timeout task insertion module calculates the target time slice for task insertion based on the timeout period, including:
[0014] Based on the timeout t of the current input task and the time slot T, calculate the number of delayed time slices, and use the current time slice index n. entry Adding this to the number of delayed time slices yields the target time slice n for task insertion. write Satisfy the following equation:
[0015] n write =n entry +t*λ
[0016] Wherein, λ is the normalization coefficient of the time slice, which is calculated based on the time slot T.
[0017] Preferably, the timeout task insertion module calculates the storage address of the task information and stores the task information in the corresponding location of the task information storage space on DDR, including:
[0018] The corresponding location ddr_awaddr in the task information storage space is obtained according to the following formula:
[0019] ddr_awaddr = addr + n write *subaddr+(num-1)*timeout_event_length where addr is the starting address of the task information storage space, num is the number of tasks stored in the corresponding time slice of Block RAM, timeout_event_length is the length of the task information, and subaddr is the address occupied by a subspace.
[0020] Preferably, the timeout task detection module processing procedure includes:
[0021] Based on the time slice index maintained by the timing module, when the time slice index points to a certain time slice and reaches the critical point to jump to the next time slice, the number of tasks stored in the current time slice is read.
[0022] If the number of tasks read is not 0, retrieve the task information from the corresponding location in the task information storage space and clear the number of tasks stored in the current time slice to zero.
[0023] If the number of tasks read is 0, then there are no tasks that need to be triggered on a schedule in the current time period.
[0024] Preferably, the processing procedure of the timing module includes:
[0025] Based on the system clock cycle, the time slice index is incremented by one every certain number of system clock cycles, pointing to the next time slice; when the time slice index reaches the last time slice, it returns to the initial time slice and continues working in a loop.
[0026] Compared with the prior art, the advantages of the present invention are:
[0027] 1. This application adopts a mechanism of on-chip and off-chip joint storage. The timeout logic judgment is completed through FPGA, which achieves a balance between occupying on-chip and off-chip resource space. There is no need to frequently poll the DDR to judge the timeout. It is only necessary to retrieve the task information from the DDR after judging the timeout on the chip. Moreover, only the task information is stored on the DDR, without the need for timestamps, thus saving bus bandwidth and DDR resources.
[0028] 2. This application stores only the number of timeout tasks in the on-chip Block RAM, without storing other information, thus saving on-chip storage resources. The timing accuracy is not affected by the number of tasks, and the same timing accuracy can be achieved regardless of the number of tasks.
[0029] 3. Multiple timeout tasks share a single timer, saving FPGA storage and logic operation resources. Attached Figure Description
[0030] Figure 1This is the overall framework diagram of the timer module;
[0031] Figure 2 This is a time-slice memory space diagram of Block RAM;
[0032] Figure 3 This is a diagram of the DDR task information storage space;
[0033] Figure 4 This is a flowchart of the timer process. Detailed Implementation
[0034] This application stores task information on DDR, so there is no need to access DDR when timeout is determined on FPGA, thus saving bus bandwidth and DDR resources.
[0035] This application utilizes both DDR and FPGA memory for storage, which saves FPGA logic resources as well as FPGA storage resources, and the timing accuracy is not limited by the number of tasks, theoretically achieving higher accuracy.
[0036] This invention addresses the need for timeout support in FPGAs, as well as the requirements for accuracy and resource consumption, by proposing an FPGA-based timer.
[0037] The timer module of this invention is implemented based on FPGA and includes a time slice storage space, a task information storage space, a timing module, a timeout task insertion module, and a timeout task detection module. Its features are as follows:
[0038] The time-slice storage space is divided into n time slices and stored in Block RAM. Each time slice represents a certain time interval, and the number of tasks that meet the conditions is stored on the time slice. That is, within the time period pointed to by the index of a certain time slice, the number of tasks that meet the timeout trigger condition is stored on that time slice. The time interval represented by each time slice is T, which can be flexibly adjusted according to actual needs. The maximum task timed trigger time provided by the method of this invention is T*(n-1).
[0039] The task information storage space is divided into n subspaces and stored on DDR. Each subspace corresponds one-to-one with each time slice. Each subspace is divided into m slots, and each slot is responsible for storing one task information. m is also the maximum number of tasks that can be stored in each time slice. The task information in the same storage subspace is arranged and stored in the order of reception.
[0040] The timing module operates as follows: It uses an upward counting mode for timing and maintains a time slice index. As the clock advances, the time slice index points to the next time slice every certain number of clock cycles. When the time slice index reaches the last time slice, it returns to the initial time slice and continues working in a loop. The timeout task insertion and detection module calculates the read and write addresses on the Block RAM and DDR based on the time slice index provided by the timing module.
[0041] The overall implementation steps of the timeout task insertion module are as follows: When a new timeout task is received from the outside, the target time slice into which the task should be inserted is determined: Based on the timeout time of the current input task, the number of delayed time slices is calculated, and the current time slice index is added to the number of delayed time slices to obtain the storage location. The number of tasks stored in the time slice is then updated. The address of the task stored in DDR is determined: The n subspaces in DDR correspond one-to-one with the n time slices in Block RAM. Each subspace is further divided into m slots, and each slot stores the relevant information of a timeout task. After the target time slice into which the task is inserted in Block RAM is calculated, the starting address of the task information storage subspace corresponding to the time slice in DDR can be calculated accordingly. Then, the relevant offset is calculated based on the number of timeout tasks already stored in the current time slice, and the new task is stored in the corresponding slot.
[0042] The overall implementation steps of the timeout task detection module are as follows: According to the logic of the timing module, when the time slice index points to a certain time slice and reaches the critical point of jumping to the next time slice, the number of tasks stored in the current time slice is read; if the number of tasks read is not 0, the task information is retrieved from the corresponding task storage space address in DDR, and the number of tasks stored in the current time slice is cleared to zero; if the number of tasks read is 0, it means that there are no tasks that need to be triggered by timer in the current time period; following the clock, the next time slice is accessed every certain clock cycle, and when the time slice index reaches the last time slice, the cycle returns to the first time slice.
[0043] The technical solution of the present invention will be described in detail below with reference to the accompanying drawings and embodiments.
[0044] Example
[0045] An embodiment of the present invention provides a timer for an FPGA. Figure 1 This is the overall framework design diagram for the module. It includes: a timeout task insertion module, a timeout task detection module, and a timing module.
[0046] The timeout task insertion module is used to receive timeout task information and timeout time, calculate the target time slice for task insertion based on the timeout time, update the number of tasks in the corresponding time slice in the time slice storage space on Block RAM, calculate the storage address of task information, and store the timeout task information in the corresponding location in the task information storage space on DDR.
[0047] The timeout task detection module is used to detect the number of tasks stored in the time slice pointed to by the index based on the time slice index maintained by the timing module, retrieve the corresponding task information, and clear the number of tasks corresponding to the current time slice to zero.
[0048] The timing module is used to time in an upward counting mode and maintain the time slice index.
[0049] Specifically, the time slice storage space stores the number of timed-out tasks in different time periods; the task information storage space stores the information of the corresponding tasks; the timing module uses an upward counting method for timing, and the time slice index jumps step by step according to the clock, jumping to the next time slice every time the set unit time precision is reached; the timed-out task insertion module calculates the target time slice for task insertion based on the timed-out time of the received task, and calculates the address where the task information is stored in DDR; the timed-out task detection module detects based on the time slice index maintained by the timing module. When the time slice index points to a certain time slice and reaches the critical point for jumping to the next time slice, it reads the number of tasks stored in the current time slice. If it is not 0, it retrieves the task information from the corresponding address in the DDR task storage space. If it is 0, there are no tasks that need to be triggered periodically in the current time period.
[0050] Figure 2 This is a diagram of the time-slice storage space structure, allocated on Block RAM. As shown, it is divided into n time slices, each representing a certain time slot, with address allocation identifiers from 0 to n-1. Each time slice stores the number of tasks that meet the conditions, num, i.e., the number of tasks that should reach the timeout trigger condition within the corresponding time period of that time slice. Each time slice represents a certain time interval T, and the maximum task timing trigger time provided by the entire timer module is T*(n-1).
[0051] Figure 3 This is a diagram of the task information storage space structure, allocated on DDR. For example... Figure 3 As shown, the task information storage space is divided into n subspaces, which are sequentially labeled and range from 0 to n-1. These subspaces correspond one-to-one with the n time slices on the Block RAM. Each storage subspace is divided into m slots, labeled from 0 to m-1. Each slot stores one task information in the order in which the task is inserted. The length of the timeout task information can be flexibly adjusted according to specific needs.
[0052] Figure 4 This is a flowchart of the overall timer module of the present invention, as shown below. Figure 4 As shown, the main working process of the timer of the present invention includes:
[0053] Step 1: The timing module operates based on the system clock cycle, using an upward counting mode and maintaining a time slice index. The time slice index increments gradually according to the set unit time precision. After a certain number of clock cycles, the time slice index is incremented by one, pointing to the next time slice.
[0054] Step 2: Receive timeout task information and the time when the task needs to be triggered from the external module;
[0055] Step 3: The time slice address range in Block RAM is 0 to n-1. Calculate the target time slice into which the task should be inserted according to equation (1), where n... write The time slice into which the task will be inserted, n entry This refers to the time slice pointed to by the current time slice index, where t represents the timeout of the current task, and λ is the normalization coefficient of the time slice, calculated based on the time slot T. After calculation, the number of tasks in the corresponding location in the Block RAM is updated.
[0056] n write =n etry +t*λ (1)
[0057] Step 4: According to Step 3 and Equation (2), calculate and store the current task information in the task information storage space of the off-chip DDR. In Equation (2), ddr_awaddr represents the address to be written to DDR, addr represents the starting address allocated to the task information storage space, num represents the number of tasks stored in the corresponding time slice of Block RAM, timeout_event_length represents the length of the task information, and subaddr represents the address occupied by a subspace.
[0058] ddr_awaddr = addr +
[0059] n write *subaddr+(num-1)*timeout_event_length (2)
[0060] Step 5: According to the timing module logic, when the time slice index points to a time slice in the time slice storage space and reaches the critical point of jumping to the next time slice, read the number of tasks stored in the time slice pointed to by the index.
[0061] Step 6: Following step 5, if the number of tasks read is not 0, the task information is retrieved by calculating and accessing the corresponding task storage space address in DDR, and the number of tasks stored in the current time slice is cleared to zero; if the number of tasks read is 0, it means that there are no tasks that need to be triggered periodically in the current time period.
[0062] Step 7: Follow the clock to continue accessing the next time slice. When the time slice index jumps to the last time slice, reset the time slice index and return to the first time slice to continue the above steps.
[0063] The following section uses the timed retransmission of NACK messages in high-reliability transmission as an example for detailed explanation. If other custom applications are required, the design can be carried out according to this principle.
[0064] High-reliability transmission NACK message timed retransmission:
[0065] NACK messages refer to "negative acknowledgments" in network protocols. They are control messages in communication protocols used to indicate that the receiver has found an error or loss when receiving data packets and to request the sender to retransmit the data. The receiver periodically notifies the sender of the sequence numbers of all unreceived packets through feedback messages for retransmission.
[0066] Taking a scenario where each NACK packet requires three retransmissions, with timeout retransmission times of 50ms, 35ms, and 20ms respectively; setting the timer precision to 0.125ms and dividing the time slice into 512 slices, the maximum timeout period provided by the currently set timer is 63.875ms; the corresponding storage subspace is divided into 512 subspaces, each subspace is divided into 1024 slots, meaning the maximum number of tasks that can be stored per time slice is 1024; setting the task information bit width of the timeout task to 64 bits, the DDR address space occupied by one slot is 0x8, the address space occupied by one subspace is 0x2000, and the address space occupied by the entire task information storage space is 0x400000; let the starting address of the task information storage space be 0x0.
[0067] When the timer module receives the first NACK timed task (Task 1), the timeout task insertion module receives the NACK timed retransmission task information and its required retransmission time. Let's assume this is the start of the first time slice, with the time slice address at address 0, referred to as time slice 0. Task 1 has a timeout of 50ms. The task insertion logic calculates that Task 1 should be inserted into a target time slice address of 400. Assuming the original number of timeout tasks in this time slice was 0, it is updated to 1. Simultaneously, the starting address of the subspace with sequence number 400 in the DDR task information storage space is calculated to be 0x320000. The task is then inserted into slot 0 with sequence number 0, at address 0x320000.
[0068] While waiting for Task 1 to time out, other new tasks may be inserted. The following example only illustrates a NACK message that needs to be retransmitted three times. When 50ms have elapsed, the time slice index points to time slice 400 and is about to jump to time slice 401, it is detected that Task 1 has reached the timing condition in the current time segment. At this time, the task is retrieved from DDR (if the number of tasks in this time slice is greater than 1, all tasks are retrieved together), output to the external NACK retransmission management module, and the number of tasks stored in time slice 400 is cleared to 0. After receiving the timeout information, the external module retransmits the NACK message for the first time; at the same time, the task for the second retransmission (Task 2) and the timing time of 35ms are input into the timer, the external module's retransmission count is incremented by 1, and the timer module repeats the above operation.
[0069] Specifically, when the calculated time slice address overflows, the lower digits are automatically taken. For example, if task 2 is input when the time slice index points to time slice 401, its target time slice address should be 169. The starting address of the subspace with sequence number 169 is calculated to be 0x152000. Assuming the original number of tasks on this time slice is 100, the number of tasks is updated to 101. The slot number where the task information should be stored is 100, corresponding to a DDR address of 0x152320. Similarly, when task 3 inputs the timer when the time slice index points to time slice 170, the calculated target time slice address is 330, which will not overflow. The DDR address calculation will not be elaborated further.
[0070] In simple terms, after receiving the task information returned by the timer, the external module determines whether three retransmissions have been reached. If so, the task is deleted; otherwise, the corresponding NACK packet is retransmitted, and the task information and its next timeout are rewritten into the timer, awaiting the next timeout retransmission. If an unexpected situation occurs during the timer and retransmission of the NACK packet is no longer necessary, the external module marks it as such. When the timer outputs task information, it does not respond and will not send subsequent retransmission tasks for the same packet back to the timer.
[0071] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to the embodiments, those skilled in the art should understand that modifications or equivalent substitutions to the technical solutions of the present invention do not depart from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.
Claims
1. A timer based on FPGA, characterized in that, include: The module includes a timeout task insertion module, a timeout task detection module, and a timing module. The timeout task insertion module is used to receive timeout task information and timeout time, calculate the target time slice for task insertion based on the timeout time, and update the number of tasks in the corresponding time slice in the time slice storage space on Block RAM. Calculate the storage address of the task information and store the timeout task information in the corresponding location of the task information storage space on DDR. The timeout task detection module is used to detect the number of tasks stored in the time slice pointed to by the index according to the time slice index maintained by the timing module, retrieve the corresponding task information, and clear the number of tasks corresponding to the current time slice to zero. The timing module is used to time in an upward counting mode and maintain a time slice index.
2. The FPGA-based timer according to claim 1, characterized in that, The time slice storage space is divided into n time slices, each time slice represents a certain time slot T, and the upper limit of the number of tasks that meet the timeout triggering conditions stored on each time slice is a set value m.
3. The FPGA-based timer according to claim 2, characterized in that, The task information storage space is divided into n subspaces, each subspace corresponding one-to-one with a time slice in the time slice storage space; each subspace is divided into m slots, and each slot stores one task information in the order of task insertion.
4. The FPGA-based timer according to claim 3, characterized in that, The maximum task timing trigger time provided by the timer is T*(n-1).
5. The FPGA-based timer according to claim 2, characterized in that, The timeout task insertion module calculates the target time slice for task insertion based on the timeout period, including: Based on the timeout t of the current input task and the time slot T, calculate the number of delayed time slices, and use the current time slice index n. entry Adding this to the number of delayed time slices yields the target time slice n for task insertion. write Satisfy the following equation: n write =n entry +t*λ Wherein, λ is the normalization coefficient of the time slice, which is calculated based on the time slot T.
6. The FPGA-based timer according to claim 1, characterized in that, The timeout task insertion module calculates the storage address of the task information and stores the task information in the corresponding location of the task information storage space on DDR, including: The corresponding location ddr_awaddr in the task information storage space is obtained according to the following formula: ddr_awaddr=addr+n write *subaddr+(num-1)*timeout_event_length Where addr is the starting address of the task information storage space, num is the number of tasks stored in the corresponding time slice of Block RAM, timeout_event_length is the length of the task information, and subaddr is the address occupied by a subspace.
7. The FPGA-based timer according to claim 1, characterized in that, The timeout task detection module processing procedure includes: Based on the time slice index maintained by the timing module, when the time slice index points to a certain time slice and reaches the critical point to jump to the next time slice, the number of tasks stored in the current time slice is read. If the number of tasks read is not 0, retrieve the task information from the corresponding location in the task information storage space and clear the number of tasks stored in the current time slice to zero. If the number of tasks read is 0, then there are no tasks that need to be triggered on a schedule in the current time period.
8. The FPGA-based timer according to claim 1, characterized in that, The processing procedure of the timing module includes: Based on the system clock cycle, the time slice index is incremented by one every certain number of system clock cycles, pointing to the next time slice; when the time slice index reaches the last time slice, it returns to the initial time slice and continues working in a loop.
Citation Information
Patent Citations
High-security data mining device
CN111831605A
Large-scale timing method and device based on FPGA
CN114280977A