Display panel for improving electrostatic discharge, panel product and preparation method thereof

Abstract

The invention provides a display panel for improving electrostatic discharge, a panel product and a preparation method of the panel product, and belongs to the technical field of photoelectron manufacturing. The display panel comprises a driving substrate, a light-emitting functional layer, a bonding metal layer and a conductive layer, the surface of the driving substrate is provided with a first area and a second area, the bonding metal layer is located in the first area and the second area, the light-emitting functional layer is located on the surface of the bonding metal layer, and the orthographic projection of the light-emitting functional layer on the surface of the driving substrate is located in the first area; the conductive layer is located on the side, away from the driving substrate, of the bonding metal layer, the conductive layer is insulated from the bonding metal layer, the orthographic projection of the conductive layer on the plate surface of the driving substrate is located in the second area, and a cavity is formed between the conductive layer and the bonding metal layer. According to the embodiment of the invention, the problem that the LED chip is liable to fail due to electrostatic discharge can be improved, and the preparation yield is improved.

Description

Display panels with improved electrostatic discharge, panel products and their preparation methods Technical Field

[0001] This disclosure relates to the field of optoelectronic manufacturing technology, and in particular to a display panel, panel article and preparation method thereof with improved electrostatic discharge. Background Technology

[0002] Micro LED (Micro Light Emitting Diode) display panels are a display technology that uses micron-sized LED chips directly as self-emissive pixels. Multiple Micro LED chips are integrated onto a driving substrate through mass transfer, enabling independent light control for each pixel.

[0003] In related technologies, the epitaxial layer of a Micro LED chip is a semiconductor with a resistivity between that of a conductor and an insulator, making it prone to accumulating static charge during friction or contact separation. During the fabrication of the display panel, friction from human movement and equipment operation generates thousands of volts of static electricity. If operators do not take effective protective measures, electrostatic discharge will occur when the static electricity carried by their bodies comes into contact with the Micro LED chip.

[0004] However, the instantaneous high voltage generated by electrostatic discharge can easily break down the PN junction of Micro LED chips, causing chip failure. Furthermore, the charged chip surface will attract airborne particles (such as dust and fibers) due to electrostatic adsorption, severely affecting the chip's cleanliness. For AR display panels with precise structures and extremely high pixel density, this contamination can lead to a significant decrease in yield. Summary of the Invention

[0005] This disclosure provides a display panel, panel product, and manufacturing method thereof with improved electrostatic discharge, which can improve the problem of LED chips easily failing due to electrostatic discharge and improve the manufacturing yield. The technical solution is as follows: On one hand, this disclosure provides a display panel, the display panel including: a driving substrate, a light-emitting functional layer, a bonding metal layer, and a conductive layer; the surface of the driving substrate has a first region and a second region, the bonding metal layer is located on the surface of the driving substrate, the light-emitting functional layer is located on the surface of the bonding metal layer, and the orthographic projection of the light-emitting functional layer on the surface of the driving substrate is located in the first region; the conductive layer is located on the side of the bonding metal layer away from the driving substrate, and the conductive layer is insulated from the bonding metal layer, the orthographic projection of the conductive layer on the surface of the driving substrate is located in the second region, and a cavity is formed between the conductive layer and the bonding metal layer.

[0006] In one implementation of this disclosure, the display panel further includes an insulating layer located on the surface of the bonding metal layer, wherein at least a portion of the insulating layer has its orthographic projection onto the surface of the driving substrate located within the second region; a conductive layer is located on the surface of the insulating layer, and the surface of the conductive layer near the driving substrate has a groove, wherein the orthographic projection of the groove onto the surface of the driving substrate is located outside the orthographic projection of the insulating layer onto the surface of the driving substrate, and the groove and the bonding metal layer form the cavity.

[0007] In another implementation of this disclosure, the cavity has a height greater than or equal to 1 μm in the direction perpendicular to the surface of the driving substrate.

[0008] In another implementation of this disclosure, the display panel includes a plurality of conductive layers, the conductive layers being block-shaped, and the plurality of conductive layers being arranged at intervals around the first region.

[0009] In another implementation of this disclosure, the conductive layer comprises a metal layer.

[0010] Secondly, embodiments of this disclosure provide a panel product, the panel product comprising: a driving substrate, a light-emitting functional layer, a bonding metal layer, and a conductive layer; the surface of the driving substrate has a plurality of arrayed first regions and cutting regions, the cutting regions being gaps between each of the first regions, the bonding metal layer being located in the first regions and the cutting regions; the light-emitting functional layer being located on the surface of the bonding metal layer, the light-emitting functional layer corresponding one-to-one with the first regions, the orthographic projection of the light-emitting functional layer on the surface of the driving substrate being located within the corresponding first region; the conductive layer being located on the side of the bonding metal layer away from the driving substrate, and the conductive layer being insulated from the bonding metal layer, the orthographic projection of the conductive layer on the surface of the driving substrate being located within the cutting regions, and a cavity being formed between the conductive layer and the bonding metal layer.

[0011] In another implementation of this disclosure, the panel product further includes an insulating layer, which corresponds one-to-one with the light-emitting functional layer. The insulating layer is located on the surface of the bonding metal layer and covers the corresponding light-emitting functional layer. At least a portion of the insulating layer extends to the cutting area. The insulating layers on two adjacent light-emitting functional layers are spaced apart within the cutting area. The conductive layer is U-shaped, with its two ends respectively connected to the surfaces of two adjacent insulating layers. The conductive layer and the bonding metal layer form the cavity.

[0012] In another implementation of this disclosure, the cavity has a height greater than or equal to 1 μm in the direction perpendicular to the surface of the driving substrate.

[0013] In another implementation of this disclosure, the panel article includes a plurality of conductive layers, the conductive layers being block-shaped, and the plurality of conductive layers being spaced apart along the extension direction of the cutting area.

[0014] Thirdly, embodiments of this disclosure provide a method for fabricating a panel product. The method includes: forming an epitaxial layer on a substrate; forming a bonding metal layer between the epitaxial layer and a driving substrate; bonding the epitaxial layer to the driving substrate; and removing the substrate. The driving substrate has a plurality of arrayed first regions and dicing regions on its surface. The dicing regions are gaps between the first regions. The bonding metal layer is located in the first regions and the dicing regions. The epitaxial layer is patterned to form a plurality of light-emitting functional layers corresponding one-to-one with the first regions. The orthographic projection of the light-emitting functional layer on the surface of the driving substrate is located within the corresponding first region. A conductive layer is formed on the side of the bonding metal layer away from the driving substrate. The conductive layer is insulated from the bonding metal layer. The orthographic projection of the conductive layer on the surface of the driving substrate is located within the dicing regions. A cavity exists between the conductive layer and the bonding metal layer.

[0015] The beneficial effects of the technical solution provided in this disclosure include at least the following: the display panel provided in this disclosure has a conductive layer in the second region, and the conductive layer and the bonding metal layer form a cavity. Since the essence of electrostatic discharge is the formation of a discharge path through a medium (such as air or semiconductor material) by an instantaneous high voltage, the timescale of air being electrostatically broken down (ionized) is on the picosecond scale, while the time for electrostatic breakdown of a semiconductor PN junction is typically on the nanosecond or microsecond scale. That is, the speed of air ionization is much faster than the time for electrostatic breakdown of the PN junction. Therefore, when static electricity generated by a human body or device is applied to the chip, the electrostatic energy will preferentially ionize through the air in the cavity, forming a low-impedance discharge path, quickly dissipating the energy of the instantaneous high voltage in the air medium. This ensures that the electrostatic energy is intercepted and released by the air layer before the PN junction of the LED chip is broken down by the high voltage, thereby avoiding the problem of PN junction failure due to overvoltage.

[0016] Meanwhile, the conductive layer is disposed in the second region of the driving substrate and is insulated from the bonding metal layer. When static electricity is released through the cavity, the discharge process is concentrated in the second region, preventing electrical interference or physical damage to the light-emitting functional layer in the first region. This partitioned design utilizes the redundant space in the second region for electrostatic protection while completely isolating the protective structure from the core display function, ensuring the yield and reliability of the first region from a physical layout perspective.

[0017] Furthermore, by preferentially dissipating electrostatic energy through the conductive layer, the residual electrostatic charge on the chip surface is fundamentally reduced. Once the static electricity is rapidly neutralized by the cavity, the chip no longer maintains a high potential state, thereby reducing the probability of electrostatic adsorption of particles. This effectively maintains the cleanliness of the chip surface and further improves the manufacturing yield of the display panel. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 is a top view of a display panel provided in an embodiment of the present disclosure; Figure 2 is a structural schematic diagram of a display panel provided in an embodiment of the present disclosure; Figure 3 is a top view of a panel product provided in an embodiment of the present disclosure; Figure 4 is a structural schematic diagram of a panel product provided in an embodiment of the present disclosure; Figure 5 is a flowchart of a method for preparing a panel product provided in an embodiment of the present disclosure; Figure 6 is a diagram of the preparation state of a panel product provided in an embodiment of the present disclosure; Figure 7 is a diagram of the preparation state of a panel product provided in an embodiment of the present disclosure; Figure 8 is a diagram of the preparation state of a panel product provided in an embodiment of the present disclosure; Figure 9 is a diagram of the preparation state of a panel product provided in an embodiment of the present disclosure.

[0020] The markings in the figure are explained as follows: 10, driving substrate; 11, first region; 12, second region; 13, dicing area; 20, light-emitting functional layer; 200, light-emitting unit; 21, epitaxial layer; 30, bonding metal layer; 31, bonding metal block; 40, conductive layer; 41, cavity; 42, sacrificial layer; 50, insulating layer; 60, transparent conductive layer; 70, connecting electrode; 80, light-harvesting structure; 90, substrate; 91, contact layer. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in further detail below with reference to the accompanying drawings.

[0022] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” “third,” and similar terms used in this patent application specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an” or “a” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “comprising” or “including” and similar terms mean that the elements or objects preceding “comprising” or “including” encompass the elements or objects listed following “comprising” or “including” and their equivalents, and do not exclude other elements or objects. The terms “connected” or “linked” and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” “right,” “top,” and “bottom,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0023] Figure 1 is a top view of a display panel provided in an embodiment of this disclosure. Figure 2 is a structural schematic diagram of a display panel provided in an embodiment of this disclosure. Figure 2 is a cross-sectional view cut along the MM section line in Figure 1.

[0024] As shown in Figure 2, the display panel includes: a driving substrate 10, a light-emitting functional layer 20, a bonding metal layer 30, and a conductive layer 40.

[0025] As shown in Figures 1 and 2, the surface of the driving substrate 10 has a first region 11 and a second region 12. The bonding metal layer 30 is located in the first region 11 and the second region 12. The light-emitting functional layer 20 is located on the surface of the bonding metal layer 30, and the orthographic projection of the light-emitting functional layer 20 on the surface of the driving substrate 10 is located in the first region 11.

[0026] As shown in Figures 1 and 2, the conductive layer 40 is located on the side of the bonding metal layer 30 away from the driving substrate 10, and the conductive layer 40 is insulated from the bonding metal layer 30. The orthographic projection of the conductive layer 40 on the surface of the driving substrate 10 is located in the second region 12, and there is a cavity 41 between the conductive layer 40 and the bonding metal layer 30.

[0027] The display panel provided in this embodiment has a conductive layer 40 in the second region 12, and the conductive layer 40 and the bonding metal layer 30 form a cavity 41. Since electrostatic discharge is essentially the formation of a discharge path through a medium (such as air or a semiconductor material) by a momentary high voltage, the timescale for air to be electrostatically broken down (ionized) is on the picosecond scale, while the time for electrostatic breakdown of a semiconductor PN junction is typically on the nanosecond or microsecond scale. That is, the speed of air ionization is much faster than the time for electrostatic breakdown of the PN junction. Therefore, when static electricity generated by a human body or device is applied to the chip, the electrostatic energy preferentially ionizes through the air in the cavity 41, forming a low-impedance discharge path, quickly dissipating the energy of the momentary high voltage in the air medium. This ensures that the electrostatic energy is intercepted and released by the air layer before the PN junction of the LED chip is broken down by the high voltage, thereby avoiding the problem of PN junction failure due to overvoltage.

[0028] Meanwhile, the conductive layer 40 is disposed in the second region 12 of the driving substrate 10 and is insulated from the bonding metal layer 30. When static electricity is released through the cavity 41, the discharge process is concentrated in the second region 12 and will not cause electrical interference or physical damage to the light-emitting functional layer 20 of the first region 11. This partitioned design utilizes the redundant space of the second region 12 to achieve electrostatic protection and completely isolates the connection between the protective structure and the core display function, ensuring the yield and reliability of the first region 11 from a physical layout perspective.

[0029] Furthermore, by preferentially dissipating electrostatic energy through the conductive layer 40, the residual electrostatic charge on the chip surface is fundamentally reduced. When the static electricity is quickly neutralized by the cavity 41, the chip no longer maintains a high potential state, thereby reducing the probability of electrostatic adsorption of particles, effectively maintaining the cleanliness of the chip surface, and further improving the manufacturing yield of the display panel.

[0030] Optionally, the second region on the driving substrate may be a region arranged along at least one side of the first region.

[0031] For example, as shown in Figure 1, the second region is arranged along all the sides of the first region. That is, the second region surrounds the first region.

[0032] In some other embodiments, the second region may also be arranged along a portion of the side of the first region, and this disclosure does not impose any limitations.

[0033] Optionally, as shown in FIG2, the display panel further includes an insulating layer 50, which is located on the surface of the bonding metal layer 30, and at least a portion of the film layer of the insulating layer 50 is projected onto the surface of the driving substrate 10 within the second region 12.

[0034] As shown in Figure 2, the conductive layer 40 is located on the surface of the insulating layer 50. The surface of the conductive layer 40 near the driving substrate 10 has a groove. The orthographic projection of the groove on the surface of the driving substrate 10 is outside the orthographic projection of the insulating layer 50 on the surface of the driving substrate 10. The groove and the bonding metal layer 30 form a cavity 41.

[0035] In the above implementation, the insulating layer 50 is located between the bonding metal layer 30 and the conductive layer 40, and at least a portion of its film is projected orthogonally into the second region 12, ensuring a stable insulating state between the conductive layer 40 and the bonding metal layer 30. Even in high humidity or complex process environments, the insulating layer 50 can effectively block direct conduction between the two, preventing accidental triggering of discharge and avoiding damage to the chip or driving circuit due to short circuits.

[0036] Meanwhile, the conductive layer 40 has a groove on its surface near the driving substrate 10. This groove, projected onto the ground plane, is located outside the insulating layer 50 and together with the bonding metal layer 30, forms a cavity 41. Thus, when static electricity is released, air is preferentially ionized within the cavity 41, forming a low-impedance discharge channel that rapidly dissipates static energy without affecting the normal operation of the first region 11. The groove also allows for adjustment of the shape of the cavity 41, making it more adaptable to the electrostatic protection requirements of different regions and further improving discharge efficiency.

[0037] Furthermore, since the conductive layer 40 and its grooves are both located in the second region 12, and the insulating layer 50 ensures that it is insulated from the bonding metal layer 30, the electrostatic discharge process is completely confined to the second region 12 and will not interfere with the electrical and optical performance of the light-emitting functional layer 20. This layout achieves efficient electrostatic protection while avoiding any potential impact of the conductive layer 40 on the first region 11, making it particularly suitable for high pixel density AR display panels.

[0038] For example, the cavity 41 can be a trapezoidal shape that is wider at the top and narrower at the bottom, with the narrower side near the bonding metal layer 30. This shape allows static electricity to be released more concentratedly through air ionization in the narrower channel. In local areas with high static electricity intensity, the discharge rate of that part of the static electricity can be accelerated, preferentially and quickly dissipating high-energy static electricity, thus playing a role in rapidly dissipating high-energy static electricity.

[0039] Optionally, the cavity 41 has a height greater than or equal to 1 μm in the direction perpendicular to the surface of the drive substrate 10.

[0040] Setting the cavity 41 at a height within the aforementioned range in the direction perpendicular to the drive substrate 10 improves electrostatic discharge (ESD) protection and the reliability of the display panel. The cavity 41's height exceeds 1 μm, ensuring ample ionization space in the air layer, allowing ESD to primarily occur within the air medium. Since air ionization time is much faster than the ESD breakdown time of the PN junction, the higher cavity 41 ensures that ESD energy is preferentially dissipated through air ionization, preventing high voltage from directly affecting the Micro LED chip's PN junction and effectively preventing chip breakdown failure. Furthermore, the larger cavity 41 height reduces parasitic capacitance between the conductive layer 40 and the bonding metal layer 30, minimizing electrical interference to the circuitry in the first region 11 and ensuring the stability of display signal transmission.

[0041] For example, the cavity 41 has a height of 1.3 μm in the direction perpendicular to the surface of the drive substrate 10.

[0042] Optionally, as shown in FIG1, the display panel includes a plurality of conductive layers 40, the conductive layers 40 being in a block shape, and the plurality of conductive layers 40 being arranged at intervals around the first region 11.

[0043] By setting multiple conductive layers 40, multiple electrostatic discharge channels can be provided. When the electrostatic discharge generated by the human body or equipment comes into contact with the Micro LED chip, the multiple conductive layers 40 can guide and release the electrostatic discharge simultaneously or in different areas, which disperses the electrostatic shock, avoids excessive concentration of local electrostatic energy, greatly reduces the risk of electrostatic breakdown of the chip PN junction, and effectively protects the chip.

[0044] Furthermore, the blocky arrangement surrounding the first region 11 at intervals can make full use of the unused space of the second region 12, without obstructing or interfering with the light-emitting functional layer 20 of the first region 11, ensuring that the first region 11 can perform its display function normally and maintain the display effect under high pixel density.

[0045] Meanwhile, the multiple conductive layers 40 arranged at intervals can provide precise protection against static electricity at different locations. The static electricity generation conditions may vary at different locations, and the multiple conductive layers 40 can function according to the actual situation, improving the targeting and effectiveness of static electricity protection.

[0046] For example, the distribution density of the conductive layer 40 can be increased in areas prone to electrostatic discharge. For instance, at junctions where the display panel is spliced ​​with other circuit boards, static electricity is more likely to be generated due to differences in manufacturing processes. In such cases, the distribution density of the conductive layer 40 can be increased to prevent static electricity from affecting the chip.

[0047] Optionally, the conductive layer 40 includes a metal layer.

[0048] For example, the conductive layer 40 may include at least one of an Al layer, a Cu layer, and a Mo layer.

[0049] For example, when the conductive layer 40 is a Cu layer, Cu has better conductivity and can conduct away static energy more efficiently than aluminum, making it particularly suitable for scenarios with extremely high requirements for electrostatic response speed, such as high pixel density AR chips.

[0050] For example, when the conductive layer 40 is an Al layer, Al has a low resistivity, which can effectively conduct away static charge and ensure rapid static discharge. At the same time, aluminum is inexpensive, has mature processing technology, and is easy to deposit and etch, making it suitable for large-scale production. Furthermore, a dense oxide layer can easily form on the aluminum surface, which can enhance insulation reliability to a certain extent and prevent accidental short circuits.

[0051] For example, when the conductive layer 40 is a Mo layer, Mo has a high melting point and good chemical stability, making it less prone to deformation or oxidation in high-temperature processes, and thus suitable for complex process environments.

[0052] Optionally, as shown in FIG2, the light-emitting functional layer 20 includes a plurality of light-emitting units 200 arranged at intervals, and each light-emitting unit 200 includes a first semiconductor layer, a multiple quantum well layer and a second semiconductor layer stacked in sequence.

[0053] In this process, one of the first semiconductor layer and the second semiconductor layer is a p-type layer, and the other of the first semiconductor layer and the second semiconductor layer is an n-type layer.

[0054] For example, the first semiconductor layer is a p-type layer and the second semiconductor layer is an n-type layer.

[0055] For example, the n-type layer is an n-type GaN layer. The thickness of the n-type GaN layer can be from 0.5 μm to 1 μm.

[0056] For example, the multi-quantum-well layer includes alternating InGaN quantum well layers and GaN quantum barrier layers. Specifically, the multi-quantum-well layer may comprise 3 to 8 alternating stacked InGaN quantum well layers and GaN quantum barrier layers.

[0057] As an example, in an embodiment of this disclosure, the multi-quantum-well layer includes five alternating stacked InGaN quantum-well layers and GaN quantum-barrier layers.

[0058] For example, the thickness of the multi-quantum well layer can be from 150 nm to 200 nm.

[0059] For example, the p-type layer is a p-type GaN layer. The thickness of the p-type GaN layer can be from 0.5 μm to 1 μm.

[0060] Optionally, as shown in FIG2, the display panel further includes a transparent conductive layer 60, an insulating layer 50 located on the driving substrate 10, and the insulating layer 50 covers the light-emitting unit 200, and the insulating layer 50 has through holes exposing each light-emitting unit 200.

[0061] As shown in Figure 2, the transparent conductive layer 60 is located on the surface of the insulating layer 50 and is connected to each light-emitting unit 200 through a via.

[0062] In the above implementation, the insulating layer 50 covers the light-emitting unit 200, which can effectively achieve electrical isolation between adjacent light-emitting units 200 and between the light-emitting unit 200 and other film layers, prevent short circuit faults between different circuits, protect the light-emitting unit 200 and the driving circuit from external interference and damage, and improve the stability and reliability of the display panel operation.

[0063] Meanwhile, the via design on the insulating layer 50 is precise, exposing only each light-emitting unit 200. The transparent conductive layer 60 is connected to the light-emitting unit 200 through the via, which can realize the precise electrical connection between the light-emitting unit 200 and the driving circuit, ensuring that each light-emitting unit 200 can independently and stably receive the driving signal, thus guaranteeing the accuracy and consistency of the display effect.

[0064] For example, the transparent conductive layer 60 may be an ITO layer or an IZO layer.

[0065] As an example, the thickness of the transparent conductive layer 60 can be greater than or equal to 2000 angstroms. This thickness range ensures good conductivity for effective transmission of electrical signals while also providing high transparency to reduce obstruction of the light emitted by the light-emitting unit 200.

[0066] For example, the insulating layer 50 may include at least one of a silicon oxide layer, a titanium oxide layer, and an epoxy resin layer.

[0067] For example, the thickness of the insulating layer 50 is 1 μm to 2.5 μm.

[0068] For example, the insulating layer 50 may be a distributed Bragg reflector (DBR) layer.

[0069] The DBR layer may include multiple alternating layers of first material and multiple layers of second material, with different refractive indices for the first and second material layers.

[0070] For example, one of the first material layer and the second material layer is a TiO2 layer, and the other of the first material layer and the second material layer is a SiO2 layer.

[0071] Among them, the reflection band of the DBR has wavelength selectivity, which can accurately reflect light while allowing other stray wavelengths to pass through, thus enhancing the directional output of effective light.

[0072] Optionally, as shown in FIG2, the display panel further includes a connecting electrode 70, which is located on the surface of the transparent conductive layer 60 and in the gap between each light-emitting unit 200.

[0073] The connecting electrode 70 can establish additional electrical connection channels in the gaps between the light-emitting units 200, which facilitates the effective connection of multiple light-emitting units 200 or light-emitting units 200 in different regions, expands the flexibility of circuit connection, helps to realize complex display driving circuit layout, and meets diverse display needs.

[0074] Meanwhile, by rationally distributing electrical signals through the connecting electrode 70, each light-emitting unit 200 can obtain a more balanced driving current, reducing brightness differences caused by uneven current distribution, thereby improving the display uniformity of the entire display panel.

[0075] Furthermore, by utilizing the gaps between the light-emitting units 200 to set the connecting electrodes 70, the main display space of the display panel is not occupied additionally, thus avoiding the compression of the first area 11 due to the addition of connecting structures. This helps to achieve miniaturization and high pixel density design of the display panel and improves space utilization efficiency.

[0076] Optionally, as shown in FIG2, in the first region 11, the bonding metal layer 30 includes a plurality of bonding metal blocks 31 corresponding one-to-one with the light-emitting unit 200, and each light-emitting unit 200 is located on the corresponding bonding metal block 31.

[0077] As shown in Figure 2, the orthographic projection of the light-emitting unit 200 on the surface of the driving substrate 10 is located within the orthographic projection of the corresponding bonding metal block 31 on the surface of the driving substrate 10.

[0078] In the above implementation, the orthographic projection of the light-emitting unit 200 is located within the bonding metal block 31, ensuring precise alignment during bonding and preventing misalignment. The bonding metal block 31 provides a large contact area, enhancing the mechanical fixing strength between the light-emitting unit 200 and the driving substrate 10, preventing loosening or detachment after long-term use. Furthermore, the bonding metal block 31 directly supports the light-emitting unit 200, effectively reducing contact resistance, improving driving current transmission efficiency, reducing signal attenuation and heat generation, and ensuring stable driving and efficient light emission of the light-emitting unit 200.

[0079] Optionally, the driving substrate 10 may be a complementary metal-oxide-semiconductor (CMOS) integrated circuit board.

[0080] As shown in Figure 2, an electrode block corresponding to each of the light-emitting units 200 is provided on the driving substrate 10. Each light-emitting unit 200 has a bonding metal block 31 on the side close to the driving substrate 10. The bonding metal block 31 of each light-emitting diode is electrically connected to the corresponding electrode block, so as to realize the purpose of the driving substrate 10 controlling the operation of each light-emitting diode.

[0081] For example, the bonding metal block 31 may include at least one of AuBe layer, Au layer, Ti layer, Ni layer and Pt layer.

[0082] Optionally, as shown in FIG2, the display panel further includes a light-collecting structure 80, which is located on the surface of the transparent conductive layer 60 away from the driving substrate 10.

[0083] Among them, the light-collecting structure 80 corresponds one-to-one with the light-emitting unit 200, and the orthographic projection of the light-emitting unit 200 on the surface of the driving substrate 10 is located within the orthographic projection of the corresponding light-collecting cone on the surface of the driving substrate 10; the surface of the end of the light-collecting structure 80 away from the driving substrate 10 is an arc surface.

[0084] In this embodiment, the top surface of the light-collecting structure 80 is designed as an arc surface. As a basic optical element, the arc surface has the characteristic of converging light. The arc surface can apply an initial deflection to the emitted light of the light-emitting unit 200, so that the originally dispersed light is concentrated in a more favorable direction.

[0085] Alternatively, the light-collecting structure 80 can be made of PDMS, PMMA, or silicon dioxide.

[0086] Polydimethylsiloxane (PDMS) is a flexible and bendable material; its light transmittance exceeds 90%, which reduces total reflection and makes it suitable for flexible Micro LED panels.

[0087] Among them, polymethyl methacrylate (PMMA) has a light transmittance of over 92%, good optical uniformity, moderate mechanical strength, good weather resistance, and is easy to mold, making it suitable for preparing light-collecting structures for large-area planar displays.

[0088] Among them, silicon dioxide has a light transmittance of over 95% and excellent thermal stability, and can be precisely processed into microstructures through etching, making it suitable for high-temperature processes and high-precision display requirements.

[0089] Figure 3 is a top view of a panel article provided in an embodiment of the present disclosure. Figure 4 is a structural schematic diagram of a panel article provided in an embodiment of the present disclosure. Figure 4 is a cross-sectional view cut along the NN section line in Figure 3.

[0090] As shown in Figures 3 and 4, the panel product includes: a driving substrate 10, a light-emitting functional layer 20, a bonding metal layer 30, and a conductive layer 40.

[0091] As shown in Figures 3 and 4, the surface of the driving substrate 10 has multiple arrayed first regions 11 and cutting regions 13, with the cutting regions 13 being the gaps between each of the first regions 11, and the bonding metal layer 30 located in the first regions 11 and the cutting regions 13.

[0092] As shown in Figures 3 and 4, the light-emitting functional layer 20 is located on the surface of the bonding metal layer 30, and the light-emitting functional layer 20 corresponds one-to-one with the first region 11. The orthographic projection of the light-emitting functional layer 20 on the surface of the driving substrate 10 is located within the corresponding first region 11. As shown in Figures 3 and 4, the conductive layer 40 is located on the side of the bonding metal layer 30 away from the driving substrate 10, and the conductive layer 40 is insulated from the bonding metal layer 30. The orthographic projection of the conductive layer 40 on the surface of the driving substrate 10 is located within the cutting area 13, and there is a cavity 41 between the conductive layer 40 and the bonding metal layer 30.

[0093] In this embodiment, the panel product is cut along the cutting area 13 to obtain multiple display panels as shown in Figures 1 and 2. The cutting area 13 of the panel product is the gap between the display panels and also the area for subsequent cutting operations, which is prone to static electricity generation due to equipment operation and personnel movement. By providing a conductive layer 40 in the cutting area 13 of the panel product, and ensuring that the conductive layer 40 is insulated from the bonding metal layer 30, with a cavity 41 between them, when static electricity is generated, the time for the air to be electrostatically broken down (ionized) in the cavity 41 is on the picosecond scale, much faster than the time for electrostatic breakdown of the Micro LED chip PN junction. Therefore, the electrostatic energy is preferentially consumed in the air within the cavity 41. This effectively avoids the instantaneous high voltage generated by electrostatic discharge from breaking down the chip PN junction, preventing chip failure and protecting the core performance of the light-emitting functional layer 20 corresponding to the first region 11 from the source.

[0094] Meanwhile, charged chip surfaces are prone to attracting dust, fibers, and other particles from the air due to electrostatic attraction, affecting chip cleanliness. This structure preferentially dissipates electrostatic energy through cavity 41, reducing residual static electricity on the chip surface and mitigating electrostatic attraction, thereby ensuring chip cleanliness. This is particularly crucial for high-pixel-density display panels subsequently cut along the cutting area 13, preventing a significant drop in yield due to contamination.

[0095] Optionally, as shown in FIG4, the panel product further includes an insulating layer 50, which corresponds one-to-one with the light-emitting functional layer 20. The insulating layer 50 is located on the surface of the bonding metal layer 30 and covers the corresponding light-emitting functional layer 20. At least a portion of the film layer of the insulating layer 50 extends to the cutting area 13, and the insulating layers 50 on two adjacent light-emitting functional layers 20 are arranged at intervals in the cutting area 13.

[0096] As shown in Figure 4, the conductive layer 40 is U-shaped, and its two ends are respectively connected to the surfaces of two adjacent insulating layers 50. The conductive layer 40 and the bonding metal layer 30 form a cavity 41.

[0097] In the above implementation, the insulating layer 50 covers the light-emitting functional layer 20 and extends to the cutting area 13, providing direct insulation protection for the display panel and anchoring points for the U-shaped conductive layer 40. The conductive layer 40 connects to adjacent insulating layers 50 in a U-shape, forming a cavity 41 with the bonding metal layer 30. When static electricity is generated, the air in the cavity 41 is preferentially ionized, confining the instantaneous high voltage energy within the cavity 41 of the cutting area 13 for release. Meanwhile, the insulating layer 50 blocks the conduction of static electricity to the light-emitting functional layer 20, preventing PN junction breakdown and ensuring the electrical stability of the high pixel density first region 11.

[0098] The U-shaped conductive layer 40 and the bonded metal layer 30 form a closed cavity 41, which concentrates and short-circuits the electrostatic discharge path. Air ionization occurs much faster than semiconductor breakdown time, rapidly dissipating electrostatic energy. The U-shaped structure increases the relative area between the conductive layer 40 and the bonded metal layer 30, enhancing the ability to capture electrostatic charge in multiple directions within the cut area 13. Compared to the planar conductive layer 40, the U-shaped design further reduces discharge resistance, ensuring instantaneous discharge of high-energy electrostatic charge. Simultaneously, the spaced arrangement of the insulating layers 50 naturally forms an independent protective boundary for the display panel during cutting, preventing residual conductive layer 40 or short circuits.

[0099] Optionally, the cavity 41 has a height greater than or equal to 1 μm in the direction perpendicular to the surface of the drive substrate 10.

[0100] Setting the cavity 41 at a height within the aforementioned range in the direction perpendicular to the drive substrate 10 improves electrostatic discharge (ESD) protection and the reliability of the display panel. The cavity 41's height exceeds 1 μm, ensuring ample ionization space in the air layer, allowing ESD to primarily occur within the air medium. Since air ionization time is much faster than the ESD breakdown time of the PN junction, the higher cavity 41 ensures that ESD energy is preferentially dissipated through air ionization, preventing high voltage from directly affecting the Micro LED chip's PN junction and effectively preventing chip breakdown failure. Furthermore, the larger cavity 41 height reduces parasitic capacitance between the conductive layer 40 and the bonding metal layer 30, minimizing electrical interference to the circuitry in the first region 11 and ensuring the stability of display signal transmission.

[0101] For example, the cavity 41 has a height of 1.3 μm in the direction perpendicular to the surface of the drive substrate 10.

[0102] Optionally, as shown in FIG3, the panel product includes a plurality of conductive layers 40, the conductive layers 40 being in the form of blocks, and the plurality of conductive layers 40 being arranged at intervals along the extension direction of the cutting area 13.

[0103] The cutting area 13 is a region prone to static electricity. Personnel operation and equipment operation may cause static electricity to accumulate in this area. The multiple conductive layers 40 arranged at intervals can accurately conduct static electricity generated in different locations, avoiding the concentration of static electricity in one place, reducing the risk of electrostatic breakdown of the chip PN junction, and effectively protecting the light-emitting functional layer 20.

[0104] Furthermore, the spacing arrangement can flexibly adapt to panel products of different sizes and layouts. The spacing and number of conductive layers 40 can be reasonably adjusted according to the actual length of the cutting area 13 and the characteristics of static electricity generation, ensuring that static electricity in each area can be released in a timely manner.

[0105] Optionally, the conductive layer 40 includes a metal layer.

[0106] For example, the conductive layer 40 may include at least one of an Al layer, a Cu layer, and a Mo layer.

[0107] It should be noted that the driving substrate 10, the light-emitting functional layer 20, and other film layer structures in the first region 11 of the panel product are the same as the corresponding structures of the display panel described above, and will not be described again in this embodiment.

[0108] Figure 5 is a flowchart of a method for preparing a panel article according to an embodiment of the present disclosure. As shown in Figure 5, the preparation method includes: S11: forming an epitaxial layer 21 on a substrate 90.

[0109] For example, the substrate is a sapphire substrate. Sapphire substrates have high light transmittance, meaning they are transparent. Furthermore, sapphire material is relatively hard and chemically stable, giving the light-emitting diode (LED) good luminous efficacy and stability.

[0110] For example, the epitaxial layer 21 may include a second semiconductor layer, a multiple quantum well layer and a first semiconductor layer sequentially stacked on the substrate 90.

[0111] The first semiconductor layer has a first conductivity type, the second semiconductor layer has a second conductivity type different from the first conductivity type, and the multiple quantum well layer is used to generate light through electron-hole recombination.

[0112] In this process, one of the first semiconductor layer and the second semiconductor layer is a p-type layer, and the other of the first semiconductor layer and the second semiconductor layer is an n-type layer.

[0113] As an example, the first semiconductor layer is an n-type layer and the second semiconductor layer is a p-type layer.

[0114] Optionally, the first semiconductor layer is an n-type GaN layer. The thickness of the n-type GaN layer can be from 0.5 μm to 1 μm.

[0115] Optionally, the multiple quantum well layer includes alternating InGaN quantum well layers and GaN quantum barrier layers. Specifically, the multiple quantum well layer may include 3 to 8 alternating stacked InGaN quantum well layers and GaN quantum barrier layers.

[0116] As an example, in an embodiment of this disclosure, the multi-quantum-well layer includes five alternating stacked InGaN quantum-well layers and GaN quantum-barrier layers.

[0117] Optionally, the thickness of the multi-quantum well layer can be from 150 nm to 200 nm.

[0118] Optionally, the second semiconductor layer is a p-type GaN layer. The thickness of the p-type GaN layer can be from 0.5 μm to 1 μm.

[0119] After growing the epitaxial layer 21 in step S11, the process may further include growing a contact layer 91 on the surface of the light-emitting functional layer 20.

[0120] For example, the contact layer 91 may be at least one of a metal layer and a transparent conductive layer 60.

[0121] For example, contact layer 91 can be an ITO layer or an IZO layer.

[0122] S12: A bonding metal layer 30 is formed between the epitaxial layer 21 and the driving substrate 10, the epitaxial layer 21 is bonded to the driving substrate 10, and the substrate 90 is removed.

[0123] The driving substrate 10 has multiple arrayed first regions 11 and cutting regions 13 on its surface. The cutting regions 13 are the gaps between the first regions 11, and the bonding metal layer 30 is located in the first regions 11 and the cutting regions 13.

[0124] As shown in Figure 6, step S12 may include: forming a bonding metal layer 30 on the surface of both the driving substrate 10 and the contact layer 91, and bonding the contact layer 91 and the driving substrate 10 together.

[0125] The bonding metal layer 30 may include at least one of a titanium layer, a platinum layer, a gold layer, an aluminum layer, and a tin layer.

[0126] Next, the substrate 90 is removed, and a contact layer 91 is formed on the surface of the epitaxial layer 21.

[0127] For example, the contact layer 91 may be at least one of a metal layer and a transparent conductive layer 60.

[0128] For example, contact layer 91 can be an ITO layer or an IZO layer.

[0129] S13: The epitaxial layer 21 is patterned to form multiple light-emitting functional layers 20 that correspond one-to-one with the first region 11.

[0130] The orthographic projection of the light-emitting functional layer 20 onto the surface of the driving substrate 10 is located within the corresponding first region 11, and each light-emitting functional layer 20 in the first region 11 includes a plurality of light-emitting units 200 arranged at intervals.

[0131] As shown in Figure 7, step S13 may specifically include the following steps: First, photoresist is spin-coated on the surface of the epitaxial layer 21 using photolithography, and then exposed and developed using a mask to define a patterned region that precisely corresponds to the position and size of each first region 11.

[0132] Subsequently, using inductively coupled plasma etching or wet etching techniques, the epitaxial layer 21 is selectively etched along the patterned boundary, retaining the epitaxial material at the corresponding position in the first region 11 while removing the epitaxial layer 21 in the gap region. The etching depth must be precisely matched to the designed thickness of the light-emitting functional layer 20 to ensure that the final light-emitting functional layer 20 exists only directly below the first region 11.

[0133] Finally, residual photoresist is removed through a photoresist stripping process to complete the patterning. This step ensures that each light-emitting functional layer 20 corresponds strictly one-to-one with a single first region 11, and its orthographic projection falls completely within the first region 11, laying the foundation for the subsequent isolation and protection of the conductive layer 40.

[0134] As shown in Figure 7, during the patterning process, in the first region 11, the bonding metal layer 30 is etched to form multiple bonding metal blocks 31; in the cutting region 13, the bonding metal layer 30 is not etched.

[0135] As shown in Figure 7, after step S13, an insulating layer 50 is formed on the surface of the driving substrate 10, such that the insulating layer 50 covers each light-emitting unit 200.

[0136] In this process, at least a portion of the insulating layer 50 extends into the cutting region 13, opening the insulating layer 50 located in the cutting region 13, so that the insulating layers 50 on two adjacent light-emitting functional layers 20 are spaced apart within the cutting region 13.

[0137] S14: A conductive layer 40 is formed on the side of the bonding metal layer 30 away from the driving substrate 10.

[0138] The conductive layer 40 is insulated from the bonding metal layer 30. The orthographic projection of the conductive layer 40 on the surface of the driving substrate 10 is located within the cutting area 13. A cavity 41 is provided between the conductive layer 40 and the bonding metal layer 30.

[0139] Step S14 may include the following steps: First, as shown in FIG8, a sacrificial material is filled into the opening of the insulating layer 50 in the cutting area 13 by magnetron sputtering or spin coating process to form a sacrificial layer 42.

[0140] If an easily corroded metal (such as Al) is selected, a metal layer of uniform thickness is deposited in the opening by electron beam evaporation; if a photoresist is selected, a high-resolution negative resist is spin-coated and soft-baked to ensure that the sacrificial layer 42 completely fills the opening, providing a support structure for the subsequent encapsulation of the conductive layer 40.

[0141] Then, as shown in Figure 8, a conductive layer 40 is fabricated on the insulating layer 50 of the cutting region 13, such that the conductive layer 40 spans the sacrificial layer 42.

[0142] Specifically, conductive metal can be deposited on the surface of insulating layer 50 using electron beam evaporation or sputtering processes. The pattern is defined by photolithography so that the two ends of the U-shaped conductive layer 40 are respectively located on the surfaces of two spaced insulating layers 50, and the sacrificial layer 42 inside the opening is wrapped downwards, ultimately forming a U-shaped structure with both ends anchored and the middle spanning the sacrificial layer 42.

[0143] Next, as shown in Figure 8, the sacrificial layer 42 is etched or ashed, so that the conductive layer 40 and the bonding metal layer 30 form a cavity 41.

[0144] Specifically, the metal sacrificial layer 42 (such as Al) is selectively etched using a phosphoric acid solution; the photoresist sacrificial layer 42 is completely removed using an oxygen plasma ashing process. After the sacrificial layer 42 disappears, the two ends of the U-shaped conductive layer 40 are fixed to the insulating layer 50, and a closed air cavity 41 is naturally formed between the U-shaped conductive layer 40 and the bonding metal layer 30 due to the absence of the sacrificial layer 42, thus completing the construction of the electrostatic discharge channel.

[0145] Step S14 may be followed by the following steps: First, the insulating layer 50 on the top of each light-emitting unit 200 is cut open to form a through hole exposing the light-emitting unit 200.

[0146] Then, as shown in Figure 9, the insulating layer 50 is covered with a transparent conductive layer 60.

[0147] The transparent conductive layer 60 is disposed on top of the insulating layer 50, and is electrically connected to each light-emitting unit 200 through through holes.

[0148] For example, the thickness of the transparent conductive layer 60 is greater than or equal to 2000 angstroms.

[0149] Next, as shown in FIG9, a connecting electrode 70 is formed on the surface of the transparent conductive layer 60, and the connecting electrode 70 is located in the gap between each light-emitting unit 200.

[0150] Then, as shown in FIG4, a light-collecting structure 80 is formed on the side of the light-emitting functional layer 20 away from the driving substrate 10.

[0151] Among them, the light-collecting structure 80 corresponds one-to-one with the light-emitting unit 200, and the orthographic projection of the light-emitting unit 200 on the surface of the driving substrate 10 is located within the orthographic projection of the corresponding light-collecting cone on the surface of the driving substrate 10; the surface of the end of the light-collecting structure 80 away from the driving substrate 10 is an arc surface.

[0152] In this embodiment, the top surface of the light-collecting structure 80 is designed as an arc surface. As a basic optical element, the arc surface has the characteristic of converging light. The arc surface can apply an initial deflection to the emitted light of the light-emitting unit 200, so that the originally dispersed light is concentrated in a more favorable direction.

[0153] Alternatively, the light-collecting structure 80 can be made of PDMS, PMMA, or silicon dioxide.

[0154] Next, a cutting blade is used to cut the conductive layer 40 along the cutting area 13 to form multiple display panels as shown in Figures 1 and 2.

[0155] It should be noted that the conductive layer can also be fabricated before etching to form multiple light-emitting units, so that the conductive layer can play a role in protecting against electrostatic breakdown throughout the entire production process.

[0156] The above description is merely an optional embodiment of this disclosure and is not intended to limit this disclosure. The data therein represents only illustrative examples. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.

Claims

1. A display panel, characterized in that, The display panel includes: a driving substrate (10), a light-emitting functional layer (20), a bonding metal layer (30), and a conductive layer (40); the surface of the driving substrate (10) has a first region (11) and a second region (12), the bonding metal layer (30) is located on the surface of the driving substrate (10), the light-emitting functional layer (20) is located on the surface of the bonding metal layer (30), and the orthographic projection of the light-emitting functional layer (20) on the surface of the driving substrate (10) is located in the first region (11); the conductive layer (40) is located on the side of the bonding metal layer (30) away from the driving substrate (10), and the conductive layer (40) is insulated from the bonding metal layer (30), the orthographic projection of the conductive layer (40) on the surface of the driving substrate (10) is located in the second region (12), and there is a cavity (41) between the conductive layer (40) and the bonding metal layer (30).

2. The display panel according to claim 1, characterized in that, The display panel further includes an insulating layer (50) located on the surface of the bonding metal layer (30), and at least a portion of the insulating layer (50) having its orthographic projection onto the surface of the driving substrate (10) within the second region (12); the conductive layer (40) located on the surface of the insulating layer (50), and the conductive layer (40) having a groove on its surface near the driving substrate (10), the orthographic projection of the groove onto the surface of the driving substrate (10) being outside the orthographic projection of the insulating layer (50) onto the surface of the driving substrate (10), and the groove and the bonding metal layer (30) forming the cavity (41).

3. The display panel according to claim 1, characterized in that, The cavity (41) has a height greater than or equal to 1 μm in the direction perpendicular to the surface of the drive substrate (10).

4. The display panel according to any one of claims 1 to 3, characterized in that, The display panel includes multiple conductive layers (40), which are block-shaped and are arranged at intervals around the first region (11).

5. The display panel according to any one of claims 1 to 3, characterized in that, The conductive layer (40) includes a metal layer.

6. A panel product, characterized in that, The panel product includes: a driving substrate (10), a light-emitting functional layer (20), a bonding metal layer (30), and a conductive layer (40); the surface of the driving substrate (10) has a plurality of arrayed first regions (11) and cutting regions (13), the cutting regions (13) being the gaps between each of the first regions (11), and the bonding metal layer (30) being located between the first regions (11) and the cutting regions (13); the light-emitting functional layer (20) is located on the surface of the bonding metal layer (30), and the light-emitting functional layer (20) is adjacent to the first regions. (11) One-to-one correspondence, the orthographic projection of the light-emitting functional layer (20) on the board surface of the driving substrate (10) is located in the corresponding first region (11); the conductive layer (40) is located on the side of the bonding metal layer (30) away from the driving substrate (10), and the conductive layer (40) is insulated from the bonding metal layer (30), the orthographic projection of the conductive layer (40) on the board surface of the driving substrate (10) is located in the cutting area (13), and there is a cavity (41) between the conductive layer (40) and the bonding metal layer (30).

7. The panel article according to claim 6, characterized in that, The panel product further includes an insulating layer (50), which corresponds one-to-one with the light-emitting functional layer (20). The insulating layer (50) is located on the surface of the bonding metal layer (30) and covers the corresponding light-emitting functional layer (20). At least a portion of the insulating layer (50) extends to the cutting area (13). The insulating layers (50) on two adjacent light-emitting functional layers (20) are spaced apart in the cutting area (13). The conductive layer (40) is U-shaped, and the two ends of the conductive layer (40) are respectively connected to the surfaces of two adjacent insulating layers (50). The conductive layer (40) and the bonding metal layer (30) form the cavity (41).

8. The panel article according to claim 6, characterized in that, The cavity (41) has a height greater than or equal to 1 μm in the direction perpendicular to the surface of the drive substrate (10).

9. The panel article according to any one of claims 6 to 8, characterized in that, The product includes multiple conductive layers (40), which are block-shaped and are spaced apart along the extension direction of the cutting area (13).

10. A method for preparing a panel product, characterized in that, The fabrication method includes: forming an epitaxial layer (21) on a substrate (90); forming a bonding metal layer (30) between the epitaxial layer (21) and a driving substrate (10); bonding the epitaxial layer (21) to the driving substrate (10); and removing the substrate (90). The driving substrate (10) has a plurality of arrayed first regions (11) and cutting regions (13) on its surface. The cutting regions (13) are the gaps between each of the first regions (11). The bonding metal layer (30) is located between the first regions (11) and the cutting regions (13). The epitaxial layer (21) is patterned to form... Multiple light-emitting functional layers (20) are formed, each corresponding to one of the first regions (11). The orthographic projection of the light-emitting functional layer (20) on the surface of the driving substrate (10) is located within the corresponding first region (11). A conductive layer (40) is formed on the side of the bonding metal layer (30) away from the driving substrate (10). The conductive layer (40) is insulated from the bonding metal layer (30). The orthographic projection of the conductive layer (40) on the surface of the driving substrate (10) is located within the cutting area (13). A cavity (41) is formed between the conductive layer (40) and the bonding metal layer (30).

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