System for capacitor assembly of multi-level inverter for electric vehicle

Abstract

A system for a capacitor assembly of a multi-level inverter for an electric vehicle. The invention provides a system comprising an inverter for converting DC power from a battery to AC power to drive an electric machine, where the inverter comprises: a capacitor assembly comprising: a first set of capacitors connected to one or more power modules, wherein the first set of capacitors is used when the one or more power modules operate as a two-level inverter; and a second set of capacitors connected to the one or more power modules, where the second set of capacitors is used when the one or more power modules operate as a three-level inverter or as the two-level inverter.

Description

Technical Field

[0001] Various embodiments of this disclosure generally relate to a capacitor assembly, and more specifically to a system of capacitor assemblies for multilevel inverters in electric vehicles. Background Technology

[0002] Inverters (such as those used to drive motors in electric vehicles) are responsible for converting direct current (DC) to alternating current (AC) to drive the motor. Some inverters, operating at higher switching frequencies, may generate output voltages that include high levels of harmonics and relatively low efficiency.

[0003] This disclosure aims to overcome one or more of the aforementioned challenges. Summary of the Invention

[0004] In some respects, the technology described herein relates to a system including an inverter for converting DC power from a battery into AC power to drive a motor, wherein the inverter includes: a capacitor assembly including: a first bus; a second bus; a third bus between the first bus and the second bus; and one or more capacitors connected to one or more of the first bus, the second bus, or the third bus.

[0005] In some respects, the technology described herein relates to a system in which a first bus is a positive DC power bus, a second bus is a negative DC power bus, and a third bus is a neutral power bus.

[0006] In some respects, the technology described herein relates to a system in which the inverter is a multilevel inverter.

[0007] In some respects, the technology described herein relates to a system in which one or more capacitors include: a first capacitor connected to a first busbar and a third busbar; and a second capacitor connected to a second busbar and a third busbar.

[0008] In some respects, the technology described herein relates to a system in which a capacitor assembly further includes a housing in which a first capacitor and a second capacitor are disposed.

[0009] In some respects, the technology described herein relates to a system in which a first capacitor is arranged in a first row and a second capacitor is arranged in a second row.

[0010] In some respects, the technology described herein relates to a system in which the inverter further includes a power module connected to a capacitor assembly.

[0011] In some respects, the technology described herein relates to a system in which one or more capacitors are located on the same side of a first busbar, a second busbar, and a third busbar.

[0012] In some respects, the technology described herein relates to a system in which one or more capacitors include a spool having a longitudinal axis in the one or more capacitors, the longitudinal axis being parallel to the longitudinal axis of each of a first busbar, a second busbar, and a third busbar.

[0013] In some respects, the technology described herein relates to a system that further includes: a battery configured to supply DC power to an inverter; and a motor configured to receive AC power from the inverter to drive the motor, wherein the system is provided as a vehicle including the inverter, the battery, and the motor.

[0014] In some respects, the technology described herein relates to a system comprising a capacitor assembly including: a first busbar; a second busbar; a third busbar between the first busbar and the second busbar; and one or more capacitors connected to one or more of the first busbar, the second busbar, or the third busbar.

[0015] In some respects, the technology described herein relates to a system that further includes: a power module connected to a capacitor assembly.

[0016] In some respects, the technology described herein relates to a system in which a power module includes a first tab connected to a first busbar, a second tab connected to a second busbar, and a third tab connected to a third busbar.

[0017] In some respects, the technology described herein relates to a system in which one or more capacitors include: a first capacitor and a second capacitor connected to a first busbar and a third busbar; and a third capacitor and a fourth capacitor connected to a second busbar and a third busbar.

[0018] In some respects, the technology described herein relates to a system in which: a first busbar includes a first opening, a second busbar includes a second opening, and a third busbar includes a third opening, and one or more capacitors include a spool extending through the first opening, the second opening, and the third opening and connected to the first busbar.

[0019] In some respects, the technology described herein relates to a system in which: one or more capacitors include a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor; and each of the first capacitor, the second capacitor, the third capacitor, and the fourth capacitor is connected to a second busbar.

[0020] In some respects, the technology described herein relates to a system comprising a bus assembly for an inverter, the bus assembly including: a first bus; a second bus; and a third bus between the first bus and the second bus.

[0021] In some respects, the technology described herein relates to a system in which a first busbar includes one or more first openings, a second busbar includes one or more second openings, and a third busbar includes one or more third openings.

[0022] In some respects, the technology described herein relates to a system in which: a first busbar includes a first capacitor connector; a second busbar includes a second capacitor connector extending through one or more first openings and one or more second openings; and a third busbar includes a third capacitor connector extending through one or more first openings.

[0023] In some respects, the technology described herein relates to a system in which: a first bus is a positive DC power bus for an inverter; a second bus is a negative DC power bus for an inverter; and a third bus is a neutral power bus for an inverter.

[0024] In some aspects, the technology described herein relates to a system including an inverter for converting DC power from a battery into AC power to drive a motor, wherein the inverter includes: a capacitor assembly comprising: a first set of capacitors connected to one or more power modules, wherein the first set of capacitors is used when the one or more power modules operate as a two-level inverter; and a second set of capacitors connected to the one or more power modules, wherein the second set of capacitors is used when the one or more power modules operate as a three-level inverter or as a two-level inverter.

[0025] In some respects, the technology described herein relates to a system in which the inverter is a T-type multilevel inverter capable of operating as a two-level inverter and a three-level inverter.

[0026] In some respects, the technology described herein relates to a system in which a capacitor assembly further includes a housing in which a first set of capacitors and a second set of capacitors are disposed.

[0027] In some respects, the technology described herein relates to a system in which: a capacitor assembly further includes: a first busbar; a second busbar; and a third busbar between the first busbar and the second busbar, a first set of capacitors connected to the first busbar and the second busbar, and a second set of capacitors connected to the first busbar, the second busbar and the third busbar.

[0028] In some respects, the technology described herein relates to a system in which a first bus is a positive DC power bus, a second bus is a negative DC power bus, and a third bus is a neutral power bus.

[0029] In some respects, the technology described herein relates to a system in which a second set of capacitors includes: a first capacitor connected to a first busbar and a third busbar; and a second capacitor connected to a second busbar and a third busbar.

[0030] In some respects, the technology described herein relates to a system in which a first group of capacitors is arranged in a first row and a second group of capacitors is arranged in a second row.

[0031] In some respects, the technology described herein relates to a system in which a first group of capacitors and a second group of capacitors are arranged alternately in a single row.

[0032] In some respects, the technology described herein relates to a system in which the inverter further includes: one or more power modules connected to a capacitor assembly.

[0033] In some respects, the technology described herein relates to a system that further includes: a battery configured to supply DC power to an inverter; and a motor configured to receive AC power from the inverter to drive the motor, wherein the system is provided as a vehicle including the inverter, the battery, and the motor.

[0034] In some aspects, the technology described herein relates to a system comprising a capacitor assembly including: a first set of capacitors connected to one or more power modules, wherein the first set of capacitors is used when the one or more power modules operate as a two-level inverter; and a second set of capacitors connected to the one or more power modules, wherein the second set of capacitors is used when the one or more power modules operate as a three-level inverter or as a two-level inverter.

[0035] In some respects, the technology described herein relates to a system in which: a capacitor assembly further includes: a first busbar; a second busbar; and a third busbar between the first busbar and the second busbar, a first set of capacitors connected to the first busbar and the second busbar, and a second set of capacitors connected to the first busbar, the second busbar and the third busbar.

[0036] In some respects, the technology described herein relates to a system in which a first current path through a first busbar and a second busbar between one or more power modules and a first set of capacitors is shorter than a second current path through the first busbar, the second busbar, and a third busbar between one or more power modules and a second set of capacitors.

[0037] In some respects, the technology described herein relates to a system in which: a first set of capacitors is rated at a first voltage; a second set of capacitors is rated at a second voltage; and the first voltage is greater than the second voltage.

[0038] In some respects, the technology described herein relates to a system in which a first set of capacitors is arranged such that the positive terminal of the first capacitor in the first set of capacitors faces the negative terminal of the second capacitor in the first set of capacitors.

[0039] In some respects, the technology described herein relates to a system in which a second set of capacitors is arranged such that the positive or negative terminal of the first capacitor in the second set of capacitors faces the neutral terminal of the second capacitor in the second set of capacitors.

[0040] In some respects, the technology described herein relates to a system comprising a capacitor assembly for an inverter, the capacitor assembly comprising: a housing; a first set of capacitors in the housing for two-level operation of the inverter; and a second set of capacitors in the housing for three-level or two-level operation of the inverter.

[0041] In some respects, the technology described herein relates to a system in which: a capacitor assembly further includes a bus assembly comprising: a positive DC power bus; a negative DC power bus; and a neutral power bus between the positive DC power bus and the negative DC power bus; a first set of capacitors connected to the positive DC power bus and the negative DC power bus; and a second set of capacitors connected to the positive DC power bus, the negative DC power bus, and the neutral power bus.

[0042] In some respects, the technology described herein relates to a system in which a first set of capacitors and a second set of capacitors are arranged between the inner surface of a housing and a busbar assembly.

[0043] In some respects, the technology described herein relates to a system in which a first set of capacitors is arranged in a first row within a housing, and a second set of capacitors is arranged in a second row within a housing.

[0044] Further objects and advantages of the disclosed embodiments will be set forth in part in the description which follows, and will be apparent in part from the description, or may be learned by practice of the disclosed embodiments. The objects and advantages of the disclosed embodiments will be realized and achieved by means of the elements and combinations particularly pointed out in the appended claims.

[0045] It should be understood that the foregoing general description and the following detailed description are merely illustrative and explanatory, and do not limit the disclosed embodiments as claimed. Attached Figure Description

[0046] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate various exemplary embodiments and, together with the description, serve to explain the principles of the disclosed exemplary embodiments.

[0047] Figure 1 An exemplary system infrastructure for a vehicle comprising a combination of inverters and converters, according to one or more embodiments, is described.

[0048] Figure 2 A schematic diagram of the electrical power of a three-phase inverter module according to one or more embodiments is depicted.

[0049] Figure 3 An exemplary system infrastructure for an inverter controller according to one or more embodiments is described.

[0050] Figure 4A An isometric view of a capacitor assembly according to one or more embodiments is depicted.

[0051] Figure 4B Depicting according to one or more embodiments Figure 4A Side view of the capacitor assembly.

[0052] Figure 4C Depicting according to one or more embodiments Figure 4A An exploded view of the capacitor assembly.

[0053] Figure 5 A complete three-level capacitor assembly including a row of wires is described according to one or more embodiments.

[0054] Figure 6 A hybrid capacitor assembly with a + / N / - spool terminal configuration for three-level functionality in a second row is depicted according to one or more embodiments.

[0055] Figure 7 A hybrid capacitor assembly with N / + / N / - spool terminals configured for three-level functionality in a second row is depicted according to one or more embodiments.

[0056] Figure 8 A hybrid capacitor assembly having a single-row configuration and a three-axis configuration per phase is described according to one or more embodiments.

[0057] Figure 9 A hybrid capacitor assembly having a triaxial configuration for all phases is depicted according to one or more embodiments.

[0058] Figure 10 A complete three-level capacitor assembly with a two-row bobbin configuration is depicted according to one or more embodiments. Detailed Implementation

[0059] Both the foregoing general description and the following detailed description are exemplary and interpretive only, and do not limit the claimed features. As used herein, the terms “comprises,” “comprising,” “has,” “having,” “includes,” “including,” or other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed or inherent to such process, method, article, or apparatus. In this disclosure, unless otherwise stated, relative terms (such as, for example, “about,” “substantially,” and “approximately”) are used to indicate possible ±10% variation in the stated values. In this disclosure, unless otherwise stated, any numerical value may include possible ±10% variation in the stated values.

[0060] The terminology used below may be interpreted in its broadest and most reasonable manner, although it is used in conjunction with a detailed description of certain specific instances of this disclosure. In fact, certain terms may even be emphasized below; however, any term intended to be interpreted in any constrained manner will be explicitly and specifically defined as such in this Detailed Description section. For example, in the context of this disclosure, a switching device may be described as a switching element or device, but may refer to any device used to control the flow of power in a circuit. For example, a switching element may be, for example, a metal-oxide-semiconductor field-effect transistor (MOSFET), a bipolar junction transistor (BJT), an insulated-gate bipolar transistor (IGBT), or a relay, or any combination thereof, but is not limited thereto.

[0061] Various embodiments of this disclosure generally relate to a capacitor assembly, and more specifically to a system of capacitor assemblies for multilevel inverters in electric vehicles. Inverters (such as those used to drive motors in electric vehicles) are responsible for, for example, converting direct current (DC) to alternating current (AC) to drive the motor. In some systems, two-level inverters have a simple structure and relatively low manufacturing cost. However, some two-level inverters may produce output voltages including high harmonic levels and relatively low efficiency at higher switching frequencies.

[0062] Some systems include three-level inverter topologies, which address the problems of two-level inverters, such as harmonics in the output voltage at higher switching frequencies and relatively lower efficiency. Some systems include multilevel inverter topologies, which generate output voltage waveforms with lower harmonics to better simulate sinusoidal references, achieving lower dv / dt and lower electromagnetic interference (EMI) emissions. Some systems may include T-type topologies of three-level inverters, which are suitable topologies among multilevel inverters due to their three-level output voltage capability and fewer switching devices.

[0063] In some systems, the traction inverter may include a power module, which can be considered an important part of the overall system. The efficiency of some systems is directly proportional to the losses occurring in the power module. In some systems, addressing the switching losses of the power module may be a key aspect of designing an efficient, cost-effective, and robust inverter. In some systems, the commutator inductance may limit improvements in switching losses. In some systems, the three main components affecting the overall commutator inductance may include the power module, the large DC capacitors, and the bus interconnects.

[0064] In one or more embodiments, the capacitor may be used for three-level inverter functionality. In one or more embodiments, a single capacitor may replace two capacitors (e.g., C1 and C2) in a multi-level inverter configuration with a single solution for three-level functionality, which can facilitate lower parasitic inductance by integrating the two capacitors (e.g., C1 and C2) into a single large-capacity capacitor. In one or more embodiments, the large-capacity capacitor may include a planar bus configuration for connecting the capacitor.

[0065] In one or more embodiments, a single hybrid solution capacitor may allow for two-level and / or three-level inverter functionality, replacing three capacitors (e.g., C1, C2, and C3) in a T-type multilevel inverter. In one or more embodiments, the single hybrid solution capacitor may include both two-level and / or three-level functionality, which can facilitate lower parasitic inductance by integrating three capacitors (e.g., C1, C2, and C3) into a single large-capacity capacitor. In one or more embodiments, the large-capacity capacitor may include a planar bus configuration for connecting the capacitor.

[0066] In some systems, integrating multiple independent capacitors (e.g., two or more capacitors) can be a technical challenge. In some systems, conductor (e.g., cable) wiring and / or the connection of multiple capacitors can result in relatively high inductance. In some systems, the combination of axial capacitor structures with common (or most common) Y-bus connections can lead to a wider gap between the positive and negative DC power buses of parallel capacitors connecting large-capacity capacitors. This can result in relatively high parasitic inductance in large-capacity capacitors.

[0067] One or more embodiments may include integrating two capacitors (e.g., C1 and C2) into a single capacitor assembly. One or more embodiments may include arranging capacitors connected to a combination of three planar buses (e.g., a positive DC power bus, a negative DC power bus, and a neutral power bus) within a single large DC capacitor to achieve a planar bus arrangement for three-level functionality, which may result in a reduction of parasitic inductance.

[0068] One or more embodiments may include a three-plane bus arrangement in a large-capacity capacitor, which allows the capacitor to be connected to a positive power bus, a negative power bus, and a neutral power bus, facilitating a three-level functional configuration. In one or more embodiments, the capacitor may be arranged to achieve full three-level functionality. In one or more embodiments, the capacitor may have different configurations based on manufacturing constraints and / or design and the current paths provided. One or more embodiments may include one or more rows of capacitors.

[0069] One or more embodiments may provide solutions for three-level DC link capacitors (or large-capacity capacitors). One or more embodiments may provide DC link capacitors that can be manufactured using the same (or similar) processes as those used to manufacture some two-level capacitors, which may be beneficial for manufacturing purposes. One or more embodiments may include DC link capacitors that can be flexible and scalable for different voltage levels, capacitance values, and inverter stages.

[0070] One or more embodiments may provide DC link capacitors that can be combined with power switches to produce relatively low parasitic inductance, which can enable higher (or relatively higher) switching speeds in the complete commutation loop. One or more embodiments may combine two capacitors (e.g., C1 and C2) into a single large DC capacitor using less space than would be used to house two separate capacitors, which can result in simplified bus wiring and reduced parasitic inductance.

[0071] One or more embodiments may include three-level capacitor functionality within a single large-capacity capacitor assembly. One or more embodiments may include a capacitor arrangement for achieving three-level functionality while taking into account shorter current paths and potential mechanical constraints provided by the manufacturer. One or more embodiments may include a planar bus arrangement for a three-level inverter with connections to large-capacity capacitors.

[0072] One or more embodiments may include integrating three capacitors (e.g., C1, C2, and C3) into a single capacitor assembly. One or more embodiments may include arranging capacitors connected to a combination of three planar buses (e.g., a positive DC power bus, a negative DC power bus, and a neutral power bus) within a single large DC capacitor. This enables a planar bus arrangement that allows for two-level functionality (or two-level operation) and / or three-level functionality (or three-level operation), which can result in a reduction in parasitic inductance.

[0073] One or more embodiments may include large-capacity capacitors having a first row of capacitors and / or a second row of capacitors. One or more embodiments may include a three-plane bus arrangement that allows capacitors in the first and / or second rows to connect to a positive power bus, a negative power bus, and a neutral power bus, which may facilitate different two-level and / or three-level functional configurations. One or more embodiments may include capacitor configurations that allow the integration of capacitors with different voltage ratings. For example, the first row of capacitors may address two-level functionality and may include high-voltage rated capacitors; and the second row of capacitors may address three-level functionality and may include capacitors with different voltage ratings than the first row.

[0074] In one or more embodiments, the capacitors in the first row may be arranged in order to cover two-level functions (e.g., + / -; + / -; + / -), and the capacitors in the second row may be arranged in different configurations based on manufacturing constraints and current path constraints, but the embodiments are not limited thereto. For example, one or more embodiments may include a single-row capacitor configuration configured to cover the same functions as the two-row capacitor configuration. The configurations of the three-level inverters disclosed above are not limited to the embodiments disclosed herein. For example, the configurations of the three-level inverters disclosed above may be applied to N-level inverters. For example, one or more embodiments may include hybrid capacitor configurations including several different current paths disclosed herein.

[0075] One or more embodiments may include solutions for DC link capacitors (or large-capacity DC capacitors) for two-level and / or three-level multilevel inverters (MLI). One or more embodiments may provide DC link capacitors (or large-capacity DC capacitors) that can be manufactured using the same (or similar) processes used to manufacture some two-level capacitors, which may be advantageous for manufacturing purposes. One or more embodiments may include DC link capacitors (or large-capacity DC capacitors) that can be flexible and scalable for different voltage levels, capacitance values, and inverter stages.

[0076] One or more embodiments may provide a DC link capacitor (or a large DC capacitor) that can be combined with power switches, which can produce relatively low parasitic inductance, enabling higher (or relatively high) switching speeds throughout the complete commutation loop. One or more embodiments may combine two-level and / or three-level functions in a single large DC capacitor using a small (or relatively small) space, which reduces parasitic inductance and achieves electromagnetic compatibility (EMC) compliance with minimal (or reduced) effort.

[0077] One or more embodiments may include two-level and / or three-level capacitor functionality in a single large-capacity capacitor assembly. One or more embodiments may include capacitor arrangements for achieving two-level and / or three-level functionality while taking into account (or including) shorter current paths and potential mechanical constraints provided by the manufacturer. One or more embodiments may include planar bus arrangements for multilevel inverters with large-capacity capacitor connections.

[0078] Figure 1 Exemplary system infrastructure for a vehicle including a combined inverter and converter, according to one or more embodiments, is depicted. Alternatively, the inverter may be an inverter without a converter. Within the context of this disclosure, both an inverter without a converter and a combined inverter and converter can be referred to as an inverter. Figure 1As shown, the electric vehicle 100 may include an inverter 110, a motor 190, and a battery 195. The inverter 110 may include components for receiving electrical power from an external source and outputting electrical power to charge the battery 195 of the electric vehicle 100. For example, the inverter 110 may convert DC power from the battery 195 in the electric vehicle 100 into AC power to drive the motor 190 of the electric vehicle 100 (e.g., to rotate it), but the embodiments are not limited thereto. For example, the inverter 110 may be bidirectional and may convert DC power to AC power or vice versa, such as during regenerative braking. The inverter 110 may be a three-phase inverter, a single-phase inverter, or a multi-phase inverter.

[0079] Figure 2 A power schematic diagram of a three-phase inverter module according to one or more embodiments is depicted. The power schematic diagram 200 may correspond to the internal configuration of inverter 110. The power schematic diagram 200 may include a first capacitor 201, a second capacitor 202, a third capacitor 203, and switches 211, 212, 213, 214, 215, 216, 217, 218, 219, 220, 221, and 222. Although... Figure 2 Not depicted, but inverter 110 can be connected to battery 195 and motor 190. Battery 195 can be any power supply device, and motor 190 can be any load. First stage A can be associated with ΦA, including switches 211, 212, 213, 214, and neutral power terminal N; second stage B can be associated with ΦB, including switches 215, 216, 217, 218, and neutral power terminal N; and third stage C can be associated with ΦC, including switches 219, 220, 221, 222, and neutral power terminal N. Switches 211-222 can be, for example, MOSFETs, IGBTs, silicon carbide (SiC) transistors, and / or gallium nitride (GaN) transistors, but embodiments are not limited thereto. Switches 211-222 can each include multiple dies, but embodiments are not limited thereto. Although... Figure 2 The switch is described as a single switch, but each switch can be one or more switches.

[0080] Switches 211-222 can be controlled by inverter controller 300 (e.g., Figure 3 The PWM signal generated (as shown in the diagram) drives the output terminals A, B, and C to transmit signals via the output terminal group ( Figure 2 DC power (not depicted in the text) is converted via the output terminal group ( Figure 2 (Not depicted in the text) Three-phase AC power is delivered to motor 190. Additionally, although... Figure 1and Figure 2 A three-phase inverter is shown, but this disclosure is not limited thereto and may include single-phase or multi-phase inverters.

[0081] Figure 3 An exemplary system infrastructure for an inverter controller according to one or more embodiments is depicted. The inverter controller 300 may include a set of instructions that can be executed to cause the inverter controller 300 to perform any one or more of the methods or computer-based functions disclosed herein. The inverter controller 300 may operate as a standalone device or may be connected to other computer systems or peripheral devices, for example, via a network.

[0082] In networked deployments, the inverter controller 300 can operate as a server, or as a client in a server-client user network environment, or as a peer-to-peer (or distributed) computer system in a peer-to-peer (or distributed) network environment. The inverter controller 300 can also be implemented as or integrated into various devices, such as personal computers (PCs), tablet PCs, set-top boxes (STBs), personal digital assistants (PDAs), mobile devices, handheld computers, laptop computers, desktop computers, communication equipment, cordless phones, landline phones, control systems, cameras, scanners, fax machines, printers, pagers, personal trusted devices, network devices, network routers, switches or bridges, or any other machine capable of executing a set of instructions (sequentially or otherwise) specifying the actions to be taken by that machine. In a particular implementation, the inverter controller 300 may be implemented using electronic devices that provide voice, video, or data communication. Furthermore, while the inverter controller 300 is presented as a single system, the term "system" should also be understood to include any collection of systems or subsystems that individually or jointly execute one or more sets of instructions to perform one or more computer functions.

[0083] like Figure 3 As depicted, the inverter controller 300 may include a processor 302, such as a central processing unit (CPU), a graphics processing unit (GPU), or both. The processor 302 can be a component in a variety of systems. For example, the processor 302 may be part of a standard inverter. The processor 302 may be one or more general-purpose processors, digital signal processors, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), servers, networks, digital circuits, analog circuits, combinations thereof, or other devices now known or later developed for analyzing and processing data. The processor 302 may implement software programs, such as manually generated (i.e., programmed) code.

[0084] Inverter controller 300 may include memory 304 communicatable via bus 308. Memory 304 may be main memory, static memory, or dynamic memory. Memory 304 may include, but is not limited to, computer-readable storage media, such as various types of volatile and non-volatile storage media, including but not limited to random access memory, read-only memory, programmable read-only memory, electrically programmable read-only memory, electrically erasable read-only memory, flash memory, magnetic tape or disk, optical media, etc. In one embodiment, memory 304 includes a cache or random access memory for processor 302. In alternative embodiments, memory 304 is decoupled from processor 302, such as processor cache memory, system memory, or other memory. Memory 304 may be an external storage device or database for storing data. Examples include hard disk drives, optical discs (“CDs”), digital video discs (“DVDs”), memory cards, memory sticks, floppy disks, universal serial bus (“USB”) storage devices, or any other device operable for storing data. Memory 304 is operable to store instructions executable by processor 302. The functions, actions, or tasks shown in the figures or described herein can be performed by processor 302, which executes instructions stored in memory 304. These functions, actions, or tasks are independent of a specific type of instruction set, storage medium, processor, or processing strategy, and can be performed by software, hardware, integrated circuits, firmware, microcode, etc., operating individually or in combination. Similarly, processing strategies may include multiprocessing, multitasking, parallel processing, etc.

[0085] As depicted, the inverter controller 300 may further include a display 310, such as a liquid crystal display (LCD), an organic light-emitting diode (OLED), a flat panel display, a solid-state display, a cathode ray tube (CRT), a projector, a printer, or other display device now known or later developed for outputting defined information. The display 310 may serve as an interface for a user to view the operation of the processor 302, or specifically as an interface with software stored in the memory 304 or the drive unit 306.

[0086] Alternatively or concurrently, the inverter controller 300 may include an output device 312 configured to allow a user to interact with any component of the inverter controller 300. The output device 312 may be a numeric keypad, keyboard, or cursor control device (such as a mouse or joystick), touchscreen display, remote control, or any other device operable to interact with the inverter controller 300.

[0087] The inverter controller 300 may also, or alternatively, include a drive unit 306 implemented as a disk or optical disc drive. The drive unit 306 may include a computer-readable medium 322 in which instructions 324 (e.g., one or more sets of instructions) (e.g., software) may be embedded. Further, the instructions 324 may embody one or more of the methods or logic described herein. The instructions 324 may reside wholly or partially within memory 304 and / or processor 302 during execution by the inverter controller 300. Memory 304 and processor 302 may also include the computer-readable medium described above.

[0088] In some systems, computer-readable medium 322 includes instructions 324 or receives and executes instructions 324 in response to a propagated signal, enabling devices connected to network 370 to transmit voice, video, audio, images, or any other data via network 370. Furthermore, instructions 324 may be transmitted or received via communication port or interface 320 through network 370 and / or using bus 308. Communication port or interface 320 may be part of processor 302 or may be a separate component. Communication port or interface 320 may be formed in software or may be a physical connector in hardware. Communication port or interface 320 may be configured to connect to network 370, external media, display 310, or any other component in inverter controller 300, or a combination thereof. Connection to network 370 may be a physical connection (such as a wired Ethernet connection) or may be established wirelessly, as described below. Similarly, additional connections to other components of inverter controller 300 may be physical connections or may be established wirelessly. Network 370 may alternatively be directly connected to bus 308.

[0089] Although computer-readable medium 322 is shown as a single medium, the term "computer-readable medium" can include a single medium or multiple media (such as a centralized or distributed database and / or associated caches and servers) storing one or more sets of instructions. The term "computer-readable medium" can also include any medium capable of storing, encoding, or carrying a set of instructions for execution by a processor or causing a computer system to perform any one or more of the methods or operations disclosed herein. Computer-readable medium 322 can be non-transitory and can be tangible.

[0090] Computer-readable medium 322 may include solid-state memory, such as a memory card, or other package housing one or more non-volatile read-only memories. Computer-readable medium 322 may be random access memory or other volatile rewritable memory. Alternatively or additionally, computer-readable medium 322 may include magneto-optical or optical media, such as magnetic disks or magnetic tapes, or other storage devices for capturing carrier signals (such as signals transmitted via a transmission medium). Digital file attachments to emails or other self-contained information archives or archive sets can be considered as distribution media as tangible storage media. Therefore, this disclosure is to be construed as including any one or more computer-readable media or distribution media in which data or instructions can be stored, as well as other equivalents and successor media.

[0091] In alternative embodiments, specialized hardware implementations (such as application-specific integrated circuits, programmable logic arrays, and other hardware devices) may be configured to implement one or more of the methods described herein. Applications that may include various implementations of the apparatus and systems can broadly encompass a wide range of electronic and computer systems. One or more implementations described herein may use two or more specific interconnected hardware modules or devices having associated control and data signals that can be transferred between or through modules, or as part of an application-specific integrated circuit, to implement functionality. Therefore, this system encompasses software, firmware, and hardware implementations.

[0092] Inverter controller 300 can be connected to network 370. Network 370 may define one or more networks, including wired or wireless networks. Wireless networks may be cellular telephone networks, 802.11, 802.16, 802.20, or WiMAX networks. Further, such networks may include public networks (such as the Internet), private networks (such as intranets), or combinations thereof, and may utilize a variety of networking protocols now available or developed later, including but not limited to TCP / IP-based networking protocols. Network 370 may include wide area networks (WANs) (such as the Internet), local area networks (LANs), campus area networks, metropolitan area networks, direct connections (such as via a universal serial bus (USB) port), or any other network that allows data communication. Network 370 may be configured to couple one computing device to another to enable data communication between the devices. Typically, network 370 may be able to use any form of machine-readable medium to transfer information from one device to another. Network 370 may include communication methods through which its information can travel between computing devices. Network 370 may be divided into subnetworks. A subnet may allow access to all other components in other components connected to it, or a subnet may restrict access between components. Network 370 may be considered a public or private network connection and may include, for example, a virtual private network or encryption or other security mechanisms employed on the public Internet.

[0093] According to various embodiments of this disclosure, the methods described herein can be implemented by software programs executable by a computer system. Further, in exemplary non-limiting embodiments, the implementation may include distributed processing, component or object distributed processing, and parallel processing. Alternatively, virtual computer system processing may be configured to implement one or more of the methods or functionalities described herein.

[0094] Although this specification describes components and functions that may be implemented in specific implementations with reference to particular standards and protocols, this disclosure is not limited to such standards and protocols. For example, standards for transmission over the Internet and other packet-switched networks (e.g., TCP / IP, UDP / IP, HTML, HTTP) represent examples of prior art. Such standards are periodically superseded by faster or more efficient equivalents with substantially the same functionality. Therefore, alternative standards and protocols with the same or similar functionality as those disclosed herein are considered their equivalents.

[0095] It will be understood that, in one embodiment, the operation of the method in question is performed by a suitable processor (or processors) of a processing (i.e., computer) system that executes instructions (computer-readable code) stored in a storage device. It will also be understood that this disclosure is not limited to any particular specific implementation or programming technique, and that any suitable technique used to implement the functionality described herein may be used to implement this disclosure. This disclosure is not limited to any particular programming language or operating system.

[0096] Figure 4A An isometric view of a capacitor assembly according to one or more embodiments is depicted. The capacitor assembly 400 may include a bus assembly 405, which includes a positive DC power bus 401, a negative DC power bus 402, and a neutral power bus 403 (in...). Figure 4C (described in more detail below); and a plurality of spools 470, including a first row of spools 471 and a second row of spools 472. In the context of this disclosure, the term spool may refer to the entirety of a capacitor or a portion of a capacitor (e.g., the winding of electrodes and dielectric), but embodiments are not limited thereto. The positive DC power bus 401 may include a positive input terminal 410, which can be connected to a battery 195 ( Figure 4A (Not depicted in the image). The negative DC power bus 402 may include a negative input terminal 412, which can be connected to the battery 195 ( Figure 4A (Not depicted in the text). Figure 4AThe embodiments depicted enable a planar arrangement of the bus assembly 405, which allows for integrated two-level and / or three-level functionality and a reduction in parasitic inductance in the capacitor assembly 400. For example, the first bobbin 471 may include a first set of bobbins configured to implement two-level functionality (or operation) of the inverter 110, and the second bobbin 472 may include a second set of bobbins configured to implement three-level functionality (or operation) of the inverter 110, but the embodiments are not limited thereto.

[0097] The positive DC power bus 401 may further include terminals for connection to a power module. The negative DC power bus 402 may include terminals 416, 418, and 420, which can be configured to connect to a power module. Figure 4A (Not depicted in the image). The neutral power bus 403 may include terminals 415, 417, and 419, which can be configured to connect to a power module (not shown in the image). Figure 4A (Not depicted in the text). For example, one or more power modules ( Figure 4A (Not depicted) may each include one or more tabs connected to the positive DC power bus 401, the negative DC power bus 402, and the neutral power bus 403. The positive DC power bus 401, the negative DC power bus 402, and the neutral power bus 403 may be configured to connect one or more of the plurality of spools 470 to one or more power modules ( Figure 4A (Not depicted in the text).

[0098] like Figure 4A As depicted, the positive DC power bus 401, the negative DC power bus 402, and the neutral power bus 403 may each include one or more openings (e.g., see [reference]). Figure 4C For example, the positive DC power bus 401 may include one or more first openings 431, the negative DC power bus 402 may include one or more second openings 432, and the neutral power bus 403 may include one or more third openings 433, but the embodiment is not limited thereto. Each of the plurality of spools 470 may include a spool 475 (e.g., see...). Figure 4C The spool is configured to extend through one or more of these openings in the positive DC power bus 401, the negative DC power bus 402, and / or the neutral power bus 403, but the embodiment is not limited thereto.

[0099] Figure 4B Depicting according to one or more embodiments Figure 4AA side view of the capacitor assembly. The capacitor assembly 400 may include a plurality of spools 470 arranged as a first row of spools 471 and a second row of spools 472, but the embodiment is not limited thereto. For example, the plurality of spools 470 may include two or more spools arranged in one or more rows. The bus assembly 405 may be arranged to have a neutral bus 403 between a positive DC power bus 401 and a negative DC power bus 402. For example, the positive DC power bus 401 may be arranged on top of the neutral bus 403, and the negative DC power bus 402 may be arranged below the neutral bus 403, but the embodiment is not limited thereto, and the bus assembly 405 may be arranged in a different order. The bus assembly 405 may be composed of a dielectric layer ( Figure 4B (Not depicted in the text) Covering, so that the individual buses in bus assembly 405 are electrically insulated from each other when arranged as a stack of planar buses (e.g. Figure 4B (As depicted in the text).

[0100] Bus assembly 405 may be arranged to allow multiple spools 470 to connect to positive DC power bus 401, negative DC power bus 402, and neutral power bus 403 to facilitate two-level and / or three-level functional configurations, but embodiments are not limited thereto. The multiple spools 470 may be arranged to provide full three-level functionality; however, each of the multiple spools 470 may have different configurations based on manufacturing constraints and / or current paths. A first row of spools 471 may be configured to address two-level functionality and may include high-voltage rated capacitors (and / or spools), and a second row of spools 472 may be configured to address three-level functionality and may include different voltage-rated capacitors (and / or spools). For example, the spools in the first row of spools 471 may be arranged (e.g., + / -, + / -, etc.) to provide two-level functionality, and the spools in the second row of spools 472 may include different configurations based on manufacturing constraints and / or current paths.

[0101] Figure 4C Depicting according to one or more embodiments Figure 4A An exploded view of the capacitor assembly. The capacitor assembly 400 may include a housing 406 (or enclosure) having an inner surface, wherein the positive DC power bus 401, the negative DC power bus 402, and the neutral power bus 403 are arranged as a stack of planar buses. Figure 4CAs depicted, the positive DC power bus may be arranged on (or on top of) the neutral power bus 403, the neutral power bus 403 may be arranged below (or beneath) the positive DC power bus 401 and on (or on top of) the negative DC power bus 402, and the negative DC power bus 402 may be arranged below (or beneath) the neutral power bus 403 and on (or on top of) a plurality of spools 470, but the embodiment is not limited thereto, and the arrangement order of the buses and / or capacitors (and / or spools) may be different. Each of the plurality of spools 470 may include a spool 475 having a longitudinal axis in one or more capacitors (and / or spools), the longitudinal axis of which may be parallel to the longitudinal axis of each of the positive DC power bus 401, the negative DC power bus 402, and the neutral power bus 403, but the embodiment is not limited thereto.

[0102] The positive DC power bus 401 may include one or more capacitor connectors 441 for connection to one or more spools of the plurality of spools 470, the negative DC power bus 402 may include one or more capacitor connectors 442 for connection to one or more spools of the plurality of spools 470, and / or the neutral power bus 403 may include one or more capacitor connectors 443 for connection to one or more spools of the plurality of spools 470. One or more capacitor connectors 442 may extend through one or more first openings 431 and one or more second openings 432. One or more capacitor connectors 443 may extend through one or more first openings 431.

[0103] Figure 5 A complete three-level capacitor assembly including a spool is depicted according to one or more embodiments. The capacitor assembly 500 may correspond to an internal configuration of an inverter 110. The capacitor assembly 500 may include a first spool 571, a first power module 505, a second power module 510, and a third power module 515. The first spool 571 may include a first spool 520, a second spool 525, a third spool 530, and a fourth spool 535. The first spool 520 may include a positive tab 521 and a neutral tab 522. The second spool 525 may include a negative tab 526 and a neutral tab 527. The third spool 530 may include a positive tab 531 and a neutral tab 532. The fourth spool 535 may include a negative tab 536 and a neutral tab 537. The first power module 505 may include a first positive tab 506, a first neutral tab 507, a first negative tab 508, and a first output tab 509. The second power module 510 may include a second positive electrode 511, a second neutral electrode 512, a second negative electrode 513, and a second output electrode 514. The third power module 515 may include a third positive electrode 516, a third neutral electrode 517, a third negative electrode 518, and a third output electrode 519.

[0104] The first spool 520, the second spool 525, the third spool 530, and the fourth spool 535 may each be configured to provide three-level functionality, but the embodiments are not limited thereto. The first power module 505, the second power module 510, and the third power module 515 may be general-purpose multilevel inverter (MLI) power modules with three special leads (or tabs), but the embodiments are not limited thereto.

[0105] like Figure 5 As depicted, the capacitor assembly 500 can be configured to have different current paths between the tabs in the first power module 505, the second power module 510, and the third power module 515, and between the tabs in a set of spools in the first cable spool 571. These different current paths can flow through one or more of the positive DC power bus 401, the negative DC power bus 402, and / or the neutral power bus 403. For example, current can flow from the first positive electrode 506 to the positive electrode 521, current can flow from the neutral electrode 522 to the first neutral electrode 507, current can flow from the first neutral electrode 507 to the neutral electrode 527, current can flow from the negative electrode 526 to the first negative electrode 508, current can flow from the negative electrode 526 to the second negative electrode 513, current can flow from the second positive electrode 511 to the positive electrode 531, current can flow from the second neutral electrode 512 to the neutral electrode 527, and current can flow from... Current flows from neutral tab 532 to second neutral tab 512, current can flow from third positive tab 516 to positive tab 531, current can flow from neutral tab 532 to third neutral tab 517, current can flow from third neutral tab 517 to neutral tab 537, and current can flow from negative tab 536 to third negative tab 518. However, the embodiment is not limited to this, and the capacitor assembly 500 may be configured to have current paths flowing along different paths between the power module and the capacitor (and / or spool).

[0106] Figure 6A hybrid capacitor assembly with + / N / - spool terminals for three-level functionality in a second row is depicted according to one or more embodiments. The hybrid capacitor assembly 600 may correspond to an internal configuration of an inverter 110. The hybrid capacitor assembly 600 may include a first spool 671, a second spool 672, a first power module 605, a second power module 610, and a third power module 615. The first spool 671 may include a first spool 620, a second spool 625, a third spool 630, and a fourth spool 635. The second spool 672 may include a fifth spool 640, a sixth spool 645, a seventh spool 650, and an eighth spool 655. The first spool 620 may include a positive tab 621 and a negative tab 622. The second spool 625 may include a positive tab 626 and a negative tab 627. The third spool 630 may include a positive tab 631 and a negative tab 632. The fourth spool may include a positive tab 636 and a negative tab 637. The fifth spool 640 may include a positive tab 641 and a neutral tab 642. The sixth spool 645 may include a negative tab 646 and a neutral tab 647. The seventh spool 650 may include a positive tab 651 and a neutral tab 652. The eighth spool 655 may include a negative tab 656 and a neutral tab 657. The first power module 605 may include a first positive tab 606, a first neutral tab 607, a first negative tab 608, and a first output tab 609. The second power module 610 may include a second positive tab 611, a second neutral tab 612, a second negative tab 613, and a second output tab 614. The third power module 615 may include a third positive tab 616, a third neutral tab 617, a third negative tab 618, and a third output tab 619.

[0107] The first spool 620, second spool 625, third spool 630, and fourth spool 635 may be a first group of capacitors (and / or spools) configured to provide a two-level function and having a voltage rating of approximately 800V-1000V, but embodiments are not limited thereto. The fifth spool 640, sixth spool 645, seventh spool 650, and eighth spool 655 may be a second group of capacitors (and / or spools) configured to provide a three-level function and having a voltage rating of approximately 500V, but embodiments are not limited thereto. Figure 6 As depicted, the first spool 671 may be closer to the first power module 605, the second power module 610, and the third power module 615 than the second spool 672, such that the current flowing between the first power module 605, the second power module 610, and / or the third power module 615 and one or more spools of the first spool 671 is shorter than the current flowing between the first power module 605, the second power module 610, and / or the third power module 615 and one or more spools of the second spool 672.

[0108] like Figure 6 As depicted, the spools in the first spool 671 can be arranged such that the positive electrode tabs (or positive electrode connectors) and negative electrode tabs (or negative electrode connectors) of different corresponding spools in the first spool 671 face each other, but the embodiments are not limited thereto. Similarly, as... Figure 6 As depicted, the spools in the second spool 672 can be arranged such that the positive and / or negative tabs of different corresponding spools in the second spool 672 face the neutral tabs (or neutral connectors) of other spools in the second spool 772, but the embodiments are not limited thereto. The first power module 605, the second power module 610, and the third power module 615 can be general-purpose multilevel inverter (MLI) power modules with three special leads (or tabs), but the embodiments are not limited thereto.

[0109] like Figure 6 As depicted, the hybrid capacitor assembly 600 can be configured to have different current paths flowing between the tabs in the first power module 605, the second power module 610, and the third power module 615, and between the tabs in a set of spools in the first spool 671 and a set of spools in the second spool 672. These different current paths can flow through one or more of the positive DC power bus 401, the negative DC power bus 402, and / or the neutral power bus 403. The current flow between the power modules and the capacitors (and / or spools) can depend on the two-level or three-level configuration of the hybrid capacitor assembly 600.

[0110] For example, in a three-level function, current can flow from the first positive tab 606 to the positive tab 641, current can flow from the neutral tab 642 to the first neutral tab 607, current can flow from the first neutral tab 607 to the neutral tab 647, current can flow from the negative tab 646 to the first negative tab 608, current can flow from the negative tab 646 to the second negative tab 613, current can flow from the second positive tab 611 to the positive tab 651, and current can flow from the second neutral tab 612 to the neutral tab 647. Current can flow from neutral tab 652 to second neutral tab 612, current can flow from third positive tab 616 to positive tab 651, current can flow from neutral tab 652 to third neutral tab 617, current can flow from neutral tab 652 to third neutral tab 617, and current can flow from negative tab 656 to third negative tab 618, but the embodiments are not limited thereto, and the hybrid capacitor assembly 600 can be configured to have current paths flowing along different paths between the power module and the capacitor (and / or spool).

[0111] For example, in a two-level function, current can flow from the first positive tab 606 to the positive tab 621, current can flow from the negative tab 622 to the first negative tab 608, current can flow from the second positive tab 611 to the positive tab 626, current can flow from the negative tab 632 to the second negative tab 613, current can flow from the third positive tab 616 to the positive tab 636, and current can flow from the negative tab 637 to the third negative tab 618. However, the embodiments are not limited to this, and the hybrid capacitor assembly 600 can be configured to have current paths flowing along different paths between the power module and the capacitor (and / or spool).

[0112] Figure 7 A hybrid capacitor assembly 700 is depicted according to one or more embodiments, having N / + / N / - spool terminals configured for three-level functionality in a second row. The hybrid capacitor assembly 700 may correspond to an internal configuration of an inverter 110. The hybrid capacitor assembly 700 may include a first spool 771, a second spool 772, a first power module 705, a second power module 710, and a third power module 715. The first spool 771 may include a first spool 720, a second spool 725, a third spool 730, and a fourth spool 735. The second spool 772 may include a fifth spool 740, a sixth spool 745, a seventh spool 750, and an eighth spool 755. The first spool 720 may include a positive tab 721 and a negative tab 722. The second spool 725 may include a positive tab 726 and a negative tab 727. The third spool 730 may include a positive tab 731 and a negative tab 732. The fourth spool 735 may include a positive tab 736 and a negative tab 737. The fifth spool 740 may include a neutral tab 741 and a positive tab 742. The sixth spool 745 may include a neutral tab 746 and a negative tab 747. The seventh spool 750 may include a neutral tab 751 and a positive tab 752. The eighth spool 755 may include a neutral tab 756 and a negative tab 757. The first power module 705 may include a first positive tab 706, a first neutral tab 707, a first negative tab 708, and a first output tab 709. The second power module 710 may include a second positive tab 711, a second neutral tab 712, a second negative tab 713, and a second output tab 714. The third power module 715 may include a third positive tab 716, a third neutral tab 717, a third negative tab 718, and a third output tab 719.

[0113] The first spool 720, second spool 725, third spool 730, and fourth spool 735 may be a first group of capacitors (and / or spools) configured to provide a two-level function and having a voltage rating of approximately 800V-1000V, but embodiments are not limited thereto. The fifth spool 740, sixth spool 745, seventh spool 750, and eighth spool 755 may be a second group of capacitors (and / or spools) configured to provide a three-level function and having a voltage rating of approximately 500V, but embodiments are not limited thereto. Figure 7 As depicted, the first spool 771 may be closer to the first power module 705, the second power module 710, and the third power module 715 than the second spool 772, such that the current flowing between the first power module 705, the second power module 710, and / or the third power module 715 and one or more spools of the first spool 771 is shorter than the current flowing between the first power module 705, the second power module 710, and / or the third power module 715 and one or more spools of the second spool 772.

[0114] like Figure 7 As depicted, the spools in the first spool 771 can be arranged such that the positive electrode tabs (or positive electrode connectors) and negative electrode tabs (or negative electrode connectors) of different corresponding spools in the first spool 771 face each other, but the embodiments are not limited thereto. Similarly, as... Figure 7 As depicted, the spools in the second spool 772 can be arranged such that the positive and / or negative tabs of different corresponding spools in the second spool 772 face the neutral tabs (or neutral connectors) of other spools in the second spool 772, but the embodiments are not limited thereto. The hybrid capacitor assembly 700 may be similar to the hybrid capacitor assembly 600, except that the polarity of the tabs on the spools in the second spool 772 may be relative to... Figure 6 The spools in the second row of spools 672 are reversed. The first power module 705, the second power module 710, and the third power module 715 can be general-purpose multilevel inverter (MLI) power modules with three special leads (or tabs), but the embodiments are not limited thereto.

[0115] like Figure 7 As depicted, the hybrid capacitor assembly 700 can be configured to have different current paths flowing between the tabs in the first power module 705, the second power module 710, and the third power module 715, and between the tabs in a set of spools in the first spool 771 and a set of spools in the second spool 772. The different current paths can flow through one or more of the positive DC power bus 401, the negative DC power bus 402, and / or the neutral power bus 403. The current flow between the power modules and the capacitors (and / or spools) can depend on the two-level or three-level configuration of the hybrid capacitor assembly 700.

[0116] For example, in a three-level function, current can flow from the first positive tab 706 to the positive tab 742, current can flow from the neutral tab 741 to the first neutral tab 707, current can flow from the first neutral tab 707 to the neutral tab 746, current can flow from the negative tab 747 to the first negative tab 708, current can flow from the negative tab 747 to the second negative tab 713, current can flow from the second positive tab 711 to the positive tab 752, current can flow from the second neutral tab 712 to the neutral tab 746, and current can flow from the negative tab 747. Current can flow from the neutral tab 751 to the second neutral tab 712 at the second negative tab 713, from the third positive tab 716 to the positive tab 752, from the neutral tab 751 to the third neutral tab 717, from the third neutral tab 717 to the neutral tab 756, and from the negative tab 757 to the third negative tab 718. However, the embodiments are not limited to this, and the hybrid capacitor assembly 700 can be configured to have current paths flowing along different paths between the power module and the capacitor (and / or spool).

[0117] For example, in a two-level function, current can flow from the first positive tab 706 to the positive tab 721, current can flow from the negative tab 722 to the first negative tab 708, current can flow from the second positive tab 711 to the positive tab 726, current can flow from the negative tab 732 to the second negative tab 713, current can flow from the third positive tab 716 to the positive tab 736, and current can flow from the negative tab 737 to the third negative tab 718. However, the embodiments are not limited to this, and the hybrid capacitor assembly 700 can be configured to have current paths flowing along different paths between the power module and the capacitor (and / or spool).

[0118] Figure 8A hybrid capacitor assembly with a single-row configuration and a three-column-per-phase configuration is depicted according to one or more embodiments. The hybrid capacitor assembly 800 may correspond to an internal configuration of an inverter 110. The hybrid capacitor assembly 800 may include a first spool 871, a first power module 805, a second power module 810, and a third power module 815. The first spool 871 may include a first spool 820, a second spool 825, a third spool 830, a fourth spool 835, a fifth spool 840, a sixth spool 845, and a seventh spool 850. The first spool 820 may include a neutral tab 821 and a positive tab 822. The second spool 825 may include a negative tab 826 and a positive tab 827. The third spool 830 may include a negative tab 831 and a neutral tab 832. The fourth spool 835 may include a negative tab 836 and a positive tab 837. The fifth spool 840 may include a neutral tab 841 and a positive tab 842. The sixth spool 845 may include a negative tab 846 and a positive tab 847. The seventh spool 850 may include a negative tab 851 and a neutral tab 852. The first power module 805 may include a first positive tab 806, a first neutral tab 807, a first negative tab 808, and a first output tab 809. The second power module 810 may include a second positive tab 811, a second neutral tab 812, a second negative tab 813, and a second output tab 814. The third power module 815 may include a third positive tab 816, a third neutral tab 817, a third negative tab 818, and a third output tab 819.

[0119] The second spool 825, fourth spool 835, and sixth spool 845 may be a first group of capacitors (and / or spools) configured to provide two-level functionality and having a voltage rating of approximately 800V-1000V, but embodiments are not limited thereto. The first spool 820, third spool 830, fifth spool 840, and seventh spool 850 may be a second group of capacitors (and / or spools) configured to provide three-level functionality and having a voltage rating of approximately 800V-1000V, but embodiments are not limited thereto. For example, a first group of spools including the second spool 825, fourth spool 835, and sixth spool 845, and a second group of spools including the first spool 820, third spool 830, fifth spool 840, and seventh spool 850 may be alternately arranged in a single row (e.g., the first row of spools 871), but embodiments are not limited thereto. The first power module 805, the second power module 810, and the third power module 815 can be general-purpose multilevel inverter (MLI) power modules with three special leads (or tabs), but the embodiments are not limited thereto.

[0120] like Figure 8As depicted, the hybrid capacitor assembly 800 can be configured to have different current paths flowing between the tabs in the first power module 805, the second power module 810, and the third power module 815, and between the tabs in a set of spools in the first cable spool 871. The different current paths can flow through one or more of the positive DC power bus 401, the negative DC power bus 402, and / or the neutral power bus 403. The current flow between the power modules and the capacitors (and / or spools) can depend on the two-level or three-level configuration of the hybrid capacitor assembly 800.

[0121] For example, in a three-level function, current can flow from the first positive tab 806 to the positive tab 822, current can flow from the neutral tab 821 to the first neutral tab 807, current can flow from the first neutral tab 807 to the neutral tab 832, current can flow from the negative tab 831 to the first negative tab 808, current can flow from the negative tab 831 to the second negative tab 813, current can flow from the second positive tab 811 to the positive tab 842, and current can flow from the second neutral tab 812 to the neutral tab 832. Current can flow from neutral tab 841 to second neutral tab 812, current can flow from neutral tab 841 to third positive tab 816, current can flow from third positive tab 816 to positive tab 842, current can flow from third neutral tab 817 to neutral tab 852, and current can flow from negative tab 851 to third negative tab 818. However, the embodiments are not limited to this, and the hybrid capacitor assembly 800 can be configured to have current paths flowing along different paths between the power module and the capacitor (and / or spool).

[0122] For example, in a two-level function, current can flow from the first positive tab 806 to the positive tab 827, current can flow from the negative tab 826 to the first negative tab 808, current can flow from the second positive tab 811 to the positive tab 837, current can flow from the negative tab 836 to the second negative tab 813, current can flow from the third positive tab 816 to the positive tab 847, and current can flow from the negative tab 846 to the third negative tab 818. However, the embodiments are not limited to this, and the hybrid capacitor assembly 800 can be configured to have current paths flowing along different paths between the power module and the capacitor (and / or spool).

[0123] Figure 9A hybrid capacitor assembly having a three-axis configuration for all phases is depicted according to one or more embodiments. The hybrid capacitor assembly 900 may correspond to an internal configuration of an inverter 110. The hybrid capacitor assembly 900 may include a first spool 971, a first power module 905, a second power module 910, and a third power module 915. The first spool 971 may include a first spool 920, a second spool 925, and a third spool 930. The first spool 920 may include a neutral tab 921 and a positive tab 922. The second spool 925 may include a negative tab 926 and a positive tab 927. The third spool 930 may include a negative tab 931 and a neutral tab 932. The first power module 905 may include a first positive tab 906, a first neutral tab 907, a first negative tab 908, and a first output tab 909. The second power module 910 may include a second positive electrode 911, a second neutral electrode 912, a second negative electrode 913, and a second output electrode 914. The third power module 915 may include a third positive electrode 916, a third neutral electrode 917, a third negative electrode 918, and a third output electrode 919.

[0124] The second spool 925 may be configured to provide two-level functionality and have a voltage rating of approximately 800V-1000V, but embodiments are not limited thereto. The first spool 920 and the third spool 830 may each be configured to provide three-level functionality and have a voltage rating of approximately 800V-1000V, but embodiments are not limited thereto. The first power module 905, the second power module 910, and the third power module 915 may be general-purpose multilevel inverter (MLI) power modules with three special leads (or tabs), but embodiments are not limited thereto.

[0125] like Figure 9 As depicted, the hybrid capacitor assembly 900 can be configured to have different current paths flowing between the tabs in the first power module 905, the second power module 910, and the third power module 915, and between the tabs in a set of spools in the first cable spool 971. The different current paths can flow through one or more of the positive DC power bus 401, the negative DC power bus 402, and / or the neutral power bus 403. The current flow between the power modules and the capacitors (and / or spools) can depend on the two-level or three-level configuration of the hybrid capacitor assembly 900.

[0126] For example, in a three-level function, current can flow from neutral tab 921 to the first neutral tab 907, current can flow from the first positive tab 906 to the positive tab 922, current can flow from the first neutral tab 907 to the neutral tab 932, current can flow from the negative tab 931 to the first negative tab 908, current can flow from neutral tab 921 to the second neutral tab 912, current can flow from the second positive tab 911 to the positive tab 922, and current can flow from the second neutral tab 912 to the neutral tab 932. Current can flow from negative electrode 931 to third negative electrode 918, current can flow from neutral electrode 921 to third neutral electrode 917, current can flow from third positive electrode 916 to positive electrode 922, current can flow from negative electrode 931 to third negative electrode 918, and current can flow from third neutral electrode 917 to neutral electrode 932. However, the embodiments are not limited to this, and the hybrid capacitor assembly 900 can be configured to have current paths flowing along different paths between the power module and the capacitor (and / or spool).

[0127] For example, in a two-level function, current can flow from negative tab 926 to first negative tab 908, current can flow from negative tab 926 to second negative tab 913, current can flow from negative tab 926 to third negative tab 918, current can flow from first positive tab 906 to positive tab 927, current can flow from second positive tab 911 to positive tab 927, and current can flow from third positive tab 916 to positive tab 927. However, the embodiments are not limited to this, and the hybrid capacitor assembly 900 can be configured to have current paths flowing along different paths between the power module and the capacitor (and / or spool).

[0128] Figure 10A complete three-level capacitor assembly with a two-row spool configuration is depicted according to one or more embodiments. The capacitor assembly 1000 may correspond to an internal configuration of an inverter 110. The capacitor assembly 1000 may include a first spool 1071, a second spool 1072, a first power module 1005, a second power module 1010, and a third power module 1015. The first spool 1071 may include a first spool 1020, a second spool 1025, a third spool 1030, and a fourth spool 1035. The second spool 1072 may include a fifth spool 1040, a sixth spool 1045, a seventh spool 1050, and an eighth spool 1055. The first spool 1020 and the fifth spool 1040 may include a positive electrode tab 1021 and a neutral electrode tab 1022. The second spool 1025 and the sixth spool 1045 may include a negative electrode tab 1026 and a neutral electrode tab 1027. The third spool 1030 and the seventh spool 1050 may include a positive electrode tab 1031 and a neutral electrode tab 1032. The fourth spool 1035 and the eighth spool 1055 may include a negative electrode tab 1036 and a neutral electrode tab 1037. The first power module 1005 may include a first positive electrode tab 1006, a first neutral electrode tab 1007, a first negative electrode tab 1008, and a first output electrode tab 1009. The second power module 1010 may include a second positive electrode tab 1011, a second neutral electrode tab 1012, a second negative electrode tab 1013, and a second output electrode tab 1014. The third power module 1015 may include a third positive electrode tab 1016, a third neutral electrode tab 1017, a third negative electrode tab 1018, and a third output electrode tab 1019.

[0129] The spools in the first spool 1071 and the second spool 1072 may be configured to provide three-level functionality, but the embodiments are not limited thereto. The first power module 1005, the second power module 1010, and the third power module 1015 may be general-purpose multilevel inverter (MLI) power modules with three special leads (or tabs), but the embodiments are not limited thereto.

[0130] like Figure 10 As depicted, the capacitor assembly 1000 can be configured to have different current paths flowing between the tabs in the first power module 1005, the second power module 1010, and the third power module 1015, and between the tabs in a set of spools in the first spool 1071 and a set of spools in the second spool 1072. These different current paths can flow through one or more of the positive DC power bus 401, the negative DC power bus 402, and / or the neutral power bus 403. The current flow between the power modules and the capacitors (and / or spools) can depend on the three-level configuration of the capacitor assembly 1000.

[0131] For example, in a three-level function, current can flow from the first positive tab 1006 to the positive tab 1021, current can flow from the neutral tab 1022 to the first neutral tab 1007, current can flow from the first neutral tab 1007 to the neutral tab 1027, current can flow from the negative tab 1026 to the first negative tab 1008, current can flow from the negative tab 1026 to the second negative tab 1013, current can flow from the second positive tab 1011 to the positive tab 1031, and current can flow from the second neutral tab 1012 to the neutral tab 1027. Current can flow from neutral tab 1032 to second neutral tab 1012, current can flow from third positive tab 1016 to positive tab 1031, current can flow from neutral tab 1032 to third neutral tab 1017, current can flow from negative tab 1036 to third negative tab 1018, and current can flow from third neutral tab 1017 to neutral tab 1037. However, the embodiment is not limited to this, and the capacitor assembly 1000 can be configured to have current paths flowing along different paths between the power module and the capacitor (and / or spool).

[0132] In one or more embodiments, the capacitor may be used for three-level inverter functionality. In one or more embodiments, a single capacitor may replace two capacitors (e.g., C1 and C2) in a multi-level inverter configuration with a single solution for three-level functionality, which can facilitate lower parasitic inductance by integrating the two capacitors (e.g., C1 and C2) into a single large-capacity capacitor. In one or more embodiments, the large-capacity capacitor may include a planar bus configuration for connecting the capacitor.

[0133] In one or more embodiments, a single hybrid solution capacitor may allow for two-level and / or three-level inverter functionality, replacing three capacitors (e.g., C1, C2, and C3) in a T-configuration multilevel inverter. In one or more embodiments, the single hybrid solution capacitor may include both two-level and / or three-level functionality, which can facilitate lower parasitic inductance by integrating three capacitors (e.g., C1, C2, and C3) into a single large-capacity capacitor. In one or more embodiments, the large-capacity capacitor may include a planar bus configuration for connecting the capacitor.

[0134] One or more embodiments may include integrating two capacitors (e.g., C1 and C2) into a single capacitor assembly. One or more embodiments may include arranging capacitors connected to a combination of three planar buses (e.g., a positive DC power bus, a negative DC power bus, and a neutral power bus) within a single large DC capacitor to achieve a planar bus arrangement for three-level functionality, which may result in a reduction of parasitic inductance.

[0135] One or more embodiments may include a three-plane bus arrangement in a large-capacity capacitor, which allows the capacitor to be connected to a positive power bus, a negative power bus, and a neutral power bus, facilitating a three-level functional configuration. In one or more embodiments, the capacitor may be arranged to achieve full three-level functionality. In one or more embodiments, the capacitor may have different configurations based on manufacturing constraints and / or design and the current paths provided. One or more embodiments may include one or more rows of capacitors.

[0136] One or more embodiments may provide solutions for three-level DC link capacitors (or large-capacity capacitors). One or more embodiments may provide DC link capacitors that can be manufactured using the same (or similar) processes as those used to manufacture some two-level capacitors, which may be beneficial for manufacturing purposes. One or more embodiments may include DC link capacitors that can be flexible and scalable for different voltage levels, capacitance values, and inverter stages.

[0137] One or more embodiments may provide DC link capacitors that can be combined with power switches to produce relatively low parasitic inductance, which can enable higher (or relatively higher) switching speeds in the complete commutation loop. One or more embodiments may combine two capacitors (e.g., C1 and C2) into a single large DC capacitor using less space than would be used to house two separate capacitors, which can result in simplified bus wiring and reduced parasitic inductance.

[0138] One or more embodiments may include three-level capacitor functionality within a single large-capacity capacitor assembly. One or more embodiments may include a capacitor arrangement for achieving three-level functionality while taking into account shorter current paths and potential mechanical constraints provided by the manufacturer. One or more embodiments may include a planar bus arrangement for a three-level inverter with connections to large-capacity capacitors.

[0139] One or more embodiments may include integrating three capacitors (e.g., C1, C2, and C3) into a single capacitor assembly. One or more embodiments may include arranging capacitors connected to a combination of three planar buses (e.g., a positive DC power bus, a negative DC power bus, and a neutral power bus) within a single large-capacity DC capacitor. This enables a planar bus arrangement that allows for two-level and / or three-level functionality, resulting in a reduction in parasitic inductance.

[0140] One or more embodiments may include large-capacity capacitors having a first row of capacitors and / or a second row of capacitors. One or more embodiments may include a three-plane bus arrangement that allows capacitors in the first and / or second rows to be connected to a positive power bus, a negative power bus, and a neutral power bus, which may facilitate different two-level and / or three-level functional configurations. One or more embodiments may include capacitor configurations that allow the integration of capacitors with different voltage ratings depending on the functionality that can be addressed. For example, the first row of capacitors may address a two-level function and may include high-voltage rated capacitors; and the second row of capacitors may address a three-level function and may include capacitors with different voltage ratings.

[0141] In one or more embodiments, the capacitors in the first row may be arranged in order to cover two-level functions (e.g., + / -; + / -; + / -), and the capacitors in the second row may be arranged in different configurations based on manufacturing constraints and current path constraints, but the embodiments are not limited thereto. For example, one or more embodiments may include a single-row capacitor configuration configured to cover the same functions as the two-row capacitor configuration. The configurations of the three-level inverters disclosed above are not limited to the embodiments disclosed herein. For example, the configurations of the three-level inverters disclosed above may be applied to N-level inverters. For example, one or more embodiments may include hybrid capacitor configurations including several different current paths disclosed herein.

[0142] One or more embodiments may include solutions for DC link capacitors (or large-capacity DC capacitors) for two-level and / or three-level multilevel inverters (MLI). One or more embodiments may provide DC link capacitors (or large-capacity DC capacitors) that can be manufactured using the same (or similar) processes used to manufacture some two-level capacitors, which may be advantageous for manufacturing purposes. One or more embodiments may include DC link capacitors (or large-capacity DC capacitors) that can be flexible and scalable for different voltage levels, capacitance values, and inverter stages.

[0143] One or more embodiments may provide a DC link capacitor (or a large DC capacitor) that can be combined with power switches, which can produce relatively low parasitic inductance, enabling higher (or relatively high) switching speeds throughout the complete commutation loop. One or more embodiments may combine two-level and / or three-level functions in a single large DC capacitor using a small (or relatively small) space, which reduces parasitic inductance and achieves electromagnetic compatibility (EMC) compliance with minimal (or reduced) effort.

[0144] One or more embodiments may include two-level and / or three-level capacitor functionality in a single large-capacity capacitor assembly. One or more embodiments may include capacitor arrangements for achieving two-level and / or three-level functionality while taking into account (or including) shorter current paths and potential mechanical constraints provided by the manufacturer. One or more embodiments may include planar bus arrangements for multilevel inverters with large-capacity capacitor connections.

[0145] Other embodiments of this disclosure will become apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. The specification and examples are intended to be illustrative only, and the true scope and spirit of the invention are indicated by the appended claims.

Claims

1. A system comprising an inverter for converting DC power from a battery into AC power to drive a motor, wherein the inverter comprises: Capacitor assembly, the capacitor assembly comprising: A first set of capacitors is connected to one or more power modules, wherein the first set of capacitors is used when the one or more power modules operate as a two-level inverter; and A second set of capacitors is connected to the one or more power modules, wherein the second set of capacitors is used when the one or more power modules operate as a three-level inverter or as a two-level inverter.

2. The system according to claim 1, wherein the inverter is a T-type multilevel inverter capable of operating as both a two-level inverter and a three-level inverter.

3. The system of claim 1, wherein the capacitor assembly further includes a housing, wherein the first set of capacitors and the second set of capacitors are disposed in the housing.

4. The system according to claim 1, wherein: The capacitor assembly further includes: First busbar; Second busbar; and A third busbar, located between the first busbar and the second busbar. The first group of capacitors is connected to the first busbar and the second busbar, and The second group of capacitors is connected to the first bus, the second bus, and the third bus.

5. The system according to claim 4, wherein the first bus is a positive DC power bus, the second bus is a negative DC power bus, and the third bus is a neutral power bus.

6. The system of claim 4, wherein the second set of capacitors comprises: A first capacitor is connected to the first busbar and the third busbar; as well as The second capacitor is connected to the second bus and the third bus.

7. The system of claim 1, wherein the first group of capacitors is arranged in a first row and the second group of capacitors is arranged in a second row.

8. The system of claim 1, wherein the first group of capacitors and the second group of capacitors are alternately arranged in a single row.

9. The system of claim 1, wherein the inverter further comprises: The one or more power modules are connected to the capacitor assembly.

10. The system according to claim 1, further comprising: The battery is configured to supply the DC power to the inverter; as well as The motor is configured to receive AC power from the inverter to drive the motor. The system is provided as a vehicle comprising the inverter, the battery, and the motor.

11. A system comprising a capacitor assembly, the capacitor assembly including: A first set of capacitors is connected to one or more power modules, wherein the first set of capacitors is used when the one or more power modules operate as a two-level inverter. as well as A second set of capacitors is connected to the one or more power modules, wherein the second set of capacitors is used when the one or more power modules operate as a three-level inverter or as a two-level inverter.

12. The system according to claim 11, wherein: The capacitor assembly further includes: First busbar; Second busbar; and A third busbar, located between the first busbar and the second busbar. The first group of capacitors is connected to the first busbar and the second busbar, and The second group of capacitors is connected to the first bus, the second bus, and the third bus.

13. The system of claim 12, wherein the first current path through the first bus and the second bus between the one or more power modules and the first set of capacitors is shorter than the second current path through the first bus, the second bus and the third bus between the one or more power modules and the second set of capacitors.

14. The system according to claim 11, wherein: The first group of capacitors is rated at a first voltage; The second group of capacitors is rated for the second voltage; and The first voltage is greater than the second voltage.

15. The system of claim 11, wherein the first set of capacitors is arranged such that the positive terminal of the first capacitor in the first set of capacitors faces the negative terminal of the second capacitor in the first set of capacitors.

16. The system of claim 11, wherein the second set of capacitors is arranged such that the positive or negative terminal connection of the first capacitor in the second set of capacitors faces the neutral terminal connection of the second capacitor in the second set of capacitors.

17. A system comprising a capacitor assembly for an inverter, the capacitor assembly comprising: case; The first set of capacitors, located in the housing, is used for two-level operation of the inverter; as well as The second set of capacitors, located in the housing, is used for three-level or two-level operation of the inverter.

18. The system according to claim 17, wherein: The capacitor assembly further includes a bus assembly, the bus assembly comprising: Positive DC power bus; Negative DC power bus; and A neutral power bus, located between the positive DC power bus and the negative DC power bus. The first set of capacitors is connected to the positive DC power bus and the negative DC power bus, and The second group of capacitors is connected to the positive DC power bus, the negative DC power bus, and the neutral power bus.

19. The system of claim 18, wherein the first set of capacitors and the second set of capacitors are arranged between the inner surface of the housing and the busbar assembly.

20. The system of claim 17, wherein the first set of capacitors is arranged in a first row in the housing, and the second set of capacitors is arranged in a second row in the housing.

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