Laterally diffused metal oxide semiconductor device and preparation method thereof
By incorporating a ramp-shaped field plate and dielectric structure into the LDMOS device, the problem of device performance degradation is solved, achieving uniform electric field distribution and improved reliability. This reduces the drain-end electric field strength and impact ionization, thereby enhancing the device's breakdown voltage performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- CSMC TECH FAB2 CO LTD
- Filing Date
- 2024-11-20
- Publication Date
- 2026-05-22
AI Technical Summary
Existing LDMOS devices are prone to performance degradation when using ramped field plates, affecting device reliability. Furthermore, common improvement methods increase costs or lead to insufficient bottom voltage withstand at the drain terminal.
A first trench and a second trench are formed on the front side of a semiconductor substrate. The body region is located at the bottom of the first trench, the drift region is located on the side of the second trench close to the first trench, and the drain region is located on the side of the second trench away from the first trench. A first dielectric structure with a slope is formed in the first trench, and a second dielectric structure is formed in the second trench, forming a slope-shaped field plate. The second dielectric structure is introduced to alleviate electric field concentration.
This achieves a uniform electric field distribution in the drift region, increases the breakdown voltage, reduces the drain electric field and collisional ionization, improves the performance degradation caused by the hot carrier effect, enhances device reliability, and avoids increasing manufacturing costs.
Smart Images
Figure CN122073828A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of integrated circuit technology, and in particular to a laterally diffused metal-oxide-semiconductor device and its fabrication method. Background Technology
[0002] With the continuous development of semiconductor technology, the application of lateral double-diffuse metal-oxide semiconductor (LDMOS) devices is becoming increasingly widespread, while higher requirements are being placed on the performance of lateral double-diffuse metal-oxide semiconductor devices.
[0003] The key to LDMOS devices is achieving high voltage and low on-resistance. To improve the breakdown voltage, the drift region length needs to be increased and the drift region concentration reduced; however, this also increases the on-resistance. To improve the breakdown voltage and alleviate the trade-off between breakdown voltage and on-resistance, a field plate is typically introduced to optimize the surface electric field. Furthermore, since the electric field increases from the source to the drain, the ideal field plate structure is a ramp-shaped field plate, with the dielectric layer thickness beneath the ramp-shaped field plate increasing progressively. However, current LDMOS devices using ramp-shaped field plates are prone to performance degradation, affecting device reliability. Summary of the Invention
[0004] Therefore, it is necessary to provide a laterally diffused metal-oxide semiconductor device and its fabrication method to address the above problems.
[0005] To achieve the above objectives, in a first aspect, this application provides a laterally diffused metal-oxide-semiconductor device, comprising:
[0006] A semiconductor substrate has a first trench and a second trench spaced apart on its front side; the semiconductor substrate has a drift region, a body region, a source region and a drain region; the body region is located at the bottom of the first trench, and the source region is located within the body region; the drift region is located on the side of the body region closer to the second trench; the drain region is located within the drift region and on the side of the second trench opposite to the first trench.
[0007] A first dielectric structure is disposed within the first trench and located between the body region and the second trench; the first dielectric structure has a slope portion on the side away from the second trench, and the thickness of the slope portion gradually decreases from the second trench to the body region;
[0008] A second dielectric structure is disposed within the second trench;
[0009] The field plate structure, at least a portion of which is disposed on the slope portion;
[0010] The gate is disposed on the bottom wall of the first trench.
[0011] In one embodiment, the depth of the first trench is equal to the depth of the second trench;
[0012] The maximum thickness of the first dielectric structure is equal to the thickness of the second dielectric structure.
[0013] In one embodiment, the second groove is disposed on one side of the first groove along the first direction;
[0014] The second trench includes a plurality of sub-trenches spaced apart along the second direction, and the second dielectric structure includes a plurality of sub-dielectric parts, with one sub-dielectric part correspondingly disposed in each of the sub-trenches;
[0015] The first direction and the second direction intersect, and both the first direction and the second direction are perpendicular to the thickness direction of the semiconductor substrate.
[0016] In one embodiment, a plurality of second trenches are provided between the first trench and the drain region; the plurality of second trenches are arranged sequentially at intervals along a direction away from the first trench; and a second dielectric structure is correspondingly provided in each second trench.
[0017] In one embodiment, the second trench is disposed on one side of the first trench along a first direction; the first direction is perpendicular to the thickness direction of the semiconductor substrate;
[0018] From the front side of the semiconductor substrate to the back side of the semiconductor substrate, the width of the second trench and the width of the second dielectric structure gradually decrease; the width of the second trench is the dimension of the second trench along the first direction, and the width of the second dielectric structure is the dimension of the second dielectric structure along the first direction.
[0019] In one embodiment, the material of the first dielectric structure includes silicon oxide;
[0020] And / or, the material of the second dielectric structure includes silicon oxide.
[0021] In one embodiment, the slope includes a bottom surface and a slope surface connected to the bottom surface; the bottom surface contacts a portion of the bottom wall of the first trench, and at least a portion of the field plate structure is disposed on the slope surface;
[0022] The angle between the slope and the bottom surface is between 15° and 20°.
[0023] In one embodiment, the gate and the field plate structure are connected and are an integral structure;
[0024] Alternatively, the gate and the field plate structure may be a separate structure.
[0025] Secondly, embodiments of this application provide a method for fabricating a laterally diffused metal-oxide-semiconductor device.
[0026] include:
[0027] Provide semiconductor substrates;
[0028] A drift region is formed within the semiconductor substrate, and a first trench and a second trench are formed at intervals on the front side of the semiconductor substrate;
[0029] A first dielectric structure is formed in the first trench, and a second dielectric structure is formed in the second trench;
[0030] A body region, a source region, a drain region, a field plate structure, and a gate are formed; the body region, the source region, and the drain region are all located within the semiconductor substrate; the body region is located at the bottom of the first trench, and the source region is located within the body region; the drift region is located on the side of the body region closer to the second trench; the drain region is located within the drift region and on the side of the second trench opposite to the first trench; a first dielectric structure is located between the body region and the second trench; the first dielectric structure has a ramp portion on the side opposite to the second trench, and the thickness of the ramp portion gradually decreases from the second trench to the body region; at least a portion of the field plate structure is disposed on the ramp portion; the gate is disposed on the bottom wall of the first trench.
[0031] In one embodiment, forming a first dielectric structure in the first trench and forming a second dielectric structure in the second trench includes:
[0032] An initial dielectric structure is formed in the first trench, and a second dielectric structure is formed in the second trench;
[0033] A patterned mask layer is formed on the semiconductor substrate;
[0034] The initial dielectric structure is etched to form the first dielectric structure having a ramp portion.
[0035] The laterally diffused metal-oxide-semiconductor device and its fabrication method provided in this application involve forming a first trench and a second trench on the front side of a semiconductor substrate. A body region is positioned at the bottom of the first trench, a drift region is positioned on the side of the body region near the second trench, and a drain region is positioned on the side of the second trench away from the first trench. Simultaneously, a first dielectric structure with a ramp is formed within the first trench, and a second dielectric structure is formed within the second trench. In this way, on one hand, the field plate structure located on the ramp can form a ramp-shaped field plate. Under the action of the ramp-shaped field plate and the ramp, the electric field in the drift region can be uniformly distributed, improving the breakdown voltage of the device. On the other hand, after introducing the second dielectric structure, the corner of the bottom of the second trench can become a new electric field concentration region, thereby alleviating the electric field intensity at the corner of the bottom of the first trench (i.e., the corner of the first dielectric structure), thus reducing the drain electric field and impact ionization, improving the device performance degradation caused by the hot carrier effect, and enhancing the reliability of the device. Attached Figure Description
[0036] To more clearly illustrate the technical solutions in the embodiments or exemplary embodiments of this application, the drawings used in the description of the embodiments or exemplary embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0037] Figure 1 This is a schematic diagram of the structure of a laterally diffused metal-oxide-semiconductor device provided in one embodiment of this application.
[0038] Figure 2 for Figure 1 This is a top view of a laterally diffused metal-oxide-semiconductor device.
[0039] Figure 3 This is a schematic diagram of another laterally diffused metal-oxide-semiconductor device provided in one embodiment of this application.
[0040] Figure 4 for Figure 1 Another top view of the laterally diffused metal-oxide-semiconductor device shown.
[0041] Figure 5 This is a schematic diagram of the structure of another laterally diffused metal-oxide-semiconductor device provided in one embodiment of this application.
[0042] Figure 6 This is a schematic flowchart of a method for fabricating a laterally diffused metal-oxide-semiconductor device provided in one embodiment of this application.
[0043] Figure 7 for Figure 6 A schematic diagram of a process for preparing S300 is shown.
[0044] Figures 8-10 for Figure 6 A schematic diagram of the cross-sectional structure of the device during the fabrication process shown.
[0045] Explanation of reference numerals in the attached figures:
[0046] 1. Laterally diffused metal-oxide-semiconductor device; 10. Semiconductor substrate; 11. First trench; 12. Second trench; 121. Sub-trench; 21. Drift region; 22. Body region; 23. Source region; 24. Drain region; 30. First dielectric structure; 31. Ramp portion; 311. Bottom surface; 312. Slope surface; 32. Flat portion; 40. Second dielectric structure; 41. Sub-dielectric portion; 50. Field plate structure; 60. Gate; 2. First film layer; 3. Second film layer; 4. Pattern mask layer; 5. Initial dielectric structure. Detailed Implementation
[0047] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.
[0048] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
[0049] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this application, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.
[0050] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.
[0051] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.
[0052] Embodiments of the application are described herein with reference to cross-sectional views illustrating ideal embodiments (and intermediate structures), thus allowing for the expectation of variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the application should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For instance, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device and do not limit the scope of the application.
[0053] With the continuous development of semiconductor technology, the application of lateral double-diffuse metal-oxide semiconductor (LDMOS) devices is becoming increasingly widespread, while higher requirements are being placed on the performance of lateral double-diffuse metal-oxide semiconductor devices.
[0054] In related LDMOS devices, shallow trench isolation technology is combined with field plate technology. The shallow trench isolation structure is configured as a ramp shape, with the field plate covering the ramp-shaped shallow trench isolation structure. However, in the high gate voltage (Vgs) and high drain voltage (Vds) conduction state, the shallow trench isolation structure near the drain corner experiences collisional ionization and a high electric field intensity, which easily leads to hot carrier effects and performance degradation, affecting device reliability. Common improvement methods are as follows: First, adding a doped strip under the drift region can improve degradation performance, increase breakdown voltage, and reduce on-resistance; second, adding a buffer layer in the drain region reduces the concentration gradient between the drift and drain regions, thereby reducing the drain electric field and improving reliability. However, on the one hand, the above methods require additional photomasks, leading to increased costs; on the other hand, introducing a buffer layer in the drain region increases the overall concentration near the drain, resulting in insufficient bottom voltage at the drain.
[0055] To address at least one of the aforementioned problems, this application provides a laterally diffused metal-oxide-semiconductor device and its fabrication method. A first trench and a second trench are formed on the front side of a semiconductor substrate. A body region is positioned at the bottom of the first trench, a drift region is positioned on the side of the body region near the second trench, and a drain region is positioned on the side of the second trench away from the first trench. Simultaneously, a first dielectric structure with a ramp is formed within the first trench, and a second dielectric structure is formed within the second trench. Thus, on one hand, the field plate structure located on the ramp can form a ramp-shaped field plate. Under the action of the ramp-shaped field plate and the ramp, the electric field in the drift region can be uniformly distributed, improving the breakdown voltage of the device. On the other hand, after introducing the second dielectric structure, the corner of the bottom of the second trench can become a new electric field concentration region, thereby alleviating the electric field intensity at the corner of the bottom of the first trench (i.e., the corner of the first dielectric structure), thereby reducing the drain electric field and impact ionization, improving the device performance degradation caused by the hot carrier effect, and enhancing the reliability of the device.
[0056] Firstly, referring to Figure 1 and Figure 2 As shown, this application provides a laterally diffused metal-oxide-semiconductor device 1, which can be an N-type laterally diffused metal-oxide-semiconductor device 1 or a P-type laterally diffused metal-oxide-semiconductor device 1.
[0057] Specifically, the laterally diffused metal-oxide-semiconductor device 1 includes a semiconductor substrate 10, a first dielectric structure 30, a second dielectric structure 40, a field plate structure 50, and a gate 60.
[0058] The semiconductor substrate 10 has a first trench 11 and a second trench 12 spaced apart on its front side. The semiconductor substrate 10 contains a drift region 21, a body region 22, a source region 23, and a drain region 24. The body region 22 is located at the bottom of the first trench 11; in other words, the body region 22 is located within the semiconductor substrate 10 at the bottom of the first trench 11. The source region 23 is located within the body region 22. The drift region 21 is located on the side of the body region 22 closest to the second trench 12. The drain region 24 is located within the drift region 21, and the drain region 24 is located on the side of the second trench 12 opposite to the first trench 11; in other words, the second trench 12 is located between the first trench 11 and the drain region 24.
[0059] Furthermore, the first dielectric structure 30 is disposed within the first trench 11 and located between the body region 22 and the second trench 12. The second dielectric structure 40 is disposed within the second trench 12. (Refer to...) Figure 2As shown, the first dielectric structure 30 is located between the source region 23 and the second dielectric structure 40. The first dielectric structure 30 has a ramp portion 31 on the side facing away from the second trench 12. The thickness of the ramp portion 31 gradually decreases in the direction from the second trench 12 to the body region 22 (the horizontal direction from the drain region 24 to the source region 23). At least a portion of the field plate structure 50 is disposed on the ramp portion 31. The gate 60 is disposed on the bottom wall of the first trench 11, and the area below the gate 60 is the channel region.
[0060] It should be noted that the second dielectric structure 40 fills the second trench 12 completely. The first dielectric structure 30 only fills a portion of the space in the first trench 11 and exposes a portion of the bottom wall of the first trench 11. At least a portion of the field plate structure 50 is located within the first trench 11.
[0061] It is understood that the material of the semiconductor substrate 10 may be single-crystal silicon, polycrystalline silicon, amorphous silicon, germanium silicon compound, silicon-on-insulator (SOI), low-temperature polycrystalline silicon (LTPS), or other materials known to those skilled in the art. The semiconductor substrate 10 can provide a supporting foundation for the structural layers on the semiconductor substrate 10.
[0062] In this embodiment, a first trench 11 and a second trench 12 are provided on the front side of the semiconductor substrate 10. A body region 22 is provided at the bottom of the first trench 11, a drift region 21 is provided on the side of the body region 22 close to the second trench 12, and a drain region 24 is provided on the side of the second trench 12 away from the first trench 11. At the same time, a first dielectric structure 30 with a slope portion 31 is provided in the first trench 11, and a second dielectric structure 40 is provided in the second trench 12. Thus, on the one hand, the source region 23 and the channel region are located at the bottom of the first trench 11, and the gate 60 is located on the bottom wall of the first trench 11, which can shorten the current path of the device and reduce the on-resistance. On the other hand, the field plate structure 50 located on the ramp portion 31 can form a ramp-shaped field plate. Under the action of the ramp-shaped field plate and the ramp portion 31, the electric field of the drift region 21 can be evenly distributed, improving the breakdown voltage of the device. Furthermore, after the introduction of the second dielectric structure 40, the corner of the bottom of the second trench 12 can become a new electric field concentration area, thereby alleviating the electric field intensity at the corner of the bottom of the first trench 11 (i.e., the corner of the first dielectric structure 30), which plays the role of distributing the concentrated electric field at the drain end. In other words, it increases the number of sharp points (or corners) near the drain end, reduces the electric field intensity at each sharp point (or corner), thereby reducing the electric field intensity and collisional ionization at the drain end, improving the device performance degradation caused by the hot carrier effect, and improving the reliability of the device.
[0063] In one embodiment, the depth of the first trench 11 is equal to the depth of the second trench 12. It is understood that due to the influence of process errors, the depth of the first trench 11 and the depth of the second trench 12 may not be absolutely equal. Therefore, the approximate equality of the depths of the first trench 11 and the second trench 12 can also be considered as equal.
[0064] Furthermore, the maximum thickness of the first dielectric structure 30 is equal to the thickness of the second dielectric structure 40. Here, the first dielectric structure 30 includes a ramp portion 31 and a flat portion 32. The thickness of the flat portion 32 is the maximum thickness of the first dielectric structure 30. It is understood that due to the influence of process errors, the maximum thickness of the first dielectric structure 30 and the thickness of the second dielectric structure 40 may not be absolutely equal. Therefore, it can be considered that the maximum thickness of the first dielectric structure 30 and the thickness of the second dielectric structure 40 are approximately equal.
[0065] The above setup allows the first groove 11 and the second groove 12 to be manufactured in the same process, thus eliminating the need for new versions and reducing manufacturing costs.
[0066] In one embodiment, reference Figure 3 As shown, a plurality of second trenches 12 are provided between the first trench 11 and the drain region 24; the plurality of second trenches 12 are arranged sequentially at intervals along a direction away from the first trench 11; a second dielectric structure 40 is correspondingly provided in each second trench 12. In this way, the number of tips (or corners) near the drain end is increased, and the electric field strength at each tip (or corner) is lower, thereby further reducing the electric field strength at the drain end and impact ionization, improving the device performance degradation caused by the hot carrier effect, and improving the reliability of the device.
[0067] In one embodiment, reference Figure 4 As shown, the second trench 12 is disposed on one side of the first trench 11 along the first direction X, and the first trench 11 and the second trench 12 are arranged along the first direction X. The second trench 12 includes a plurality of sub-trenches 121 arranged at intervals along the second direction Y, and the second dielectric structure 40 includes a plurality of sub-dielectric portions 41, with one sub-dielectric portion 41 correspondingly disposed in each sub-trench 121. The first direction X and the second direction Y intersect, and both the first direction X and the second direction Y are perpendicular to the thickness direction of the semiconductor substrate 10.
[0068] This is equivalent to dividing the second dielectric structure 40 into multiple parts. This structure can also reduce the drain-end electric field strength and impact ionization, improve the device performance degradation caused by hot carrier effects, and enhance the device reliability.
[0069] It is understood that the plurality of sub-grooves 121 can be arranged uniformly or non-uniformly. In a preferred embodiment, the first direction X and the second direction Y are perpendicular.
[0070] In one embodiment, reference Figure 1 As shown, the second trench 12 is disposed on one side of the first trench 11 along the first direction X; the first direction X is perpendicular to the thickness direction of the semiconductor substrate 10. From the front side to the back side of the semiconductor substrate 10, the width of the second trench 12 and the width of the second dielectric structure 40 gradually decrease; the width of the second trench 12 is the dimension of the second trench 12 along the first direction X, and the width of the second dielectric structure 40 is the dimension of the second dielectric structure 40 along the first direction X. That is, from top to bottom, the widths of the second trench 12 and the second dielectric structure 40 gradually decrease.
[0071] The above arrangement makes it easier for the corner of the bottom of the second dielectric structure 40 to become a concentrated area of electric field, thereby helping to reduce the electric field strength at the corner of the first dielectric structure 30.
[0072] In one embodiment, the first dielectric structure 30 is made of silicon oxide. And / or, the second dielectric structure 40 is made of silicon oxide. This, on the one hand, helps reduce manufacturing costs; on the other hand, it helps ensure the dielectric properties of the first dielectric structure 30 and the second dielectric structure 40.
[0073] In one embodiment, the first dielectric structure 30 is a shallow trench isolation structure. This effectively combines sloping field plate technology with shallow trench isolation technology, which helps to shorten the current path and reduce on-resistance of the device at a lower cost.
[0074] In one embodiment, reference Figure 1 As shown, the slope portion 31 includes a bottom surface 311 and a slope surface 312 connected to the bottom surface 311; the bottom surface 311 contacts a portion of the bottom wall of the first trench 11, and at least a portion of the field plate structure 50 is disposed on the slope surface 312. The included angle α between the slope surface 312 and the bottom surface 311 is between 15° and 20°. Exemplarily, the included angle α can be 15°, 16°, 18°, 19°, 20°, or between any two of the above values.
[0075] The above settings can make the electric field distribution in the drift region 21 uniform, the breakdown voltage of the device higher, and the on-resistance lower.
[0076] In one embodiment, the gate 60 and the field plate structure 50 are connected and are an integral structure. Specifically, the gate 60 includes a stacked gate dielectric layer (not shown) and a gate conductive layer (not shown). The gate conductive layer and the field plate structure 50 are an integral structure. In this way, the gate 60 and the field plate structure 50 can be fabricated in the same process, which helps to reduce manufacturing costs.
[0077] In one embodiment, the gate 60 and the field plate structure 50 are separate structures. Here, "separate structure" means that the gate 60 and the field plate structure 50 are fabricated separately in different processes; they are not formed in the same process. It should be noted that even when the gate 60 and the field plate structure 50 are separate structures, they can still be connected.
[0078] In one specific embodiment, the gate conductive layer and the field plate structure 50 are fabricated in different processes.
[0079] In one embodiment, the gate conductive layer is made of polycrystalline silicon, and the gate dielectric layer is made of silicon dioxide. It is understood that a silicon dioxide film layer may be disposed beneath the field plate structure 50.
[0080] In one embodiment, the field plate structure 50 also covers at least a portion of the surface of the flat portion 32.
[0081] In one embodiment, reference Figure 5 As shown, two adjacent cell devices can share the same source region 23. In this structure, the first trench 11 contains two first dielectric structures 30, two gates 60, and two field plate structures 50.
[0082] In one embodiment, the semiconductor substrate 10 includes a substrate (not shown), a buried layer (not shown), and an epitaxial layer (not shown) stacked together. The substrate and epitaxial layer are P-type, and the buried layer is N-type. Further, the drift region 21, the drain region 24, and the source region 23 are N-type, and the body region 22 is P-type.
[0083] Secondly, referring to Figure 6 As shown in the figure, this application provides a method for fabricating a laterally diffused metal-oxide-semiconductor device 1, which includes the following steps:
[0084] S100: Provides a semiconductor substrate 10. Specifically, a buried layer can be formed by implanting doped ions into the substrate, and then an epitaxial layer can be fabricated on the substrate to form the semiconductor substrate 10.
[0085] S200: A drift region 21 is formed in the semiconductor substrate 10, and a first trench 11 and a second trench 12 are formed on the front side of the semiconductor substrate 10 at intervals.
[0086] S300: A first dielectric structure 30 is formed in the first trench 11, and a second dielectric structure 40 is formed in the second trench 12.
[0087] S400: Forming a body region 22, a source region 23, a drain region 24, a field plate structure 50, and a gate 60. The body region 22, source region 23, and drain region 24 are all located within the semiconductor substrate 10. The body region 22 is located at the bottom of the first trench 11, and the source region 23 is located within the body region 22. A drift region 21 is located on the side of the body region 22 closest to the second trench 12. The drain region 24 is located within the drift region 21 and on the side of the second trench 12 opposite to the first trench 11. A first dielectric structure 30 is located between the body region 22 and the second trench 12. The first dielectric structure 30 has a ramp portion 31 on the side opposite to the second trench 12, and the thickness of the ramp portion 31 gradually decreases in the direction from the second trench 12 to the body region 22 (the horizontal direction from the drain region 24 to the source region 23). At least a portion of the field plate structure 50 is disposed on the ramp portion 31. The gate 60 is disposed on the bottom wall of the first trench 11.
[0088] The fabrication method of the laterally diffused metal-oxide-semiconductor device 1 provided in this application embodiment has the following advantages: First, the source region 23 and the channel region are located at the bottom of the first trench 11, and the gate 60 is located on the bottom wall of the first trench 11, which can shorten the current path of the device and reduce the on-resistance. Second, the field plate structure 50 located on the ramp portion 31 can form a ramp-shaped field plate. Under the action of the ramp-shaped field plate and the ramp portion 31, the electric field of the drift region 21 can be uniformly distributed, thereby improving the breakdown voltage of the device. Third, a second dielectric is introduced. After structure 40, the corners at the bottom of the second trench 12 can become new electric field concentration areas, thereby alleviating the electric field intensity at the corners at the bottom of the first trench 11 (i.e., the corners of the first dielectric structure 30), which plays the role of distributing the concentrated electric field at the drain end. In other words, it increases the number of sharp points (or corners) near the drain end, reduces the electric field intensity at each sharp point (or corner), thereby reducing the electric field intensity and collision ionization at the drain end, improving the device performance degradation caused by the hot carrier effect, and improving the reliability of the device.
[0089] In one embodiment, reference Figure 7 As shown, S300: A first dielectric structure 30 is formed in the first trench 11, and a second dielectric structure 40 is formed in the second trench 12, specifically including the following steps:
[0090] S310: An initial dielectric structure 5 is formed in the first trench 11, and a second dielectric structure 40 is formed in the second trench 12. It is understood that dielectric materials can be deposited using processes such as Chemical Vapor Deposition (CVD), vacuum deposition, pulsed laser deposition (PLD), and atomic layer deposition (ALD). Figure 9 As shown, in one example, a dielectric material is deposited using a high-density plasma chemical vapor deposition (HDP) process. The dielectric material fills the first trench 11 and the second trench 12. Then, a chemical mechanical polishing (CMP) process is used to treat the surface of the semiconductor substrate 10. The dielectric material located in the first trench 11 forms the initial dielectric structure 5, and the dielectric material located in the second trench 12 forms the second dielectric structure 40.
[0091] S320: A patterned mask layer 4 is formed on the semiconductor substrate 10. Specifically, as shown... Figure 10 As shown, photoresist can be formed on semiconductor substrate 10, and then photolithography can be performed on the photoresist to form a pattern mask layer 4.
[0092] S330: The initial dielectric structure 5 is etched to form a first dielectric structure 30 having a ramp portion 31. Specifically, a wet etching process can be used to etch the initial dielectric structure 5.
[0093] In this embodiment of the application, the second dielectric structure 40 can be fabricated simultaneously during the fabrication of the first dielectric structure 30, thereby eliminating the need for additional versions and improving the reliability of the device without increasing additional costs.
[0094] In one embodiment, S200: A drift region 21 is formed in the semiconductor substrate 10, and a first trench 11 and a second trench 12 are formed on the front side of the semiconductor substrate 10 at intervals, specifically including the following steps:
[0095] S210: A drift region 21 is formed within the semiconductor substrate 10. Specifically, the drift region 21 can be formed using an ion implantation process.
[0096] S220: A first film layer 2 and a second film layer 3 are sequentially stacked on a semiconductor substrate 10 to form a hard mask layer. Specifically, refer to... Figure 8 As shown, the first film layer 2 can be a silicon oxide film layer, and the second film layer 3 can be a silicon nitride film layer.
[0097] S230: Pattern the hard mask layer to define the etching window.
[0098] S240: Etch the semiconductor substrate 10 to form a first trench 11 and a second trench 12.
[0099] S250: Remove hard mask layer.
[0100] In one embodiment, S400: forming body region 22, source region 23, drain region 24, field plate structure 50 and gate 60, specifically includes the following steps:
[0101] S410: A body region 22 is formed at the bottom of the first groove 11.
[0102] S420: Forms the gate 60 and the field plate structure 50.
[0103] S430: Source region 23 is formed in body region 22, and drain region 24 is formed in drift region 21.
[0104] In the description of this specification, the references to terms such as "some embodiments," "other embodiments," "ideal embodiments," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example that are included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.
[0105] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0106] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.
Claims
1. A laterally diffused metal-oxide-semiconductor device, characterized in that, include: A semiconductor substrate, wherein a first trench and a second trench are provided on the front side of the semiconductor substrate at intervals; The semiconductor substrate is provided with a drift region, a body region, a source region, and a drain region; The body region is located at the bottom of the first trench, and the source region is located within the body region; the drift region is located on the side of the body region closer to the second trench; the leak region is located within the drift region and on the side of the second trench opposite to the first trench. A first dielectric structure is disposed within the first trench and located between the body region and the second trench; the first dielectric structure has a slope portion on the side away from the second trench, and the thickness of the slope portion gradually decreases from the second trench to the body region; A second dielectric structure is disposed within the second trench; The field plate structure, at least a portion of which is disposed on the slope portion; The gate is disposed on the bottom wall of the first trench.
2. The laterally diffused metal-oxide-semiconductor device according to claim 1, characterized in that, The depth of the first trench is equal to the depth of the second trench; The maximum thickness of the first dielectric structure is equal to the thickness of the second dielectric structure.
3. The laterally diffused metal-oxide-semiconductor device according to claim 1, characterized in that, The second groove is located on one side of the first groove along the first direction; The second trench includes a plurality of sub-trenches spaced apart along the second direction, and the second dielectric structure includes a plurality of sub-dielectric parts, with one sub-dielectric part correspondingly disposed in each of the sub-trenches; The first direction and the second direction intersect, and both the first direction and the second direction are perpendicular to the thickness direction of the semiconductor substrate.
4. The laterally diffused metal-oxide-semiconductor device according to claim 1, characterized in that, A plurality of second trenches are provided between the first trench and the drain region; the plurality of second trenches are arranged sequentially at intervals along a direction away from the first trench; and a second dielectric structure is provided in each second trench.
5. The laterally diffused metal-oxide-semiconductor device according to claim 1, characterized in that, The second trench is disposed on one side of the first trench along a first direction; the first direction is perpendicular to the thickness direction of the semiconductor substrate; From the front side of the semiconductor substrate to the back side of the semiconductor substrate, the width of the second trench and the width of the second dielectric structure gradually decrease; the width of the second trench is the dimension of the second trench along the first direction, and the width of the second dielectric structure is the dimension of the second dielectric structure along the first direction.
6. The laterally diffused metal-oxide-semiconductor device according to claim 1, characterized in that, The material of the first dielectric structure includes silicon oxide; And / or, the material of the second dielectric structure includes silicon oxide.
7. The laterally diffused metal-oxide-semiconductor device according to claim 1, characterized in that, The slope includes a bottom surface and a slope surface connected to the bottom surface; the bottom surface is in contact with a portion of the bottom wall of the first trench, and at least a portion of the field plate structure is disposed on the slope surface; The angle between the slope and the bottom surface is between 15° and 20°.
8. The laterally diffused metal-oxide-semiconductor device according to claim 1, characterized in that, The gate and the field plate structure are connected, and the two are an integral structure; Alternatively, the gate and the field plate structure may be a separate structure.
9. A method for fabricating a laterally diffused metal-oxide-semiconductor device, characterized in that, include: Provide semiconductor substrates; A drift region is formed within the semiconductor substrate, and a first trench and a second trench are formed at intervals on the front side of the semiconductor substrate; A first dielectric structure is formed in the first trench, and a second dielectric structure is formed in the second trench; Forming the body region, source region, drain region, field plate structure, and gate; The body region, the source region, and the drain region are all located within the semiconductor substrate; the body region is located at the bottom of the first trench, and the source region is located within the body region; the drift region is located on the side of the body region closer to the second trench; the drain region is located within the drift region and on the side of the second trench opposite to the first trench; the first dielectric structure is located between the body region and the second trench; the first dielectric structure has a ramp portion on the side opposite to the second trench, and the thickness of the ramp portion gradually decreases from the second trench to the body region; at least a portion of the field plate structure is disposed on the ramp portion; the gate is disposed on the bottom wall of the first trench.
10. The method for fabricating a laterally diffused metal-oxide-semiconductor device according to claim 9, characterized in that, The formation of a first dielectric structure in the first trench and the formation of a second dielectric structure in the second trench include: An initial dielectric structure is formed in the first trench, and a second dielectric structure is formed in the second trench; A patterned mask layer is formed on the semiconductor substrate; The initial dielectric structure is etched to form the first dielectric structure having a ramp portion.