USB4 standard-based connection circuitry and expandable modules

Abstract

This invention discloses a connection circuit and expandable module based on the USB4 standard. The technical problem it aims to solve is to meet the needs of different peripheral combinations, improve signal stability during high-speed data transmission and extended connections, and reduce costs. The invention adopts the following technical solution: a connection circuit and expandable module based on the USB4 standard, consisting of a USB4 standard link circuit and an expandable module connected together; the USB4 standard link circuit includes a USB4 interface, a data processing unit, a dynamic splitting unit, and a system management unit. Compared with existing technologies, this invention uses a USB4 standard link circuit and expandable module, and utilizes the data processing unit, dynamic splitting unit, and system management unit to select and combine different expansion interfaces according to actual needs, dynamically allocate resources, meet the needs of different peripheral combinations, shorten the development cycle, improve the compatibility and resource utilization of the interface circuit equipment, improve signal stability during high-speed data transmission and extended connections, and reduce costs.

Description

Technical Field

[0001] This invention relates to a multimedia device, and more particularly to an interface circuit. Background Technology

[0002] With the continuous improvement of computing performance and peripheral requirements, such as resolution With the increasing demands for data transmission bandwidth and interface expansion capabilities from users in 4K or 8K video processing, virtual reality (VR) applications, high-speed storage, and professional capture cards, traditional Universal Serial Bus (USB) interfaces, such as USB 3.2, are insufficient to meet the needs of these high-performance applications, typically offering bandwidth and stability below 20Gbps. Current technologies, to support the high-speed bandwidth of USB4 (40Gbps) and connect various peripherals such as M.2 NVMe SSDs, U.2 SSDs, CFexpress cards, and high-speed network cards, typically employ a single printed circuit board (PCBA) assembly integrating a USB4 controller chip, such as the ASM2464, and directly designing multiple peripheral interfaces (single-board integration). However, this approach has significant drawbacks: 1. High development cost and long cycle: Each time a peripheral interface type is added or changed, the entire PCBA needs to be redesigned. The development cycle usually lasts for several weeks, such as 6 to 8 weeks, and each design needs to undergo complete electrical and signal integrity testing.

[0003] 2. Poor flexibility and limited scalability: Single-board integration solutions are difficult to configure flexibly according to user needs. High-speed serial point Point-to-point dual-channel high-bandwidth transmission PCIe channel resources. Fixed-allocation channels cannot be dynamically split and reassembled to adapt to peripherals and combinations with different bandwidth requirements.

[0004] 3. Signal Stability Challenges: Integrating a high-speed USB4 interface, PCIe multi-channel conversion, and various types of peripheral interfaces on a single complex printed circuit board (PCB) places extremely high demands on wiring design and signal integrity. This makes the circuit susceptible to interference and signal attenuation, affecting stability. Summary of the Invention

[0005] The purpose of this invention is to provide a connection circuit and expandable module based on the USB4 standard. The technical problems to be solved are to meet the needs of different peripheral combinations, improve signal stability during high-speed data transmission and expanded connections, and reduce costs.

[0006] The present invention adopts the following technical solution: a connection circuit and an expandable module based on the USB4 standard, which is composed of a USB4 standard link circuit and an expandable module connected together; the USB4 standard link circuit is provided with a USB4 interface, a data processing unit, a dynamic splitting unit and a system management unit; The USB4 interface receives uplink data of PCIe Transaction Layer (TLP) packets in the USB4 tunneling protocol sent by the terminal device and sends them to the data processing unit. The data processing unit converts the uplink data into PCIe interface signals suitable for high-speed transmission and sends them to the dynamic splitting unit; The dynamic splitting unit receives the PCIe interface signal sent by the data processing unit and dynamically splits the PCIe interface signal: it sets the reference clock signal REFCLKN pin to a high level or a low level to match the corresponding PCIe channel allocation mode. The high level or low level state is identified by the dynamic splitting unit, triggering channel reallocation, realizing dynamic switching of channel mode, and outputting the switched channel. The system management unit generates configuration instructions for the dynamically split units.

[0007] The scalable module is a user-end expansion module, and its expansion interface originates from the output physical port of the dynamically split unit.

[0008] The system management unit of this invention is responsible for power management, status monitoring, and hot-swap detection.

[0009] The high or low level of this invention is generated by the configuration instruction of the system management unit.

[0010] The configuration instructions of this invention are generated based on user instructions, which are derived from the setting of hardware switches, the invocation of terminal device host software system drivers, or the default firmware configuration.

[0011] The data processing unit and dynamic splitting unit of this invention use a main control chip.

[0012] The main control chip of this invention is ASM2464PDX.

[0013] The channel redistribution of the present invention converts the original PCIe signal into different split-combination outputs: 1×4, 2×2, 1×2+2×1 or 4×1 PCIe signals.

[0014] In this invention, REFCLKN0 is high for the 1×4 PCIe signal; REFCLKN0 and REFCLKN1 are high for the 2×2 PCIe signal; REFCLKN0, REFCLKN1, and REFCLKN2 are high for the 1×2+2×1 PCIe signal; and REFCLKN0, REFCLKN1, REFCLKN2, and REFCLKN3 are high for the 4×1 PCIe signal.

[0015] The terminal device of this invention is a computer or a workstation.

[0016] The high-speed transmission of this invention refers to high-speed serial transmission under the PCIe Gen4 standard.

[0017] Compared with existing technologies, this invention adopts USB4 standard link circuit and expandable module, and utilizes data processing unit, dynamic splitting unit and system management unit to select and combine different expansion interfaces according to actual needs, dynamically allocate resources, meet the needs of different peripheral combinations, shorten the development cycle, improve the compatibility and resource utilization of interface circuit equipment, improve the signal stability during high-speed data transmission and expansion connection, and reduce costs. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the connection circuit and expandable module based on the USB4 standard of the present invention.

[0019] Figure 2 This is a schematic diagram (a) of the PCIe channel splitting mode of the present invention.

[0020] Figure 3 This is a schematic diagram (II) of the PCIe channel splitting mode of the present invention. Detailed Implementation

[0021] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments.

[0022] like Figure 1 As shown, the USB4 standard-based connection circuit and expandable module (system) of the present invention are composed of a USB4 standard link circuit and an expandable module connected together. The USB4 standard link circuit includes a USB4 interface, a data processing unit, a dynamic splitting unit, and a system management unit. The expandable module is a user-end expansion module. The USB4 interface is connected to the user-end expansion module via the data processing unit and the dynamic splitting unit.

[0023] The USB4 interface is used to connect to and exchange data with terminal devices. These terminal devices can be computers or workstations. The USB4 interface receives uplink data from the PCIe Transaction Layer Packet (TLP) sent by the terminal device via the USB4 Tunneling Protocol, and transmits it to the data processing unit. The data processing unit converts and processes the uplink data to obtain a high-speed serial point-to-point dual-channel high-bandwidth PCIe interface signal. PCIe (PCI Express) is a high-speed serial computer expansion bus standard.

[0024] The data processing unit is used to convert and process uplink data, receive and process uplink data from PCIe transaction layer data packets from terminal devices, convert them into PCIe interface signals suitable for high-speed transmission, and send them to the dynamic splitting unit.

[0025] High-speed transmission refers to high-speed serial transmission under the PCIe Gen4 standard, with a data rate of up to 16 GT / s per channel and a total bandwidth of up to 64 GT / s for a ×4 configuration. It is characterized as high-speed point-to-point bidirectional transmission and supports high-bandwidth applications such as external GPUs or storage expansion.

[0026] In this embodiment, the data processing unit uses the main control chip ASM2464PDX, existing peripheral circuits and decoding chips. The main control chip ASM2464PDX, existing peripheral circuits and decoding chips are collectively referred to as hardware circuits.

[0027] The data processing unit and the dynamic splitting unit use the same main control chip. The main control chip ASM2464PDX is configured to execute data processing logic and PCIe channel dynamic splitting logic. The logic functions of the data processing unit and the dynamic splitting unit are implemented by the same hardware circuit.

[0028] The dynamic splitting unit receives the PCIe interface signal sent by the data processing unit and dynamically splits the PCIe interface signal. The specific process of dynamic splitting is as follows: the corresponding reference clock signal REFCLKN pin is set to an active state on the dynamic splitting unit. An active state means that the REFCLKN pin level of the main control chip clock generator is set to a high level or a low level through hardware circuit or firmware configuration, and matched with the corresponding PCIe channel allocation mode.

[0029] High or low level signals are provided by the system management unit. These signals are generated based on user commands, which originate from hardware circuit switch settings, such as DIP switches or jumper caps on the circuit board. These commands are directly connected to the configuration pins of the ASM2464PDX to provide high or low levels. Alternatively, they can be invoked by the host software system driver of the terminal device, such as sending software commands from the terminal device via the USB4 data link. The system management unit then parses and sets the level. Finally, they can be set by firmware default configurations, such as the default logic pre-programmed into the internal memory of the ASM2464PDX main control chip or the external EEPROM, which automatically sets the level when no active command is received.

[0030] When the REFCLKN pin of the main control chip's clock generator is configured to a high or low level (e.g., high level represents split mode A, low level represents split mode B), this high or low level state is recognized as a valid reference clock configuration by the dynamic splitting unit, thereby triggering the subsequent channel reallocation process. At this time, the dynamic splitting unit detects the level change of the main control chip's REFCLKN pin, triggering its internal channel reallocation logic to dynamically switch between different modes and output the switched channel. Through this dynamic switching method, the original PCIe signal can be converted into various different splitting combinations: 1×4, 2×2, 1×2+2×1, or 4×1 PCIe signals.

[0031] In this embodiment, the dynamic splitting unit reads the level state of the reference clock request pins from the main control chip ASM2464PDX, such as REFCLKN0, REFCLKN1, REFCLKN2, and REFCLKN3, and dynamically reassembles the four data channels of the PCIeGen4×4 bus into different topologies, binding them to the corresponding physical ports inside the main control chip. These physical ports are pre-defined interfaces within the main control chip used for signal output, and their number matches the maximum splitting mode. Finally, the split signals establish a detachable connection with the user-end expansion module. The dynamic splitting unit sends the split PCIe signals to the user-end expansion interface to complete data transmission, thus achieving a detachable connection between the USB4 standard link circuit and the expansion module.

[0032] In this embodiment, the channel redistribution is 1×4, 2×2, 1×2+2×1, and 4×1, and the correspondence between the PCIe signals and high or low levels is as follows: 1×4 PCIe signals, with only REFCLKN0 high (active level signal), and REFCLKN1, REFCLKN2, and REFCLKN3 low (inactive), binding all 4 channels to Port 0 for high-bandwidth single-device expansion; The 2×2 PCIe signals, REFCLKN0 and REFCLKN1 are high (active level signals), and REFCLKN2 and REFCLKN3 are low (inactive), splitting the channel into two 2-channel groups bound to Port 0 and Port 1 for dual-device bandwidth equalization; The 1×2+2×1 PCIe signal (equivalent to 1×2 + two 1× channels), REFCLKN0, REFCLKN1, and REFCLKN2 are high (active level signal), and REFCLKN3 is low (inactive), splitting the channel into a 2-channel group (Port 2) and two 1-channel groups (Port 0, Port 1) for mixed device expansion; The 4×1 PCIe signals, REFCLKN0, REFCLKN1, REFCLKN2 and REFCLKN3 are all high (active level signals), splitting the channel into four 1-channel groups and binding them to Port 0, Port 1, Port 2 and Port 3 for expansion of multiple low-speed devices.

[0033] The expansion interfaces of the user-end expansion module originate from the output physical ports of the dynamic split unit. Depending on the configuration mode, the dynamic split unit connects PCIe signals to different user-end interfaces to form an expandable module. The expansion interfaces of the user-end expansion module are USB signal interfaces, DP signal interfaces [DP (DisplayPort) is a high-performance digital audio and video transmission standard], control signal interfaces, or PCIe interfaces. These interfaces are provided to the user through standard connectors (such as USB-C, DP, or PCIe slots) for connecting external devices.

[0034] The system management unit is responsible for power management, status monitoring, hot-plug detection, and configuration command generation.

[0035] Power management refers to managing the power timing of chips on the core board. The core board is the circuit board where the system management unit is located. It contains hardware circuitry that ensures the main control chip, ASM2464PDX, is powered on before other circuits and chips upon power-up. Simultaneously, through controllable power switches, such as MOSFETs or power management ICs, power is provided to the downstream USB expansion board and DP display board (function boards), which are detachably connected to the core board via connectors. Overvoltage and overcurrent protection is also provided for these function boards.

[0036] Status monitoring is conducted via the I2C bus, System Management Bus (SMBus), or Serial Peripheral Interface (SPI) to monitor the operating status of the USB4 to PCIe connection, such as link speed, bandwidth, and temperature. Simultaneously, by reading the ID information of the electrically erasable programmable read-only memory (EEPROM) on the function board, its type is identified, and the bus monitors the operating status of the USB4 to PCIe connection, including link speed, bandwidth, and temperature. Furthermore, by reading the ID information of the EEPROM on the function board, its type is identified as an NVMe SSD, a network card, or a video capture card.

[0037] Hot-plug detection uses a dedicated detection pin (such as the PRSNT# pin) on the downstream high-speed interface (such as a PCIe slot) to detect the insertion and removal of function boards. This is a dedicated detection pin for the downstream high-speed interface used to detect the insertion and removal of function boards.

[0038] The configuration command is generated based on user instructions and the current system status, such as the type of connected function board and power supply status. It generates a channel splitting mode configuration command and sends the user command to the dynamic splitting unit by controlling the REFCLKN pin level of the USB4 to PCIe control via the system management unit. User instructions originate from hardware switch settings, calls to terminal device host software system drivers, or firmware default configurations.

[0039] The hardware switch settings refer to directly setting the level signal through the physically present DIP switches or jumper components on the circuit board of this invention, and connecting it to the configuration pins of the ASM2464PDX. The system management unit obtains user commands by sampling the levels of these pins.

[0040] Host software driver invocation: This refers to the issuance of software commands from a computer or workstation acting as a terminal, through the device driver or configuration application within its operating system. These commands are transmitted to the ASM2464PDX via the USB4 data link, where they are received and parsed into user instructions by its system management unit.

[0041] Firmware default configuration: refers to a set of default logic pre-programmed into the internal memory of the ASM2464PDX chip or the external EEPROM decoding chip. During power-on initialization, if the system management unit does not detect the above two types of active commands, it will execute the default strategy preset in this firmware (such as fixed to the set split mode, or select the mode according to the automatically identified function board type) as the user command.

[0042] like Figure 2 As shown, the PCIe dynamic splitting unit splits the PCIe interface signals into two signals. The main control chip, according to configuration instructions, remaps and groups the original four data channels of the PCIe x4 bus through its internal switching logic. Specifically, it logically binds channels 0 and 1 (low and high levels) and assigns them to an independent physical port, forming the first x2 link; simultaneously, it binds channels 2 and 3 and assigns them to another physical port, forming the second x2 link. This process is completed by triggering the chip's internal channel reallocation logic, achieving dynamic splitting from one x4 interface to two independent x2 interfaces.

[0043] like Figure 3As shown, the PCIe dynamic splitting unit splits the PCIe interface signal into four signals. Each data channel of the original PCIe x4 bus is directly connected to the corresponding four independent physical port controllers inside the main control chip through an independent signal path. The splitting process is as follows: After receiving the corresponding configuration command, the main control chip sets the operating mode of its internal PCIe controller to "x1 split". Subsequently, the redistribution logic decouples channel 0, channel 1, channel 2, and channel 3 respectively, and binds them one by one to four different physical ports, thus forming four completely independent x1 links. The entire process is coordinated by the main control chip, realizing the splitting from one x4 interface to four independent x1 interfaces.

[0044] The first and second expansion interfaces can be PCIe or M.2 interface modules, providing more connection options for external devices. The PCIe interface module includes a USB signal interface, a DisplayPort (DP) signal interface, a control signal interface, and a power interface, outputting a DP signal up to 8kHz. If used as an M.2 interface module, it can also function as a signal source, converting different video formats for output via other chips; for example, a DP-to-HDMI chip can output HDMI format video. The USB signal interface allows for the expansion of more peripheral devices compatible with USB signal interfaces.

[0045] This invention utilizes a USB4 standard interface to increase data conversion bandwidth, thereby improving the uplink scale and speed of data transmission to terminal devices. It is a high-bandwidth, highly flexible, low-development-cost, and signal-stable USB4 extension solution.

[0046] The USB4 standard link circuit and the expandable module are detachably connected. When the USB4 standard-based link circuit and expandable module are connected to the user-end expansion module, the main control chip of the USB4 standard-based link circuit is connected to the expansion interface of the user-end expansion module. The USB4 standard link circuit transmits the split PCIe channels, power, management signals, etc. to the user-end expansion module.

[0047] The expansion interface is a pluggable module designed for a specific peripheral interface type.

[0048] Each expansion interface contains circuitry that implements one or more specific physical interfaces, such as an M.2 Key M interface, a U.2 (SFF-8639) interface, a CFexpress Type B interface, or a standard PCIe slot. Necessary bridging chips or signal conditioning circuitry depend on the specific interface requirements. Users can select and combine different expansion interfaces according to their actual needs.

[0049] The dynamic PCIe lane splitting control unit dynamically reassembles the four data lanes of the PCIe Gen4×4 bus into different topologies by configuring the level state of the specific reference clock request pin of the USB4 / PCIe control chip ASM2464PDX, and binds them to different physical ports. Ultimately, these are detachably linked via the USB4 module and the user-end module. It supports the following four main configuration modes: 1. 1×4 Mode: Only REFCLKN0 is activated (valid). All four PCIe lanes are bound to Port 0. Suitable for single devices requiring high bandwidth, such as high-performance NVMe SSDs.

[0050] 2.2×2 Mode: Activate REFCLKN0 and REFCLKN1 (enabled). Split the channel into two 2-channel groups: Port 0 (2 channels) and Port 1 (2 channels). Suitable for connecting two medium-bandwidth devices simultaneously, such as two medium-speed SSDs or one SSD plus a medium-speed capture card.

[0051] 3.4×1 Mode: Activates REFCLKN0, REFCLKN1, REFCLKN2, and REFCLKN3 (all are effective). The channel is split into four independent single-channel interfaces: Port 0 (1 channel), Port 1 (1 channel), Port 2 (1 channel), and Port 3 (1 channel). Suitable for connecting multiple low-bandwidth devices, such as low-speed network cards, SATA controller cards, and USB hub controller cards.

[0052] 4.2×1 + 1×2 mode: Activates REFCLKN0, REFCLKN1, and REFCLKN2 (enabled). Splits the channels into: Port 0 (1 channel) + Port 1 (1 channel) + Port 2 (2 channels). Suitable for mixed connectivity scenarios, such as a low-bandwidth device, a medium-bandwidth device, and a device requiring higher bandwidth (such as an SSD).

[0053] In mode switching, the system management unit sets the effective state of the corresponding REFCLKN pin according to the preset configuration or user instructions (through firmware, hardware switch, host software driver), triggering the channel reallocation logic inside the control chip to achieve dynamic switching of the above modes.

[0054] The technical effects of this invention are as follows: 1. Ultra-high bandwidth: Based on the USB4 standard, it provides data transfer rates of up to 40Gbps and supports high-speed peripherals through the PCIe Gen4×4 interface.

[0055] 2. Development costs and time have been significantly reduced: USB4 modules require only a single design and rigorous electrical testing and signal integrity optimization. For different peripheral interfaces (M.2, U.2, CFExpress, PCIe), users only need to design and manufacture relatively simple expansion interfaces. The development cycle for these expansion interfaces is short, requiring no complex USB4 and PCIe core logic design, and primarily focuses on functional testing, reusing the electrical certification foundation of the USB4 expansion module.

[0056] 3. Excellent flexibility and scalability: On-demand combination: Users can select and combine different extension interfaces according to their actual needs.

[0057] Dynamic resource allocation: Dynamic PCIe lane splitting allows for flexible allocation of valuable PCIe lane bandwidth resources, enabling a single USB4 expansion module to efficiently adapt to various complex scenarios, from single-device full-speed operation to multi-device mixed access, significantly improving interface circuit device compatibility and resource utilization.

[0058] 4. Improve stability: The USB4 module focuses on high-speed signal processing (USB4, PCIe Gen4), featuring a simpler design and easier optimization of routing to ensure signal integrity. The lower complexity of the functional board also helps ensure the stability of its interface signals. The discrete architecture reduces signal interference sources on the board.

[0059] 5. Easy to test and certify: The USB4 module serves as the foundation for comprehensive electrical testing and compliance certification. Subsequent verification primarily focuses on the functionality of its specific interfaces, significantly simplifying the testing process.

Claims

1. A connection circuit and expandable module based on the USB4 standard, characterized in that: The USB4 standard-based connection circuit and expandable module are composed of a USB4 standard link circuit and an expandable module connected together; the USB4 standard link circuit is equipped with a USB4 interface, a data processing unit, a dynamic splitting unit, and a system management unit. The USB4 interface receives uplink data of PCIe Transaction Layer (TLP) packets in the USB4 tunneling protocol sent by the terminal device and sends them to the data processing unit. The data processing unit converts the uplink data into PCIe interface signals suitable for high-speed transmission and sends them to the dynamic splitting unit; The dynamic splitting unit receives the PCIe interface signal sent by the data processing unit and dynamically splits the PCIe interface signal: it sets the reference clock signal REFCLKN pin to a high level or a low level to match the corresponding PCIe channel allocation mode. The high level or low level state is identified by the dynamic splitting unit, triggering channel reallocation, realizing dynamic switching of channel mode, and outputting the switched channel. The system management unit generates configuration instructions for the dynamically split units; The scalable module is a user-end expansion module, and its expansion interface originates from the output physical port of the dynamically split unit.

2. The connection circuit and expandable module based on the USB4 standard according to claim 1, characterized in that: The system management unit is responsible for power management, status monitoring, and hot-swap detection.

3. The connection circuit and expandable module based on the USB4 standard according to claim 2, characterized in that: The high or low level is generated by the configuration instructions of the system management unit.

4. The connection circuit and expandable module based on the USB4 standard according to claim 3, characterized in that: The configuration instructions are generated based on user instructions, which are derived from hardware switch settings, calls to terminal device host software system drivers, or firmware default configurations.

5. The connection circuit and expandable module based on the USB4 standard according to claim 4, characterized in that: The data processing unit and the dynamic splitting unit are equipped with a main control chip.

6. The connection circuit and expandable module based on the USB4 standard according to claim 5, characterized in that: The main control chip is ASM2464PDX.

7. The connection circuit and expandable module based on the USB4 standard according to claim 6, characterized in that: The channel redistribution involves converting the original PCIe signal into different split-combination outputs: 1×4, 2×2, 1×2+2×1, or 4×1 PCIe signals.

8. The connection circuit and expandable module based on the USB4 standard according to claim 7, characterized in that: For the 1×4 PCIe signal, REFCLKN0 is high; for the 2×2 PCIe signal, REFCLKN0 and REFCLKN1 are high; for the 1×2+2×1 PCIe signal, REFCLKN0, REFCLKN1, and REFCLKN2 are high; and for the 4×1 PCIe signal, REFCLKN0, REFCLKN1, REFCLKN2, and REFCLKN3 are high.

9. The connection circuit and expandable module based on the USB4 standard according to claim 1, characterized in that: The terminal device is a computer or workstation.

10. The connection circuit and expandable module based on the USB4 standard according to claim 1, characterized in that: The high-speed transmission refers to high-speed serial transmission under the PCIe Gen4 standard.

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