An efficient QR matrix decomposition method for pulsating matrices based on FPGA

Abstract

This invention discloses an efficient QR matrix decomposition method based on FPGA for implementing systolic matrices, belonging to the field of software-defined radio signal transmission technology for airborne networks. It is based on the design of a multi-channel digital front-end implemented on an FPGA chip. The method includes: designing a general handshake coordination mechanism, designing a timing flow for systolic matrix multiplication, performing fast QR matrix decomposition single-loop operations by calculating the Householder mirror transformation matrix, designing a top-level loop pipeline for QR matrix decomposition, and finally verifying the hardware scheme of the fast QR decomposition algorithm. This invention converts resource consumption into timing consumption by designing the overall pipeline logic and loop operations, enabling fast processing and accurate decomposition of digital information in a multi-channel digital front-end on an FPGA, effectively saving on-chip resources. In addition, this invention has excellent scalability, supporting 64 to 128-bit high-precision fixed-point number formats, and the data matrix order can reach up to 128.

Description

Technical Field

[0001] This invention relates to the field of software-defined radio information transmission technology in airborne networks, and more particularly, to a design for implementing a multi-channel digital front-end on an FPGA chip, which utilizes QR decomposition technology to reduce the computational complexity of baseband signal processing and improve computational efficiency. Background Technology

[0002] Software-defined radio (SDR) technology has become widely accepted and applied. It has emerged as a common modern method in radio engineering, representing a new design concept and philosophy in the field. SDR overcomes the limitations of traditional radio designs that rely on single-function, poorly scalable hardware. It emphasizes using open, minimal hardware as a universal platform, and implementing various radio functions through upgradeable and reconfigurable application software. Users can configure different application software on the same hardware platform to meet diverse functional requirements at different times and in different usage environments.

[0003] Avionics systems are the "brain" and "nerve center" of a flight platform, supporting modern aircraft in completing a wide variety of missions. As a typical highly safe and reliable real-time system, the main characteristic of avionics systems is ensuring the real-time performance and reliability of information perception, processing, and transmission in harsh spatial and complex electromagnetic environments. Airborne network systems are the means by which real-time and reliable information transmission is achieved within avionics systems, and their development level and capabilities determine the overall configuration and comprehensive information efficiency of the avionics system. Due to the stringent real-time and security requirements of avionics system information transmission, airborne network systems differ from ordinary computer networks in terms of topology, transmission protocols, media connection methods, and design verification methods. In the development of aviation technology, a series of airborne network systems adapted to various levels of avionics integration have been developed. Initially, discrete avionics systems used the point-to-point bus ARINC429, while integrated avionics systems used the centrally controlled bus MIL-STD-1553B. To adapt to bandwidth growth, distributed control fiber optic data interfaces FDDI and linear token passing buses LTPB were adopted. As avionics systems enter a phase of integration and modularization, the demands for data transmission capacity, real-time performance, and reliability are constantly increasing. New-generation switching network technologies, such as Fibre Channel (FC), Avionics Full-Duplex Switched Ethernet (AFDX), and Time-Triggered Ethernet (TTE), are being applied in advanced integrated avionics systems. To support the increasing integration of avionics systems, airborne network systems inevitably require continuous system upgrades and architectural improvements. Due to the strong constraints and significant complexity of these networks in application, enhancing their functionality and improving their performance has always been a research hotspot in the international aviation industry and the field of real-time communication.

[0004] Field-Programmable Gate Arrays (FPGAs) emerged as a semi-custom circuit in the field of integrated circuits, addressing the shortcomings of custom circuits while overcoming the limited gate count of traditional programmable devices. An FPGA chip typically consists of three programmable circuits and an SRAM for storing programming data. These three programmable circuits are: Configurable Logic Blocks (CLBs), Input / Output Blocks (IOBs), and Interconnect Resources (IRs). CLBs are the basic units for implementing logic functions in an FPGA, generally composed of logic function generators, flip-flops, data selectors, and other circuits. IOBs provide connections between the internal logic arrays of the pins in the FPGA chip; each IOB controls one pin and can be configured for input, output, or bidirectional I / O functions. Interconnect Resources (IRs) include metal interconnect segments of various lengths and programmable connection switches, which connect the CLBs to each other and between CLBs and IOBs, forming systems with various complex functions.

[0005] With the development and performance improvement of FPGA chip technology, the functions that multi-channel digital front-ends need to perform will continue to increase, and the burden on signal processing will continue to grow. Software-defined radio (SDR) extends the traditional front-end concept, defining it as all transceiver circuits and various processing stages between the antenna and baseband processing; the baseband processing section is defined as the SDR back-end. The transceiver circuits and processing stages between the antenna and analog-to-digital / digital-to-analog converters are defined as the analog front-end; while the processing stages between analog-to-digital / digital-to-analog converters and baseband processing are defined as the digital front-end. In other words, the digital front-end of SDR includes three parts: the RF analog front-end, the A / D / A converter, and the digital front-end.

[0006] In the field of array signal processing, multi-channel signal processing algorithms such as phased array beamforming and Multiple-Input Multiple-Output (MIMO) typically involve a large number of matrix decomposition and matrix inversion operations. For example, the adaptive beamforming (SMI) algorithm requires inverting the data covariance matrix to obtain beam weights, and the core of the inversion algorithm lies in matrix decomposition. Furthermore, because beam weight calculation requires extremely high real-time performance, and matrix decomposition operations have a high computational load, stringent requirements are placed on the computational speed and resource consumption of the solution module, necessitating the design of a fast QR decomposition technology based on FPGA.

[0007] In practical engineering, the choice of matrix decomposition and inversion algorithm is mainly related to computational complexity, matrix order, number of elimination iterations, and number of multiplication iterations. Mathematically, commonly used matrix decomposition methods include Cholesky matrix decomposition, LU triangular matrix decomposition, SVD singular value matrix decomposition, and QR matrix decomposition. While the Cholesky matrix decomposition method proposed by Zhou Jinqiang et al. (Zhou Jinqiang, Feng Jifeng, Design of Complex Matrix Inversion Based on FPGA [J]. Modern Computing, 2020, 5(15): 82 − 87) avoids the square root operation by introducing an auxiliary matrix, it has better real-time performance, but it can only handle conjugate symmetric matrices, which has a large limitation; the LU triangular matrix decomposition method proposed by Wang Weijiang et al. (Wang Weijiang, Zhang Tuofeng, Jiang Rongkun, et al. Fast FPGA Implementation of Generalized Inverse Matrix Solving of ESPRIT Algorithm [J]. Journal of Beijing Institute of Technology, 2022, 42(11): 1200-1206.) has a faster solution speed and improved efficiency, it is only applicable to all matrices with sequential principal minors greater than 0, and the calculation error is large when the main diagonal elements are small or 0 during the decomposition process; Ying Jun et al. (Ying Jun, Zhu Yunpeng. FPGA Implementation Based on Singular Value Decomposition of CORDIC Matrix [J]. Journal of Chongqing University of Posts and Telecommunications, 2020, Although the SVD singular value matrix decomposition method proposed in 32(3):434 − 440. can be applied to any matrix, the SVD singular value matrix decomposition method introduces many other computational units, making the implementation process relatively complex.

[0008] With the development of various reconfigurable computing platforms, such as Xilinx's Versal architecture, real-time high-precision, high-dimensional matrix factorization operations have become possible in different array signal processing applications. However, current research on hardware implementations of matrix factorization largely focuses on sparse and low-bit matrices. Research on non-sparse and high-bit matrix factorization circuits is limited, and most hardware implementations of QR factorization are slow and resource-intensive, failing to meet high-speed, real-time requirements. Therefore, to meet the requirements of multi-channel digital front-ends for array signal processing, researching how to implement a fast QR matrix factorization algorithm suitable for high-precision data matrices on FPGA chips is a worthwhile area of ​​investigation. Summary of the Invention

[0009] To achieve array signal processing in a multi-channel digital front-end, this invention employs a combination of Vivado software and FPGA chips to construct a digital front-end module applicable to airborne network systems, such as... Figure 1As shown, the digital front-end module performs pulsating multiplication and QR optimization decomposition on the multi-channel waveform data output from the airborne network on the Vivado software platform. This results in orthogonal matrix Q-waveforms and non-singular upper triangular matrix R-waveforms output by the digital front-end module exhibiting advantages such as fast response and low loss. This method rapidly achieves QR matrix decomposition based on Householder mirror transformation with maximum resource utilization, effectively saving on-chip resources. Simultaneously, it supports 64- to 128-bit high-precision fixed-point number formats, improving the accuracy of the matrix decomposition results. At the hardware level, the efficient QR matrix decomposition algorithm for pulsating matrices is deployed on an FPGA hardware platform, completing the hardware implementation and time and resource evaluation of the 8th-order matrix decomposition circuit, thus verifying the theory of the method of this invention.

[0010] This invention discloses an efficient QR matrix decomposition method based on FPGA for implementing systolic matrices. The method utilizes an FPGA chip and FPGA software to jointly construct a digital front-end module for software-defined radio information. The digital front-end module includes a systolic multiplier and an improved QR decomposer. The design steps of the digital front-end module include:

[0011] Step 1: Configure the handshake and collaboration mechanism for the FPGA chip;

[0012] when When the rising edge is valid, it passes through the multiplexer port. The input waveform digital information is stored in the data loading register. Inside;

[0013] when When the rising edge is valid, the waveform digital information to be output on the FPGA chip is stored in the data output register. middle;

[0014] Step 2: Design an optimized timing sequence for systolic matrix multiplication on the FPGA chip;

[0015] The waveform digital information in the waveform digital information set is arranged into a row according to the waveform digital information of the same channel, and the waveform digital information of the same snapshot is arranged into a column to form the waveform-row-column sorting.

[0016] After transposing the waveform-row-column sort, a waveform-row-column-transpose is formed.

[0017] The waveform-row-column sorting is called the front matrix, and the waveform-row-column-transpose is called the back matrix. The elements of each column in the front matrix are multiplied by the elements of each row in the back matrix to obtain a single addition unit. The column and row elements of the two matrices are traversed sequentially, and then the addition units are accumulated to obtain the pulsation matrix.

[0018] Step 3: Optimize the Householder mirror transformation method;

[0019] Based on the initial non-singular matrix column vector Mirror vector Calculate the Householder unit vector ,and ;Will Corresponding dimensions The identity matrix is ​​denoted as Then the first Householder mirror transformation array can be obtained. ,and , for transpose;

[0020] No. The Householder mirror transformation matrix in the next cycle is , for transpose;

[0021] Step 4: Fast QR matrix decomposition in a single loop;

[0022] The QR-cycle module based on mirror transformation, designed on the PFGA chip, is used to quickly complete a single loop operation of QR matrix decomposition; all QR-cycle modules are triggered by a valid rising edge.

[0023] Step 5: Decompose the top-level loop pipeline using the QR matrix;

[0024] The QR matrix decomposition adopts a top-level loop design in a serial stepping manner and reuses the QR-cycle module to the greatest extent.

[0025] Compared with the prior art, the method proposed in this invention has the following significant technical effects:

[0026] (1) The fast QR matrix factorization algorithm based on Householder mirror transformation designed in this invention was implemented with a clock cycle of 250MHz on a hardware platform with chip model xcvu13p-fhgb2104-2-i. It can perform 8th order matrix decomposition operations internally, with high speed and reliability. Theoretically, it can be applied to the decomposition of matrices up to order 128, and is suitable for engineering applications such as multi-channel real-time communication.

[0027] (2) The fast QR decomposition algorithm based on Householder mirror transformation proposed in this invention is suitable for fast decomposition of high-dimensional, high-precision non-singular matrices in the real number domain. The algorithm is optimized through local serial-parallel processing to form a pipeline design, which achieves a better balance between resource utilization and data processing efficiency.

[0028] (3) The present invention confirms the validity of the data by triggering the rising edge. When the data is valid, it latches and outputs, which reduces the dynamic power consumption of modules such as systolic matrix multiplication, QR decomposition, and top-level pipeline, and avoids the subsequent stage from re-latching the input, saving the consumption of register resources of the front and rear stages, and improving the reuse efficiency and modifiability of the module, greatly simplifying the overall module design process.

[0029] (4) In fields such as array signal processing, matrix decomposition algorithms are frequently used in hardware platforms. This invention utilizes a fast QR decomposition algorithm based on mirror transformation, employing a "pulsating" matrix multiplication method to design a top-level loop pipeline for QR matrix decomposition, significantly improving development efficiency. Compared to traditional parallel matrix computation methods, it can save [data / efforts]. This method consumes significantly more resources. Compared to High Level Synthesis (HLS), it can improve computational efficiency by more than 35 times in the same clock cycle when performing 8th-order matrix decomposition operations. Figure 10 As shown.

[0030] (5) The "pulsating" matrix multiplier module designed in this invention optimizes the calculation of row and column vectors. By using the idea of ​​inputting in rows and columns, it performs multiplication and addition of specific elements. Theoretically, it can achieve the following calculations: To exchange for one clock cycle The resource savings are several times greater, and the improvement in resource utilization is particularly significant when using this module for high-dimensional matrices. Compared to serial data streams, this method transforms serial data streams into parallel data streams, resulting in substantial resource savings, such as... Figure 11 As shown.

[0031] (6) Matrix operations in traditional FPGA design and HLS rely heavily on Bram-based registers and reads, which severely consume register resources and suffer from low read rates. This invention configures the mirror transformation as a cyclic calculation mode, which can quickly obtain the results. Matrix and Matrix-based computation reduces computational complexity, supports 64- to 128-bit high-precision fixed-point number formats, exhibits good numerical stability in high-precision calculations, and has no intermediate register matrix, resulting in better scalability and higher resource utilization. Attached Figure Description

[0032] Figure 1 A block diagram of the digital front-end module designed for this invention.

[0033] Figure 2 This is a flowchart illustrating the efficient QR matrix decomposition of the pulsating matrix based on FPGA, as described in this invention.

[0034] Figure 3 A block diagram for setting up the on-chip handshake collaboration mechanism of the FPGA.

[0035] Figure 4 This is a flowchart illustrating the construction process of the pulsation matrix of this invention.

[0036] Figure 5 This is a schematic diagram illustrating the column-by-column calculation principle of the pulsating matrix multiplication method of this invention.

[0037] Figure 6 This is a schematic diagram of the Householder mirror transformation principle.

[0038] Figure 7 This is a design diagram of the Householder mirror transformation on the FPGA chip according to the present invention.

[0039] Figure 8 This is a design diagram of the QR-cycle module based on Householder mirror transformation according to the present invention.

[0040] Figure 9 This is a block diagram of the top-level loop operation control structure of the QR-cycle module of the present invention.

[0041] Figure 10 This invention is a resource utilization rate diagram after QR decomposition processing.

[0042] Figure 11 This is a comparison diagram of the 8th-order matrix multiplier of the present invention.

[0043] Figure 12 This is a comparison chart of the matrix factorization Q and the theoretical solution obtained from MATLAB.

[0044] Figure 13 This is a comparison chart of the matrix factorization R and the theoretical solution obtained by MATLAB in this invention. Detailed Implementation

[0045] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. The examples of the parameters listed are merely preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

[0046] In terms of hardware, this invention employs an FPGA chip and FPGA software to jointly construct a digital front-end module for software-defined radio information. (See [link to relevant documentation]). Figure 1As shown, the digital front-end module includes a pulsating multiplier and an improved QR decomposer. The input of the digital front-end module receives multi-channel waveform data from the analog-to-digital converter (ADC); the output of the digital front-end module is used to output baseband signals.

[0047] In this invention, multi-channel waveform data refers to waveform data from the search and tracking channel, sidelobe cancellation channel, and airborne communication channel. The multi-channel waveform data is denoted as a waveform digital information set. And expressed in set form as subscript The channel identifier, subscript Indicates the total number of channels, and ,in:

[0048] This represents the waveform digital information of channel 1, and .

[0049] This represents the waveform digital information of the second channel, and .

[0050] Indicates the first The digital waveform information of the channel, and .

[0051] Indicates the first The digital waveform information of the channel, and .

[0052] In this invention, superscript This represents the total number of time-domain snapshots, and The maximum value that can be assigned is 1024. (Superscript) This is the identifier for the number of snapshots in the time domain, and Superscript These are letters used to distinguish the number of time-domain snapshots in different channels.

[0053] This represents the first time-domain snapshot data of the first channel. This represents the second time-domain snapshot data of the first channel. Indicates the first channel's... Time-domain snapshot data. Indicates the first channel's... Time-domain snapshot data.

[0054] This represents the first time-domain snapshot data of the second channel. This represents the second time-domain snapshot data of the second channel. Indicates the second channel's... Time-domain snapshot data. Indicates the second channel's... Time-domain snapshot data.

[0055] Indicates the first The first time-domain snapshot data of the channel. Indicates the first The second time-domain snapshot data of the channel. Indicates the first The first channel Time-domain snapshot data. Indicates the first The first channel Time-domain snapshot data.

[0056] Indicates the first The first time-domain snapshot data of the channel. Indicates the first The second time-domain snapshot data of the channel. Indicates the first The first channel Time-domain snapshot data. Indicates the first The first channel Time-domain snapshot data.

[0057] For ease of explanation, the following Also known as arbitrary time-domain snapshot data of any channel.

[0058] By comprehensively representing the number of snapshots in each time domain of each channel, the waveform digital information set is represented as follows: .when When the value is 1024, the waveform digital information set is represented as follows: .

[0059] The digital front-end module design of this invention mainly includes the following five core steps: on-chip handshake collaboration mechanism design, on-chip optimized systolic matrix multiplication process, optimized Householder mirror transformation method, fast QR matrix decomposition single loop and its top-level loop operation control module. For details on the relationships between each step, please refer to... Figure 2 The flowchart.

[0060] Step 1: Configure the handshake and collaboration mechanism for the FPGA chip;

[0061] In this invention, for the hardware design of the FPGA chip, antenna receiver, and input / output data exchange interface, waveform digital information interaction must be established under an effective link mechanism. To improve the efficiency and accuracy of information interaction, this invention designs a simple and effective inter-module handshake collaboration mechanism based on the "handshake" mechanism design concept. For example... Figure 3 As shown.

[0062] In order to accurately capture data and determine its validity, the FPGA software running on the FPGA chip incorporates a data loading register as described in this invention. With data output register And the data processing module Func. Used to store data information output by the radar receiver; Used to store data that needs to be transmitted.

[0063] In the hardware design of FPGA chips For input data valid signals, This is to output a valid data signal. For multiple data input ports, This is a multi-channel data output port.

[0064] when When the rising edge is valid, it passes through the multiplexer port. Input waveform digital information Registered data loading register Inside.

[0065] when When the rising edge is valid, the waveform digital information that needs to be output on the FPGA chip is displayed. Registered in the data output register In order to facilitate subsequent modules to process the... The use of.

[0066] In this invention, it is triggered by the rising edge ( , The validity of the waveform digital information is confirmed. When the waveform digital information is valid, the output is latched, which reduces the dynamic power consumption of each module and avoids the subsequent stage from latching the input. This saves the consumption of register resources of the front and rear stages and greatly simplifies the design process of the overall FPGA software function.

[0067] Step 2: Design an optimized timing sequence for systolic matrix multiplication on the FPGA chip;

[0068] In this invention, the waveform-row-column sorting is called the front matrix, and the waveform-row-column-transpose is called the back matrix. Each element in each column of the front matrix is ​​multiplied correspondingly with each element in each row of the back matrix to obtain a single addition unit; the column and row elements of the two matrices are traversed sequentially, and then the addition units are accumulated to obtain the pulsation matrix.

[0069] The process of constructing the pulsation matrix is ​​as follows: Figure 4 As shown in the figure The front matrix representing the waveform – sorted by rows and columns; The matrix after waveform-row-column-transpose sorting; The elements of each column in the array Multiplying the elements in each row of the expression results in a single addition unit. ; represent The element in the nth column and kth row and The product of the elements in the k-th row and n-th column; k represents the number of accumulations. Since the covariance matrix is ​​a square matrix with an equal number of rows and columns, it is constructed using an n-row, n-column form with subscript nn.

[0070] In this invention, the waveform digital information set The waveform digital information is arranged in a row according to the waveform digital information of the same channel, and the waveform digital information of the same snapshot is arranged in a column, thus forming a waveform-row-column sorting. Where N is the total number of channels, and M is the total number of time-domain snapshots. any element in Represents the number sorted by waveform rows and columns. Corresponding channel Digital information.

[0071] In this invention, the waveform is further sorted by row and column. After transposition, a waveform-row-column-transpose is formed. ,Right now ;in, any element in Represents the number of rows and columns sorted according to the waveform transpose. Corresponding channel Digital information.

[0072] This invention employs a pulse matrix construction method. and The construction yields the column-row waveform pulsation matrix. In this invention, It is . a non-singular matrix.

[0073] Let this be the first addition unit, simplified to .

[0074] Let this be the second addition unit, simplified to .

[0075] Recorded as the number One addition unit, simplified to .

[0076] Let it be the Mth addition unit, which is simplified to .

[0077] The addition unit is represented in matrix form as a column-row waveform pulsation matrix. .

[0078] In this invention, initially, The first column vector in the matrix is ​​denoted as the initial non-singular matrix column vector. Mirror the unit vector in a given direction Below, the mirror vector can be obtained. , and based on Get a dimension The identity matrix is (Non-singular matrix column vectors) Mirror unit vector Mirror vector All (A column vector.)

[0079] In terms of resource consumption, two and When multiplying matrices, if the output... When performing conventional parallel matrix multiplication on elements, it is necessary to A multiplier, One adder, in one clock cycle The output is then processed. However, when using the "pulsating" matrix column and row calculation method designed in this invention, due to the limitations of this invention... and Each element in the algorithm is multiplied and then added together, using the same adder and multiplier repeatedly, meaning only one multiplier is needed. A multiplier and Adders. Due to two matrices and The dimension after multiplication is M. clock cycles Then the matrix multiplication operation can be completed. That is, compared to conventional parallel matrix multiplication, this invention can almost completely automate the computation. The module trades one clock cycle for a resource saving that is a multiple of the number of channels. If used on high-order dimensional matrices, the gain is considerable.

[0080] The present invention is based on the following: Figure 5 The timing flow for the "pulsating" matrix multiplication with column-by-column and row-by-row calculations is as follows: Where, the clock signal... Input data valid signal With output data valid signal All are triggered on the rising edge. For Each output element Based on the modules for outputting from rows and outputting from columns, matrices can be used sequentially. Each column With matrix each line Perform element-wise multiplication on each addition unit to obtain... (i represents the number of times the row is looped, and j represents the number of times the column is looped), then by accumulating each iteration... Each output element is obtained by value. The result. The accumulation operation is evenly distributed across the time dimension. clock cycles Each clock cycle The corresponding intermediate accumulated value is .for and Matrix multiplication only requires The entire addition and accumulation operation can be completed in one clock cycle. This is possible with a valid input data signal. After the rising edge, use clock cycles To ensure timing consistency during computation, the following steps are performed. The final result is the output three clock cycles after the first clock cycle. And simultaneously pull up the output valid signal. .

[0081] Essentially, the "pulsating" matrix multiplication proposed in this invention is a parallel computing architecture optimization strategy based on the idea of ​​"time for space." Its core lies in achieving a balance between "high parallelism" and "low resource consumption" in matrix multiplication through the orderly flow of data and the reuse of computational units. Specifically, this method transforms the traditional matrix multiplication's "fully parallel computation" (requiring the simultaneous use of numerous independent multipliers and adders) operation mode into a "pipeline-style serial accumulation" mode: for example, taking the first matrix... With the second matrix Taking multiplication as an example, traditional parallel solutions require A multiplier and One adder, and the first matrix needs to be read at once. of Elements and the second matrix of The presence of multiple elements puts immense pressure on on-chip storage bandwidth and resources; however, the pulsating multiplication architecture of this invention only requires N multipliers (matching the first matrix). The number of columns and the second matrix (number of rows) and N adders, by using the first matrix column vectors and the second matrix The row vectors are input into the arithmetic unit sequentially in an "element stream" manner. Each clock cycle completes a set of element-wise multiplications and intermediate summations, ultimately completing the dot product operation of a single set of row and column vectors within N clock cycles. Although the overall computation cycle is extended to [number missing], [details missing]. However, resource consumption is only related to the intermediate dimension N of the matrix, not the product of the final dimensions of the matrix (i.e., ).

[0082] This architecture design exhibits three core advantages in multi-channel signal processing scenarios: First, it significantly improves resource utilization. In signal processing, the matrix dimension often increases with the number of channels (e.g., the covariance matrix dimension for 128 channels is...). Traditional parallel multipliers consume resources that increase quadratically with the dimension, easily exceeding the resource limits of the selected processor (such as FPGA or DSP). In contrast, the pulsating architecture of this invention consumes resources only linearly with the number of channels. Taking 128 channels as an example, it reduces the need for multipliers and adders by approximately 128 times compared to traditional solutions, effectively adapting to medium- and high-order matrix operations and reserving sufficient resources for subsequent QR decomposition and other modules. Secondly, it offers stronger data bandwidth adaptability. The multi-channel waveform data output from the antenna receiver is mostly "stream data" (e.g., output point-by-point in snapshot order). Traditional matrix multiplication requires buffering the complete matrix before operation, resulting in significant data latency. Pulsating multiplication, however, can directly handle stream data input, processing the first matrix... column vectors and the second matrix The row vectors are read sequentially according to the operation sequence, eliminating the need to store the complete matrix. This reduces on-chip RAM resource usage by more than 60% and avoids latency caused by large amounts of data transfer, meeting the "low latency" requirement of real-time signal processing. Thirdly, it offers higher timing stability. In timing analysis on the Vivado platform, traditional parallel multipliers are prone to routing congestion due to a large number of interconnects and signal fan-out. However, the systolic architecture of this invention reduces the interconnects of programmable interconnect resources (IR) by more than 90% by reusing the operation units.

[0083] Step 3: Optimize the Householder mirror transformation method;

[0084] In this invention, the Householder method refers to "Modern Numerical Analysis" published by National Defense Industry Press in September 2004, authors: Lin Xiaolin, Jiang Yaolin, pages 150 - 152.

[0085] There are many algorithms to implement QR decomposition, and their implementation difficulties and costs on hardware are different. Since the "systolic" matrix multiplication module with low time and resource consumption has been constructed in Step 2, this invention selects the Householder mirror transformation method that requires a large number of matrix multiplication operations to perform QR decomposition on the matrix.

[0086] According to the column vectors of the initial non - singular matrix , mirror vector , calculate the Householder unit vector , and , denote the identity matrix corresponding to the dimension of ( ) as , then the first Householder mirror transformation matrix can be obtained, and , is the transpose of

[0091] .

[0087] This invention designs covariance matrices and orthogonal matrices for QR decomposition based on the Householder mirror transformation for the basic reversible covariance matrix (real (complex) non - singular matrix) of array signals. Among them, the covariance matrix is a matrix containing noise components. For the convenience of explanation, denote the covariance matrix as . Since the covariance matrix is a square matrix with equal number of rows and columns, the number of rows p is equal to the number of columns q, and n is used to represent it in the QR decomposition calculation process, that is, n = p = q. Then there is covariance matrix . Denote the orthogonal matrix as , and the is also a square matrix with equal number of rows and columns. When satisfying , is the transpose of , represents - order identity matrix. That is, perform Householder transformation on the column vectors of the real (complex) non - singular matrix , and left - multiply by the mirror transformation matrix times to obtain the non - singular upper triangular matrix , as shown in formula (1).

[0088] .

[0089] in, It is the product of all n mirror transformation matrices. However, It is an orthogonal matrix The transpose of is expressed by formula (2):

[0090] .

[0091] The Householder mirror transformation array of the present invention is according to Figure 6 The method shown yields the result for non-singular matrices. The The non-zero column vector of the second cycle In two-dimensional space, it can be transformed into a unit vector with a given mirror direction. Vectors in the same direction ,Right now Intuitively achievable , Representing vectors In Householder unit vector The projection in the direction satisfies formula (3).

[0092] .

[0093] In this invention, That is, the first Householder mirror transformation array in the next cycle for transpose, For the first The identity matrix of the second cycle, according to Figure 6 The geometric projection relationship shown yields the Householder unit vector. The calculation expression satisfies formula (4).

[0094] .

[0095] This invention designs sub-modules, as listed in Table 1, to calculate the mirror transformation matrix required by each module. and .

[0096] Table 1 Householder Mirror Transformation Module Design

[0097]

[0098] Molecular calculation module: based on the input and calculate The molecular part.

[0099] Vector magnitude calculation module: Calculates the magnitude of the input molecule vector.

[0100] Vector normalization calculation module: Normalizes the input vector by its magnitude.

[0101] Matrix calculation module: based on the input Calculation required .

[0102] According to Table 2, this invention corresponds to an FPGA chip, and is achieved through, as follows: Figure 7 The Householder mirror transformation module shown calculates the Householder mirror transformation matrix.

[0103] The Householder mirror transformation module is named The input is Corresponding column vector and Corresponding column vector Soon Transform into The direction is specified, and the output is the corresponding mirror transformation matrix. . The module contains Calculation module and Matrix calculation module . Module completed The calculation. Module completed The calculation.

[0104] exist In the module, firstly by Molecular calculation module calculate The molecule part is then calculated by the vector magnitude calculation module. calculate The molecular modulus is finally calculated by the vector normalization module. Calculate the normalized result And by latch module Latch output .

[0105] exist In the module, through input calculate The calculation process is divided into diagonal elements. off-diagonal elements Calculation in two parts. Diagonal elements off-diagonal elements ,in Let i be the Householder unit vector for the i-th iteration. Let be the Householder unit vector for the s-th iteration.

[0106] Step 4: Fast QR matrix decomposition in a single loop;

[0107] The overall block diagram of the QR-cycle module design method based on mirror transformation in PFGA chip design according to this invention is as follows: Figure 8 As shown, Input is the input pin and Output is the output pin. The QR-cycle module based on mirror transformation is used to quickly complete a single loop operation of QR matrix decomposition. All QR-cycle modules are triggered by a valid rising edge. Input1 is... OK The non-singular sampling covariance matrix of the column Also known as module (1), where n represents the matrix The number of rows and columns is equal, so both are represented by 'n'. The same applies to subsequent variables; Input2 is... The column vector to be transformed by mirroring Also known as module (2); Input3 is the column vector Unit column vectors of the same dimension Also known as module (3); Input4 is the first input. OK column identity matrix Also known as module (4); it serves as the input for the cumulative multiplication of the mirror transformation matrix in subsequent loops. The multipliers shown in the figure are (8) and (12), both of which use the "pulsating" matrix multiplier based on the Householder mirror transformation matrix described in step three. The multiplier time is... The matrices corresponding to the separate output module (7) and the separate output timing module (10) in the diagram are the left matrices when multiplying matrices, and the matrices corresponding to the separate output timing modules (6) and (11) are the right matrices when multiplying matrices. In this invention, the separate output timing method refers to outputting each row element of the matrix in a row-by-row serial manner for the matrix to be processed, and outputting data through a peak output mode with a timing pulse at a specific time to ensure clock synchronization. In this invention, the separate output timing method refers to outputting each row element of the matrix in a row-by-row serial manner for the matrix to be processed, and outputting data through a peak output mode with a timing pulse at a specific time to ensure clock synchronization.

[0108] First, in module (5), Vector and Vector Seeking After Obtain the mirror transformation matrix This is how long it has taken. .then, Time spent The column vector data obtained from the separate module (7) is compared with... The row vector data obtained after passing through the row output timing module (6) is multiplied by the "pulsating" matrix multiplier (8) to obtain Output1, which corresponds to (13). , Input1 serves as the input for the next module (1). Module (9)... The Extract the column and the first Setting rows to zero takes time Output2, i.e., module (14), is obtained. , Input2 serves as the input for the next module (2).

[0109] The column vector data obtained by the timing module (10) and the row vector data obtained by the timing module (11) after the row output of module (4) are synchronously entered into the "pulsating" matrix multiplier (12) and multiplied to obtain Output3, which serves as the input Input4 (15) of the next module (4). The function of all the timing modules in the figure is to synchronize the time consumption of the four links, Input1 to Output1, Input2 and Input3 to Output1, Input2 and Input3 to Output2, and Input4 to Output3, through the peak output mode of the timing module. The time consumption of each link is 1. .

[0110] Step 5: Decompose the top-level loop pipeline using the QR matrix;

[0111] This invention is for 1-th order matrix The decomposition requires reuse. The QR-cycle module in step four. For QR matrix decomposition, the... The outputs output1, output2, and output3 of the next loop are respectively the outputs of the [number]th [cycle]. The loop iterates through input1, input2, and input4. The input 'input3' in the next loop is the corresponding Column vectors. This QR matrix decomposition uses a top-level loop design in a serial stepping form and maximizes the reuse of the QR-cycle module.

[0112] Based on this, the present invention is based on the following Figure 9 The top-level loop operation control module shown constructs a QR matrix decomposition top-level loop pipeline. Each loop step uses 4 inputs and 3 outputs. Except for the first loop where input4 is... Apart from the above steps, all other inputs are processed in a cascading mode. After the cumulative multiplication in the second iteration, a non-singular upper triangular matrix can be obtained at Output1. At Output3, we get After transposing, an orthogonal matrix can be obtained. ,satisfy ,in , The Output1 values ​​during the intermediate process (excluding the final loop output) are respectively Output2 are respectively Output3 are respectively .

[0113] In this invention, a digital front-end module for receiving multi-channel information is designed on an FPGA chip incorporating software-defined radio (FPGA software). Within the digital front-end module, through steps three to five, Householder-based mirror transformation is completed. non-singular matrix of order This invention employs a fast QR matrix decomposition method, culminating in hardware verification of the fast QR decomposition algorithm. By designing the overall pipeline logic and loop operations, this invention converts resource consumption into timing consumption, enabling rapid processing and accurate decomposition of digital information from a multi-channel digital front-end on an FPGA chip, effectively saving on-chip resources. Furthermore, this invention exhibits excellent scalability, supporting 64- to 128-bit high-precision fixed-point number formats, with a maximum data matrix order of 128. Example: Hardware solution verification of fast decomposition algorithm

[0114] To verify the feasibility of the method designed in this invention, when this invention is specifically implemented on an FPGA chip, the hardware platform chip selected is xcvu13p-fhgb2104-2-i, with an operating frequency of 250MHz.

[0115] The "pulsating" matrix multiplier module designed in this invention optimizes row and column vector calculations. By using the idea of ​​inputting data in rows and columns, it performs multiplication and addition of specific elements. Theoretically, this can save resources at the cost of clock cycles, effectively conserving resources. Figure 10 As shown in the figure, LUTs represent the basic units for building combinational logic, using 20% ​​of the total LUT resources; Block RAM represents block random access memory, occupying 0.5% of the total; and FPGAs represent programmable digital signal processors, using 17% of the total. The resource usage is relatively low. It can be seen that compared with serial data streams, this method converts serial data streams into parallel data streams, which can save a lot of resources.

[0116] This invention presents a fast QR decomposition algorithm based on mirror transformation. It employs a "pulsating" matrix multiplication method and designs a top-level loop pipeline for QR matrix decomposition, which can convert serial data streams into parallel data streams, effectively improving computational efficiency. Figure 11 The comparison diagram of the 8th-order matrix multiplier module shows that, compared with the traditional method of parallel computation of all matrix elements, this method can save 20% of resource consumption and improve the computational efficiency by 35 times.

[0117] To ensure the accuracy of the method of this invention, this embodiment decomposes the 8th-order matrix in two ways: one is by using the qr function in MATLAB, and the other is by using an FPGA-based systolic multiplier and an improved QR decomposer. Finally, we compare and analyze the Q and R matrices obtained by MATLAB using the qr function with the Q and R matrices obtained by FPGA simulation.

[0118] Error analysis of the difference between the two sets of data, such as Figure 12 As shown in Figure 13: Among them, Figure 12 The horizontal axis represents the index of each element in the decomposed Q matrix (an 8x8, 64-order matrix), and the vertical axis represents the difference between the calculated result and the theoretical value. It can be seen that the maximum error of the Q matrix is ​​controlled within ±0.05. Figure 13 The horizontal axis represents the index of each element in the decomposed R matrix (an 8x8, 64-order matrix), and the vertical axis represents the difference between the calculated result and the theoretical value. It can be seen that the maximum error of the R matrix is ​​controlled within ±0.005.

[0119] Therefore, the QR matrix decomposition results based on FPGA are very close to the theoretical results, and can be said to be very accurate.

[0120] Regarding the resource consumption of this invention, taking 8th-order matrix factorization as an example, the resource data report for a single loop operation of QR matrix factorization by the QR-cycle module is shown in Table 2. Based on the top-level loop pipeline for QR matrix factorization designed in step five of this invention, for an 8th-order matrix... The QR decomposition requires reusing the QR-cycle module 7 times, and the resource consumption is fixed as shown in Table 2.

[0121] Table 2. Resources consumed by the QR-cycle module in completing a single loop operation of QR matrix decomposition.

[0122]

[0123] Regarding clock delay, this invention sets the clock period to 250MHz. Verification shows that a single QR-cycle can be completed in 230 clock cycles. Therefore, after 1610 clock cycles, the QR decomposition of an 8th-order matrix can be completed, yielding the corresponding orthogonal matrix. Non-singular upper triangular matrix .

[0124] Specifically, when solving for 64 output elements by multiplying two matrices, the resource consumption and clock latency of the multipliers and adders corresponding to the traditional parallel multiplication and the "pulsating" matrix multiplication designed in this invention are shown in Table 3. It can be seen that although the "pulsating" matrix multiplication incurs an additional time cost of 8 clock delays, it can be exchanged for nearly 8 times the resource savings, which can free up more resource margin for the entire system.

[0125] Table 3. Comparison of resource consumption and clock latency between the two matrix multiplication methods.

[0126]

[0127] As can be seen, the fast QR matrix factorization algorithm based on mirror transformation designed in this invention was implemented with a clock cycle of 250MHz on a hardware platform with chip model xcvu13p-fhgb2104-2-i. This invention can perform QR decomposition of an 8th-order matrix at high speed and with accurate and reliable results. Theoretically, it can be applied to the decomposition of matrices up to the 128th order and is suitable for engineering applications such as multi-channel array signal processing and real-time communication.

Claims

1. A highly efficient QR matrix decomposition method based on FPGA for implementing pulsation matrices, wherein a digital front-end module for software-defined radio information is jointly constructed using FPGA chips and FPGA software; characterized in that: The digital front-end module includes a pulsating multiplier and an improved QR decomposer; the design steps of the digital front-end module include: Step 1: Configure the handshake and collaboration mechanism for the FPGA chip; when When the rising edge is valid, it passes through the multiplexer port. The input waveform digital information is stored in the data loading register. Inside; when When the rising edge is valid, the waveform digital information to be output on the FPGA chip is stored in the data output register. middle; Step 2: Design an optimized timing sequence for systolic matrix multiplication on the FPGA chip; The waveform digital information in the waveform digital information set is arranged into a row according to the waveform digital information of the same channel, and the waveform digital information of the same snapshot is arranged into a column to form the waveform-row-column sorting. After transposing the waveform-row-column sort, a waveform-row-column-transpose is formed. The waveform-row-column sorting is called the front matrix, and the waveform-row-column-transpose is called the back matrix; multiplying the elements of each column in the front matrix with the corresponding elements of each row in the back matrix yields a single addition unit. The column and row elements of the two matrices are traversed sequentially, and then the addition units are accumulated to obtain the pulsation matrix; Step 3: Optimize the Householder mirror transformation method; Based on the initial non-singular matrix column vector Mirror vector Calculate the Householder unit vector ,and ;Will Corresponding dimensions The identity matrix is ​​denoted as Then the first Householder mirror transformation array can be obtained. ,and , for transpose; No. The Householder mirror transformation matrix in the next cycle is , for transpose; Step 4: Fast QR matrix decomposition in a single loop; The QR-cycle module based on mirror transformation, designed on the PFGA chip, is used to quickly complete a single loop operation of QR matrix decomposition; all QR-cycle modules are triggered by a valid rising edge. Step 5: Decompose the top-level loop pipeline using the QR matrix; The QR matrix decomposition adopts a top-level loop design in a serial stepping manner and reuses the QR-cycle module to the greatest extent.

2. The efficient QR matrix decomposition method based on FPGA for implementing pulsating matrices according to claim 1, characterized in that: The timing flow for the column-by-column calculation of the pulsating matrix multiplication in step two is as follows: clock signal Input data valid signal With output data valid signal All are valid only when triggered by the rising edge; for Each output element Based on the row-out module and the column-out module, the matrix is ​​used in sequence. Each column With matrix each line Perform element-wise multiplication on each addition unit to obtain... Then by accumulating each time Each output element is obtained by value. The result; Accumulation operations are evenly distributed across the time dimension. clock cycles Each clock cycle The corresponding intermediate accumulated value is ; for and Matrix multiplication only requires The entire addition and accumulation operation can be completed in one clock cycle; with the input data valid signal After the rising edge, use clock cycles To ensure timing consistency during computation, the following steps are performed. The final result is the output three clock cycles after the first clock cycle. And simultaneously pull up the output valid signal. .

3. The efficient QR matrix decomposition method based on FPGA for implementing pulsating matrices according to claim 1, characterized in that: In step three, the Householder mirror transformation matrix is ​​calculated using the Householder mirror transformation. The Householder mirror transformation module is named The input is Corresponding column vector and Corresponding column vector Soon Transform into The direction is specified, and the output is the corresponding mirror transformation matrix. ; The module contains Calculation module and Matrix calculation module ; Module completed Calculation; Module completed Calculation; exist In the module, firstly by Molecular calculation module calculate The molecule part is then calculated by the vector magnitude calculation module. calculate The molecular modulus is finally calculated by the vector normalization module. Calculate the normalized result And by latch module Latch output ; exist In the module, through input calculate The calculation process is divided into diagonal elements. off-diagonal elements Two-part calculation; diagonal elements off-diagonal elements ,in Let i be the Householder unit vector for the i-th iteration. Let be the Householder unit vector for the s-th iteration.

4. The efficient QR matrix decomposition method based on FPGA for implementing systolic matrices according to claim 1, characterized in that: In step four, the QR-cycle module has a built-in Householder mirror transformation submodule and matrix multiplier unit. After being triggered, it first calls the Householder mirror transformation matrix output in step three to perform mirror transformation operation on the input matrix fragment to be decomposed, obtaining the upper triangular matrix fragment and the orthogonal matrix fragment. During the operation, data verification is completed synchronously. A single loop operation is started only when the input data valid signal and the module ready signal are both high. After the operation is completed, the output valid signal is pulled high, and the intermediate QR decomposition results obtained in this loop are latched synchronously to provide input for the top-level loop pipeline. The single loop operation cycle of a single QR-cycle module is time-aligned with the pulsating matrix multiplication cycle in step two to ensure that there is no delay in data transmission.

5. The efficient QR matrix decomposition method based on FPGA for implementing pulsating matrices according to claim 1, characterized in that: In step five, for the QR matrix decomposition, the first... The next loop has three outputs: output1, output2, and output3, which are respectively the outputs of the first, second, and third iterations. The four inputs in the second loop are input1, input2, and input4, and the fourth loop... The input 'input3' for the next loop is the corresponding Column vector.

6. The efficient QR matrix decomposition method based on FPGA for implementing systolic matrices according to claim 1, characterized in that: It possesses high-precision data processing capabilities and flexible scalability, supporting 64 to 128-bit high-precision fixed-point number formats. Different bit width data formats can be switched through parameterized configuration to adapt to software radio signal processing scenarios with different precision requirements. The order of the data matrix can be flexibly configured, supporting matrix decomposition up to order 128. This method converts resource consumption into timing consumption, effectively saving core resources such as on-chip lookup tables and triggers on FPGAs while ensuring decomposition efficiency and accuracy, thus adapting to the application requirements of airborne networks in scenarios with limited hardware resources.

Images