Carry compression circuit, chip, and electronic device

Abstract

This disclosure provides a carry compression circuit, a chip, and an electronic device. The carry compression circuit includes a first selection module and a second selection module. The first selection module is used to perform XOR processing on a first input signal and a second input signal to obtain a first XOR result, select a first carry output signal from the first input signal and a third input signal based on the first XOR result, and output it; and determine an intermediate processing result based on the first XOR result and the third input signal and send it to the second selection module. The second selection module is used to perform XOR processing on the intermediate processing result and a fourth input signal to obtain a second XOR result, and determine a second carry output signal and an XOR output signal based on the second XOR result and the carry input signal, and output them. Embodiments of this disclosure can reduce the number of transistors.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and in particular to a carry compression circuit, chip, and electronic device. Background Technology

[0002] With the continuous development of computer technology, compressors in computer equipment have also been widely used. This compressor is a core arithmetic component in a standard unit library. Its function is to receive 5 input signals and, after processing the 5 input signals, output 3 signals.

[0003] However, the compressors in related technologies have a large number of transistors, and many of these transistors are redundant, resulting in low chip area utilization. How to reduce the number of transistors in the compressor and improve chip area utilization has become an urgent technical problem to be solved. Summary of the Invention

[0004] This disclosure provides a carry compression circuit, a chip, and an electronic device.

[0005] In a first aspect, this disclosure provides a carry compression circuit, which includes: a first selection module and a second selection module connected to the first selection module.

[0006] The first selection module is used to perform XOR processing on the first input signal and the second input signal to obtain a first XOR result, select a first carry output signal from the first input signal and the third input signal according to the first XOR result and output it; and determine the intermediate processing result according to the first XOR result and the third input signal and send it to the second selection module.

[0007] The second selection module is used to perform XOR processing on the intermediate processing result and the fourth input signal to obtain the second XOR result, and to determine and output the second carry output signal and the XOR output signal based on the second XOR result and the carry input signal.

[0008] In some possible implementations, the first selection module is specifically used to perform XOR processing on the first input signal, the second input signal, and the second inverted signal corresponding to the second input signal to obtain a first XOR result; select a first carry output signal from the first input signal and the third input signal according to the first XOR result and output it; and select an intermediate processing result from the third input signal and the third inverted signal corresponding to the third input signal according to the first XOR result and send it to the second selection module.

[0009] The second selection module is specifically used to perform XOR processing on the intermediate processing result, the fourth input signal, and the fourth inverted signal corresponding to the fourth input signal to obtain the second XOR result, and select the second carry output signal and the XOR output signal from the fourth inverted signal, the carry input signal, and the carry input inverted signal corresponding to the carry input signal according to the second XOR result and output them.

[0010] In some possible implementations, the first selection module includes a first XOR processing unit, a first selection inverter, a first selector, and a second selector; the first XOR processing unit is used to perform XOR processing on the first input signal, the second input signal, and the second inverted signal corresponding to the second input signal to obtain a first XOR result; the first selection inverter is used to invert the first XOR result to obtain a first XOR inverted result; the first selector is used to select and output a first carry output signal from the first input signal and the third input signal according to the first XOR result and the first XOR inverted result; the second selector is used to select an intermediate processing result from the third input signal and the third inverted signal corresponding to the third input signal according to the first XOR result and the first XOR inverted result and send it to the second selection module.

[0011] In some possible implementations, the first selector includes a first NMOS transistor, a first PMOS transistor corresponding to the first NMOS transistor, a second NMOS transistor, and a second PMOS transistor corresponding to the second NMOS transistor. The first selector is used to control the first NMOS transistor and the first PMOS transistor to conduct when the first XOR result is low and the first XOR inverted result is high, thereby determining the first input signal as the first carry output signal and outputting it; or, when the first XOR result is high and the first XOR inverted result is low, control the second NMOS transistor and the second PMOS transistor to conduct, thereby determining the third input signal as the first carry output signal and outputting it.

[0012] In some possible implementations, the second selector includes a third NMOS transistor, a third PMOS transistor corresponding to the third NMOS transistor, a fourth NMOS transistor, and a fourth PMOS transistor corresponding to the fourth NMOS transistor. The second selector is used to control the third NMOS transistor and the third PMOS transistor to conduct when the first XOR result is low and the first XOR inverted result is high, thereby determining the third input signal as an intermediate processing result and sending it to the second selection module; or, when the first XOR result is high and the first XOR inverted result is low, control the fourth NMOS transistor and the fourth PMOS transistor to conduct, thereby determining the third inverted signal as an intermediate processing result and sending it to the second selection module.

[0013] In some possible implementations, the second selection module includes a second XOR processing unit, a second selection inverter, a third selector, and a fourth selector; the second XOR processing unit is used to perform XOR processing on the intermediate processing result, the fourth input signal, and the fourth inverted signal to obtain a second XOR result; the second selection inverter is used to invert the second XOR result to obtain a second XOR inverted result; the third selector is used to select and output a second carry output signal from the fourth inverted signal and the carry input inverted signal based on the second XOR result and the second XOR inverted result; the fourth selector is used to select and output an XOR output signal from the carry input signal and the carry input inverted signal based on the second XOR result and the second XOR inverted result.

[0014] In some possible implementations, the third selector includes a fifth NMOS transistor, a fifth PMOS transistor corresponding to the fifth NMOS transistor, a sixth NMOS transistor, and a sixth PMOS transistor corresponding to the sixth NMOS transistor. The third selector is used to control the fifth NMOS transistor and the fifth PMOS transistor to conduct when the second XOR result is low and the second XOR inverted result is high, and to determine the fourth inverted signal as the second carry output signal and output it; or when the second XOR result is high and the second XOR inverted result is low, to control the sixth NMOS transistor and the sixth PMOS transistor to conduct, and to determine the carry input inverted signal as the second carry output signal and output it.

[0015] In some possible implementations, the fourth selector includes a seventh NMOS transistor, a seventh PMOS transistor corresponding to the seventh NMOS transistor, an eighth NMOS transistor, and an eighth PMOS transistor corresponding to the eighth NMOS transistor. The fourth selector is used to control the seventh NMOS transistor and the seventh PMOS transistor to conduct when the second XOR result is low and the second XOR inverted result is high, thereby determining the carry input inverted signal as the XOR output signal and outputting it; or, when the second XOR result is high and the second XOR inverted result is low, to control the eighth NMOS transistor and the eighth PMOS transistor to conduct, thereby determining the carry input signal as the XOR output signal and outputting it.

[0016] In some possible implementations, the second selection module further includes a first output inverter; the first output inverter is used to invert the fourth inverted signal to obtain and output the second carry output signal; or to invert the carry input inverted signal to obtain and output the second carry output signal.

[0017] In some possible implementations, the second selection module further includes a second output inverter; the second output inverter is used to invert the carry input inverted signal to obtain an XOR output signal and output it; or to invert the carry input signal to obtain an XOR output signal and output it.

[0018] In some possible implementations, the first XOR processing unit includes a ninth NMOS transistor, a tenth NMOS transistor, a ninth PMOS transistor corresponding to the ninth NMOS transistor, and a tenth PMOS transistor corresponding to the tenth NMOS transistor. The first input terminal corresponding to the first input signal is connected to the first terminal of the ninth PMOS transistor, the first terminal of the ninth NMOS transistor, the control terminal of the tenth PMOS transistor, and the control terminal of the tenth NMOS transistor. The second input terminal corresponding to the second input signal is connected to the control terminal of the ninth PMOS transistor and the first terminal of the tenth PMOS transistor. The second inverted input terminal corresponding to the second inverted signal is connected to the control terminal of the ninth NMOS transistor and the first terminal of the tenth NMOS transistor. The second terminals of the ninth PMOS transistor, the ninth NMOS transistor, the tenth PMOS transistor, and the tenth NMOS transistor are connected to the output terminal of the first XOR processing unit to output the first XOR result.

[0019] In some possible implementations, the carry compression circuit further includes a second inverter corresponding to the second input signal, a third inverter corresponding to the third input signal, a fourth inverter corresponding to the fourth input signal, and a fifth inverter corresponding to the carry input signal; the second inverter is used to invert the second input signal to obtain a second inverted signal; the third inverter is used to invert the third input signal to obtain a third inverted signal; the fourth inverter is used to invert the fourth input signal to obtain a fourth inverted signal; and the fifth inverter is used to invert the carry input signal to obtain a carry input inverted signal.

[0020] Secondly, this disclosure provides a chip that includes the aforementioned carry compression circuit.

[0021] Thirdly, this disclosure provides an electronic device, which includes the aforementioned chip.

[0022] The carry compression circuit provided in this embodiment includes a first selection module and a second selection module connected to the first selection module. The first selection module processes the input signal to obtain a first carry output signal and generates an intermediate processing result, which is then sent to the second selection module. The second selection module can reuse the intermediate processing result of the first selection module to obtain a second carry output signal and an XOR output signal, and then output them. In this process, because the intermediate processing result is reused, the second selection module can use fewer transistors to complete the signal processing, thereby reducing the number of transistors in the carry compression circuit and improving the chip area utilization rate.

[0023] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0024] The accompanying drawings are provided to further illustrate the present disclosure and form part of the specification. They are used together with the embodiments of the present disclosure to explain the disclosure and do not constitute a limitation thereof. The above and other features and advantages will become more apparent to those skilled in the art from the detailed exemplary embodiments described with reference to the accompanying drawings.

[0025] Figure 1 This is a schematic diagram of a carry compression circuit provided in an embodiment of the present disclosure.

[0026] Figure 2 This is a structural block diagram of a first selection module in a carry compression circuit provided in an embodiment of the present disclosure.

[0027] Figure 3 This is a structural block diagram of a second selection module in a carry compression circuit provided in an embodiment of the present disclosure.

[0028] Figure 4 This is a schematic diagram of a first selection module and a second selection module in a carry compression circuit provided in an embodiment of this disclosure.

[0029] Figure 5 This is a schematic diagram of multiple inverters in a carry compression circuit provided in an embodiment of the present disclosure. Detailed Implementation

[0030] To enable those skilled in the art to better understand the technical solutions of this disclosure, exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments of this disclosure to aid understanding. These should be considered merely exemplary. Therefore, those skilled in the art should recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this disclosure. Similarly, for clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.

[0031] Where there is no conflict, the various embodiments of this disclosure and the features thereof in the embodiments may be combined with each other.

[0032] As used herein, the term “and / or” includes any and all combinations of one or more related enumerated entries.

[0033] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular forms “a” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that when the terms “comprising” and / or “made of” are used in this specification, they specify the presence of features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. Words such as “connected” or “linked” are not limited to physical or mechanical connections but can include electrical connections, whether direct or indirect.

[0034] Unless otherwise specified, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted as having an idealized or overly formal meaning, unless expressly so defined herein.

[0035] The technical terms used in the embodiments of this disclosure are explained below.

[0036] Static Complementary CMOS Logic is a logic gate implementation method used in digital integrated circuits. It utilizes the complementary characteristics of PMOS (P-type metal-oxide-semiconductor) and NMOS (N-type metal-oxide-semiconductor) transistors to construct logic gates with low power consumption, high noise margin, and full output swing.

[0037] VDD (Voltage Drain): refers to the "positive power supply" (Digital Power Supply), which is the power supply voltage of the PMOS.

[0038] VSS (Voltage Source): refers to "ground" or "negative power source", which is used as a grounding reference point (such as 0V).

[0039] VNW: refers to N-type well, used to ensure the normal operation of PMOS.

[0040] VPW: refers to P-type substrate / well, used to ensure the normal operation of NMOS.

[0041] With the continuous development of computer technology, compressors have been widely used in computer equipment. A compressor is a core arithmetic component in a standard cell library, capable of receiving five input signals and outputting three signals after processing them. However, compressors in this technology often employ a large number of transistors, many of which are redundant, resulting in low chip area utilization.

[0042] Specifically, in the field of digital integrated circuit technology, the 4-2 compressor with carry input is a core arithmetic component in the standard cell library. Its function is to receive 5 input signals (A, B, C, D, ICI) and output 3 signals (SUM, CO, ICO), where: ICI is the carry input; SUM is the XOR result of the 5 input signals (SUM=A⊕B⊕C⊕D⊕ICI); CO is the final carry output (reflecting the logic state of ≥3 1s in the input); and ICO is the cascaded carry output (used as carry input for the next stage compressor, reflecting the logic state of ≥2 1s in the input).

[0043] For 4-2 compressors with carry, the mainstream 4-2 compressors with carry in the existing standard cell library adopt a CMOS static complementary logic structure. The implementation of its logic architecture includes: 1. SUM path: cascaded through 4 stages of 2-input XOR gates (6 transistors per stage), for a total of 24 MOS transistors; 2. CO path: through 9 2-input AND gates (4 transistors per stage) + 1 9-input OR gate (18 transistors), for a total of 54 MOS transistors; after optimization, 36 transistors can be retained; 3. ICO path: reuse part of the AND gate output of the CO path, and add 3 AND gates (12 transistors) + 1 6-input OR gate (12 transistors), for a total of 24 MOS transistors; 4. Input / output buffer: 8 inverters (16 transistors) to enhance signal drive.

[0044] Based on the above logical architecture, the total number of devices in the compressors of existing related technologies is: 24+36+24+16=100 MOS transistors.

[0045] Based on the above description of the compressor, it can be seen that the compressor of the related technology has significant drawbacks, including the following three aspects: 1. High transistor count: The implementation of the related technology requires 52 transistors, of which 30% are redundant buffer devices, resulting in low chip area utilization. 2. High power consumption: The high number of transistors leads to high static and dynamic power consumption, making it unsuitable for low-power applications. 3. Circuit complexity: The complex structure makes design and manufacturing difficult, hindering high-density integration.

[0046] Based on this, the present disclosure provides a carry compression circuit, a chip, and an electronic device, as detailed in the following embodiments.

[0047] Figure 1 This is a schematic diagram of a carry compression circuit provided in an embodiment of this disclosure. (Refer to...) Figure 1 The carry compression circuit includes: a first selection module 10, and a second selection module 20 connected to the first selection module 10.

[0048] The first selection module 10 is used to perform XOR processing on the first input signal and the second input signal to obtain a first XOR result, select a first carry output signal from the first input signal and the third input signal according to the first XOR result and output it; and determine the intermediate processing result according to the first XOR result and the third input signal and send it to the second selection module 20.

[0049] The second selection module 20 is used to perform XOR processing on the intermediate processing result and the fourth input signal to obtain the second XOR result, and to determine and output the second carry output signal and the XOR output signal based on the second XOR result and the carry input signal.

[0050] Specifically, the input signals of the carry compression circuit provided in this disclosure include: a first input signal, a second input signal, a third input signal, a fourth input signal, and a carry input signal; the first input signal, the second input signal, the third input signal, and the fourth input signal can be understood as four data bits (i.e., data inputs) of the carry compression circuit; the carry input signal can be understood as one carry input (i.e., carry from the lower-order compressor or adder) of the carry compression circuit.

[0051] The output signals of this carry compression circuit include: a first carry output signal, a second carry output signal, and an XOR output signal. The first carry output signal can be a cascaded carry output, used as the carry input signal for the next stage compressor; it reflects a logic state of at least two 1s in the input signals of the carry compression circuit. The second carry output signal can be the final carry output, reflecting a logic state of at least three 1s in the input signals of the carry compression circuit. The XOR output signal can be understood as the XOR result obtained by XORing the first input signal, the second input signal, the third input signal, the fourth input signal, and the carry input signal; for example, the XOR output signal could be SUM.

[0052] The intermediate processing result can be understood as the result generated by the first selection module 10 in determining the first carry output signal and which can be reused by the second selection module 20. In this embodiment, it can be determined whether to use the third input signal as the intermediate processing result based on the first XOR result. If yes, the third input signal is used as the intermediate processing result; if no, the intermediate processing result can be regenerated.

[0053] In some embodiments, regenerating the intermediate processing result includes: performing signal conversion on the third input signal and using the converted third input signal as the intermediate processing result; the signal conversion operation includes, but is not limited to: inverting the third input signal, amplifying the third input signal (increasing the input signal proportionally), and scaling down the third input signal (scaling down the input signal proportionally), etc.

[0054] This disclosure sends the intermediate processing result determined based on the first XOR result and the third input signal to the second selection module 20, so that the second selection module 20 can reuse the intermediate processing result to determine the second carry output signal and the XOR output signal, thereby reducing the processing logic of the second selection module 20 and reducing the number of transistors in the second selection module 20.

[0055] It should be noted that the XOR processing and selection operations in the first selection module 10 and the second selection module 20 can be implemented by transistors, including NMOS transistors and PMOS transistors.

[0056] In some embodiments, determining the second carry output signal and the XOR output signal based on the second XOR result and the carry input signal can be understood as: determining whether to determine the carry input signal as the second carry output signal and / or the XOR output signal based on the second XOR result; if yes (e.g., the second XOR result is high), then the carry input signal is determined as the second carry output signal or the XOR output signal; if no (e.g., the second XOR result is low), then the second carry output signal or the XOR output signal is regenerated.

[0057] In some embodiments, regenerating the second carry output signal includes: performing signal conversion on the fourth input signal or the carry input signal, and using the converted input signal as the second carry output signal; the signal conversion operation includes, but is not limited to: inverting the signal, multiplying or adding the signal with a preset coefficient (such as a gain coefficient), etc.

[0058] In some embodiments, regenerating the XOR output signal includes: performing signal conversion on the fourth input signal or the carry input signal, and using the converted input signal as the XOR output signal; the signal conversion operation includes, but is not limited to: inverting the signal, multiplying the signal with a preset coefficient (such as a gain coefficient), adding or subtracting the signal, etc.

[0059] As can be seen from the above embodiments, the carry compression circuit provided in this disclosure includes a first selection module 10 and a second selection module 20 connected to the first selection module 10. The first selection module 10 processes the input signal to obtain a first carry output signal, and at the same time generates an intermediate processing result and sends it to the second selection module 20. The second selection module 20 can obtain a second carry output signal and an XOR output signal by reusing the intermediate processing result of the first selection module 10. In this process, since the intermediate processing result is reused, the second selection module 20 can use fewer transistors to complete the signal processing, thereby reducing the number of transistors in the carry compression circuit and improving the chip area utilization rate.

[0060] In some embodiments, the first selection module 10 is specifically configured to perform XOR processing on the first input signal, the second input signal, and the second inverted signal corresponding to the second input signal to obtain a first XOR result; select a first carry output signal from the first input signal and the third input signal according to the first XOR result and output it; and select an intermediate processing result from the third input signal and the third inverted signal corresponding to the third input signal according to the first XOR result and send it to the second selection module 20. The second selection module 20 is specifically configured to perform XOR processing on the intermediate processing result, the fourth input signal, and the fourth inverted signal corresponding to the fourth input signal to obtain a second XOR result; and select a second carry output signal and an XOR output signal from the fourth inverted signal, the carry input signal, and the carry input inverted signal corresponding to the carry input signal according to the second XOR result and output them.

[0061] Specifically, the input signals of the carry compression circuit provided in this disclosure include: a first input signal, a second input signal, a third input signal, a fourth input signal, and a carry input signal; the second input signal has a corresponding second inverted signal, the third input signal has a corresponding third inverted signal, the fourth input signal has a corresponding fourth inverted signal, and the carry input signal has a corresponding carry input inverted signal.

[0062] The intermediate processing result can be understood as the result generated by the first selection module 10 in determining the first carry output signal and can be reused by the second selection module 20; the intermediate processing result can be the third input signal or the third inverted signal corresponding to the third input signal; this disclosure sends the third input signal or the third inverted signal as the intermediate processing result to the second selection module 20, so that the second selection module 20 can reuse the intermediate processing result to determine the second carry output signal and the XOR output signal, thereby reducing the processing logic of the second selection module 20 and reducing the number of transistors in the second selection module 20.

[0063] It should be noted that the XOR processing and selection operations in the first selection module 10 and the second selection module 20 can be implemented by transistors, including NMOS transistors and PMOS transistors.

[0064] As can be seen from the above embodiments, the carry compression circuit provided in this disclosure includes a first selection module 10 and a second selection module 20 connected to the first selection module 10. The first selection module 10 processes the input signal to obtain a first carry output signal, and at the same time generates an intermediate processing result and sends it to the second selection module 20. The second selection module 20 can obtain a second carry output signal and an XOR output signal by reusing the intermediate processing result of the first selection module 10. In this process, since the intermediate processing result is reused, the second selection module 20 can use fewer transistors to complete the signal processing, thereby reducing the number of transistors in the carry compression circuit and improving the chip area utilization rate.

[0065] It should be noted that the carry compression circuit provided in this disclosure can be a basic unit for implementing parallel multipliers and carry-lookahead adders, and the number of its components directly affects the integration density and power consumption of the chip; therefore, by reducing the number of transistors in the carry compression circuit, the integration density and power consumption of the chip are reduced.

[0066] In some embodiments, the first selection module includes a first XOR processing unit 101, a first selection inverter 102, a first selector 103, and a second selector 104. The first XOR processing unit 101 is used to perform XOR processing on a first input signal, a second input signal, and a second inverted signal corresponding to the second input signal to obtain a first XOR result. The first selection inverter 102 is used to invert the first XOR result to obtain a first XOR inverted result. The first selector 103 is used to select a first carry output signal from the first input signal and a third input signal according to the first XOR result and the first XOR inverted result, and output it. The second selector 104 is used to select an intermediate processing result from the third input signal and a third inverted signal corresponding to the third input signal according to the first XOR result and the first XOR inverted result, and send it to the second selection module.

[0067] Specifically, Figure 2 This is a structural block diagram of a first selection module in a carry compression circuit provided in an embodiment of the present disclosure, based on... Figure 2As can be seen, the first XOR processing unit 101 of this disclosure is connected to the first selection inverter 102, the first selector 103 and the second selector 104. The first XOR processing unit 101 is used to perform XOR processing on the first input signal, the second input signal and the second inverted signal corresponding to the second input signal to obtain the first XOR result; then, the first XOR result is sent to the first selection inverter 102, the first selector 103 and the second selector 104.

[0068] The first selection inverter 102 is connected to the first selector 103 and the second selector 104. The first selection inverter 102 can be understood as an inverter deployed in the first selection module 10. After receiving the first XOR result, the first selection inverter 102 will invert the first XOR result to obtain the first XOR inverted result corresponding to the first XOR result. Then, the first XOR inverted result is sent to the first selector 103 and the second selector 104. The first selection inverter 102 is composed of at least one NMOS transistor and at least one PMOS transistor.

[0069] The first selector 103 is used to select a first carry output signal from the first input signal and the third input signal based on the first XOR result and the first XOR inversion result, and then outputs the first carry output signal. It should be noted that after being output, the first carry output signal can be used as the input of a downstream or next-stage carry compression circuit (such as a carry input signal), or it can be used as the input of a multiplier or adder.

[0070] The second selector 104 is used to select an intermediate processing result from the third input signal and the third inverted signal corresponding to the third input signal based on the first XOR result and the first XOR inverted result, and send the intermediate processing result to the second selection module for multiplexing.

[0071] As can be seen from the above embodiments, this disclosure uses the same XOR result and its inversion to drive multiple selectors, avoiding redundant logic; by generating reusable intermediate processing results, the second selection module is prevented from repeatedly generating the corresponding signal, further avoiding redundant logic and reducing the number of transistors.

[0072] In some embodiments, the second selection module includes a second XOR processing unit 201, a second selection inverter 202, a third selector 203, and a fourth selector 204; the second XOR processing unit 201 is used to perform XOR processing on the intermediate processing result, the fourth input signal, and the fourth inverted signal to obtain a second XOR result; the second selection inverter 202 is used to invert the second XOR result to obtain a second XOR inverted result; the third selector 203 is used to select and output a second carry output signal from the fourth inverted signal and the carry input inverted signal according to the second XOR result and the second XOR inverted result; the fourth selector 204 is used to select and output an XOR output signal from the carry input signal and the carry input inverted signal according to the second XOR result and the second XOR inverted result.

[0073] Specifically, Figure 3 This is a structural block diagram of a second selection module in a carry compression circuit provided in an embodiment of the present disclosure, based on... Figure 3 As can be seen, the second XOR processing unit 201 of this disclosure is connected to the second selector inverter 202, the third selector 203 and the fourth selector 204. The second XOR processing unit 201 is used to perform XOR processing on the intermediate processing result, the fourth input signal and the fourth inverted signal corresponding to the fourth input signal to obtain the second XOR result; then, the second XOR result is sent to the second selector inverter 202, the third selector 203 and the fourth selector 204.

[0074] The second selection inverter 202 is connected to the third selector 203 and the fourth selector 204. The second selection inverter 202 can be understood as an inverter deployed in the second selection module. After receiving the second XOR result, the second selection inverter 202 inverts the second XOR result to obtain the corresponding second XOR inverted result. Then, it sends the second XOR inverted result to the third selector 203 and the fourth selector 204. In some embodiments, the second selection inverter 202 is composed of at least one NMOS transistor and at least one PMOS transistor.

[0075] The third selector 203 is used to select the second carry output signal from the fourth inverted signal and the carry input inverted signal based on the second XOR result and the second XOR inverted result, and output the second carry output signal. It should be noted that after the second carry output signal is output, it can be used as the input of the downstream or next stage carry compression circuit (such as the carry input signal), or it can be used as the input of the multiplier or adder.

[0076] The fourth selector 204 is used to select an XOR output signal from the carry input signal and the carry input inverted signal based on the second XOR result and the second XOR inverted result, and output the XOR output signal; the XOR output signal can be used as the input of the downstream or next stage carry compression circuit (such as the carry input signal) after the output, or it can be used as the input of the multiplier or adder.

[0077] As can be seen from the above embodiments, the second selection module of this disclosure can determine the second carry output signal and the XOR output signal by reusing intermediate processing results, thereby reducing redundant logic in the second selection module and reducing the number of transistors.

[0078] In some embodiments, the first selector 103 includes a first NMOS transistor, a first PMOS transistor corresponding to the first NMOS transistor, a second NMOS transistor, and a second PMOS transistor corresponding to the second NMOS transistor. The first selector 103 is used to control the first NMOS transistor and the first PMOS transistor to conduct when the first XOR result is low and the first XOR inverted result is high, thereby determining the first input signal as the first carry output signal and outputting it; or to control the second NMOS transistor and the second PMOS transistor to conduct when the first XOR result is high and the first XOR inverted result is low, thereby determining the third input signal as the first carry output signal and outputting it.

[0079] Among them, there is at least one first NMOS transistor, a first PMOS transistor, a second NMOS transistor, and a second PMOS transistor.

[0080] Figure 4 This is a schematic diagram of a first selection module and a second selection module in a carry compression circuit provided in an embodiment of this disclosure, based on... Figure 4 It can be seen that the connection relationship of the first NMOS transistor, the first PMOS transistor, the second NMOS transistor, and the second PMOS transistor included in the first selector 103 is as follows.

[0081] The control stage of the first NMOS transistor is connected to the output terminal of the first select inverter 102. The first select inverter 102 outputs the first XOR inverted result (i.e., Figure 4 The signal (X1B) is sent to the control stage of the first NMOS transistor; the first stage of the first NMOS transistor is connected to the first input signal (i.e., X1B). Figure 4 The first input terminal corresponding to B in the diagram is connected; the second stage of the first NMOS transistor is connected to the output terminal of the first selector 103, outputting the first carry output signal (i.e., Figure 4 (ICO in China).

[0082] The control stage of the first PMOS transistor is connected to the output terminal of the first XOR processing unit 101. The first XOR processing unit 101 outputs the first XOR result (i.e., Figure 4 The signal X1 in the first PMOS transistor is sent to the control stage of the first PMOS transistor; the first stage of the first PMOS transistor is connected to the first input signal (i.e., Figure 4 The first input terminal corresponding to B in the diagram is connected; the second stage of the first PMOS transistor is connected to the output terminal of the first selector 103, outputting the first carry output signal (i.e., Figure 4 (ICO in China).

[0083] The control stage of the second NMOS transistor is connected to the output terminal of the first XOR processing unit 101. The first XOR processing unit 101 outputs the first XOR result (i.e., Figure 4 The X1 signal is sent to the control stage of the second NMOS transistor; the first stage of the second NMOS transistor and the third input signal (i.e. Figure 4 The third output terminal corresponding to C in the first NMOS transistor is connected; the second stage of the second NMOS transistor is connected to the output terminal of the first selector 103, outputting the first carry output signal (i.e., Figure 4 (ICO in China).

[0084] The control stage of the second PMOS transistor is connected to the output terminal of the first select inverter 102, which outputs the first XOR inverted result (i.e., ... Figure 4 The signal (X1B) is sent to the control stage of the second PMOS transistor; the first stage of the second PMOS transistor and the third input signal (i.e. Figure 4 The third output terminal corresponding to C in the first PMOS transistor is connected; the second stage of the second PMOS transistor is connected to the output terminal of the first selector 103, outputting the first carry output signal (i.e., Figure 4 (ICO in China).

[0085] Specifically, based on Figure 4 It can be seen that the first selector 103 is used for the first XOR result (i.e. Figure 4 X1 in the first XOR statement is low, and the first inverted XOR result (i.e., ...) is low. Figure 4 When X1B is high, the first NMOS transistor and the first PMOS transistor are turned on, and the first input signal (i.e., ...) is turned on. Figure 4 B) in the equation is determined to be the first carry output signal (i.e. Figure 4 (ICO in the middle) and output; or in the first XOR result (i.e. Figure 4 X1 in the first XOR statement is high, and the first inverted XOR result (i.e., ...) is high. Figure 4 When X1B is low, the second NMOS transistor and the second PMOS transistor are turned on, and the third input signal (i.e., ...) is turned on. Figure 4 C) is determined as the first carry output signal (i.e. Figure 4 (ICO in the code) and output.

[0086] As can be seen from the above embodiments, this disclosure uses CMOS transmission gates to achieve multiplexing, which reduces the number of transistors compared to the scheme based on static logic gates. Furthermore, this disclosure directly drives the NMOS and PMOS gates of the transmission gates, ensuring synchronous switching operations, low on-resistance, and high signal integrity. In addition, this disclosure adopts an architecture with direct ICO output, where the cascaded carry signal ICO is directly led out from the transmission tube network without the need for inverter driving, thus reducing the number of MOS transistors.

[0087] In some embodiments, the second selector 104 includes a third NMOS transistor, a third PMOS transistor corresponding to the third NMOS transistor, a fourth NMOS transistor, and a fourth PMOS transistor corresponding to the fourth NMOS transistor. The second selector 104 is used to control the third NMOS transistor and the third PMOS transistor to conduct when the first XOR result is low and the first XOR inverted result is high, thereby determining the third input signal as an intermediate processing result and sending it to the second selection module; or to control the fourth NMOS transistor and the fourth PMOS transistor to conduct when the first XOR result is high and the first XOR inverted result is low, thereby determining the third inverted signal as an intermediate processing result and sending it to the second selection module.

[0088] Among them, there is at least one third NMOS transistor, a third PMOS transistor, a fourth NMOS transistor, and a fourth PMOS transistor.

[0089] based on Figure 4 It can be seen that the connection relationship of the third NMOS transistor, the third PMOS transistor, the fourth NMOS transistor, and the fourth PMOS transistor included in the second selector 104 is as follows.

[0090] The control stage of the third NMOS transistor is connected to the output of the first select inverter 102, which outputs the first XOR inverted result (i.e., ... Figure 4 The signal (X1B) is sent to the control stage of the third NMOS transistor; the first stage of the third NMOS transistor and the third input signal (i.e., Figure 4 The third output terminal corresponding to C in the diagram is connected; the second stage of the third NMOS transistor is connected to the output terminal of the second selector 104, outputting the intermediate processing result (i.e., Figure 4 SI in (the context of SI).

[0091] The control stage of the third PMOS transistor is connected to the output terminal of the first XOR processing unit 101. The first XOR processing unit 101 outputs the first XOR result (i.e., Figure 4 The signal X1 in the signal is sent to the control stage of the third PMOS transistor; the first stage of the third PMOS transistor and the third input signal (i.e. Figure 4 The third output terminal corresponding to C in the diagram is connected; the second stage of the third PMOS transistor is connected to the output terminal of the second selector 104, outputting the intermediate processing result (i.e., Figure 4 SI in (the context of SI).

[0092] The control stage of the fourth NMOS transistor is connected to the output of the first XOR processing unit 101. The first XOR processing unit 101 outputs the first XOR result (i.e., Figure 4 The X1 signal is sent to the control stage of the fourth NMOS transistor; the first stage of the fourth NMOS transistor is connected to the third inverted signal (i.e., Figure 4 The output terminal of the CB in the first NMOS transistor is connected to the second NMOS transistor; the second stage of the fourth NMOS transistor is connected to the output terminal of the second selector 104, which outputs the intermediate processing result (i.e., Figure 4 SI in (the context of SI).

[0093] The control stage of the fourth PMOS transistor is connected to the output of the first select inverter 102, which outputs the first XOR inverted result (i.e., Figure 4 The X1B signal is sent to the control stage of the fourth PMOS transistor; the first stage of the fourth PMOS transistor and the third inverted signal (i.e., Figure 4 The output terminal of the CB in the middle is connected; the second stage of the fourth PMOS transistor is connected to the output terminal of the second selector 104, and outputs the intermediate processing result (i.e. Figure 4 SI in (the context of SI).

[0094] Specifically, based on Figure 4 It is understood that the second selector 104 of this disclosure is used for the first XOR result (i.e. Figure 4 X1 in the first XOR statement is low, and the first inverted XOR result (i.e., ...) is low. Figure 4 When X1B is high, the third NMOS transistor and the third PMOS transistor are turned on, and the third input signal (i.e., Figure 4 C) in the middle is determined as the intermediate processing result (i.e. Figure 4 In the SI) and send to the second selection module 20; or in the first XOR result (i.e. Figure 4 X1 in the first XOR statement is high, and the first inverted XOR result (i.e., ...) is high. Figure 4 When X1B is low, the fourth NMOS transistor and the fourth PMOS transistor are turned on, thus turning on the third inverted signal (i.e., Figure 4 CB in the middle is determined as the intermediate processing result (i.e. Figure 4 The SI in the middle is sent to the second selection module 20.

[0095] As can be seen from the above embodiments, this disclosure uses CMOS transmission gates to achieve multiplexing, which reduces the number of transistors compared to the scheme based on static logic gates. Furthermore, this disclosure directly drives the NMOS and PMOS gates of the transmission gates, ensuring synchronous switching actions, low on-resistance, and high signal integrity while stably sending intermediate processing results to the second selection module 20.

[0096] In some embodiments, the third selector 203 includes a fifth NMOS transistor, a fifth PMOS transistor corresponding to the fifth NMOS transistor, a sixth NMOS transistor, and a sixth PMOS transistor corresponding to the sixth NMOS transistor. The third selector 203 is configured to control the fifth NMOS transistor and the fifth PMOS transistor to conduct when the second XOR result is low and the second XOR inverted result is high, and to determine the fourth inverted signal as the second carry output signal and output it; or, when the second XOR result is high and the second XOR inverted result is low, control the sixth NMOS transistor and the sixth PMOS transistor to conduct, and to determine the carry input inverted signal as the second carry output signal and output it. Each of the fifth NMOS transistor, the fifth PMOS transistor, the sixth NMOS transistor, and the sixth PMOS transistor is at least one.

[0097] based on Figure 4 It can be seen that the connection relationship of the fifth NMOS transistor, the fifth PMOS transistor, the sixth NMOS transistor, and the sixth PMOS transistor included in the third selector 203 is as follows.

[0098] The control stage of the fifth NMOS transistor is connected to the output of the second selector inverter 202, which outputs the second XOR inverted result (i.e., Figure 4 The X2B signal is sent to the control stage of the fifth NMOS transistor; the first stage of the fifth NMOS transistor is connected to the fourth inverted signal (i.e., Figure 4 The output terminal of the fifth NMOS transistor is connected to the output terminal of the third selector 203; the second stage of the fifth NMOS transistor is connected to the output terminal of the third selector 203 to output the second carry output signal.

[0099] The control stage of the fifth PMOS transistor is connected to the output of the second XOR processing unit 201. The second XOR processing unit 201 outputs the second XOR result (i.e., Figure 4 The X2 signal is sent to the control stage of the fifth NMOS transistor; the first stage of the fifth PMOS transistor and the fourth inverted signal (i.e. Figure 4 The output terminal of the fifth PMOS transistor is connected to the output terminal of the third selector 203; the second stage of the fifth PMOS transistor is connected to the output terminal of the third selector 203 to output the second carry output signal.

[0100] The control stage of the sixth NMOS transistor is connected to the output of the second XOR processing unit 201. The second XOR processing unit 201 outputs the second XOR result (i.e., Figure 4 The X2 signal is sent to the control stage of the sixth NMOS transistor; the first stage of the sixth NMOS transistor is connected to the inverted carry input signal (i.e., Figure 4 The output terminal of the ICIB in the third selector is connected to the second stage of the sixth NMOS transistor; the second stage of the sixth NMOS transistor is connected to the output terminal of the third selector 203 to output the second carry output signal.

[0101] The control stage of the sixth PMOS transistor is connected to the output of the second selector inverter 202, which outputs the second XOR inverted result (i.e., Figure 4 The X2B signal is sent to the control stage of the sixth PMOS transistor; the first stage of the sixth PMOS transistor is connected to the inverted carry input signal (i.e., Figure 4 The output terminal of the ICIB in the third selector is connected to the second stage of the sixth PMOS transistor; the second stage of the sixth PMOS transistor is connected to the output terminal of the third selector 203 to output the second carry output signal.

[0102] Specifically, the third selector 203 of this disclosure is used for the second XOR result (i.e. Figure 4 X2) is low, and the second XOR inverted result (i.e. Figure 4 When X2B is high, the fifth NMOS transistor and the fifth PMOS transistor are turned on, and the fourth inverted signal (i.e., Figure 4 The DB in the middle is determined as the second carry output signal and output, or the second XOR result (i.e., Figure 4 X2) is high, and the second XOR inverted result (i.e. Figure 4 When X2B is low, the sixth NMOS transistor and the sixth PMOS transistor are turned on, and the carry input inverted signal (i.e., Figure 4 The ICIB in the signal is determined as the second carry output signal and output.

[0103] As can be seen from the above embodiments, this disclosure uses CMOS transmission gates to achieve multiplexing, which reduces the number of transistors compared to the scheme based on static logic gates. Furthermore, this disclosure directly drives the NMOS and PMOS gates of the transmission gates, which can ensure synchronous switching action, low on-resistance, and high signal integrity while accurately outputting the second carry output signal.

[0104] In some embodiments, the fourth selector 204 includes a seventh NMOS transistor, a seventh PMOS transistor corresponding to the seventh NMOS transistor, an eighth NMOS transistor, and an eighth PMOS transistor corresponding to the eighth NMOS transistor. The fourth selector 204 is used to control the seventh NMOS transistor and the seventh PMOS transistor to conduct when the second XOR result is low and the second XOR inverted result is high, thereby determining the carry input inverted signal as an XOR output signal and outputting it; or to control the eighth NMOS transistor and the eighth PMOS transistor to conduct when the second XOR result is high and the second XOR inverted result is low, thereby determining the carry input signal as an XOR output signal and outputting it.

[0105] Among them, there is at least one seventh NMOS transistor, a seventh PMOS transistor, an eighth NMOS transistor, and an eighth PMOS transistor.

[0106] based on Figure 4 It can be seen that the connection relationship of the seventh NMOS transistor, the seventh PMOS transistor, the eighth NMOS transistor, and the eighth PMOS transistor included in the fourth selector 204 is as follows.

[0107] The control stage of the seventh NMOS transistor is connected to the output of the second selector inverter 202, which outputs the second XOR inverted result (i.e., Figure 4 The X2B signal is sent to the control stage of the seventh NMOS transistor; the first stage of the seventh NMOS transistor is connected to the inverted carry input signal (i.e., Figure 4 The output terminal of the ICIB in the seventh NMOS transistor is connected to the output terminal of the fourth selector 204, and the XOR output signal is output.

[0108] The control stage of the seventh PMOS transistor is connected to the output of the second XOR processing unit 201. The second XOR processing unit 201 outputs the second XOR result (i.e., Figure 4 The X2 signal is sent to the control stage of the seventh PMOS transistor; the first stage of the seventh PMOS transistor is connected to the inverted carry input signal (i.e., Figure 4 The output terminal of the ICIB in the circuit is connected; the second stage of the seventh PMOS transistor is connected to the output terminal of the fourth selector 204 to output an XOR output signal.

[0109] The control stage of the eighth NMOS transistor is connected to the output of the second XOR processing unit 201. The second XOR processing unit 201 outputs the second XOR result (i.e., Figure 4 The X2 signal is sent to the control stage of the eighth NMOS transistor; the first stage of the eighth NMOS transistor is connected to the carry input signal (i.e., Figure 4 The carry-out terminal of the ICI in the circuit is connected to the circuit; the second stage of the eighth NMOS transistor is connected to the output terminal of the fourth selector 204 to output an XOR output signal.

[0110] The control stage of the eighth PMOS transistor is connected to the output of the second selector inverter 202, which outputs the second XOR inverted result (i.e., Figure 4 The X2B signal is sent to the control stage of the eighth PMOS transistor; the first stage of the eighth PMOS transistor is connected to the carry input signal (i.e., Figure 4 The carry output terminal of the ICI in the circuit is connected to the circuit; the second stage of the eighth PMOS transistor is connected to the output terminal of the fourth selector 204 to output an XOR output signal.

[0111] Specifically, this disclosure provides a fourth selector 204, used for the second XOR result (i.e. Figure 4 X2) is low, and the second XOR inverted result (i.e. Figure 4 When X2B is high, the seventh NMOS and seventh PMOS transistors are turned on, inverting the carry input signal (i.e., ...). Figure 4 The ICIB in the first XOR statement is determined as the XOR output signal and output; or in the second XOR result (i.e., Figure 4 X2) is high, and the second XOR inverted result (i.e. Figure 4 When X2B is low, the eighth NMOS transistor and the eighth PMOS transistor are turned on, and the carry input signal (i.e., Figure 4 The ICI in the signal is determined as an XOR output signal and output.

[0112] As can be seen from the above embodiments, this disclosure uses CMOS transmission gates to achieve multiplexing, which reduces the number of transistors compared to the scheme based on static logic gates. Furthermore, this disclosure directly drives the NMOS and PMOS gates of the transmission gates, which can ensure synchronous switching action, low on-resistance, and high signal integrity while accurately outputting the XOR output signal.

[0113] In some embodiments, the second selection module further includes a first output inverter 205; the first output inverter 205 is used to invert the fourth inverted signal to obtain a second carry output signal and output it; or to invert the carry input inverted signal to obtain a second carry output signal and output it.

[0114] The first output inverter includes at least one NMOS transistor and at least one PMOS transistor. The first output inverter is used to invert the fourth inverted signal or the carry input inverted signal, and to determine the inverted signal corresponding to the fourth inverted signal or the carry input inverted signal as the second carry output signal and output it.

[0115] based on Figure 4 It can be seen that the third selector 203 outputs a fourth inverted signal (i.e., Figure 4DB in the middle) or carry input inverted signal (i.e. Figure 4 After (ICIB in the middle), DB and ICIB are determined as the output signals that need to be inverted (i.e., Figure 4 The COB in the signal is input to the first output inverter 205 for inversion to obtain the second carry output signal (i.e., the carry-out signal). Figure 4 (CO in the middle), and output the second carry output signal.

[0116] In some embodiments, the second carry output signal can be used as an input to a downstream or next-stage carry compression circuit, or as an input to a multiplier or adder.

[0117] In some embodiments, the second selection module further includes a second output inverter 206; the second output inverter 206 is used to invert the carry input inverted signal to obtain an XOR output signal and output it; or to invert the carry input signal to obtain an XOR output signal and output it.

[0118] The second output inverter 206 includes at least one NMOS transistor and at least one PMOS transistor. The second output inverter 206 is used to invert the carry input inverted signal or the carry input signal, and determine the corresponding inverted signal of the carry input inverted signal or the carry input signal as an XOR output signal and output it.

[0119] based on Figure 4 It can be seen that the fourth selector 204 outputs a carry-in inverted signal (i.e., Figure 4 ICIB in the middle) or carry input signal (i.e. Figure 4 After ICI in the middle, ICIB and ICI are determined as the output signals that need to be inverted (i.e., Figure 4 The SUMB signal is input to the second output inverter 206 for inversion, resulting in an XOR output signal (i.e., the XOR signal). Figure 4 The SUM signal is used to output an XOR output signal.

[0120] It should be noted that, among them, Figure 4 In this context, VNM represents an N-type well; VPM represents a P-type substrate.

[0121] As can be seen from the above embodiments, this disclosure provides a dual-output buffer design that only configures inverters for CO and SUM, thereby reducing the number of transistors while realizing the output buffer layout in the compressor.

[0122] In some embodiments, the first XOR processing unit 101 includes a ninth NMOS transistor, a tenth NMOS transistor, a ninth PMOS transistor corresponding to the ninth NMOS transistor, and a tenth PMOS transistor corresponding to the tenth NMOS transistor; the first input terminal corresponding to the first input signal is connected to the first terminal of the ninth PMOS transistor, the first terminal of the ninth NMOS transistor, the control terminal of the tenth PMOS transistor, and the control terminal of the tenth NMOS transistor; the second input terminal corresponding to the second input signal is connected to the control terminal of the ninth PMOS transistor and the first terminal of the tenth PMOS transistor; the second inverted input terminal corresponding to the second inverted signal is connected to the control terminal of the ninth NMOS transistor and the first terminal of the tenth NMOS transistor; the second terminals of the ninth PMOS transistor, the ninth NMOS transistor, the tenth PMOS transistor, and the tenth NMOS transistor are connected to the output terminal of the first XOR processing unit 101 to output the first XOR result.

[0123] The second inverting input terminal can be understood as the input terminal corresponding to the second inverted signal, which is used to send the second inverted signal to the corresponding PMOS or NMOS transistor.

[0124] In some embodiments, the second XOR processing unit 201 includes an eleventh NMOS transistor, a twelfth NMOS transistor, an eleventh PMOS transistor corresponding to the eleventh NMOS transistor, and a twelfth PMOS transistor corresponding to the twelfth NMOS transistor; the output terminal corresponding to the intermediate processing result is connected to the first terminal of the eleventh PMOS transistor, the first terminal of the eleventh NMOS transistor, the control terminal of the twelfth PMOS transistor, and the control terminal of the twelfth NMOS transistor; the fourth input terminal corresponding to the fourth input signal is connected to the control terminal of the eleventh PMOS transistor and the first terminal of the twelfth PMOS transistor; the fourth inverted input terminal corresponding to the fourth inverted signal is connected to the control terminal of the eleventh NMOS transistor and the first terminal of the twelfth NMOS transistor; the second terminals of the eleventh PMOS transistor, the eleventh NMOS transistor, the twelfth PMOS transistor, and the twelfth NMOS transistor are connected to the output terminal of the second XOR processing unit 201 to output the second XOR result.

[0125] The output terminal corresponding to the intermediate processing result can be the output terminal of the second selector 104; the fourth inverting input terminal can be understood as the input terminal corresponding to the fourth inverting signal, which is used to send the fourth inverting signal to the corresponding PMOS transistor or NMOS transistor.

[0126] As can be seen from the above embodiments, the XOR logic in the carry compression circuit is realized through the first XOR processing unit or the second XOR processing unit, thereby ensuring that the carry compression circuit can accurately generate the corresponding output signal.

[0127] In some embodiments, the carry compression circuit further includes a second inverter corresponding to the second input signal, a third inverter corresponding to the third input signal, a fourth inverter corresponding to the fourth input signal, and a fifth inverter corresponding to the carry input signal; the second inverter is used to invert the second input signal to obtain a second inverted signal; the third inverter is used to invert the third input signal to obtain a third inverted signal; the fourth inverter is used to invert the fourth input signal to obtain a fourth inverted signal; and the fifth inverter is used to invert the carry input signal to obtain a carry input inverted signal.

[0128] The second, third, fourth, and fifth inverters each include at least one PMOS transistor and at least one NMOS transistor.

[0129] Figure 5 This is a schematic diagram of multiple inverters in a carry compression circuit provided in an embodiment of the present disclosure, based on... Figure 5 It can be seen that the second inverter 501 of this disclosure is used to inverter the second input signal (i.e. Figure 5 The A signal in the first part is inverted to obtain the second inverted signal (i.e., ...). Figure 5 (AB in the diagram); the third inverter 502 is used to process the third input signal (i.e., AB in the diagram); Figure 5 The C signal in the middle is inverted to obtain the third inverted signal (i.e., Figure 5 (CB in the middle); the fourth inverter 503, used for the fourth input signal (i.e. Figure 5 The D signal in the middle is inverted to obtain the fourth inverted signal (i.e., Figure 5 (DB in the middle); the fifth inverter 504 is used to process the carry input signal (i.e. Figure 5 The ICI in the middle is inverted to obtain the carry input inverted signal (i.e., Figure 5 (ICIB in the context).

[0130] in, Figure 5 In this context, VDD represents the positive power supply; VSS represents the negative power supply; VNM represents the N-type well; and VPM represents the P-type substrate.

[0131] Based on the above embodiments, this disclosure provides a B-signal-free inverting design, in which the input preprocessing module includes four inverters of type A, C, D, and ICI, thereby reducing the number of MOS transistors by two.

[0132] In some embodiments of this disclosure, the control stage of the MOS transistor (i.e., PMOS transistor or NMOS transistor) can be the gate (G); the first stage of the MOS transistor can be the source (S) or the drain (D); the second stage of the MOS transistor can also be the source (S) or the drain (D); wherein the first stage and the second stage of the same MOS transistor are different.

[0133] In some embodiments, the carry compression circuit includes a first output inverter and a second output inverter. The size of the MOS transistors (PMOS and NMOS transistors) in the first and second output inverters is larger than the size of other MOS transistors included in the carry compression circuit; for example, the size of the MOS transistors in the first and second output inverters is larger than the size of the MOS transistors included in multiple selectors or multiple XOR processing units. By setting larger sizes for the MOS transistors in the first and second output inverters, a second carry output signal and an XOR output signal with stronger driving capability are ensured by the carry compression circuit, ensuring that the downstream processing circuit can receive a stable and accurate second carry output signal and XOR output signal.

[0134] Based on the above one or more embodiments, it can be seen that the carry compression circuit disclosed herein is a 4-2 compressor with carry input based on a transmission tube structure; the compressor disclosed herein adopts a hybrid architecture of "transmission tube core logic + simplified static buffer", with a total of 40 MOS transistors (20 VPW / NMOS and 20 VNW / PMOS), and the composition of each module is shown in Table 1 below.

[0135] Table 1

[0136]

[0137] Based on the overall architecture and device allocation shown in Table 1 above, this disclosure provides a 4-2 compressor with carry input containing only 40 MOS transistors. Through a hybrid architecture of transmission transistor logic and simplified static logic, it reduces the number of devices by 23% while maintaining compatibility with standard cell libraries, and optimizes power consumption and latency characteristics. It is suitable for standard cell integration of high-density, low-power chips.

[0138] In other words, this disclosure provides a 4-2 compressor that uses fewer transistors, has a smaller area, and lower power consumption. The number of MOS transistors in the carry-based 4-2 compressor is reduced from 52 to 40, decreasing the total device size by 23% and reducing the chip area by more than 20%; redundant buffers are eliminated, reducing static power consumption by 30% and total power consumption (static + dynamic) by more than 25%; and the wiring structure is simplified.

[0139] The beneficial effects of the technical solution provided in this disclosure include: 1. Fewer MOS transistors and smaller area: This disclosure uses transmission transistor logic (VPW for NMOS, VNW for PMOS) to replace the traditional CMOS gate-level structure, reducing the number of MOS transistors and the chip area occupied, which is conducive to high-density integration. "VPW for NMOS" means that the source / drain regions of the NMOS transistor are formed on a P-type substrate / P-well (i.e., VPW); "VNW for PMOS" means that the source / drain regions of the PMOS transistor are formed on an N-type well (i.e., VNW). 2. Low power consumption: The transmission transistor structure of this disclosure reduces static power consumption, shortens the signal transmission path, and significantly reduces dynamic power consumption. 3. High speed: This disclosure simplifies the logic hierarchy, resulting in short signal delays and fast operation speed, meeting the requirements of high-frequency scenarios. 4. Reliable logic: The transmission transistor logic topology of this disclosure is clear, reducing the difficulty of device matching and improving circuit stability and operational accuracy.

[0140] Compared with related technologies, the overall structure of the carry compression circuit provided in this disclosure includes, but is not limited to, the following five design elements.

[0141] 1. 40-tube matching topology: It consists of 4 input inverters, 36 transmission tube logic cores, and 2 output inverters, with ICO direct output.

[0142] II. No B-type inverter design: The input preprocessing module contains only four inverters: A, C, D, and ICI, reducing the number of MOSFETs by two.

[0143] III. Direct CO Output Architecture: The cascaded carry signal ICO is directly derived from the transmission tube network, eliminating the need for inverters and reducing the number of MOSFETs by 2.

[0144] IV. Core of 36-tube transmission: The summation, CO, and ICO logics are all implemented through the transmission tube network, without static gate cascading.

[0145] V. Dual-output buffer design: Only CO and SUM are configured with inverters.

[0146] As can be seen from the carry compression circuit described in the above embodiments, this disclosure belongs to the field of digital integrated circuit technology, specifically involving the arithmetic logic unit (ALU) module in the standard cell library. It is suitable for large-scale integrated circuits that require high integration and low power consumption (such as multiplier arrays of CPU, GPU, and AI chips). In particular, it provides a lightweight solution to the problem of redundancy of traditional 4-2 carry compressor devices in the standard cell library. The technical effects achieved by this carry compression circuit include: 1. Circuit consistency: It fully matches the topology of the circuit in the attached drawing and can be directly mass-produced based on the attached drawing; 2. High device efficiency: 40 transistors achieve the function of 52 transistors, and the device utilization rate is improved by 23%; 3. Fast cascading speed: ICO has no buffer delay, and the cascading operation frequency is improved by 15%; 4. Low design risk: It strictly follows the signal path in the attached drawing, and the verification cost is reduced by 30%.

[0147] It should be noted that in some embodiments, the present disclosure can adjust the type ratio of transmission transistors or the output buffer structure, such as changing the combination of some VPW (NMOS) and VNW (PMOS), or increasing the number of inverter stages to enhance the driving capability, all of which can achieve the purpose while maintaining the characteristics of fewer transistors and low power consumption.

[0148] According to embodiments of this disclosure, a chip is also provided that includes the carry compression circuit described above.

[0149] An electronic device comprising the chip described above is also provided according to embodiments of this disclosure.

[0150] It should be noted that the present disclosure provides chips, electronic devices, and the above can all be used to implement the carry compression circuit in any of the embodiments provided in the present disclosure. The corresponding technical solutions and descriptions are as described in the corresponding records in the above embodiments section, and will not be repeated here.

[0151] Those skilled in the art will understand that all or some of the steps, systems, and apparatuses disclosed above, and their functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof. In hardware implementations, the division between functional modules / units mentioned above does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software can be distributed on a computer-readable storage medium, which may include computer storage media (or non-transitory media) and communication media (or transient media).

[0152] Example embodiments have been disclosed herein, and while specific terminology has been used, it is for illustrative purposes only and should be construed as such, and is not intended to be limiting. In some instances, it will be apparent to those skilled in the art that features, characteristics, and / or elements described in connection with particular embodiments may be used alone, or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless otherwise expressly indicated. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the scope of this disclosure as set forth by the appended claims.

Claims

1. A carry compression circuit, characterized by, It includes a first selection module and a second selection module connected to the first selection module; The first selection module is used to perform XOR processing on the first input signal and the second input signal to obtain a first XOR result, and select a first carry output signal from the first input signal and the third input signal according to the first XOR result and output it. And determine the intermediate processing result based on the first XOR result and the third input signal and send it to the second selection module; The second selection module is used to perform XOR processing on the intermediate processing result and the fourth input signal to obtain a second XOR result, and to determine and output a second carry output signal and an XOR output signal based on the second XOR result and the carry input signal.

2. The carry compression circuit of claim 1, wherein, The first selection module is specifically used to perform XOR processing on the first input signal, the second input signal and the second inverted signal corresponding to the second input signal to obtain the first XOR result, and select the first carry output signal from the first input signal and the third input signal according to the first XOR result and output it. And based on the first XOR result, the intermediate processing result is selected from the third input signal and the third inverted signal corresponding to the third input signal and sent to the second selection module; The second selection module is specifically used to perform XOR processing on the intermediate processing result, the fourth input signal, and the fourth inverted signal corresponding to the fourth input signal to obtain the second XOR result, and select the second carry output signal and the XOR output signal from the fourth inverted signal, the carry input signal, and the carry input inverted signal corresponding to the carry input signal according to the second XOR result and output them.

3. The carry compression circuit of claim 2, wherein, The first selection module includes a first XOR processing unit, a first selection inverter, a first selector, and a second selector; The first XOR processing unit is used to perform XOR processing on the first input signal, the second input signal, and the second inverted signal corresponding to the second input signal to obtain the first XOR result; The first selection inverter is used to invert the first XOR result to obtain the first XOR inverted result; The first selector is used to select and output a first carry output signal from the first input signal and the third input signal based on the first XOR result and the first XOR inversion result; The second selector is used to select an intermediate processing result from the third input signal and the third inverted signal corresponding to the third input signal based on the first XOR result and the first XOR inverted result, and send it to the second selection module.

4. The carry compression circuit of claim 3, wherein, The first selector includes a first NMOS transistor, a first PMOS transistor corresponding to the first NMOS transistor, a second NMOS transistor, and a second PMOS transistor corresponding to the second NMOS transistor; The first selector is configured to control the first NMOS transistor and the first PMOS transistor to turn on when the first XOR result is low and the first XOR inverted result is high, thereby determining the first input signal as the first carry output signal and outputting it; or When the first XOR result is high and the first XOR inverted result is low, the second NMOS transistor and the second PMOS transistor are turned on, and the third input signal is determined as the first carry output signal and output.

5. The carry compression circuit of claim 3, wherein, The second selector includes a third NMOS transistor, a third PMOS transistor corresponding to the third NMOS transistor, a fourth NMOS transistor, and a fourth PMOS transistor corresponding to the fourth NMOS transistor; The second selector is configured to control the third NMOS transistor and the third PMOS transistor to conduct when the first XOR result is low and the first XOR inverted result is high, thereby determining the third input signal as the intermediate processing result and sending it to the second selection module; or When the first XOR result is high and the first XOR inverted result is low, the fourth NMOS transistor and the fourth PMOS transistor are turned on, and the third inverted signal is determined as the intermediate processing result and sent to the second selection module.

6. The carry compression circuit according to any one of claims 2 to 5, characterized in that, The second selection module includes a second XOR processing unit, a second selection inverter, a third selector, and a fourth selector; The second XOR processing unit is used to perform XOR processing on the intermediate processing result, the fourth input signal, and the fourth inverted signal to obtain a second XOR result; The second selection inverter is used to invert the second XOR result to obtain the second XOR inverted result; The third selector is used to select the second carry output signal from the fourth inverted signal and the carry input inverted signal based on the second XOR result and the second XOR inverted result, and then output the second carry output signal. The fourth selector is used to select and output an XOR output signal from the carry input signal and the carry input inverted signal based on the second XOR result and the second XOR inverted result.

7. The carry compression circuit according to claim 6, characterized in that, The third selector includes a fifth NMOS transistor, a fifth PMOS transistor corresponding to the fifth NMOS transistor, a sixth NMOS transistor, and a sixth PMOS transistor corresponding to the sixth NMOS transistor; The third selector is used to control the fifth NMOS transistor and the fifth PMOS transistor to conduct when the second XOR result is low and the second XOR inverted result is high, and to determine the fourth inverted signal as the second carry output signal and output it, or When the second XOR result is high and the second XOR inverted result is low, the sixth NMOS transistor and the sixth PMOS transistor are turned on, and the carry input inverted signal is determined as the second carry output signal and output.

8. The carry compression circuit according to claim 6, characterized in that, The fourth selector includes a seventh NMOS transistor, a seventh PMOS transistor corresponding to the seventh NMOS transistor, an eighth NMOS transistor, and an eighth PMOS transistor corresponding to the eighth NMOS transistor; The fourth selector is used to control the seventh NMOS transistor and the seventh PMOS transistor to conduct when the second XOR result is low and the second XOR inverted result is high, thereby determining the carry input inverted signal as the XOR output signal and outputting it; or When the second XOR result is high and the second XOR inverted result is low, the eighth NMOS transistor and the eighth PMOS transistor are turned on to determine the carry input signal as the XOR output signal and output it.

9. The carry compression circuit according to claim 7, characterized in that, The second selection module also includes a first output inverter; The first output inverter is used to invert the fourth inverted signal to obtain the second carry output signal and output it. or The carry-in inverted signal is inverted to obtain the second carry-out output signal, which is then output.

10. The carry compression circuit according to claim 8, characterized in that, The second selection module also includes a second output inverter; The second output inverter is used to invert the carry input inverted signal to obtain the XOR output signal and output it. or The carry input signal is inverted to obtain the XOR output signal and then output.

11. The carry compression circuit according to claim 3, characterized in that, The first XOR processing unit includes a ninth NMOS transistor, a tenth NMOS transistor, a ninth PMOS transistor corresponding to the ninth NMOS transistor, and a tenth PMOS transistor corresponding to the tenth NMOS transistor; The first input terminal corresponding to the first input signal is connected to the first terminal of the ninth PMOS transistor, the first terminal of the ninth NMOS transistor, the control terminal of the tenth PMOS transistor, and the control terminal of the tenth NMOS transistor; The second input terminal corresponding to the second input signal is connected to the control electrode of the ninth PMOS transistor and the first electrode of the tenth PMOS transistor; The second inverting input terminal corresponding to the second inverting signal is connected to the control terminal of the ninth NMOS transistor and the first terminal of the tenth NMOS transistor; The second terminals of the ninth PMOS transistor, the ninth NMOS transistor, the tenth PMOS transistor, and the tenth NMOS transistor are connected to the output terminal of the first XOR processing unit to output the first XOR result.

12. The carry compression circuit according to any one of claims 2 to 5, characterized in that, The carry compression circuit further includes a second inverter corresponding to the second input signal, a third inverter corresponding to the third input signal, a fourth inverter corresponding to the fourth input signal, and a fifth inverter corresponding to the carry input signal; The second inverter is used to invert the second input signal to obtain the second inverted signal; The third inverter is used to invert the third input signal to obtain the third inverted signal; The fourth inverter is used to invert the fourth input signal to obtain the fourth inverted signal; The fifth inverter is used to invert the carry input signal to obtain the inverted carry input signal.

13. A chip, characterized in that, The chip includes a carry compression circuit as described in any one of claims 1-12.

14. An electronic device, characterized in that, The electronic device includes the chip as described in claim 13.

Images