Laterally diffused metal-oxide semiconductor devices and their manufacturing methods

Abstract

This invention relates to a laterally diffused metal-oxide-semiconductor device and its manufacturing method. The device includes: a bottom semiconductor layer; a buried dielectric layer located on the bottom semiconductor layer; a well region of a second conductivity type; a source region located in the well region of the second conductivity type; a drain region; a drift region; a gate; a first trench structure extending downward from the well region of the second conductivity type below the gate to the buried dielectric layer or the bottom semiconductor layer, including a first dielectric layer located on the inner surface of the first trench, and a first conductive material filling the first trench, the first conductive material being electrically connected to the gate; and a first doped region having a first conductivity type located below the first trench structure, the top of the first doped region being in direct contact with the bottom of the buried dielectric layer or the bottom of the first trench structure. This invention can reduce the on-resistance of the device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and in particular to a laterally diffused metal oxide semiconductor device, and also to a method for manufacturing a laterally diffused metal oxide semiconductor. Background Technology

[0002] With the development of high-voltage power devices, the performance of LDMOS (Laterally Diffused Metal-Oxide-Semiconductor Field-Effect Transistor), a core device in monolithic integrated power ICs (integrated circuits), is particularly important, and optimizing the on-resistance is key to improving LDMOS performance. Exemplary methods for optimizing on-resistance include RESURF (reducing surface electric field) and surface superjunctions. Summary of the Invention

[0003] Therefore, it is necessary to provide a laterally diffused metal-oxide-semiconductor device and its manufacturing method that reduce the on-resistance of the device through a novel structure.

[0004] A laterally diffused metal-oxide-semiconductor device includes: a bottom semiconductor layer having a second conductivity type; a buried dielectric layer located on the bottom semiconductor layer; a well region of the second conductivity type; a source region located in the well region of the second conductivity type; a drain region; a drift region having a first conductivity type and at least partially located between the source region and the drain region; the first conductivity type and the second conductivity type are opposite conductivity types; a gate located above the region between the source region and the drain region; a first trench structure extending downward from the well region of the second conductivity type below the gate to the buried dielectric layer or the bottom semiconductor layer, including a first dielectric layer located on the inner surface of the first trench and a first conductive material filling the first trench, the first conductive material being electrically connected to the gate; and a first doped region having a first conductivity type located below the first trench structure, the top of the first doped region being in direct contact with the bottom of the buried dielectric layer or the bottom of the first trench structure.

[0005] In the aforementioned laterally diffused metal-oxide-semiconductor (MOS) device, the conductive material in the trench of the channel region is electrically connected to the gate and will induce the same potential as the gate. This inverts the second conductivity type well region in a portion of the area surrounding the trench, thereby improving the device's current carrying capacity and reducing its on-resistance. The first conductivity type region below the bottom of the trench forms an inverted PN junction with the bottom semiconductor layer, which prevents the gate current from flowing to the bottom semiconductor layer.

[0006] In one embodiment, the first conductivity type is N-type and the second conductivity type is P-type.

[0007] In one embodiment, the first conductive material is polycrystalline silicon of a first conductivity type.

[0008] In one embodiment, the laterally diffused metal-oxide-semiconductor device further includes: a second trench structure extending downward from the drift region to the buried dielectric layer or the bottom semiconductor layer, the second trench structure including a second dielectric layer located on the inner surface of the second trench and a second conductive material filling the second trench; and a second doped region having a first conductivity type located below the second trench structure, the top of the second doped region being in direct contact with the bottom of the buried dielectric layer or the bottom of the second trench structure.

[0009] In one embodiment, the second conductive material is polycrystalline silicon of a first conductivity type.

[0010] In one embodiment, the second trench structure has multiple second trench structures, and each second trench structure is arranged to form an array structure.

[0011] In one embodiment, the row direction of the array structure is the direction of the conductive channel length, and the column direction is the direction of the conductive channel width.

[0012] In one embodiment, the laterally diffused metal-oxide-semiconductor device further includes: a field oxide layer disposed on the drift region; and multiple conductive equipotential strips, each of which extends along the width direction of the conductive channel and passes downward through the field oxide layer via a conductive structure, and is electrically connected to a second conductive material in a row of second trench structures below.

[0013] In one embodiment, each of the conductive equipotential bars is connected to zero potential when the laterally diffused metal-oxide-semiconductor device is off, and to a high level when it is on.

[0014] In one embodiment, the conductive equipotential strip is made of metal.

[0015] In one embodiment, the laterally diffused metal-oxide-semiconductor device further includes: a substrate lead-out region having a second conductivity type, disposed on the side of the source region away from the gate, wherein the doping concentration of the substrate lead-out region is greater than the doping concentration of the second conductivity type well region; and a first conductivity type well region connected to the drift region, wherein the drain region is located in the first conductivity type well region, wherein the doping concentration of the drain region is greater than the doping concentration of the first conductivity type well region.

[0016] A method for manufacturing a laterally diffused metal-oxide-semiconductor device includes: obtaining a wafer comprising a bottom semiconductor layer, a buried dielectric layer, and a top semiconductor layer stacked sequentially, the bottom semiconductor layer having a second conductivity type; forming a trench extending downward from the top semiconductor layer to the buried dielectric layer or the bottom semiconductor layer; forming a first conductivity type region in the bottom semiconductor layer below the trench by ion implantation, the top of the first conductivity type region being in direct contact with the bottom of the buried dielectric layer; the first conductivity type and the second conductivity type being opposite conductivity types; and forming a trench... A dielectric layer is formed on the inner surface of the trench; a conductive material is filled in the trench where the dielectric layer is formed; a second conductivity type well region is formed in the top semiconductor layer; the trench has multiple trenches, some or all of which penetrate the second conductivity type well region; a gate is formed above some or all of the trenches, and the conductive material is electrically connected to the gate; a source region and a drain region are formed on both sides of the trench, respectively, and the source region is formed in the second conductivity type well region; wherein, the top semiconductor layer includes a first conductivity type drift region, and the drift region is at least partially located between the source region and the drain region.

[0017] In the above-described method for manufacturing a laterally diffused metal-oxide-semiconductor device, the first conductive material in the second conductivity type well region below the gate (i.e., the first conductive material in the channel region) is electrically connected to the gate. The first conductive material will sense the same potential as the gate, inverting a portion of the second conductivity type well region around the first trench structure, thereby improving the device's current carrying capacity and reducing its on-resistance. The first doped region below the bottom of the first trench structure forms an inverted PN junction with the bottom semiconductor layer, which can prevent the gate current from flowing to the bottom semiconductor layer.

[0018] In one embodiment, a portion of the trenches extends through the drift region, and the trenches are arranged to form an array structure; after the step of filling the trenches in which the dielectric layer is formed with conductive material and before the step of forming the second type of conductive well region, the step of forming a field oxygen layer is further included.

[0019] In one embodiment, the method further includes: etching the field oxide layer to form a plurality of through-holes of conductive material extending to the bottom of each trench; forming a conductive structure in the through-holes; and forming a plurality of conductive equipotential strips on the field oxide layer, each conductive equipotential strip extending along the width direction of the conductive channel and electrically connected to the conductive material in a row of trenches below through the conductive structure. Attached Figure Description

[0020] To better describe and illustrate embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more accompanying drawings. Additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed inventions, the currently described embodiments and / or examples, or the best mode of these inventions as currently understood.

[0021] Figure 1 This is a perspective view of a laterally diffused metal-oxide-semiconductor device according to an embodiment of this application.

[0022] Figure 2 This is a perspective view of a laterally diffused metal-oxide-semiconductor device according to another embodiment of this application.

[0023] Figure 3 This is a perspective view of a laterally diffused metal-oxide-semiconductor device in another embodiment of this application.

[0024] Figure 4 This is a flowchart of a method for manufacturing a laterally diffused metal-oxide-semiconductor device according to an embodiment of this application.

[0025] Figures 5a to 5e This is an example of an implementation. Figure 4 The diagram shows a cross-sectional structure of the device during the fabrication of LDMOS using the method shown. Detailed Implementation

[0026] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0027] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0028] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0029] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0030] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0031] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of ideal embodiments (and intermediate structures). Thus, variations in the shape shown can be anticipated due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing processes. For example, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shapes of the regions of the device and are not intended to limit the scope of the invention.

[0032] The semiconductor terminology used in this article is the technical terminology commonly used by those skilled in the art. For example, for P-type and N-type impurities, in order to distinguish the doping concentration, P+ type represents heavily doped P-type, P type represents moderately doped P-type, P- type represents lightly doped P-type, N+ type represents heavily doped N-type, N type represents moderately doped N-type, and N- type represents lightly doped N-type.

[0033] Figure 1 This is a perspective view of a laterally diffused metal-oxide-semiconductor (LDMOS) device in one embodiment. In one embodiment of this application, the LDMOS is an SOI LDMOS, including a bottom semiconductor layer 101, a buried dielectric layer 114, a second conductivity type well region 104, a source region 106, a drain region 108, a drift region 102, a gate 107, a first doped region 111, and a plurality of first trench structures. The bottom semiconductor layer 101 has a second conductivity type. The buried dielectric layer 114 is located on the bottom semiconductor layer 101. The source region 106 is located in the second conductivity type well region 104. The drift region 102 has a first conductivity type and is at least partially located between the source region 106 and the drain region 108. The gate 107 is located above the region between the source region 106 and the drain region 108. The first trench structures include the first trench ( Figure 1 The first dielectric layer 109 (not shown) is located on the inner surface of the first trench, and a first conductive material 110 is filled within the first trench. The first trench structure extends downward from the second conductivity type well region 104 (i.e., the channel region) below the gate 107 to the buried dielectric layer 114 or the bottom semiconductor layer 101. The first conductive material 110 is electrically connected to the gate 107. Figure 1In the illustrated embodiment, the top of the first conductive material 110 is in direct contact with the bottom of the gate 107. The first doped region 111, having a first conductivity type, is located below the first trench structure, and the top of the first doped region 111 is in direct contact with the bottom of the buried dielectric layer 114 or the bottom of the first trench structure. For the NLDMOS embodiment, the first conductivity type is N-type, and the second conductivity type is P-type.

[0034] In the aforementioned laterally diffused metal-oxide-semiconductor device, the first conductive material 110 in the second conductivity type well region 104 below the gate 107 is electrically connected to the gate 107. The first conductive material 110 will sense the same potential as the gate 107, inverting a portion of the second conductivity type well region 104 around the first trench structure, thereby improving the device's current carrying capacity and reducing its on-resistance. The first doped region 111 below the bottom of the first trench structure forms a reverse PN junction with the bottom semiconductor layer 101, which can prevent the current from the gate 107 from flowing to the bottom semiconductor layer 101, reducing the impact of the back gate effect on the device.

[0035] In one embodiment of this application, the first conductive material 110 is polycrystalline silicon of a first conductivity type. In one embodiment of this application, the first dielectric layer 109 is made of silicon oxide, such as silicon dioxide.

[0036] In one embodiment of this application, the depth of the first trench is approximately equal to the sum of the thickness of the second conductivity type well region 104 (i.e., the thickness of the drift region 102) and the thickness of the buried dielectric layer 114, i.e., the bottom of the first trench is located at the junction of the bottom of the buried dielectric layer 114 and the top of the bottom semiconductor layer 101.

[0037] In one embodiment of this application, the buried medium layer 114 is a buried oxide layer, and its material can be silicon oxide, such as silicon dioxide.

[0038] exist Figure 1 In the embodiment shown, the laterally diffused metal-oxide semiconductor device further includes a field oxide layer 112 located on the drift region 102. Figure 1 The structure of the middle part of the field oxygen layer 112 is omitted, and the top of the drift region 102 at that location is exposed.

[0039] In one embodiment of this application, the first trench structures are arranged to form a multi-row, multi-column array structure. (Refer to...) Figure 1 In this embodiment, the row direction of the array structure is the direction of the conductive channel length (X-axis direction), and the column direction is the direction of the conductive channel width (Z-axis direction). The number of first trench structures is at least two, and at least two first trench structures are located at different positions in the direction of the conductive channel length (i.e., the X-axis coordinates of the two first trench structures are different).

[0040] In one embodiment of this application, the laterally diffused metal-oxide-semiconductor device further includes a substrate lead-out region 105. In one embodiment of this application, the substrate lead-out region 105 has a second conductivity type and is disposed on the side of the source region 106 opposite to the gate 107. The doping concentration of the substrate lead-out region 105 is greater than the doping concentration of the well region 104 of the second conductivity type.

[0041] In one embodiment of this application, the laterally diffused metal-oxide-semiconductor device further includes a first conductivity type well region 103. The first conductivity type well region 103 is connected to the drift region 102, and a drain region 108 is located in the first conductivity type well region 103. The doping concentration of the drain region 108 is greater than the doping concentration of the first conductivity type well region 103.

[0042] In one embodiment of this application, the laterally diffused metal-oxide-semiconductor device further includes a gate dielectric layer 113. A gate 107 is located on the gate dielectric layer 113.

[0043] Figure 2 This is a perspective view of a laterally diffused metal-oxide-semiconductor device according to another embodiment of this application. It is related to... Figure 1 The main difference in the illustrated embodiment is that it also includes a second trench structure and a second doped region 111a. Specifically, a second trench structure similar to the first trench structure is also provided in the drift region 102, and a second doped region 111a is correspondingly provided in the bottom semiconductor layer 101 below the bottom of the second trench structure. The second trench structure includes a second trench (… Figure 2 The second trench structure comprises a second dielectric layer 109a (not shown) on the inner surface of the second trench, and a second conductive material 110a filling the second trench. The second trench structure extends downward from the drift region 102 to the buried dielectric layer 114 or the bottom semiconductor layer 101. The second doped region 111a has a first conductivity type and is located below the second trench structure, with the top of the second doped region 111a in direct contact with the bottom of the buried dielectric layer 114 or the bottom of the second trench structure. Figure 2 The ellipsis “…” in the text indicates that several second trench structures are omitted. In one embodiment of this application, the second dielectric layer 109a and the first dielectric layer 109 are formed simultaneously (in the same process step), the second conductive material 110a and the first conductive material 110 are filled into the corresponding trenches simultaneously, and the second doped region 111a and the first doped region 111 are formed simultaneously.

[0044] In one embodiment of this application, the second trench structures are arranged to form a multi-row, multi-column array structure. (Refer to...) Figure 2 In this embodiment, the row direction of the array structure is the length direction of the conductive channel (X-axis direction), and the column direction is the width direction of the conductive channel (Z-axis direction). Figure 2In the illustrated embodiment, the second conductive material 110a serves as a floating field plate. As those skilled in the art will know, "floating" means that the field plate is not externally connected to a potential. The number of second trench structures is at least two, and at least two second trench structures are located at different positions along the length of the conductive channel (i.e., the X-axis coordinates of the two second trench structures are different).

[0045] In one embodiment of this application, the second conductive material 110a is polycrystalline silicon of the first conductivity type. In one embodiment of this application, the second dielectric layer 109a is made of silicon oxide, such as silicon dioxide.

[0046] Figure 3 This is a perspective view of a laterally diffused metal-oxide-semiconductor device according to another embodiment of this application. It is related to... Figure 2 The main difference in the illustrated embodiment is that it also includes multiple conductive equipotential strips 115. Each conductive equipotential strip extends along the width of the conductive channel and passes downward through the field oxide layer 112 via a conductive structure 116, electrically connecting to the second conductive material 110a in a row of second trench structures below, thereby pulling the bottom potential of the connected second conductive material 110a to be equal to the surface potential. In one embodiment of this application, each conductive equipotential strip 115 is connected to zero potential when the laterally diffused metal-oxide-semiconductor device is turned off and to a high level when it is turned on.

[0047] In one embodiment of this application, the conductive equipotential strip 115 is made of metal; the conductive equipotential strip 115 can be formed using common aluminum interconnect or copper interconnect processes.

[0048] Figures 1 to 3 In this embodiment of NLDMOS, the bottom semiconductor layer 101 is a P-type substrate, and the drift region 102 is an N-type drift region disposed on the bottom semiconductor layer 101. A first trench structure and a second trench structure are disposed between the N-type source region 106 and the N-type drain region 108. The substrate lead-out region 105 is a P-type doped region. The first conductivity type well region 103 is an N-well, and the second conductivity type well region 104 is a P-well.

[0049] exist Figures 1 to 3 In the illustrated embodiment, the source region 106 and the substrate lead-out region 105 are disposed in the second conductivity type well region 104, and the drain region 108 is disposed in the first conductivity type well region 103. Figures 1 to 3 In the illustrated embodiment, the first conductivity type well region 103 is an N-well, and the second conductivity type well region 104 is a P-well. The second conductivity type well region 104 serves as the channel formation region of the device, and its concentration will also affect the drift region depletion and the on-state voltage. The first conductive material 110 and the second conductive material 110a are N-type doped polysilicon. The gate 107 is made of N-type polysilicon.

[0050] In one embodiment of this application, in order to obtain a higher breakdown voltage, the P-type substrate can be selected from a substrate material with higher resistivity to achieve substrate depletion.

[0051] In one embodiment of this application, the drift region 102 is formed by high-temperature push junction after ion implantation, and must reach a certain depth to ensure the depletion of the device substrate and the current conduction path.

[0052] In one embodiment of this application, the first conductivity type well region 103 serves as a drain drift region buffer layer, which can improve the on-state breakdown voltage of the LDMOS during forward operation.

[0053] This application also provides a method for manufacturing a laterally diffused metal-oxide-semiconductor device, used to manufacture the laterally diffused metal-oxide-semiconductor device described in any of the foregoing embodiments. Figure 4 This is a flowchart of a method for manufacturing a laterally diffused metal-oxide-semiconductor device according to an embodiment of this application, including the following steps:

[0054] S210, acquire wafer.

[0055] In one embodiment of this application, the wafer is an SOI (silicon-on-insulator) wafer, comprising a bottom semiconductor layer 101, a buried dielectric layer 114, and a top semiconductor layer stacked sequentially. The bottom semiconductor layer 101 has a second conductivity type. In this embodiment, the laterally diffused metal-oxide-semiconductor device is an NLDMOS device, with a first conductivity type of N-type and a second conductivity type of P-type, and the bottom semiconductor layer 101 is a P-type substrate.

[0056] In one embodiment of this application, the top semiconductor layer has a first conductivity type, and a portion of the top semiconductor layer subsequently serves as the drift region 102 of the device.

[0057] S220, forming a groove.

[0058] Trench 121 extends downward from the top semiconductor layer to the buried dielectric layer 114 or the bottom semiconductor layer 101. Trench 121 can be formed by photolithography and etching.

[0059] In one embodiment of this application, the depth of trench 121 is approximately equal to the sum of the thickness of the top semiconductor layer and the thickness of the buried dielectric layer 114, that is, the bottom of trench 121 is located at the junction of the bottom of the buried dielectric layer 114 and the top of the bottom semiconductor layer 101, referring to... Figure 5a .

[0060] The trench 121 has multiple trenches. In one embodiment of this application, each trench 121 is formed only in the region where the second conductivity type well region 104 is formed in a subsequent step. In another embodiment of this application, each trench 121 is also formed in the region where the drift region 102 is located.

[0061] In one embodiment of this application, the trenches 121 are arranged to form a multi-row, multi-column array structure. Further, the row direction of the array structure is the length direction of the conductive channel, and the column direction is the width direction of the conductive channel. The number of trenches 121 is at least two, and at least two trenches 121 are located at different positions along the length direction of the conductive channel.

[0062] S230, a first conductivity type region is formed in the bottom semiconductor layer below the trench by ion implantation.

[0063] The top of the first conductivity type region is in direct contact with the bottom of the buried dielectric layer 114 or the bottom of the trench 121. Figure 5b In the illustrated embodiment, the first conductivity type region includes a first doped region 111 and a second doped region 111a, with the first doped region 111 located in the second conductivity type well region 104. Figure 5b Below the groove 121 (not shown in the image).

[0064] S240, a dielectric layer is formed on the inner surface of the trench.

[0065] In one embodiment of this application, silicon dioxide is formed as a dielectric layer on the inner surface of trench 121 by a thermal oxidation process. Figure 5c In the illustrated embodiment, the dielectric layer includes a first dielectric layer 109 and a second dielectric layer 109a, wherein the first dielectric layer 109 is located in the second conductivity type well region 104 ( Figure 5c The inner surface of groove 121 (not shown in the image).

[0066] S250, filling the trenches where the dielectric layer is formed with conductive material.

[0067] In one embodiment of this application, the conductive material is polycrystalline silicon of a first conductivity type. Figure 5c In the illustrated embodiment, the conductive material includes a first conductive material 110 and a second conductive material 110a, wherein the first conductive material 110 is located in the second conductivity type well region 104. Figure 5d In the groove 121 (not shown in the text).

[0068] S260, a second conductivity type well region is formed in the top semiconductor layer.

[0069] In one embodiment of this application, before step S260, a step of forming a field oxide layer 112 is included. The second conductivity type well region 104 can be formed by ion implantation. In one embodiment of this application, after forming the field oxide layer 112 and before step S270, a step of forming a first conductivity type well region 103 is included. The first conductivity type well region 103 can be formed by ion implantation, and the first conductivity type well region 103 is located on one side of the field oxide layer 112, while the second conductivity type well region 104 is located on the other side of the field oxide layer 112.

[0070] S270, a gate is formed above part or all of the trench.

[0071] The trench 121 can be disposed only below the gate 107, or it can be disposed together in the drift region 102. Before forming the gate 107, a gate dielectric layer 113 can be formed first, and the gate dielectric layer 113 on the trench 121 can be removed by photolithography and etching, so that the bottom of the gate 107 contacts the top of the first conductive material 110.

[0072] S280 forms source and drain regions on both sides of the trench, respectively.

[0073] A source region 106 of the first conductivity type is formed in the second conductivity type well region 104 by ion implantation, and a drain region 108 of the first conductivity type is formed in the first conductivity type well region 103. In one embodiment of this application, a substrate lead-out region 105 is also formed in the second conductivity type well region 104 by ion implantation. The device structure after step S280 can be found in [reference needed]. Figure 2 .

[0074] In the aforementioned laterally diffused metal-oxide-semiconductor device, the conductive material in the trench 121 of the channel region is electrically connected to the gate 107, and will induce the same potential as the gate 107. This will invert the second conductivity type well region 104 in a portion of the area surrounding the trench 121, thereby improving the device's current carrying capacity and reducing its on-resistance. The first conductivity type region below the bottom of the trench 121 forms a reverse PN junction with the bottom semiconductor layer 101, which can prevent the current from the gate 107 from flowing to the bottom semiconductor layer 101, reducing the impact of the back gate effect on the device.

[0075] In one embodiment of this application, the method for manufacturing a laterally diffused metal-oxide-semiconductor device further includes the following steps:

[0076] The field oxide layer 112 is etched to form a plurality of through-holes of conductive material extending to the bottom of each trench 121;

[0077] A conductive structure 116 is formed in the through hole;

[0078] Multiple conductive equipotential strips 115 are formed on the field oxygen layer 112. Each conductive equipotential strip 115 extends along the width direction of the conductive channel and is electrically connected to the conductive material in a row of trenches 121 below through the conductive structure 116.

[0079] The manufacturing method of the laterally diffused metal oxide semiconductor device in this application is based on the same inventive concept as the laterally diffused metal oxide semiconductor device. For details not specifically described in the manufacturing method of the laterally diffused metal oxide semiconductor device, please refer to the above introduction of the laterally diffused metal oxide semiconductor device.

[0080] It should be understood that although the steps in the flowchart of this application are shown sequentially as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowchart of this application may include multiple steps or multiple stages, which are not necessarily completed at the same time, but may be executed at different times, and the execution order of these steps or stages is not necessarily sequential, but may be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0081] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0082] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0083] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A laterally diffused metal-oxide-semiconductor device, characterized in that, include: The bottom semiconductor layer has a second conductivity type; A buried dielectric layer is located on the bottom semiconductor layer; Second type of conductivity well region; The source region is located in the well region of the second conductivity type; Drain region; The drift region has a first conductivity type and is at least partially located between the source region and the drain region; the first conductivity type and the second conductivity type are opposite conductivity types; The gate is located above the region between the source region and the drain region; The first trench structure extends downward from the second conductivity type well region below the gate to the buried dielectric layer or the bottom semiconductor layer, including a first dielectric layer located on the inner surface of the first trench, and a first conductive material filling the first trench, wherein the first conductive material is electrically connected to the gate. A first doped region, having a first conductivity type, is located below the first trench structure, and the top of the first doped region is in direct contact with the bottom of the buried dielectric layer or the bottom of the first trench structure.

2. The laterally diffused metal-oxide-semiconductor device according to claim 1, characterized in that, The first conductivity type is N-type, and the second conductivity type is P-type.

3. The laterally diffused metal-oxide-semiconductor device according to claim 1 or 2, characterized in that, The first conductive material is polycrystalline silicon of the first conductivity type.

4. The laterally diffused metal-oxide-semiconductor device according to claim 1, characterized in that, Also includes: The second trench structure extends downward from the drift region to the buried dielectric layer or the bottom semiconductor layer. The second trench structure includes a second dielectric layer located on the inner surface of the second trench and a second conductive material filled in the second trench. The second doped region, having a first conductivity type, is located below the second trench structure, and the top of the second doped region is in direct contact with the bottom of the buried dielectric layer or the bottom of the second trench structure.

5. The laterally diffused metal-oxide-semiconductor device according to claim 4, characterized in that, The second trench structure has multiple structures, and the second trench structures are arranged to form an array structure.

6. The laterally diffused metal-oxide-semiconductor device according to claim 5, characterized in that, Also includes: An oxygen layer is provided on the drift region; Multiple conductive equipotential strips extend along the width of the conductive channel and pass downward through the field oxygen layer via a conductive structure, electrically connecting with the second conductive material in a row of second trench structures below.

7. The laterally diffused metal-oxide-semiconductor device according to claim 1, characterized in that, Also includes: A substrate lead-out region having a second conductivity type is disposed on the side of the source region away from the gate, and the doping concentration of the substrate lead-out region is greater than the doping concentration of the well region of the second conductivity type. A first conductivity type well region is connected to the drift region, and the drain region is located in the first conductivity type well region. The doping concentration of the drain region is greater than that of the first conductivity type well region.

8. A method for manufacturing a laterally diffused metal-oxide-semiconductor device, comprising: Obtain a wafer comprising a bottom semiconductor layer, a buried dielectric layer and a top semiconductor layer stacked sequentially, wherein the bottom semiconductor layer has a second conductivity type; A trench is formed, the trench extending downward from the top semiconductor layer to the buried dielectric layer or the bottom semiconductor layer; A first conductivity type region is formed in the bottom semiconductor layer below the trench by ion implantation, and the top of the first conductivity type region is in direct contact with the bottom of the buried dielectric layer. The first conductivity type and the second conductivity type are opposite conductivity types; A dielectric layer is formed on the inner surface of the trench; A conductive material is filled into the trench in which the dielectric layer is formed. A second conductivity type well region is formed in the top semiconductor layer; The trench has multiple trenches, some or all of which penetrate the second conductivity type well region; A gate is formed over some or all of the trenches, and the conductive material is electrically connected to the gate; A source region and a drain region are formed on both sides of the trench, respectively, with the source region formed in the second conductivity type well region; The top semiconductor layer includes a drift region of a first conductivity type, which is at least partially located between the source region and the drain region.

9. The method for manufacturing a laterally diffused metal-oxide-semiconductor device according to claim 8, characterized in that, Some of the grooves penetrate the drift region, and the grooves are arranged to form an array structure; The step of filling the trench in which the dielectric layer is formed with conductive material, after the step of forming the second type of conductive well region, further includes the step of forming a field oxygen layer.

10. The method for manufacturing a laterally diffused metal-oxide-semiconductor device according to claim 9, characterized in that, Also includes: The field oxide layer is etched to form multiple vias of conductive material that extend to the bottom of each trench; A conductive structure is formed in the through hole; Multiple conductive equipotential strips are formed on the field oxygen layer. Each conductive equipotential strip extends along the width direction of the conductive channel and is electrically connected to the conductive material in a row of trenches below through the conductive structure.

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