LDMOS and LDMOS devices in a BCD process platform

Abstract

This application discloses an LDMOS and LDMOS device in a BCD process platform. The LDMOS includes a P-type well region and an N-type drift region fabricated in a substrate. The source region is located in the P-type well region, and the drain region is located in the N-type drift region. The gate region includes a connected upper substrate region and a lower substrate region. The upper substrate region covers the substrate, and the lower substrate region is located between the P-type well region and the N-type drift region. The LDMOS also includes a trench region extending from the upper surface of the LDMOS to the substrate of the LDMOS. This trench region penetrates the drain region, and its drain connection terminal is located on the trench region. Due to the use of a trench structure for the drain, the contact area between the drain electrode and the N-type drift region is increased, thereby reducing the series resistance of the drift layer by increasing the effective conduction area. Furthermore, the simultaneous use of a trench structure for the gate optimizes the internal electric field distribution of the device. Since the peak electric field of the drift layer is still limited within a safe range, the breakdown voltage is not lost.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically to an LDMOS and LDMOS device in a BCD process platform. Background Technology

[0002] DMOS stands for Double-Diffused Metal-Oxide-Semiconductor Field-Effect Transistor, primarily consisting of two types: VDMOS and LDMOS (Laterally Diffused MOSFET). LDMOS, with its advantages of high voltage withstand capability, high transconductance, and high gain, is widely used as a high-voltage power device in radio frequency power integrated circuits. An LDMOS device is composed of hundreds or thousands of single-structure LDMOS cells. In the BCD (Bipolar-CMOS-DMOS) process platform, the LDMOS device is the core component for achieving "high-voltage / high-current power switching capability," working in conjunction with on-chip low-voltage CMOS control and logic, as well as BJTs, ESD protection devices, and isolation devices to complete power conversion and intelligent control on a single chip.

[0003] LDMOS devices belong to the category of laterally diffused metal-oxide-semiconductor (LDMOS) devices. They are widely used in power management, automotive electronics, and power conversion due to their advantages such as low on-resistance, adjustable breakdown voltage, and good process compatibility. For low-voltage applications in the 20V range, traditional LDMOS devices typically employ planar gate or shallow trench gate structures. The trade-off between breakdown voltage (BV) and specific on-resistance (Ron,sp) is balanced by controlling the doping concentration and thickness of the N-type drift layer. However, existing LDMOS devices suffer from the following technical drawbacks:

[0004] 1. The contradiction between on-resistance and breakdown voltage is prominent.

[0005] To meet the 20V breakdown voltage requirement, the N-type drift layer needs to maintain a low doping concentration and sufficient thickness, which results in an excessively high proportion of series resistance in the drift layer, a large Ron,sp, limited on-current (Ids), and a significant increase in power loss.

[0006] 2. Limitations of trench structure application.

[0007] Existing trench technologies are mostly focused on the gate region, reducing channel resistance by shortening the gate length and improving channel control capabilities. However, they do not adequately optimize the current conduction path in the drain region, and the expansion effect of drain current is not fully utilized.

[0008] 3. Process compatibility limitations.

[0009] Structural innovations for the drain must be compatible with existing BCD process flows to avoid adding complex process steps, which would increase manufacturing costs and process risks. Therefore, how to further reduce the Ron,sp of LDMOS devices and increase the on-state current while maintaining a breakdown voltage in the 20V range has become a key challenge in the design of low-voltage and high-voltage power devices using BCD technology. Summary of the Invention

[0010] The main technical problem this invention addresses is how to increase the on-current of an LDMOS transistor.

[0011] According to a first aspect, one embodiment provides an LDMOS in a BCD process platform, including a P-type well region and an N-type drift region fabricated in a substrate; the source region of the LDMOS is disposed in the P-type well region, and the drain region of the LDMOS is disposed in the N-type drift region; the gate region of the LDMOS includes a connected on-substrate region and an under-substrate region, the on-substrate region covering the substrate, and the under-substrate region being disposed between the P-type well region and the N-type drift region in the substrate;

[0012] The source connection terminal of the LDMOS is disposed on the source region, and the gate connection terminal of the LDMOS is disposed on the substrate region.

[0013] The LDMOS also includes a trench region extending from the upper surface of the LDMOS toward the substrate of the LDMOS, the trench region penetrating the drain region, and the drain connection terminal of the LDMOS is disposed on the trench region.

[0014] In one embodiment, the trench region also extends through the N-type drift region.

[0015] In one embodiment, the trench region disposed on the substrate is a vertical trench, a U-shaped trench, or a V-shaped trench.

[0016] In one embodiment, the depth of the under-substrate region extending into the LDMOS substrate is greater than the depth of the source region and the drain region extending into the LDMOS substrate, and less than the depth of the P-type well region and the N-type drift region extending into the LDMOS substrate.

[0017] In one embodiment, the trench region extends into the substrate at a greater depth than the under-substrate region extends into the LDMOS substrate.

[0018] In one embodiment, the P-type well region and the N-type drift region are separated by the underlay region.

[0019] In one embodiment, the upper surface of the P-type well region is further provided with a P-body region, which is isolated from the source region on the upper surface of the P-type well region by a shallow trench.

[0020] In one embodiment, the trench region is made of aluminum; and / or the gate region is made of polysilicon; and / or the LDMOS substrate is a P-type substrate or an N-type substrate.

[0021] In one embodiment, the trench region extends from the upper surface of the LDMOS to the substrate of the LDMOS at a depth between 0.2 μm and 1.0 μm.

[0022] According to a second aspect, one embodiment provides an LDMOS device comprising a plurality of MOS cells, wherein at least one MOS cell is an LDMOS as described in any one of claims 1 to 9.

[0023] According to the LDMOS of the above embodiment, the use of a trench structure drain increases the contact area between the drain electrode and the N-type drift region, thereby reducing the series resistance of the drift layer by increasing the effective conduction area.

[0024] Furthermore, a trench gate structure was adopted simultaneously, which optimized the electric field distribution inside the device. Since the peak electric field of the drift layer is still limited within a safe range, the breakdown voltage is not lost. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of the cross-sectional structure of an LDMOS transistor.

[0026] Figure 2 This is a schematic cross-sectional view of an LDMOS structure in one embodiment;

[0027] Figure 3 A cross-sectional view of the net doping distribution of an LDMOS device in one embodiment;

[0028] Figure 4 This is a graph showing the relationship between the deep trench drain depth and the device conduction performance in one embodiment. Detailed Implementation

[0029] The present invention will now be described in further detail with reference to specific embodiments and accompanying drawings. Similar elements in different embodiments are referred to by associated similar element reference numerals. In the following embodiments, many details are described to facilitate a better understanding of this application. However, those skilled in the art will readily recognize that some features may be omitted in different situations, or may be replaced by other elements, materials, or methods. In some cases, certain operations related to this application are not shown or described in the specification. This is to avoid obscuring the core parts of this application with excessive description. For those skilled in the art, detailed description of these related operations is not necessary; they can fully understand the related operations based on the description in the specification and general technical knowledge in the art.

[0030] Furthermore, the features, operations, or characteristics described in the specification can be combined in any suitable manner to form various embodiments. At the same time, the steps or actions in the method description can be rearranged or adjusted in a manner obvious to those skilled in the art. Therefore, the various orders in the specification and drawings are only for the clear description of a particular embodiment and do not imply a necessary order, unless otherwise stated that a particular order must be followed.

[0031] The serial numbers assigned to components in this document, such as "first" and "second," are used only to distinguish the described objects and have no sequential or technical meaning. The terms "connection" and "linkage" used in this application, unless otherwise specified, include both direct and indirect connections (linkages).

[0032] Please refer to Figure 1 This is a schematic diagram of the cross-sectional structure of an LDMOS. Planar LDMOS typically uses a gate-N-type drift region (N-drift) 30 for lateral voltage withstand to achieve high-voltage turn-off support. The P-body region 22 of the LDMOS is usually short-circuited to the source. Its core functions are to form a conductive channel, constitute the main breakdown voltage PN junction with the N-drift, and suppress parasitic BJT effects and prevent latch-up by short-circuiting with the source. The shallow trench isolation 23 (STI) has the following functions:

[0033] 1) Although the body electrode and the source electrode are shorted in the circuit, the STI between them can physically isolate the direct contact between the source N⁺ and the body P-type silicon, thus avoiding the formation of parasitic PN junctions and additional leakage current.

[0034] 2) STI can block the carrier injection path of parasitic NPN transistors, effectively suppress latch-up effect and device mis-conduction, and improve the reliability of high voltage operation.

[0035] 3) It can simultaneously smooth the peak value of the source electric field and reduce the body parasitic capacitance, thus balancing the voltage withstand capability and high-frequency and switching performance of LDMOS.

[0036] The source, as the current input terminal of an LDMOS (for N-LDMOS), is characterized by a key structural feature: the internal N+ region (providing charge carriers) and the P+ contact region (connecting the body) are shorted in a metal layer, forming a "source-body short." Polysilicon serves as the polysilicon gate, acting as the gate electrode (above the gate oxide, applying voltage to control the opening and closing of the channel below) and extending as a field plate (often extending to cover part of the drift region, becoming a "gate field plate" to smooth the surface electric field). Silicon nitride (Si3N4), as a dielectric material, is used in the process for etching hard masks / stop layers (due to its higher etching selectivity compared to silicon dioxide), passivation protection layers, and stress layers (to improve CMOS performance). In LDMOS, it is usually part of the process, not the active region of the device. The drain is the current output terminal / high voltage withstand terminal of the LDMOS, located at the end of the N-drift region, led out through a metal contact, and withstands a high voltage when the LDMOS is turned off. The P-well region 20 and the body region are usually the same area. From a manufacturing perspective, "P-well" emphasizes that it is a P-type doped region formed by ion implantation, used to form the body region of the MOSFET and the necessary PN junction. The N-drift region 30 is the core region for achieving high-voltage capability in LDMOS. Its functions are voltage withstand (lightly doped, sufficient to withstand high voltage when off) and conductivity (providing a path for current from the channel to the drain when on). Its length and doping distribution are key considerations in the trade-off design of breakdown voltage (BV) and specific on-resistance (Ron, sp). The substrate 1 is the mechanical base and common electrical ground of the chip. Its functions are to support all devices, provide electrical isolation (forming a PN junction with the N-type region above), and be connected to the lowest potential (e.g., grounding, providing a path for parasitic currents). The gate region 2 is provided with a gate connection terminal, and the gate oxide region 11 is used to isolate the gate region 2 and the substrate 1.

[0037] In this application embodiment, a silicon-based LDMOS device with a deep trench drain structure is provided to solve the following problems: Figure 1 The LDMOS device shown addresses the trade-off bottleneck between on-resistance and breakdown voltage in BCD process applications with a 20V breakdown voltage, solving the problems of limited on-current and high power loss. In one embodiment, by adjusting the depth of the deep trench drain, Ron,sp can be significantly reduced while maintaining a stable breakdown voltage, thereby increasing the on-current.

[0038] Example 1:

[0039] Please refer to Figure 2This is a schematic cross-sectional view of an LDMOS in one embodiment. The LDMOS disclosed in this application, based on a BCD process platform, includes a P-type well region 20 and an N-type drift region 30 fabricated in a substrate 1. The source region 21 of the LDMOS is disposed in the P-type well region 20, and the drain region 31 is disposed in the N-type drift region 30. The gate region 2 of the LDMOS includes a connected upper substrate region 13 and an under substrate region 12. The upper substrate region 13 covers the substrate 1, and the under substrate region 12 is disposed between the P-type well region 20 and the N-type drift region 30 in the substrate 1. The source terminal of the LDMOS is disposed on the source region 21, and the gate terminal is disposed on the upper substrate region 13. The LDMOS also includes a trench region 32 extending from the upper surface of the LDMOS towards the substrate 1 of the LDMOS. The trench region 32 penetrates the drain region 31, and the drain terminal of the LDMOS is disposed on the trench region 32. In one embodiment, the trench region 32 also penetrates the N-type drift region 30.

[0040] In one embodiment, the trench region 32 disposed on the substrate 1 is a vertical trench, a U-shaped trench, or a V-shaped trench. In another embodiment, the depth of the under-substrate region 12 extending into the substrate 1 of the LDMOS is greater than the depth of the source region 21 and the drain region 31 extending into the substrate 1 of the LDMOS, and less than the depth of the P-type well region 20 and the N-type drift region 30 extending into the substrate 1 of the LDMOS.

[0041] In one embodiment, the trench region 31 extends into the substrate 1 to a greater depth than the under-substrate region 12 extends into the LDMOS substrate 1. In another embodiment, the P-type well region 20 and the N-type drift region 30 are separated by the under-substrate region 12.

[0042] In one embodiment, a P-body region 22 is further provided on the upper surface of the P-type well region 20, and is isolated from the source region 21 on the upper surface of the P-type well region 20 by a shallow trench isolation 23.

[0043] In one embodiment, the trench region 32 is made of aluminum. In one embodiment, the gate region 1 is made of polysilicon. In one embodiment, the substrate 1 of the LDMOS is a P-type substrate. In one embodiment, the trench region 32 extends from the upper surface of the LDMOS to the substrate 1 of the LDMOS to a depth between 0.2 μm and 1.0 μm. In one embodiment, the substrate of the LDMOS is an N-type substrate.

[0044] In one embodiment of this application, an LDMOS device is also disclosed, comprising a plurality of MOS units, wherein at least one MOS unit is an LDMOS as described above.

[0045] The LDMOS disclosed in the embodiments of this application (such as...) Figure 2 (as shown) and as Figure 1Compared to the conventional planar gate LDMOS, the added deep trench drain, by embedding an N-type drift layer in a deep trench, alters the drain current distribution path. As the depth of the deep trench drain increases, the contact area between the drain electrode and the N-type drift layer increases, enhancing the current propagation effect from the drift layer to the drain and increasing the effective conduction area, thereby reducing the drift layer series resistance. The coordinated layout of the added deep trench gate and deep trench drain optimizes the internal electric field distribution of the device. Even as the depth of the deep trench drain increases, the peak electric field of the drift layer remains within a safe range, ensuring that the 20V-level breakdown voltage is not compromised. In one embodiment, the aluminum deep trench drain has low resistivity, further reducing the series resistance of the drain electrode. This, combined with the reduction in drift layer resistance, creates a synergistic effect, jointly improving the device's conduction performance.

[0046] Please refer to Figure 3 This is a cross-sectional view of the net doping distribution of an LDMOS device in one embodiment, using a 90nm BCD process with a breakdown voltage in the 20V range. The relative positions of the source, gate, drain, P-type well, and N-type drift regions can be compared. Figure 2 The LDMOS structure shown has color codes on the right indicating the net doping concentration and type. Red / orange indicates N-type doping (source, drift layer, and drain regions), and purple / blue indicates P-type doping (body region). The color code values ​​are exponents in cm⁻³. The lower left corner scale is 0.1 μm and is used to identify device feature dimensions.

[0047] Please refer to Figure 4 The graph shows the relationship between the deep trench drain depth and the device conduction performance in one embodiment. The horizontal axis represents the trench drain depth (μm), and the vertical axis represents the specific on-resistance (mΩ·mm). 2 The test conditions were Vgs=10V, Vds=0.1V, and the breakdown voltage was maintained in the range of 20 to 25V.

[0048] Based on the above structural differences, compared with the prior art, the LDMOS device disclosed in the embodiments of this application has the following significant advantages:

[0049] 1) Conductivity performance is significantly optimized.

[0050] As the depth of the deep trench drain increases, the on-current (Ids) of the device increases linearly, while the specific on-resistance (Ron,sp) decreases significantly. TCAD simulation data shows that under 90nm BCD process and 20V breakdown voltage conditions, when the depth of the deep trench drain increases from 0μm to 1.0μm, Ron,sp can be reduced by more than 20%, effectively reducing device power loss.

[0051] 2) Excellent breakdown voltage stability.

[0052] Through optimized layout of deep trench gate and deep trench drain, the internal electric field distribution of the device is uniform, and the change in deep trench drain depth has minimal impact on the breakdown voltage, which can be stably maintained in the 20V~25V range, meeting the application requirements of 20V level.

[0053] 3) Strong process compatibility.

[0054] The etching and aluminum filling process for deep trench drains is compatible with the deep trench etching and metal filling steps of the existing 90nm BCD process, without the need for additional photolithography, etching, or deposition equipment, and the manufacturing cost and process risk are controllable.

[0055] 4) Flexible structural design.

[0056] The depth of the deep trench drain can be flexibly adjusted according to specific application requirements (such as conduction current and power consumption limits), providing flexible design space for performance optimization of LDMOS devices in different scenarios.

[0057] The LDMOS in the BCD process platform disclosed in this application includes a P-type well region and an N-type drift region fabricated in a substrate. The source region is disposed in the P-type well region, the drain region is disposed in the N-type drift region, and the gate region includes a connected upper substrate region and an under substrate region. The upper substrate region covers the substrate, and the under substrate region is disposed between the P-type well region and the N-type drift region. The LDMOS also includes a trench region extending from the upper surface of the LDMOS to the substrate of the LDMOS. This trench region penetrates the drain region, and its drain connection terminal is disposed on the trench region. Due to the use of a trench structure for the drain, the contact area between the drain electrode and the N-type drift region is increased, thereby reducing the series resistance of the drift layer by increasing the effective conduction area. Furthermore, the simultaneous use of a trench structure for the gate optimizes the internal electric field distribution of the device. Since the peak electric field of the drift layer is still limited within a safe range, the breakdown voltage is not lost.

[0058] The above examples illustrate this application only to aid understanding and are not intended to limit its scope. Those skilled in the art to which this application pertains can make various simple deductions, modifications, or substitutions based on the ideas presented.

Claims

1. An LDMOS in a BCD process platform, characterized in that, It includes a P-type well region and an N-type drift region fabricated in a substrate; the source region of the LDMOS is disposed in the P-type well region, and the drain region of the LDMOS is disposed in the N-type drift region; the gate region of the LDMOS includes a connected on-substrate region and an under-substrate region, the on-substrate region covering the substrate, and the under-substrate region being disposed between the P-type well region and the N-type drift region in the substrate. The source connection terminal of the LDMOS is disposed on the source region, and the gate connection terminal of the LDMOS is disposed on the substrate region. The LDMOS also includes a trench region extending from the upper surface of the LDMOS toward the substrate of the LDMOS, the trench region penetrating the drain region, and the drain connection terminal of the LDMOS is disposed on the trench region.

2. The LDMOS as described in claim 1, characterized in that, The trench area also extends through the N-type drift area.

3. The LDMOS as described in claim 1, characterized in that, The trench area disposed on the substrate is a vertical trench, a U-shaped trench, or a V-shaped trench.

4. The LDMOS as described in claim 3, characterized in that, The depth to which the under-substrate region extends into the LDMOS substrate is greater than the depth to which the source region and the drain region extend into the LDMOS substrate, and less than the depth to which the P-type well region and the N-type drift region extend into the LDMOS substrate.

5. The LDMOS as described in claim 4, characterized in that, The trench region extends into the substrate to a greater depth than the under-substrate region extends into the LDMOS substrate.

6. The LDMOS as described in claim 5, characterized in that, The P-type well region and the N-type drift region are separated by the underlay region.

7. The LDMOS as described in claim 1, characterized in that, The upper surface of the P-type well region is also provided with a P-body region, which is isolated from the source region on the upper surface of the P-type well region by a shallow trench.

8. The LDMOS as described in claim 1, characterized in that, The trench region is made of aluminum; and / or the gate region is made of polysilicon; and / or the LDMOS substrate is a P-type substrate or an N-type substrate.

9. The LDMOS as described in claim 1, characterized in that, The trench region extends from the upper surface of the LDMOS to the substrate of the LDMOS at a depth between 0.2 μm and 1.0 μm.

10. An LDMOS device, characterized in that, It includes multiple MOS units, wherein at least one MOS unit is an LDMOS as described in any one of claims 1 to 9.

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