A static random access memory and a method of manufacturing the same

Abstract

The application relates to a static random access memory and a preparation method thereof. The method comprises the following steps: providing a semiconductor substrate, forming a shallow trench isolation structure and an active region on the substrate, wherein the active region of a transfer tube and the active region of a pull-down tube are perpendicular to each other in the channel direction; performing well ion implantation on the active region, forming a gate structure, and then performing light-doped drain ion implantation; respectively performing pocket ion implantation on the transfer tube and the pull-down tube, so that the transfer tube and the pull-down tube obtain different channel doping distributions; and finally forming a complete static random access memory unit. According to the application, the active region channel directions of the transfer tube and the pull-down tube are designed to be perpendicular to each other, and the pocket ion implantation with an inclined angle is combined, the independent regulation and control of the channel doping of the two types of transistors is realized by using the difference of the shadow effect, and therefore, under the premise of not increasing the number of transistors and the number of mask layers, a more optimal current ratio and a higher read-write noise margin are obtained.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a static random access memory and its fabrication method. Background Technology

[0002] Static Random Access Memory (SRAM) plays an indispensable role in high-speed cache applications such as portable mobile electronic devices and systems-on-a-chip (SoCs) due to its significant advantages such as fast read / write speeds, stable operation, and no need for refresh. As the critical linewidth of chips continues to shrink, the process compatibility window between SRAM devices and logic devices is narrowing. To balance the performance of memory cells and logic circuits, the industry practice is to add additional photomasks to separate the SRAM region and logic region for trap ion implantation and lightly doped drain ion implantation. While this approach optimizes the electrical parameters of both types of devices, it significantly increases manufacturing costs and extends production cycles, hindering cost control and capacity expansion. To reduce the chip area occupied by SRAM cells and increase storage density, the fin ratio of pull-up transistors, pull-down transistors, and transfer transistors is typically designed as 1:1:1. However, read / write stability analysis shows that a six-transistor SRAM cell with a 1:1:1 fin ratio often has lower static noise margin and write margin, making it difficult to meet the reliability requirements of advanced process nodes.

[0003] The current industry-standard solution is to add additional transfer transistors, splitting the transfer transistors that originally handled both read and write functions into separate read and write transfer transistors. This transforms the traditional six-transistor static random access memory (SRAM) structure into an eight-transistor structure. While the eight-transistor structure effectively improves read / write noise margins, the increased transistor count directly leads to a larger cell area, significantly reducing the chip's storage density and correspondingly increasing manufacturing complexity and cost. Summary of the Invention

[0004] Therefore, it is necessary to provide a static random access memory and its preparation method to address the above-mentioned technical problems.

[0005] In a first aspect, this application discloses a method for preparing a static random access memory (SRAM), which includes the following steps:

[0006] A semiconductor substrate is provided, on which a shallow trench isolation structure and an active region are formed, wherein the active region of the transmission transistor and the active region of the pull-down transistor are perpendicular to each other in the channel direction, and the pull-down transistor and the pull-up transistor are located on the same active region.

[0007] Trap ion implantation is performed on the active region to form a gate structure, the gate structure including a gate oxide layer and a gate polysilicon layer, wherein the pull-down transistor and the pull-up transistor share the same gate polysilicon layer;

[0008] Lightly doped drain ion implantation is performed, and the same lightly doped drain implantation conditions are used for the transport tube and the pull-down tube.

[0009] Bag-shaped ion implantation was performed on the transport tube and the pull-down tube respectively. By utilizing the difference in the shadowing effect caused by the perpendicularity of the channel direction, the transport tube and the pull-down tube obtained different channel doping distributions.

[0010] The second sidewall, heavily doped source-drain implantation, self-aligned metal silicide, contact vias, and metal interconnects are completed to form a complete static random access memory cell.

[0011] Furthermore, the active channel direction of the transmission tube forms a 90-degree angle with the active channel direction of the pull-down tube.

[0012] Furthermore, the pull-down transistor and the pull-up transistor are arranged side by side along the length of the active region, and both share the same gate polysilicon spanning above the active region.

[0013] Furthermore, the lightly doped drain ion implantation is an N-type impurity implantation, and the implanted impurity is arsenic or phosphorus.

[0014] Furthermore, during bag-shaped ion implantation of the transport tube, the implanted impurity is boron or boron difluoride, the implantation tilt angle ranges from 30 degrees to 45 degrees, the twist angle is 0 degrees, and the wafer rotates twice during the implantation process, each rotation being 180 degrees.

[0015] Furthermore, when performing bag-shaped ion implantation on the pull-down tube, the implanted impurity is boron or boron difluoride, and the implantation dose ranges from 1 × 10¹² ions per square centimeter to... The implantation tilt angle ranges from 30 to 45 degrees, the twist angle is 0 degrees, and the wafer rotates twice during the implantation process, each rotation being 180 degrees.

[0016] Furthermore, the drain terminals of the two pull-up transistors are internally connected through the first layer of metal interconnects, and the two memory nodes are cross-coupled through the second layer of metal interconnects.

[0017] On the other hand, this application also discloses a static random access memory, comprising:

[0018] Semiconductor substrate;

[0019] A shallow trench isolation structure formed in the substrate and an active region defined by the shallow trench isolation structure;

[0020] A six-tube memory cell consisting of two transmission tubes, two pull-down tubes, and two pull-up tubes; wherein the active area channel direction of the transmission tubes is perpendicular to the active area channel direction of the pull-down tubes, and the pull-down tubes and their corresponding pull-up tubes are located on the same active area.

[0021] The gate structure is such that the pull-down transistor and the corresponding pull-up transistor share the same gate structure.

[0022] Metal interconnect structures are used to achieve cross-coupling connections between transistors.

[0023] Furthermore, the active region of the transmission tube extends along a first direction, and the active regions of the pull-down tube and the pull-up tube extend along a second direction, wherein the first direction and the second direction are perpendicular to each other.

[0024] Furthermore, the gate structure comprises, from bottom to top, a gate oxide layer and a gate polysilicon layer.

[0025] Furthermore, the drain terminals of the two pull-up transistors are connected to each other through the first layer of metal interconnects, and the two memory nodes are respectively connected to the gates on the opposite side through the second metal interconnects, forming a bistable latch structure.

[0026] Furthermore, the channel of the transmission tube and the channel of the pull-down tube have different bag-shaped doping distributions, and their threshold voltages allow the current ratios β and γ to be adjusted independently.

[0027] Furthermore, the source of the transmission transistor is connected to the bit line, and the gate is connected to the word line; the source of the pull-down transistor is grounded, and the drain is connected to the memory node; the source of the pull-up transistor is connected to the power supply, and the drain is connected to the memory node.

[0028] Furthermore, the ratio of the number of fins of the transmission tube, pull-down tube, and pull-up tube in the six-tube memory unit is 1:1:1, and the static noise tolerance and write tolerance are obtained by adjusting the bag injection parameters.

[0029] The aforementioned static random access memory (SRAM) and its fabrication method achieve the following beneficial effects: By designing a special layout structure where the active region channels of the transfer transistor and the pull-down transistor are perpendicular to each other, combined with a bag-shaped ion implantation process at an inclined angle, and utilizing the shadow blocking effect of the shallow trench isolation sidewalls and photoresist on the inclined ion beam, the doping of the transfer transistor and the pull-down transistor channels can be independently controlled separately. Without adding an additional photomask, the electrical parameters of the pull-down transistor and the transfer transistor can be freely adjusted, thereby optimizing a more suitable current ratio β and γ, significantly improving the static noise margin and write margin of the SRAM cell. On the other hand, this application maintains the basic structure of a six-transistor memory cell, without needing to split the transfer transistor into read and write transistors, nor increasing the number of transistors; therefore, the cell area does not increase, and the storage density remains unaffected. Simultaneously, lightly doped drain implantation can still use uniform implantation conditions, without needing an additional implantation photomask, effectively controlling manufacturing costs. Furthermore, the design of the pull-down transistor and the pull-up transistor sharing the same gate polysilicon further simplifies the layout structure and improves the compactness of the layout. The overall solution takes into account the requirements of performance, area, and cost. Attached Figure Description

[0030] Figure 1 This is a flowchart illustrating a method for preparing a static random access memory (SRAM) in one embodiment.

[0031] Figure 2 This is a structural design layout of a static random access memory in one embodiment;

[0032] Figure 3 This is a schematic diagram of the structure of a static random access memory in one direction according to one embodiment;

[0033] Figure 4 This is a schematic diagram of the structure of a static random access memory in another direction in one embodiment;

[0034] Figure 5 This is a schematic diagram of the injection angle for bag-shaped ion implantation using a pull-down tube in one embodiment;

[0035] Figure 6 This is a schematic diagram of the implantation angle for bag-shaped ion implantation using a transport tube in one embodiment. Detailed Implementation

[0036] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0037] In one embodiment, such as Figure 1As shown, a method for fabricating a static random access memory (SRAM) is disclosed, which includes the following steps:

[0038] S1: Provide a semiconductor substrate, on which a shallow trench isolation structure 104 and an active region 103 are formed, wherein the active region 103 of the transmission transistor and the active region 103 of the pull-down transistor are perpendicular to each other in the channel direction, and the pull-down transistor and the pull-up transistor are located on the same active region 103.

[0039] S2: Trap ion implantation is performed on the active region 103 to form a gate structure, the gate structure including a gate oxide layer 102 and a gate polysilicon 101, wherein the pull-down transistor and the pull-up transistor share the same gate polysilicon 101.

[0040] S3: Perform lightly doped drain ion implantation. The transport tube and pull-down tube use the same lightly doped drain implantation conditions.

[0041] S4: Bag ion implantation is performed on the transport tube and the pull-down tube respectively. The difference in the shadowing effect caused by the vertical channel direction is utilized to obtain different channel doping distributions for the transport tube and the pull-down tube.

[0042] S5: Complete the second sidewall, heavily doped source / drain implantation, self-aligned metal silicide, contact vias, and metal interconnects processes to form a complete static random access memory cell.

[0043] This embodiment details the manufacturing method of static random access memory (SRAM) and its corresponding semiconductor device structure. The entire manufacturing process mainly includes substrate preparation, shallow trench isolation and active region 103 formation, trap ion implantation, gate structure fabrication, lightly doped drain implantation, bag ion implantation, sidewall and source / drain heavy doping, metal silicide formation, contact vias, and metal interconnection. Each step is explained below with specific process parameters.

[0044] Please refer to Figures 2 to 4In this embodiment, step S1 specifically includes substrate preparation and shallow trench isolation formation. First, a P-type single-crystal semiconductor substrate is selected as the starting material. The substrate surface is first subjected to standard cleaning treatment to remove surface particles, organic contaminants, and the natural oxide layer, providing a clean surface for subsequent processes. Then, the shallow trench isolation structure 104 is fabricated. First, a pad oxide layer is grown on the substrate surface using a thermal oxidation process. This oxide layer is used to alleviate the stress caused by the subsequent silicon nitride layer. Next, a silicon nitride layer is deposited on the pad oxide layer using a low-pressure chemical vapor deposition process. This silicon nitride layer is used as a hard mask in the subsequent shallow trench etching. The shallow trench isolation pattern is transferred to photoresist using a photolithography process. Then, using the photoresist and the silicon nitride hard mask as barrier layers, a dry etching process is used to etch shallow trenches in the silicon substrate. A trench oxide layer is grown on the inner wall of the trench using a thermal oxidation process. This oxide layer can repair lattice damage caused by etching, reduce interface state density, and make the trench sidewalls smoother. Next, a high-density plasma chemical vapor deposition process is used to fill the shallow trench with silicon oxide material, completely filling it. After filling, a chemical mechanical polishing process is used to planarize the wafer surface, using a silicon nitride layer as a polishing stop layer to remove excess silicon oxide outside the trench. Finally, a hot phosphoric acid wet etching process is used to remove the silicon nitride layer, and then a dilute hydrofluoric acid process is used to remove the pad oxide layer, ultimately obtaining a smooth shallow trench isolation structure 104. The shallow trench isolation structure 104 defines the active region 103 range of each transistor. According to the design of this embodiment, the active region 103 of the transmission transistor extends along a first direction, and the active regions 103 of the pull-down and pull-up transistors extend along a second direction, with the first and second directions perpendicular to each other, i.e., forming a 90-degree angle.

[0045] Step S2 in this embodiment specifically includes well ion implantation. After shallow trench isolation is completed, ion implantation of N-wells and P-wells is performed. First, the N-well region is defined using a photoresist mask, and N-type impurities are implanted. The implanted impurities can be phosphorus or arsenic. The N-well is used to fabricate pull-up transistors, i.e., P-type metal-oxide-semiconductor transistors. After N-well implantation, the photoresist is removed, and then the P-well region is defined using another photolithography step, and P-type impurities are implanted. The implanted impurities are boron or boron difluoride. The P-well is used to fabricate pull-down transistors and transport transistors, i.e., N-type metal-oxide-semiconductor transistors. After well implantation, high-temperature well push-pull annealing is performed. The purpose of annealing is to fully activate the implanted impurities and diffuse them inward, forming a well structure with a certain depth and concentration distribution.

[0046] Step S2 of this embodiment further includes the fabrication of the gate structure. After the well structure is completed, the gate structure is fabricated. First, a gate oxide layer 102 is grown. An ultrathin gate oxide layer is grown on the surface of the active region 103 using a thermal oxidation process or a chemical oxidation process. After the gate oxide layer 102 is grown, a gate polysilicon layer 101 is deposited using a chemical vapor deposition process. During the polysilicon deposition process, N-type impurities such as phosphorus are doped in situ, making the polysilicon exhibit an N-type heavily doped state and reducing the sheet resistance of the gate. After the polysilicon deposition is completed, the polysilicon layer is patterned using photolithography and dry etching processes to form the gate line. According to the design of this embodiment, the pull-down transistor and the corresponding pull-up transistor share the same gate polysilicon 101. This gate line spans across the active region 103 shared by the pull-down and pull-up transistors and serves as the gate electrode of both transistors. This shared gate design not only saves layout area but also ensures the natural consistency of the gate potentials of the two transistors. After the gate etching is completed, ion implantation can be performed to adjust the threshold voltage of the gate. For N-type transistors, i.e., pull-down and transmission transistors, P-type impurities such as boron are injected to adjust the threshold voltage; for P-type transistors, i.e., pull-up transistors, N-type impurities such as arsenic or phosphorus are injected to adjust the threshold voltage. The dosage of the threshold voltage injection is precisely set according to the target threshold voltage.

[0047] Step S3 in this embodiment specifically includes lightly doped drain ion implantation. After the gate structure is formed, lightly doped drain ion implantation is performed. The function of the lightly doped drain structure is to reduce the electric field strength at the source-drain junction, suppress the hot carrier effect, and improve the reliability of the device. First, N-type lightly doped drain implantation is performed. The P-type transistor region is masked with photoresist, and N-type impurity implantation is performed uniformly on the N-type transistor region, i.e., the pull-down transistor and the transport transistor. The implanted impurity is arsenic or phosphorus. In this embodiment, the pull-down transistor and the transport transistor share the same lightly doped drain implantation conditions, and it is not necessary to set separate implantation photomasks for the two types of transistors. This is the same as the conventional solution and will not add additional process steps or costs. After the lightly doped drain implantation is completed, the photoresist is removed. Then, P-type lightly doped drain implantation is performed. The N-type transistor region is masked with photoresist, and P-type impurity implantation is performed on the P-type transistor region where the pull-up transistor is located. The implanted impurity is boron difluoride or boron, and the implantation dose and energy are determined according to the device design requirements.

[0048] Step S4 in this embodiment specifically includes bag-shaped ion implantation. After light doping and drain implantation are completed, bag-shaped ion implantation is performed. Bag-shaped implantation, also known as halo implantation, uses a large-angle tilting implantation method to implant impurities below both ends of the channel, forming a pocket-shaped doping distribution to suppress short-channel effects and drain-induced barrier reduction effects. Please refer to... Figure 5 and Figure 6This embodiment utilizes the structural feature that the channels of the transport transistor and the pull-down transistor are perpendicular to each other, and achieves independent control of the doping of the two types of transistor channels through two separate bag implantations. First, bag implantation of the transport transistor is performed. Areas that do not need implantation are protected by a photoresist mask, exposing only the static random access memory region. The implanted impurity is boron or boron difluoride, a P-type impurity used for bag implantation of N-type transistors. The implantation dose ranges from 1 × 10¹² ions per square centimeter to... The implantation tilt angle, i.e., the angle between the ion beam and the wafer normal, ranges from 30 degrees to 45 degrees. Figure 5 In this embodiment, the implantation angle is set to 30 degrees. The twist angle is set to 0 degrees, meaning the projection direction of the ion beam is parallel to the channel direction of the transport tube. During implantation, the wafer rotates twice, 180 degrees each time, to ensure symmetrical bag-shaped doping distribution on both sides of the channel. Next, bag-shaped ion implantation is performed using the pull-down tube. Boron or boron difluoride is used as the implanted impurity, with an implantation dose ranging from 1 × 10¹² ions per square centimeter. Each injection angle ranges from 30 degrees to 45 degrees. Figure 6 In this embodiment, the implantation angle is set to 30 degrees, and the torsion angle is also set to 0 degrees. During the implantation process, the wafer rotates twice, each time by 180 degrees. It is important to note that the torsion angle in this implantation is equivalent to a 90-degree rotation compared to the previous implantation, ensuring that the projection direction of the ion beam is parallel to the channel direction of the pull-down diode and perpendicular to the channel direction of the transport diode. As a result, in this implantation, the channel direction of the pull-down diode is parallel to the ion projection direction, allowing tilted ions to be effectively implanted below the channel of the pull-down diode, forming a bag-shaped doping distribution within the pull-down diode. The transport diode, however, because its channel direction is perpendicular to the ion projection direction, is blocked by the shadowing effect and receives almost no additional bag-shaped doping.

[0049] Through two independent bag-shaped ion implantations, the transport transistor and the pull-down transistor each achieved their own independently adjustable channel bag-shaped doping distributions. By adjusting parameters such as the dose, energy, and angle of the two implantations, key electrical parameters such as the threshold voltage, drain-induced barrier reduction effect, and subthreshold swing of the transport transistor and the pull-down transistor can be controlled separately. This allows for flexible adjustment of the current ratio β (the ratio of the pull-down transistor drive current to the transport transistor drive current) and the current ratio γ (the ratio of the transport transistor drive current to the pull-up transistor drive current). By properly matching the two sets of implantation parameters, the β value can be adjusted to above 1.2, and the γ value to above 1.5, enabling the static random access memory (SRAM) cells to obtain sufficiently high static noise margins and write margins, effectively improving the read and write stability of the cells. In this embodiment, the two bag-shaped implantations do not require additional photolithographic masks to separately block the transport transistor or the pull-down transistor. Separate implantation of the two types of devices is achieved solely by relying on the natural shading effect caused by the difference in channel orientation.

[0050] Step S5 of this embodiment further includes sidewall formation and heavily doped source / drain implantation. After bag-shaped ion implantation, a first secondary sidewall, i.e., an offset sidewall, is formed on both sides of the gate structure. Typically, a silicon oxide or silicon nitride thin film is deposited using chemical vapor deposition, followed by anisotropic dry etching to retain only a portion of the dielectric material on the gate sidewalls, forming the sidewall structure. For N-type transistors (i.e., pull-down and transport transistors), heavily doped N-type impurities such as arsenic or phosphorus are implanted to form low-resistance source and drain electrodes. For P-type transistors (i.e., pull-up transistors), heavily doped P-type impurities such as boron or boron difluoride are implanted to form heavily doped P-type source / drain regions.

[0051] Step S5 of this embodiment further includes a self-aligned metal silicide process. After the sidewalls are completed, a self-aligned metal silicide process is performed to reduce the contact resistance of the source / drain regions and the gate. First, a metal thin film is sputtered and deposited on the wafer surface. After deposition, a first annealing is performed to allow the metal to react with the silicon on the surface of the active region 103 and the gate polysilicon 101 to form metal silicides. On dielectric surfaces such as silicon oxide and silicon nitride, the metal does not react with silicon and remains in a metallic state. After the first annealing, a wet etching process is used to remove the unreacted metal portion, leaving only the silicide region. Then, a second high-temperature annealing is performed to transform the metal silicide from a high-resistivity phase to a low-resistivity phase, further reducing the contact resistance. After the self-aligned silicide process, a low-resistivity metal silicide layer is formed on the surface of the source / drain regions of the pull-down transistor, the transfer transistor, and the pull-up transistor, as well as on the surface of the gate polysilicon 101, effectively reducing the contact resistance and improving the device's operating speed.

[0052] Step S5 of this embodiment further includes contact holes and metal interconnects. After the silicide process is completed, a first metal pre-dielectric layer is deposited. The dielectric material is typically boron-phosphorus-doped silicate glass or tetraethyl orthosilicate silicon oxide. After deposition, chemical mechanical polishing is performed to planarize the dielectric surface and obtain a smooth dielectric surface. Next, photolithography and etching of the contact holes are performed. Contact holes are etched above the source, drain, and gate electrodes where electrodes need to be brought out, penetrating the dielectric layer to the underlying metal silicide surface. Then, a barrier layer and tungsten metal are sputtered, and excess tungsten is removed by chemical mechanical polishing to form tungsten contact plugs. After the contact holes are completed, the first metal interconnect is fabricated. An aluminum-copper alloy or copper interconnect process is used to form metal interconnect lines. According to the layout design of this embodiment, the drains of the two pull-up transistors are internally connected through the first layer of metal interconnects. The two memory nodes, node 1 and node 2, are cross-coupled through metal interconnects. Specifically, node 1 is connected to the output of the left inverter and the input gate of the right inverter, and node 2 is connected to the output of the right inverter and the input gate of the left inverter, thus forming a bistable cross-coupled latch structure. The gate of the transmission transistor is connected to the word line. The source of the pull-up transistor is connected to the power supply voltage, and the source of the pull-down transistor is connected to the ground voltage.

[0053] The static random access memory (SRAM) semiconductor device formed by the above manufacturing method has the following structural features: an active region 103 defined by a shallow trench isolation structure 104 is formed on the substrate, wherein the channel direction of the active region 103 of the transfer transistor is perpendicular to the channel direction of the active region 103 of the pull-down transistor; each pull-down transistor and its corresponding pull-up transistor are located on the same active region 103 and share the same gate structure; the channel below the transfer transistor and the channel below the pull-down transistor have different bag-shaped doping distributions, and their threshold voltages and drive currents can be adjusted separately; the overall structure is a six-transistor unit, with the ratio of the number of fins of the transfer transistor, pull-down transistor, and pull-up transistor being 1:1:1. On the other hand, since the electrical parameters of the transfer transistor and the pull-down transistor can be adjusted separately through two bag-shaped injections, the β and γ values ​​can be optimized to the optimal range, the static noise margin of the cell can be effectively improved, and the write margin is also significantly improved, effectively improving the read / write stability and yield of the memory cell. At the same time, the cell area maintains the compact size of the traditional six-transistor structure, without increasing the number of transistors, and the storage density is not affected. In terms of process, there is no need to add an additional trap implantation or lightly doped drain implantation mask. The parameters can be controlled separately by simply performing two bag implantations with different twist angles. The overall manufacturing cost increase is very limited, and it has a high cost performance.

[0054] On the other hand, please continue to refer to Figures 2 to 4 This embodiment describes the static random access memory (SRAM) cell in detail from the perspective of semiconductor device structure. The semiconductor device described in this embodiment corresponds to the product structure prepared by the manufacturing method described in Embodiment 1, and the two correspond and corroborate each other in technical features. The semiconductor device of the static random access memory is a six-transistor memory cell structure, mainly including a semiconductor substrate, a shallow trench isolation structure 104, an active region 103, six metal-oxide-semiconductor transistors (MOS transistors), namely two transfer transistors, two pull-down transistors, and two pull-up transistors, a gate structure, a sidewall structure, source and drain doped regions, a metal silicide layer, and a multilayer metal interconnect structure. The structure of each part and its interrelationships are described one by one below.

[0055] I. Semiconductor Substrate and Trap Structure

[0056] The semiconductor substrate is a P-type single-crystal silicon substrate, with both N-well and P-well structures formed inside. The N-wells house two P-type pull-up transistors, while the P-wells house two N-type pull-down transistors and two N-type transfer transistors. The N-wells are formed by N-type impurity ion implantation followed by high-temperature push-well annealing, with phosphorus or arsenic as the dopant. The P-wells are formed by P-type impurity ion implantation followed by high-temperature push-well annealing, with boron as the dopant. The N-wells and P-wells are adjacent to each other, together forming the substrate doping basis for the six-transistor memory cell.

[0057] II. Shallow trench isolation structure 104 and active region 103

[0058] A shallow trench isolation structure 104 is formed on the upper part of the semiconductor substrate to define the active region 103 of each transistor and achieve electrical isolation between different transistors. The shallow trench is filled with silicon oxide dielectric material, and a thin trench oxide layer is grown on the inner wall of the trench. The top surface of the shallow trench isolation is substantially flush with the silicon surface of the active region 103, and the overall surface is flat.

[0059] The active regions 103 defined by the shallow trench isolation structure 104 are divided into two categories, with the channel directions of the two types of active regions 103 being perpendicular to each other. The first type is the active region 103 for transmission transistors, extending along the first direction, i.e., the horizontal direction, and used to form two transmission transistors. Each transmission transistor occupies its own active region 103, and the two transmission transistor active regions 103 are parallel to each other. The second type is the active region 103 shared by pull-down and pull-up transistors, extending along the second direction, i.e., the vertical direction. The first direction and the second direction form a 90-degree angle, that is, the channel current direction of the transmission transistor is perpendicular to the channel current direction of the pull-down transistor.

[0060] Each pull-down and pull-up transistor shares an active region 103, with one pull-down transistor and one pull-up transistor arranged sequentially along the length of the active region 103. The pull-down transistor is located in the P-well region, and the pull-up transistor is located in the N-well region. The two transistors are connected end-to-end on the active region 103 without any shallow trench isolation in between. The entire memory cell has two such shared active regions 103, corresponding to the left and right inverters respectively.

[0061] The above-mentioned vertically arranged active region 103 structure is one of the core structural features of the device in this embodiment, providing a structural basis for the subsequent use of the shadow effect to realize separate bag injection of the two types of transistors.

[0062] III. Transistor Structure

[0063] 1. Gate structure

[0064] The gate structure spans above the active region 103 and, from bottom to top, includes a gate oxide layer 102 and a gate polysilicon layer 101. The gate oxide layer 102 is made of thermally oxidized silicon dioxide. The gate polysilicon layer 101 is made of in-situ doped N-type polysilicon. According to the structural design of this embodiment, the pull-down transistor and its corresponding pull-up transistor share the same gate polysilicon layer 101. That is, the same gate line spans above both the pull-down and pull-up transistor active regions 103, serving as the gate electrode for both transistors. The extension direction of the gate line is perpendicular to the length direction of the active region 103. This shared gate design not only simplifies the layout structure and saves cell area but also ensures the natural consistency of the gate potentials of the pull-down and pull-up transistors in the same inverter. The two transmission transistors each have independent gate structures, and their gates are interconnected and connected to the word line.

[0065] 2. Lightly doped drain region and heavily doped source / drain region

[0066] On both sides of the gate structure, lightly doped drain regions and heavily doped source / drain regions are formed. The lightly doped drain region is located on the side closer to the channel, with a relatively low doping concentration, used to mitigate the electric field at the source / drain junction. For N-type transistors, i.e., pull-down transistors and transport transistors, the lightly doped drain region is N-type doped, with arsenic or phosphorus as the impurity. The lightly doped drain regions of pull-down transistors and transport transistors use the same doping conditions and doping distribution.

[0067] Heavily doped source / drain regions are located outside the lightly doped drain regions, with a higher doping concentration, and are used to form low-resistance source and drain contact regions. In N-type transistors, the heavily doped source / drain regions contain arsenic or phosphorus as impurities. In P-type transistors (pull-up transistors), the heavily doped source / drain regions contain boron or boron difluoride as impurities.

[0068] 3. Pouch-shaped doped region

[0069] At the lower ends of the channel region, bag-shaped doped regions, also known as halo-shaped doped regions, are formed. These bag-shaped doped regions are arc-shaped and distributed below the source-drain junctions at both ends of the channel, extending slightly towards the center of the channel. They are used to suppress short-channel effects and drain-induced barrier reduction effects. In this embodiment, the bag-shaped doping distribution below the channel of the transport transistor and the pull-down transistor are different. Specifically, the bag-shaped doped regions of the transport transistor are formed by a first bag-shaped ion implantation, with boron or boron difluoride as the dopant. The doping concentration and distribution depth are determined by the dose and energy of the first implantation. The bag-shaped doped regions of the pull-down transistor are formed by a second bag-shaped ion implantation, also with boron or boron difluoride doping, but the doping concentration and distribution depth are independently determined by the parameters of the second implantation.

[0070] Because the parameters for the two implantations can be adjusted separately, the bag doping concentration, junction depth, and impact on the threshold voltage differ between the transport transistor and the pull-down transistor, resulting in different threshold voltages and saturation drive currents for the two types of transistors. By adjusting the two sets of bag implantation parameters, the current ratio β (the ratio of the pull-down drive current to the transport transistor drive current) and the current ratio γ (the ratio of the transport transistor drive current to the pull-up drive current) can be independently controlled. This allows β to be adjusted to above 1.2 and γ to above 1.5, achieving optimal static noise margin and write margin. The difference in bag doping distribution between the two types of transistors stems from the perpendicular channel direction of the active region 103 of the transport transistor and the pull-down transistor, causing the tilted ion beam to produce varying degrees of shadowing blocking effect on the channel in different directions.

[0071] 4. Side wall structure

[0072] Sidewall structures are formed on both sides of the gate structure. The sidewall structures include a first secondary sidewall, i.e., an offset sidewall, and a second secondary sidewall, i.e., a main sidewall. The first secondary sidewall is made of silicon oxide or silicon nitride and is used to define the extent of the lightly doped drain region. The second secondary sidewall is typically made of silicon nitride and is used to separate the source / drain contact region from the gate, preventing self-aligned metal silicide bridging.

[0073] 5. Self-aligned metal silicide layer

[0074] A self-aligned metal silicide layer is formed on the surface of the heavily doped source / drain regions and on the top surface of the gate polysilicon 101. The metal silicide material can be cobalt silicide, nickel silicide, or nickel-platinum silicide, etc. The metal silicide layer exhibits low resistance characteristics, which can significantly reduce the source / drain contact resistance and gate resistance, thereby improving the operating speed of the device.

[0075] IV. Metal Interconnect Structure

[0076] 1. Contact hole and contact plug

[0077] Above the transistor structure, a first metal-front dielectric layer is deposited. Multiple contact holes are formed in the dielectric layer, located above the source, drain, and gate of each transistor, respectively. The contact holes penetrate the dielectric layer to reach the surface of the underlying metal silicide.

[0078] 2. First layer of metal interconnect

[0079] Above the contact plug, a first layer of metal interconnect lines is formed. The metal material is typically an aluminum-copper alloy or copper. The first layer of metal interconnect lines is wired according to the circuit connection relationship of a six-transistor static random access memory (SRAM), realizing cross-coupling connections between the transistors. The above metal interconnect structure fully realizes the circuit function of a six-transistor SRAM. Specifically, the drains of the two pull-up transistors are internally connected through the first metal layer, and the two memory nodes are cross-coupled.

[0080] 3. Upper metal interconnect and passivation layer

[0081] Depending on the overall wiring requirements of the chip, a second, third, or even more layers of metal interconnect structures can be fabricated on top of the first metal layer, with the metal layers connected through vias.

[0082] V. Number of fins and unit area

[0083] In the six-transistor memory cell described in this embodiment, the ratio of the number of fins for the transmission transistor, pull-down transistor, and pull-up transistor is 1:1:1, meaning that all three types of transistors use a single-fin design. In finned field-effect transistor technology, the single-fin structure is the choice for achieving the smallest cell area.

[0084] In summary, the static random access memory (SRAM) semiconductor device described in this embodiment, through a unique layout where the active regions 103 of the transfer transistor and pull-down transistor are perpendicular to each other in channel direction, combined with their independently adjustable pouch doping distributions, achieves flexible control of the current ratios β and γ while maintaining a six-transistor structure and single-fin configuration. This results in higher static noise margin and write margin. The device has a compact structure, good process compatibility, and does not require an additional photomask, offering significant advantages in performance, area, and cost.

[0085] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0086] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for fabricating a static random access memory (SRAM), characterized in that, Includes the following steps: A semiconductor substrate is provided, on which a shallow trench isolation structure and an active region are formed, wherein the active region of the transmission transistor and the active region of the pull-down transistor are perpendicular to each other in channel direction, and the pull-down transistor and the pull-up transistor are located on the same active region. Trap ion implantation is performed on the active region to form a gate structure, the gate structure including a gate oxide layer and a gate polysilicon layer, wherein the pull-down transistor and the pull-up transistor share the same gate polysilicon layer; Lightly doped drain ion implantation is performed, and the same lightly doped drain implantation conditions are used for the transport tube and the pull-down tube. Bag-shaped ion implantation was performed on the transport tube and the pull-down tube respectively. By utilizing the difference in the shadowing effect caused by the perpendicularity of the channel direction, the transport tube and the pull-down tube obtained different channel doping distributions. The second sidewall, heavily doped source-drain implantation, self-aligned metal silicide, contact vias, and metal interconnects are completed to form a complete static random access memory cell.

2. The method for preparing a static random access memory according to claim 1, characterized in that, The active channel direction of the transmission tube forms a 90-degree angle with the active channel direction of the pull-down tube.

3. The method for preparing a static random access memory according to claim 1, characterized in that, The pull-down diode and pull-up diode are arranged side by side along the length of the active region, and they share the same gate polysilicon strip spanning above the active region.

4. The method for preparing a static random access memory according to claim 1, characterized in that, When performing bag-shaped ion implantation on the transport tube, the implanted impurity is boron or boron difluoride, the implantation tilt angle ranges from 30 degrees to 45 degrees, the twist angle is 0 degrees, and the wafer rotates twice during the implantation process, each rotation being 180 degrees.

5. The method for preparing a static random access memory according to claim 1, characterized in that, When performing bag-shaped ion implantation on a pull-down tube, the implanted impurity is boron or boron difluoride, and the implantation dose ranges from 1 × 10¹² ions per square centimeter to... The implantation tilt angle ranges from 30 to 45 degrees, the twist angle is 0 degrees, and the wafer rotates twice during the implantation process, each rotation being 180 degrees.

6. A static random access memory, characterized in that, include: Semiconductor substrate; A shallow trench isolation structure formed in the substrate and an active region defined by the shallow trench isolation structure; A six-tube memory cell consisting of two transmission tubes, two pull-down tubes, and two pull-up tubes; wherein the active area channel direction of the transmission tubes is perpendicular to the active area channel direction of the pull-down tubes, and the pull-down tubes and their corresponding pull-up tubes are located on the same active area. The gate structure is such that the pull-down transistor and the corresponding pull-up transistor share the same gate structure. Metal interconnect structures are used to achieve cross-coupling connections between transistors.

7. The static random access memory according to claim 6, characterized in that, The active region of the transmission tube extends along a first direction, and the active regions of the pull-down tube and the pull-up tube extend along a second direction, wherein the first direction and the second direction are perpendicular to each other.

8. The static random access memory according to claim 6, characterized in that, The drain terminals of the two pull-up transistors are connected by the first layer of metal interconnects, and the two memory nodes are respectively connected to the gates on the opposite side by the second metal interconnects, forming a bistable latch structure.

9. The static random access memory according to claim 6, characterized in that, The channel of the transmission tube has a different bag-shaped doping distribution below it than the channel of the pull-down tube.

10. The static random access memory according to claim 6, characterized in that, The source of the transmission transistor is connected to the bit line, and the gate is connected to the word line; the source of the pull-down transistor is grounded, and the drain is connected to the memory node; the source of the pull-up transistor is connected to the power supply, and the drain is connected to the memory node.

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