10T SRAM (Static Random Access Memory) storage unit applied to multi-bit storage and calculation integrated multiplication circuit

Abstract

The invention provides a 10T SRAM (Static Random Access Memory) storage unit applied to a multi-bit storage and calculation integrated multiplication circuit, which comprises a first phase inverter, a second phase inverter, a first NMOS (N-channel Metal Oxide Semiconductor) tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube and a first PMOS (P-channel Metal Oxide Semiconductor) tube, the output end of the first phase inverter and the input end of the second phase inverter are connected with the drain electrode of the second NMOS tube; the grid electrode of the first NMOS tube is controlled by a word line, and the source electrode of the first NMOS tube is connected with the first write-in end; the grid electrode of the second NMOS tube is controlled by the word line, and the source electrode of the second NMOS tube is connected with the second write-in end; the grid electrode of the third NMOS tube is connected with the first storage node, the drain electrode of the third NMOS tube is connected with the source electrode of the fourth NMOS tube, and the source electrode of the third NMOS tube is grounded; the drain electrode of the fourth NMOS tube is connected with the first reading end, and the grid electrode of the fourth NMOS tube is connected with a first control signal. According to the invention, the in-memory calculation of the multi-bit multiplication circuit is realized.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a 10T SRAM storage unit applied to a multi-bit storage-calculation integrated multiplication circuit. Background Art

[0002] In recent years, the storage-computing integrated computing architecture has attracted more and more attention and is expected to become a new architecture that breaks through the von Neumann bottleneck. Storage-computing integrated means moving part or all of the computing to the storage, so that the storage unit has computing functions. This architecture eliminates data access latency and power consumption, breaks through the von Neumann bottleneck, and is unanimously recognized by the industry and academia as a future development trend.

[0003] According to the distance between storage and computing, storage-computing integrated technology solutions are divided into three categories: near memory computing (Near Memory), in-memory processing (In-Memory-Periphery) and in-memory computing (In-Memory-Array).

[0004] SRAM is currently the only storage medium that is fully compatible with advanced CMOS processes and can be mass-produced. The compatibility of SRAM with advanced processes makes its peripheral logic interface best meet the requirements of efficient utilization of current macro units. The design technology of SRAM is very mature. Compared with new non-volatile memories, SRAM's manufacturing process, R&D tools, and CMOS integrated circuit models are more mature and stable. At the same time, SRAM has faster operating speed and durability, and can refresh calculation data in storage and calculation units in real time, providing important guarantees for large computing power.

[0005] How to realize multi-bit multiplication circuit through SRAM storage unit is the direction we want to study. Summary of the invention

[0006] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a 10T SRAM storage unit applied to a multi-bit storage-computation integrated multiplication circuit, for realizing in-memory calculation of the multi-bit multiplication circuit.

[0007] To achieve the above-mentioned and other related purposes, the present invention provides a 10T SRAM storage cell applied to a multi-bit storage-computation integrated multiplication circuit, which comprises:

[0008] a first inverter, a second inverter, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor and a first PMOS transistor,

[0009] The input end of the first inverter and the output end of the second inverter are connected to the drain of the first NMOS tube, and the connection point is recorded as a first storage node, the output end of the first inverter and the input end of the second inverter are connected to the drain of the second NMOS tube, and the connection point is recorded as a second storage node, wherein the second storage node and the first storage node are mutually coupled storage nodes and are logically inverted;

[0010] The gate of the first NMOS tube is controlled by a word line, and the source thereof is connected to the first writing end;

[0011] The gate of the second NMOS tube is controlled by the word line, and the source thereof is connected to the second writing end;

[0012] The gate of the third NMOS tube is connected to the first storage node, the drain of the third NMOS tube is connected to the source of the fourth NMOS tube, and the source of the third NMOS tube is grounded;

[0013] The drain of the fourth NMOS tube is connected to the first reading end, and the gate thereof is connected to the first control signal;

[0014] The gate of the first PMOS tube is connected to the second storage node, the drain of the first PMOS tube is connected to the drain of the fifth NMOS tube, and the source of the first PMOS tube is connected to the operating voltage;

[0015] The source of the fifth NMOS tube is connected to the second reading end, and the gate thereof is connected to the second control signal.

[0016] Optionally, the first control signal controls the switch of the fourth NMOS tube, and the second control signal controls the switch of the fifth NMOS tube.

[0017] Optionally, the first reading end is pre-charged with a high potential; and the second reading end is pre-charged with a low potential.

[0018] Optionally, the current at the first reading end is proportional to the current at the second reading end.

[0019] Optionally, the current ratio between the first reading end and the second reading end is adjusted by adjusting device sizes of the third NMOS tube, the fourth NMOS tube, the first PMOS tube, and the fifth NMOS tube.

[0020] Optionally, the first inverter includes a second PMOS tube and a sixth NMOS tube, the source of the second PMOS tube is connected to the operating voltage, the drain of the second PMOS tube is connected to the drain of the sixth NMOS tube, and the gate of the second PMOS tube is connected to the gate of the sixth NMOS tube to form the first storage node; the source of the sixth NMOS tube is grounded.

[0021] Optionally, the second inverter includes a third PMOS tube and a seventh NMOS tube, the source of the third PMOS tube is connected to the operating voltage, the drain of the third PMOS tube is connected to the drain of the seventh NMOS tube, and the gate of the third PMOS tube is connected to the gate of the seventh NMOS tube to form a second storage node; the source of the seventh NMOS tube is grounded.

[0022] As described above, the 10T SRAM storage unit applied to the multi-bit storage-calculation integrated multiplication circuit of the present invention enables the multi-bit multiplication circuit to realize in-memory calculation by providing the 10T SRAM storage unit, thereby improving the operation speed of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 Shown is a circuit diagram of a 10T SRAM storage cell applied to a multi-bit storage-calculation-in-one multiplication circuit of the present invention.

[0024] Figure 2 Shown is a circuit diagram of a first inverter and a second inverter of the present invention.

[0025] Figure 3 Shown is a circuit diagram of the present invention for implementing a 2bit*2bit multiplication function.

[0026] Figure 4 Shown as the present invention Figure 3 Schematic diagram of current flow in the circuit shown. DETAILED DESCRIPTION

[0027] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0028] See also Figures 1 to 4 It should be noted that the illustrations provided in this embodiment are only schematic illustrations of the basic concept of the present invention. Although the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation, the form, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the component layout may also be more complicated.

[0029] like Figure 1 As shown, this embodiment provides a 10T SRAM storage cell applied to a multi-bit storage-computation integrated multiplication circuit, which includes:

[0030] A first inverter INV1, a second inverter INV2, a first NMOS transistor M1, a second NMOS transistor M2, a third NMOS transistor M3, a fourth NMOS transistor M4, a fifth NMOS transistor M5 and a first PMOS transistor P1,

[0031] The input end of the first inverter INV1 and the output end of the second inverter INV2 are connected to the drain of the first NMOS tube M1, and the connection point is marked as the first storage node W, the output end of the first inverter INV1 and the input end of the second inverter INV2 are connected to the drain of the second NMOS tube M2, and the connection point is marked as the second storage node W', wherein the second storage node W' and the first storage node W are mutually coupled storage nodes and are logically inverted;

[0032] The gate of the first NMOS transistor M1 is controlled by the word line WL, and the source thereof is connected to the first writing terminal BLB;

[0033] The gate of the second NMOS transistor M2 is controlled by the word line WL, and the source thereof is connected to the second writing terminal BL;

[0034] The gate of the third NMOS transistor M3 is connected to the first storage node W, the drain of the third NMOS transistor M3 is connected to the source of the fourth NMOS transistor M4, and the source of the third NMOS transistor M3 is grounded;

[0035] The drain of the fourth NMOS transistor M4 is connected to the first reading terminal RBL[0], and the gate thereof is connected to the first control signal X[0];

[0036] The gate of the first PMOS transistor P1 is connected to the second storage node W', the drain thereof is connected to the drain of the fifth NMOS transistor M5, and the source thereof is connected to the working voltage;

[0037] The source of the fifth NMOS transistor M5 is connected to the second read end RBL[1], and the gate thereof is connected to the second control signal X[1].

[0038] like Figure 2 As shown, specifically, the first inverter INV1 includes a second PMOS tube P2 and a sixth NMOS tube M6, the source of the second PMOS tube P2 is connected to the working voltage, the drain thereof is connected to the drain of the sixth NMOS tube M6, and the gate thereof is connected to the gate of the sixth NMOS tube M6 to form the first storage node W; the source of the sixth NMOS tube M6 is grounded.

[0039] like Figure 2As shown, specifically, the second inverter INV2 includes a third PMOS tube P3 and a seventh NMOS tube M7, the source of the third PMOS tube P3 is connected to the working voltage, the drain thereof is connected to the drain of the seventh NMOS tube M7, and the gate thereof is connected to the gate of the seventh NMOS tube M7 to form a second storage node W'; the source of the seventh NMOS tube M7 is grounded.

[0040] Specifically, the first control signal X[0] controls the switch of the fourth NMOS transistor M4, and the second control signal X[1] controls the switch of the fifth NMOS transistor M5.

[0041] Specifically, the first read end RBL[0] is pre-charged with a high potential; and the second read end RBL[1] is pre-charged with a low potential.

[0042] Specifically, the current of the first read end RBL[0] is proportional to the current of the second read end RBL[1].

[0043] Specifically, the current ratio between the first read end RBL[0] and the second read end RBL[1] is adjusted by adjusting the device sizes of the third NMOS transistor M3, the fourth NMOS transistor M4, the first PMOS transistor P1, and the fifth NMOS transistor M5.

[0044] Furthermore, if Figure 3 As shown, in this embodiment, the circuit structure formed by combining the above two 10T SRAM storage units is realized to realize the 2bit*2bit multiplication function. In the circuit structure, the first 10T SRAM storage unit is represented as Q1, and the second 10T SRAM storage unit is represented as Q0. The circuit structure includes a first read terminal RBL[0], a second read terminal RBL[1], and a third read terminal RBL[2]. Moreover, the first write terminal in Q1 is represented as BLB[1], the second write terminal is represented as BL[1], the first storage node is represented as W[1], and the second storage node is represented as W'[1]. The first write terminal in Q0 is represented as BLB[0], the second write terminal is represented as BL[0], the first storage node is represented as W[0], and the second storage node is represented as W'[0].

[0045] In the process of layout implementation of this embodiment, the device sizes of the third NMOS tube / fourth NMOS tube and the first PMOS tube / fifth NMOS tube in Q0, and the third NMOS tube / fourth NMOS tube and the first PMOS tube / fifth NMOS tube in Q1 are adjusted to meet the design requirement of current I4:I3:I2:I1=4:2:2:1, so that the final result I of the multiplier is 总 =I4+I3+I2+I1. Moreover, if Figure 4As shown, in this embodiment, current I4 is obtained from the third read terminal RBL[2], current I3 is obtained from the second read terminal RBL[1], current I2 is obtained from the second read terminal RBL[1], and current I1 is obtained from the first read terminal RBL[0]. The multiplication function implemented by the circuit can be represented by the following truth table, where:

[0046] RBL[2] = X1&Q1 = X1*Q1;

[0047] RBL[2]=X1&Q1=X1*Q1+X0&Q1=X1*Q0+X0*Q1;

[0048] RBL[0]=X0&Q0=X0*Q0;

[0049] Truth Table 1

[0050]

[0051]

[0052] In summary, the 10T SRAM storage unit applied to the multi-bit storage-computation integrated multiplication circuit of the present invention provides a 10T SRAM storage unit to enable the multi-bit multiplication circuit to realize in-memory calculation and improve the circuit's operation speed. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0053] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A 10T SRAM storage cell applied to a multi-bit storage-computation integrated multiplication circuit, characterized in that: It includes: a first inverter, a second inverter, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor and a first PMOS transistor, The input end of the first inverter and the output end of the second inverter are connected to the drain of the first NMOS tube, and the connection point is recorded as a first storage node, the output end of the first inverter and the input end of the second inverter are connected to the drain of the second NMOS tube, and the connection point is recorded as a second storage node, wherein the second storage node and the first storage node are mutually coupled storage nodes and are logically inverted; The gate of the first NMOS tube is controlled by a word line, and the source thereof is connected to the first writing end; The gate of the second NMOS tube is controlled by the word line, and the source thereof is connected to the second writing end; The gate of the third NMOS tube is connected to the first storage node, the drain of the third NMOS tube is connected to the source of the fourth NMOS tube, and the source of the third NMOS tube is grounded; The drain of the fourth NMOS tube is connected to the first reading end, and the gate thereof is connected to the first control signal; The gate of the first PMOS tube is connected to the second storage node, the drain of the first PMOS tube is connected to the drain of the fifth NMOS tube, and the source of the first PMOS tube is connected to the operating voltage; The source of the fifth NMOS tube is connected to the second reading end, and the gate thereof is connected to the second control signal.

2. The 10T SRAM storage unit applied to a multi-bit storage-computation integrated multiplication circuit according to claim 1, characterized in that: The first control signal controls the switch of the fourth NMOS tube, and the second control signal controls the switch of the fifth NMOS tube.

3. The 10T SRAM storage unit applied to a multi-bit storage-computation integrated multiplication circuit according to claim 1 or 2, characterized in that: The first reading end is pre-charged with a high potential; the second reading end is pre-charged with a low potential.

4. The 10T SRAM storage unit applied to a multi-bit storage-computation integrated multiplication circuit according to claim 1, characterized in that: The current at the first read end is proportional to the current at the second read end.

5. The 10T SRAM storage unit applied to a multi-bit storage-computation integrated multiplication circuit according to claim 4, characterized in that: The current ratio between the first reading end and the second reading end is adjusted by adjusting the device sizes of the third NMOS tube, the fourth NMOS tube, the first PMOS tube, and the fifth NMOS tube.

6. The 10T SRAM storage unit applied to a multi-bit storage-computation integrated multiplication circuit according to claim 1, characterized in that: The first inverter includes a second PMOS tube and a sixth NMOS tube, the source of the second PMOS tube is connected to the working voltage, the drain of the second PMOS tube is connected to the drain of the sixth NMOS tube, and the gate of the second PMOS tube is connected to the gate of the sixth NMOS tube to form the first storage node; the source of the sixth NMOS tube is grounded.

7. The 10T SRAM storage unit applied to a multi-bit storage-computation integrated multiplication circuit according to claim 6, characterized in that: The second inverter includes a third PMOS tube and a seventh NMOS tube, the source of the third PMOS tube is connected to the working voltage, the drain of the third PMOS tube is connected to the drain of the seventh NMOS tube, and the gate of the third PMOS tube is connected to the gate of the seventh NMOS tube to form a second storage node; the source of the seventh NMOS tube is grounded.

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