Multiplier operation method, multiplier, field-programmable gate array and digital circuit

Abstract

The invention belongs to the field of multiplying units, and particularly discloses a multiplying unit operation method, a multiplying unit, a field-programmable gate array and a digital circuit, a multiplier is coded through Booth coding, and coding is carried out according to sign bit information of the multiplier for a sign integer multiplier; carrying out multiplication operation on the generated codes by utilizing a cross multiplication principle of the bark multiplication; and adding the multiplication operation result to obtain a final multiplication operation result. According to the invention, Booth coding and Vedic multiplication (bark multiplication) are combined, the operation speed is improved, area reduction and resource optimization are realized, and the performance of the multiplier is improved.

Description

Technical Field

[0001] The invention belongs to the field of multipliers, and in particular relates to a multiplier operation method, a multiplier, a field programmable gate array and a digital circuit. Background Art

[0002] At present, with the development and iteration of smart products, electronic devices are rapidly updated in the direction of small size, low power consumption and high speed. For electronic products, their speed depends on arithmetic operations. At the same time, in the current intelligent era, the application of technologies such as multimedia, artificial intelligence, machine learning, deep learning, and the Internet of Things also involves huge basic arithmetic calculations. Multiplication operation is an important computing unit in the processor, which determines the overall performance. Designing the processing module of any electronic device requires a high-speed multiplier.

[0003] For multipliers, their speed, area and power consumption are the main indicators of application. Speed ​​determines the computing efficiency of devices and models. The higher the speed, the smaller the latency, which in turn increases efficiency. The area problem determines the size and cost of chips and devices, limiting their development in compact devices. The power consumption problem affects the energy consumption and heat generation of the device. Currently, existing multipliers are based on traditional algorithms and structures. There is often a trade-off between area and speed. It is difficult to meet the requirements of small area and high speed at the same time. There are limitations when processing complex operations. There is still a lot of room for improvement in the above indicators. Summary of the invention

[0004] To solve the above problems, the present invention provides a multiplier operation method, a multiplier, a field programmable gate array and a digital circuit, which combine Booth coding and Vedic multiplication to improve the operation speed, achieve area reduction and resource optimization, and improve the performance of the multiplier.

[0005] In a first aspect, the technical solution of the present invention is a multiplier operation method, comprising the following steps: Encoding the multiplier by Booth coding, including encoding the multiplier according to the sign bit information of the multiplier for a signed integer multiplier; The generated codes are multiplied using the cross-multiplication principle of Vedic multiplication; The results of the multiplication operations are added together to obtain the final result of the multiplication operation.

[0006] In an optional implementation, the generated code is multiplied using the cross-multiplication principle of Vedic multiplication, specifically including: Each coded bit of the multiplier is ANDed with the corresponding bit of the multiplicand to achieve bit multiplication; The partial product elements obtained by bitwise multiplication are combined and calculated according to the cross-multiplication principle of Vedic multiplication.

[0007] In an optional implementation, the multipliers are Booth-encoded to generate partial products, specifically including: Use the Radix-4 Booth algorithm to combine every three consecutive multiplier bits into a new code group; Or, use the Radix-8 Booth algorithm to combine every four consecutive multiplier bits into a new encoding group.

[0008] In an optional implementation, every three consecutive multiplier bits are combined into a new coding group using the Radix-4 Booth algorithm, specifically including: receiving as input a multiplier and a multiplicand; Insert a "0" in the least significant bit of the multiplier; By looping through each bit of the multiplier, each consecutive three bits of the multiplier are converted into a corresponding encoding group according to the Booth encoding rule.

[0009] In an optional implementation, in the Radix-4 Booth algorithm, when three consecutive multipliers are 100, the encoding is -2, and when three consecutive multipliers are 101 or 110, the encoding is -1.

[0010] In an optional implementation, every four consecutive multiplier bits are combined into a new coding group using the Radix-8 Booth algorithm, specifically including: receiving as input a multiplier and a multiplicand; Insert a "0" in the least significant bit of the multiplier; By looping through each bit of the multiplier, each consecutive four bits of the multiplier are converted into the corresponding encoding group according to the Booth encoding rule.

[0011] In an optional implementation, the multiplication operation results are added to obtain a final result of the multiplication operation, specifically including: Receive multiplication operation results in parallel; The multiplication operation results are added together through a Wallace tree, a Dadda tree, or a carry-finding adder to obtain the final result of the multiplication operation.

[0012] In a second aspect, the technical solution of the present invention provides a multiplier that executes any of the calculation methods described above.

[0013] In a third aspect, the technical solution of the present invention provides a programmable gate array configured with the above-mentioned multiplier.

[0014] In a fourth aspect, the technical solution of the present invention provides a digital circuit configured with the above-mentioned programmable gate array.

[0015] The invention provides a multiplier operation method, a multiplier, a field programmable gate array and a digital circuit, which have the following beneficial effects compared with the prior art: firstly, the multiplier is encoded by Booth coding, then the generated code is multiplied by the cross-multiplication principle of Vedic multiplication, and finally the final result of the multiplication operation is obtained by addition. The invention reduces the critical path delay, improves the operation speed of the multiplier, reduces the area of ​​the multiplier and reduces the power by compressing the partial products by using the cross-multiplication principle of Vedic multiplication. BRIEF DESCRIPTION OF THE DRAWINGS In order to more clearly illustrate the technical solution of the present invention, the accompanying drawings required for use in the description will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0016] Figure 1 A flowchart of a multiplier operation method provided by an embodiment of the present invention.

[0017] Figure 2 Schematic diagram of a 4-bit wide Radix-4 multiplier.

[0018] Figure 3 Schematic diagram of a 4-bit wide Radix-8 multiplier.

[0019] Figure 4 Schematic diagram of 4-bit wide Vedic multiplication using the cross multiplication principle.

[0020] Figure 5 This is a schematic diagram of the overall architecture of BVR-4.

[0021] Figure 6 This is a schematic diagram of a BVR-4 multiplication example. DETAILED DESCRIPTION

[0022] In order to make the purpose, features and advantages of the present invention more obvious and easy to understand, the technical scheme of the present invention will be clearly and completely described below in conjunction with the drawings in this specific embodiment. Obviously, the embodiments described below are only part of the embodiments of the present invention, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0023] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used in the specification of the present invention herein are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0024] The key terms appearing in the present invention are explained below.

[0025] Booth coding: A binary coding method used to encode multiplication operations.

[0026] Vedic multiplication: also known as Vedic mathematics or part of ancient Indian mathematics, is a multiplication algorithm based on ancient Indian mathematics used to perform fast multiplication calculations.

[0027] In order to improve system performance, adapt to complex application requirements, and achieve the above-mentioned improvement effect, this embodiment provides a multiplier operation method, which combines the advantages of Booth coding and Vedic multiplication (Vedic multiplication), including three stages: PPG (partial product generation) - Booth coding Radix-4 and Radix-8 algorithms, PPR (partial product reduction) - Vedic multiplication (using UTsutra for parallel processing), PPA (partial accumulation and addition), improves the operating speed, achieves area reduction and resource optimization, and improves multiplier performance.

[0028] Figure 1 A schematic diagram of a multiplier operation method provided by an embodiment of the present invention is shown in FIG. Figure 1 As shown, the method specifically includes the following steps.

[0029] S1, encode the multiplier by Booth encoding, including encoding the signed integer multiplier according to the sign bit information of the multiplier.

[0030] S2, multiply the generated code using the cross-multiplication principle of Vedic multiplication.

[0031] S3, adding the multiplication operation results to obtain the final result of the multiplication operation.

[0032] The above step S1 implements the first stage, namely, PPG (partial product generation), which is implemented by Booth coding. The first stage is the first step in the multiplication operation and is also the basis for the subsequent partial product reduction (PPR) and partial accumulation and addition (PPA).

[0033] In this embodiment, generating partial products through Booth coding includes two aspects: on the one hand, using the Radix-4Booth algorithm to combine every three consecutive multiplier bits into a new coding group to generate partial products; on the other hand, using the Radix-8 Booth algorithm to combine every four consecutive multiplier bits into a new coding group to generate partial products. These two aspects divide Booth coding into the Radix-4 booth algorithm and the Radix-8 booth algorithm. According to the difference between the two algorithms, the multiplication operation in this embodiment is divided into BVR-4 (Booth-Vedic-Radix-4) and BVR-8 (Booth-Vedic-Radix-8).

[0034] For the Radix-4 booth algorithm, the consecutive multiplication bits overlap with the previous coding group. Every three consecutive multiplier bits are combined into a new coding group. To ensure the trinity, a -1 bit is added before the least significant bit. Figure 2 As shown in the figure, a 4-bit multiplier, with Mlr-1 added, will form two new coding groups (Yn0 and Yn1) due to the overlapped parts. For an 8-bit multiplier, four new coding groups Yn0, Yn1, Yn2 and Yn3 can be generated, and so on. Each coding group represents a specific mode of the multiplier. This encoding method can reduce the number of rows of partial products (PP) and reduce the number of rows of partial products to half of the original number.

[0035] For the BVR-4 method, every three consecutive multiplier bits are combined into a new coding group using the Radix-4 Booth algorithm, which specifically includes the following steps.

[0036] Step 1, receiving the multiplier and the multiplicand as input.

[0037] This step implements data input, receiving the multiplier (Mlr) and the multiplicand (Mld) as input.

[0038] Step 2, insert a "0" in the least significant bit of the multiplier.

[0039] This step implements the insertion of "0". A "0" is inserted into the least significant bit (LSB) of the multiplier (Mlr). This is a preprocessing step of Booth coding and is used to simplify subsequent calculations.

[0040] Step 3, by looping through each bit of the multiplier, converting each consecutive three bits of the multiplier into a corresponding coding group according to the Booth coding rule.

[0041] This step implements traversing the multiplier, Booth coding and multiplication. By looping through each bit of the multiplier (starting from the LSB, but because "0" is inserted, it actually starts from the second bit), according to the Booth coding rule, each consecutive three bits (or trits) of the multiplier are converted into corresponding coding groups, and then multiplied with the multiplicand to generate partial products. Table 1 shows the Booth coding rules.

[0042] Table 1: Booth encoding rules

[0043] For the Radix-8 booth algorithm, every four consecutive multiplier bits are combined into a new encoding group. This encoding method further reduces the number of rows of partial products. Figure 3 As shown, a 6-bit multiplier will form two new encoding groups (Yn0, Yn1), and so on for other bit multipliers, thereby further reducing the number of partial products.

[0044] For the BVR-8 algorithm, the steps are similar to those of BVR-4, but an 8-bit wide multiplier is processed. Every four consecutive multiplier bits are combined into a new coding group using the Radix-8 Booth algorithm, which includes the following steps.

[0045] Step 1, receiving the multiplier and the multiplicand as input.

[0046] This step implements data input, receiving the multiplier (Mlr) and the multiplicand (Mld) as input.

[0047] Step 2, insert a "0" in the least significant bit of the multiplier.

[0048] This step inserts "0" into the LSB of the multiplier.

[0049] Step 3, by looping through each bit of the multiplier, convert each consecutive 4 bits of the multiplier into a corresponding coding group according to the Booth coding rule.

[0050] This step implements grouping, Booth coding, and multiplication. The bits of the multiplier are divided into groups of 4 bits (due to the insertion of "0", 5-bit groups are actually processed, but the last bit is only used for grouping and is not directly involved in coding and multiplication). Each group of 4 bits (or quads) is converted according to the Booth coding rule, and then the coded group is multiplied with the multiplicand to generate partial products.

[0051] In this embodiment, for a signed integer multiplier, encoding is performed according to the sign bit information of the multiplier. First, the sign bit (the leftmost bit) of the multiplier is checked. If the multiplier is positive, it is kept as is; if the multiplier is negative, it is converted to a positive number (i.e., a two's complement operation is performed), and the negative sign is restored in the final result.

[0052] The partial products generated according to Booth's encoding rule need to be adjusted and accumulated in a specific way to reflect the actual value and sign of the multiplier. If the original multiplier is negative, the final result should also be negative. Therefore, after accumulating all the partial products, if the multiplier was originally negative, the final result needs to be negated.

[0053] This embodiment performs special processing on the encoding of negative numbers. For example, in the Radix-4 booth algorithm, when the three-digit multiplier is 100, the encoding is -2 (indicating -2 times the multiplicand); when the three-digit multiplier is 101 or 110, the encoding is -1 (indicating -1 times the multiplicand). This encoding method can effectively integrate the sign bit information into the Booth encoding value, so that the subsequent multiplication operation can correctly process the calculation of signed numbers.

[0054] After Booth coding, each new coding group is multiplied with the multiplicand to generate the corresponding partial products. The number of these partial products is much smaller than that generated by traditional multiplication methods because Booth coding reduces the number of combinations that need to be calculated by combining the multiplier bits. This stage effectively reduces the number of partial products through Booth coding technology, providing more efficient and compact input for subsequent multiplication operations.

[0055] The above step S2 is the second stage, which implements PPR (Vedic multiplication), which can effectively reduce the power consumption and cost of the multiplier and improve the overall performance. In the traditional Booth multiplier, PPG and PPR are performed in series, and the PPR operation must be started after the PPG is fully completed, which increases the vertical critical path delay. The method proposed in this embodiment adopts a parallel processing mechanism in the PPR stage, which can process multiple partial products at the same time, thereby further shortening the delay of the multiplication operation. The concept of Vedic multiplication is introduced in this stage, and the UT sutra (cross multiplication) principle of Vedic multiplication is used to quickly compress the partial products, and multiple partial product elements will be calculated at the same time, instead of waiting for the previous partial product to be completely processed before the next one. The UT principle allows vertical and cross multiplication operations to be performed on multiple partial products at the same time, and then these partial product elements are received in parallel, thereby realizing parallel processing in the PPR stage, and there is no need to wait for all partial products to be generated before obtaining the final output, which greatly shortens the vertical critical path delay.

[0056] Step S2 uses the cross-multiplication principle of Vedic multiplication to perform a multiplication operation on the generated code, which specifically includes the following steps.

[0057] S2.1, perform an AND gate operation on each coded bit of the multiplier and the corresponding bit of the multiplicand to implement bit multiplication.

[0058] First, after the encoding in step S1, the multiplier is converted into a series of coding groups, each coding group corresponds to the calculation of a partial product. At this time, the multiplicand remains unchanged. This step implements the initial multiplication operation (bit multiplication). For each bit in the coding group, an AND gate operation is performed with the corresponding bit of the multiplicand to implement bit multiplication.

[0059] S2.2, combine and calculate the partial product elements obtained by bitwise multiplication according to the cross-multiplication principle of Vedic multiplication.

[0060] This step performs vertical and cross multiplication operations, combining and calculating the partial product elements obtained by bitwise multiplication according to the cross multiplication rule of UT sutra.

[0061] Figure 4 The 4-bit wide Vedic multiplication using the cross multiplication principle is demonstrated, where X0, X1, X2, and X3 represent the four bits of the multiplicand, Yn0 and Yn1 represent two encoding groups formed by the 4-bit width, step1 to step6 represent the calculation steps, and vertical and cross multiplication operations are used. It takes 6 calculation steps to complete the multiplication of the multiplier and the multiplicand.

[0062] UT sutra further reduces the delay in the compression stage by converting the compression of partial products into a multiplication problem, achieving high-speed, low-complexity multiplication calculations. The multiplication operation is completed through AND gate operations, and there is no need to wait for all partial products to be generated before obtaining the final output. After performing multiplication using UT sutra, partial products are generated according to the bit width of different operand sizes. By completing the final addition result, it is finally sent to the encoder, where the final addition is performed to obtain a 2N-bit product result.

[0063] At the same time, the Booth-encoded multiplier contains the sign bit information in its encoding value, and then the encoded multiplier and the multiplicand are multiplied according to the Vedic multiplication (UT rule). In the UT rule, bit multiplication is realized by a simple AND gate operation, and then vertical and cross multiplication are performed. Since the Booth encoding has processed the sign bit, the Vedic multiplication can correctly handle the multiplication operations of positive and negative numbers according to these encoding values ​​during the calculation process, realizing the multiplication calculation of signed integers.

[0064] The above step S3 is the third stage, which implements PPA addition, and finally adds the partial products processed by the PPR (Partial Product Reduction) stage to obtain the final result of the multiplication operation.

[0065] Specifically, the results of the combined calculation in step S2 are received in parallel, and all processed partial product elements are finally accumulated to obtain the final bit product result. In this stage, the accurate calculation of the final product is ensured by efficient adder design, such as Wallace tree, Dadda tree or carry-lookahead adder (CLA), etc., to reduce the complexity and delay of addition. After all partial products are added, the final result of the multiplication operation is obtained.

[0066] Figure 5 The overall architecture of BVR-4 in this embodiment is as follows: Figure 6 This is a multiplication example of BVR-4 of this embodiment, which is used to implement the operation of 7*7=49. The operand size is 4x4, the multiplicand values ​​are designated as X0, X1, X2, X3, and the multiplier values ​​are designated as Y-1, Y0, Y1, Y2, Y3. After assigning values ​​to the multiplicand and the multiplier, "0" is added to the LSB of the multiplier bit, and then the multiplier bits are grouped, and the process is performed on the grouping of consecutive bits. The newly encoded groups are formed into Yn0 and Yn1. Then, by following the values ​​in Table 1, multiplication operations are performed to form PP rows of 1 and 2. After the first PP row is generated, the consecutive rows are shifted by 2 bits. Add these rows to form intermediate results P0, P1, P2, P3, P4, P5. The encoded values ​​of these results are shown in Table 2 to obtain the final result. For 8-bit and 16-bit operand sizes, this can be deduced in the same way.

[0067] Table 2: Result encoding values

[0068] By simulating and verifying the multiplier of the operation method of this embodiment with other current multipliers, the speed of this multiplier can be increased by 50%-80%, the area is reduced by 20%-40%, the power is improved by 1%-10%, the critical path delay is reduced, the performance is greatly improved, and it can be used for high-performance computing.

[0069] This embodiment provides a multiplier to execute the calculation method of the above embodiment.

[0070] This embodiment provides a programmable gate array, which is configured with the multiplier of the above embodiment. Exemplarily, the multiplier of the above embodiment is configured on an FPGA.

[0071] This embodiment provides a digital circuit configured with the programmable gate array of the above embodiment.

[0072] The above description of the disclosed embodiments enables one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A multiplier operation method, characterized in that: The following steps are involved: Encoding the multiplier by Booth coding, including encoding the multiplier according to the sign bit information of the multiplier for a signed integer multiplier; The generated codes are multiplied using the cross-multiplication principle of Vedic multiplication; The results of the multiplication operations are added together to obtain the final result of the multiplication operation.

2. The multiplier operation method according to claim 1, characterized in that: The generated code is multiplied using the cross-multiplication principle of Vedic multiplication, including: Each coded bit of the multiplier is ANDed with the corresponding bit of the multiplicand to achieve bit multiplication; The partial product elements obtained by bitwise multiplication are combined and calculated according to the cross-multiplication principle of Vedic multiplication.

3. The multiplier operation method according to claim 1, characterized in that: The multipliers are encoded using Booth code to generate partial products, including: Use the Radix-4 Booth algorithm to combine every three consecutive multiplier bits into a new code group; Or, use the Radix-8 Booth algorithm to combine every four consecutive multiplier bits into a new encoding group.

4. The multiplier operation method according to claim 3, characterized in that: Use the Radix-4 Booth algorithm to combine every three consecutive multiplier bits into a new encoding group, including: receiving as input a multiplier and a multiplicand; Insert a "0" in the least significant bit of the multiplier; By looping through each bit of the multiplier, each consecutive three bits of the multiplier are converted into a corresponding encoding group according to the Booth encoding rule.

5. The multiplier operation method according to claim 4, characterized in that: In the Radix-4 Booth algorithm, when three consecutive multipliers are 100, the code is -2, and when three consecutive multipliers are 101 or 110, the code is -1.

6. The multiplier operation method according to claim 3, characterized in that: Use the Radix-8 Booth algorithm to combine every four consecutive multiplier bits into a new encoding group, including: receiving as input a multiplier and a multiplicand; Insert a "0" in the least significant bit of the multiplier; By looping through each bit of the multiplier, each consecutive four bits of the multiplier are converted into the corresponding encoding group according to the Booth encoding rule.

7. The multiplier operation method according to claim 2, characterized in that: The multiplication operation results are added together to obtain the final result of the multiplication operation, which includes: Receive multiplication operation results in parallel; The multiplication operation results are added together through a Wallace tree, a Dadda tree, or a carry-finding adder to obtain the final result of the multiplication operation.

8. A multiplier, characterized in that: Execute the operation method described in any one of claims 1 to 7.

9. A programmable gate array, characterized in that: A multiplier according to claim 8 is provided.

10. A digital circuit, characterized in that: A programmable gate array as claimed in claim 9 is provided.

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