Low-power-consumption low-noise linear voltage regulator based on delay bypass switch
By introducing a delay bypass switch MOS tube into a linear regulator, the delay signal is used to control its conduction and disconnection, forming an RC low-pass filter, which solves the output noise and establishment time of the linear regulator in the prior art The problem is that a linear regulator design with low power consumption and low noise is realized, meeting the system's demand for fast response and low noise.
Patent Information
- Application Number
- CN202420783364.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-04-16
- Publication Date
- 2024-12-10
- Estimated Expiration
- 2034-04-16
AI Technical Summary
The prior art usually requires increasing power consumption and area when reducing linear regulator output noise, making it difficult to meet the demand for low output noise voltage in systems with limited chip area and power consumption.
Using a low-power, low-noise linear regulator design based on a delayed bypass switch, the RC low-RC is formed by setting the bypass switch MOS tube MN1 at resistor R2 and controlling its conduction and disconnection with a delayed enable signal. Pass the filter to reduce output noise without changing the bandgap reference and increasing power consumption.
The setup time of the linear regulator output voltage is significantly improved without increasing power consumption, improved transient response characteristics, and met the system's demand for low output noise and fast setup time.
Smart Images
Figure CN222145436U_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of low-noise analog chip design, and in particular to a low-power and low-noise linear regulator based on a delayed bypass switch. Background Art
[0002] Analog chips with high requirements for noise performance usually require a low-noise voltage source to power them. The existing technology generally reduces the output noise of the linear regulator by increasing power consumption and area. The disadvantage of this method is that it will increase the area and power consumption of the system. In a system with requirements for chip area and power consumption, the power consumption and area allocated to the power supply system are limited, making it difficult to meet the system's requirements for low output noise voltage of the linear regulator. Utility Model Content
[0003] In order to meet the system's requirement for low output noise voltage of a linear regulator, the present application provides a low-power and low-noise linear regulator based on a delayed bypass switch.
[0004] The present application provides a low-power and low-noise linear regulator based on a delayed bypass switch, which adopts the following technical solution:
[0005] A low-power and low-noise linear regulator based on a delayed bypass switch comprises a bandgap reference source BG, an error amplifier EA, a resistor, a capacitor, a MOS tube and an inverter;
[0006] The output end of the bandgap reference source BG is electrically connected to the inverting input end of the error amplifier EA, and the output end of the error amplifier EA is electrically connected to the upper end of the resistor R2 and the source of the MOS tube MP1; the lower end of the resistor R2 is electrically connected to the drain end of the MOS tube MN1, the lower end of the capacitor C2 and the gate of the power tube MP1, and the resistor R2 and the MOS tube MN1 are connected in parallel; the upper end of the capacitor C2 and the source end of the power tube MP1 are electrically connected to the common power supply VIN; the drain of the power tube MP1 and the upper end of the resistor R4 are electrically connected to the non-inverting input end of the error amplifier EA, and the non-inverting input end of the error amplifier EA is the output end VOUT of the circuit; the lower end of the resistor R4 is electrically connected to the common ground potential;
[0007] The control signal EN is electrically connected to the input end of the inverter INV1, the output end of the inverter INV1 is electrically connected to the upper end of the resistor R5, the lower end of the resistor R5 is electrically connected to the upper end of the capacitor C4 and the input end of the inverter INV2, and the lower end of the capacitor C4 is connected to the common ground; the output end of the inverter INV2 is electrically connected to the input end of the inverter INV3, and the output end of the inverter INV3 is electrically connected to the gate of the MOS tube MN1.
[0008] By adopting the above technical solution, the resistor R2 and the capacitor C2 are RC low-pass filters. In order to make the cut-off frequency low enough to reduce the output noise of the linear regulator, the resistance and capacitance values should be large, and a certain delay is also caused at the node of RC, and the delay time is τ=R2*C2. The core of this solution is to set a bypass switch MOS tube MN1 at the resistor R2, and control MN1 with a delayed enable signal; MN1 is turned off when the circuit is working normally, that is, EN=1, and is turned on when the circuit is closed, that is, EN=0. When the enable signal EN switches from 0 to 1, the entire linear regulator circuit starts to start. The enable signal EN switches from 1 to 0 after passing through the inverter INV1, the resistor R5 and the capacitor C4. However, due to the delay generated at the resistor R5 and the capacitor C4, the gate node of MN1 is still 1 at this moment. At this moment, the NMOS tube MN1 is still turned on, which is equivalent to short-circuiting R2. The gate charge of the power device MP1 is quickly discharged to the ground through MN1-EA. After the time τ=R5*C4, ENB switches from 1 to 0, the NMOS tube MN1 is turned off, and the resistor R2 returns to normal. The low-pass filter composed of the resistor R2 and the capacitor C2 continues to filter at the output end of the error amplifier EA. Without changing the bandgap reference source BG and increasing power consumption, the output noise voltage of the linear regulator is reduced by only changing the internal circuit of the linear regulator. In addition, the output voltage establishment time of the linear regulator is not affected within the entire process angle redundancy, power supply voltage range, and temperature range, thereby meeting the design requirements of the system. The present application is suitable for use in power supply systems where the circuit has a large RC node and has speed requirements to improve the transient establishment time of the circuit, so as to achieve the transient response characteristic requirements of the entire system.
[0009] Optionally, the output end of the bandgap reference source BG is electrically connected to the upper end of the resistor R1 , and the lower end of the resistor R1 is electrically connected to the common ground potential through the capacitor C1 .
[0010] By adopting the above technical solution, the resistor R1 and the capacitor C1 form a low-pass filter to achieve a filtering effect.
[0011] Optionally, the lower end of the resistor R2 is electrically connected to the upper end of the resistor R3, the lower end of the resistor R3 is electrically connected to the upper end of the capacitor C3, the resistor R3 and the capacitor C3 are connected in series, and the lower end of the capacitor C3 is electrically connected to the drain of the power tube MP1.
[0012] By adopting the above technical solution, the resistor R3 and the capacitor C3 form a low-pass filter to achieve a filtering effect.
[0013] Optionally, the resistance of the resistor R2 is greater than the resistance of the resistor R3; the capacitance of the capacitor C2 is greater than the capacitance of the capacitor C3.
[0014] By adopting the above technical solution, in order to make the cut-off frequency low enough to reduce the output noise of the LDO, the resistance and capacitance values should be large. At the same time, this also causes a certain delay at the node of RC, and the delay time is τ=R2*C2.
[0015] Optionally, the power tube MP1 is configured as a P-type MOS tube.
[0016] Optionally, the MOS transistor MN1 is configured as an N-type MOS transistor.
[0017] In summary, the present application includes at least one of the following beneficial technical effects: The present invention proposes a new circuit structure, which can significantly improve the settling time of the output voltage of the linear regulator without increasing power consumption, and its structure is simple and the idea is clear. It can improve the settling time of the output voltage of the linear regulator under the entire process redundancy, power supply voltage, and temperature, and solve the problem of slow power-on of the output node caused by RC low-pass filtering. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] Figure 1 This is a linear regulator circuit structure in the prior art when the NMOS switch is not connected in parallel to the resistor R2.
[0019] Figure 2 for Figure 1 VBG transient simulation results when the enable signal EN switches from 1 to 0.
[0020] Figure 3 The present application discloses a circuit structure of a low-power and low-noise linear regulator based on a delayed bypass switch.
[0021] Figure 4 for Figure 3 VBG transient simulation results of the circuit structure.
[0022] Figure 5 for Figure 2 and Figure 4 In the figure, the transient simulation results of the two circuit structures are compared. DETAILED DESCRIPTION
[0023] The present application is further described in detail below in conjunction with the accompanying drawings. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.
[0024] As attached Figure 1 As shown in the prior art, the circuit diagram of the linear regulator is shown in FIG. Figure 2 It is the transient simulation result of VBG when the enable signal EN switches from 1 to 0.
[0025] The embodiment of the present application discloses a low-power and low-noise linear regulator based on a delayed bypass switch. Figure 1 , including a bandgap reference source BG, an error amplifier EA, resistors R1-R5, capacitors C1-C4, a MOS tube M1, and inverters INV1-INV3.
[0026] As attached Figure 3 and Figure 4 As shown, the output end of the bandgap reference source BG is connected to the upper end of the resistor R1, the lower end of the resistor R1 is connected to the upper end of the capacitor C1 and the reverse end of the error amplifier EA, the lower end of the capacitor C1 is connected to the common ground potential, and R1 and the capacitor C1 form a low-pass filter. The output end of the error amplifier EA is connected to the upper end of the resistor R2 and the source end of the MOS tube MN1; the lower end of the resistor R2 is connected to the drain end of the MOS tube MN1, the lower end of the capacitor C2, the upper end of R3 and the gate of the power tube MP1, the resistor R2 and the NMOS tube MN1 are connected in parallel, the upper end of the capacitor C2 and the source end of the power tube MP1 are connected to the common power supply VIN, the resistors R2 and C2 form another set of low-pass filters, the lower end of the resistor R3 is connected to the upper end of the capacitor C3, and the resistor R3 and the capacitor C3 are connected in series. The lower end of the capacitor C3, the power tube M1 and the resistor R4 are connected to the non-inverting input end of the error amplifier, which is also the output end VOUT of the circuit. The lower end of the resistor R4 is connected to the common ground potential.
[0027] The control signal EN is connected to the input end of the inverter INV1. The control signal EN also controls the bandgap reference circuit BG and the error amplifier EA. The output end of the inverter INV1 is connected to the upper end of the resistor R5. The lower end of the resistor R5 is connected to the upper end of the capacitor C4 and the input end of the inverter INV2. The lower end of the capacitor C4 is connected to the common ground. The output end of the inverter INV2 is connected to the input end of the inverter INV3. The output end of the inverter INV3 is connected to the gate of the NMOS tube MN1.
[0028] As attached Figure 5 As shown in FIG. 1 , a comparison diagram of transient simulation results of the circuit in the prior art and the circuit of this embodiment shows that connecting an NMOS switch in parallel with the resistor R2 can significantly improve the output voltage settling time.
[0029] The implementation principle of a low-power, low-noise linear regulator based on a delayed bypass switch in an embodiment of the present application is: resistor R2 and capacitor C2 are RC low-pass filters. In order to make the cut-off frequency low enough to reduce the output noise of the linear regulator, the resistance and capacitance values should be large, and a certain delay is also caused at the node of RC, and the delay time is τ=R2*C2. In this embodiment, the resistance value of resistor R2 is greater than the resistance value of resistor R3; the capacitance value of capacitor C2 is greater than the capacitance value of capacitor C3. The core of this solution is to set a bypass switch MOS tube MN1 at the resistor R2, and control the NMOS tube MN1 with a delayed enable signal; the NMOS tube MN1 is turned off when the circuit is working normally, that is, when EN=1, and is turned on when the circuit is closed, that is, when EN=0. When the enable signal EN switches from 0 to 1, the entire linear regulator circuit starts to start. The enable signal EN switches from 1 to 0 after passing through the inverter INV1, the resistor R5 and the capacitor C4. However, due to the delay generated at the resistor R5 and the capacitor C4, the gate node of the NMOS tube MN1 is still 1 at this moment. At this moment, the NMOS tube MN1 is still turned on, which is equivalent to short-circuiting the resistor R2. The gate charge of the power device MP1 is quickly discharged to the ground through MN1-EA. After the time τ=R5*C4, ENB switches from 1 to 0, the NMOS tube MN1 is turned off, and the resistor R2 returns to normal. The low-pass filter composed of the resistor R2 and the capacitor C2 continues to filter at the output end of the error amplifier EA. Without changing the bandgap reference source BG and increasing power consumption, the output noise voltage of the linear regulator is reduced by only changing the internal circuit of the linear regulator. In addition, the output voltage establishment time of the linear regulator is not affected within the entire process angle redundancy, power supply voltage range, and temperature range, thereby meeting the design requirements of the system. The present application is suitable for use in power supply systems where the circuit has a large RC node and has speed requirements to improve the transient establishment time of the circuit, so as to achieve the transient response characteristic requirements of the entire system.
[0030] The above are all preferred embodiments of the present application, and the protection scope of the present application is not limited thereto. Therefore, any equivalent changes made according to the structure, shape, and principle of the present application should be included in the protection scope of the present application.
Claims
1. A low power consumption and low noise linear regulator based on a delayed bypass switch, characterized in that: It includes a bandgap reference source BG, an error amplifier EA, a resistor, a capacitor, a MOS tube and an inverter; The output end of the bandgap reference source BG is electrically connected to the inverting input end of the error amplifier EA, and the output end of the error amplifier EA is electrically connected to the upper end of the resistor R2 and the source of the MOS tube MP1; the lower end of the resistor R2 is electrically connected to the drain end of the MOS tube MN1, the lower end of the capacitor C2 and the gate of the power tube MP1, and the resistor R2 and the MOS tube MN1 are connected in parallel; the upper end of the capacitor C2 and the source end of the power tube MP1 are electrically connected to the common power supply VIN; the drain of the power tube MP1 and the upper end of the resistor R4 are electrically connected to the non-inverting input end of the error amplifier EA, and the non-inverting input end of the error amplifier EA is the output end VOUT of the circuit; the lower end of the resistor R4 is electrically connected to the common ground; The control signal EN is electrically connected to the input end of the inverter INV1, the output end of the inverter INV1 is electrically connected to the upper end of the resistor R5, the lower end of the resistor R5 is electrically connected to the upper end of the capacitor C4 and the input end of the inverter INV2, and the lower end of the capacitor C4 is connected to the common ground; the output end of the inverter INV2 is electrically connected to the input end of the inverter INV3, and the output end of the inverter INV3 is electrically connected to the gate of the MOS tube MN1.
2. The low-power and low-noise linear regulator based on a delayed bypass switch according to claim 1, characterized in that: The output terminal of the bandgap reference source BG is electrically connected to the upper end of the resistor R1, and the lower end of the resistor R1 is electrically connected to the common ground through the capacitor C1.
3. The low power consumption and low noise linear regulator based on the delayed bypass switch according to claim 1, characterized in that: The lower end of the resistor R2 is electrically connected to the upper end of the resistor R3, the lower end of the resistor R3 is electrically connected to the upper end of the capacitor C3, the resistor R3 and the capacitor C3 are connected in series, and the lower end of the capacitor C3 is electrically connected to the drain of the power tube MP1.
4. The low-power and low-noise linear regulator based on a delayed bypass switch according to claim 1, characterized in that: The resistance value of the resistor R2 is greater than the resistance value of the resistor R3; the capacitance value of the capacitor C2 is greater than the capacitance value of the capacitor C3.
5. The low power consumption and low noise linear regulator based on delayed bypass switch according to claim 1, characterized in that: The power tube MP1 is configured as a P-type MOS tube.
6. The low-power and low-noise linear regulator based on a delayed bypass switch according to claim 1, characterized in that: The MOS tube MN1 is configured as an N-type MOS tube.