Quantum bit test circuit, layout structure, quantum chip and quantum computer

Abstract

The utility model discloses a quantum bit test circuit, a layout structure, a quantum chip and a quantum computer, and the quantum bit test circuit comprises a quantum bit, a resonant cavity and a reading signal line which are sequentially coupled on a signal transmission line. The quantum bit comprises a first input end which inputs a test signal at least covering a quantum bit frequency and a resonant cavity frequency through coupling, and the quantum bit frequency and the resonant cavity frequency are different in numerical value. The quantum bit test circuit has the advantages that the test circuit only needs to be connected with one input port, so that the quality of the quantum bit can be quickly judged, and the related information of the resonant cavity frequency and the quantum bit frequency can be obtained.

Description

Technical Field

[0001] The utility model belongs to the technical field of quantum computers, and in particular relates to quantum bit test circuits, layout structures, quantum chips and quantum computers. Background Art

[0002] In a quantum computer, the quantum chip is an important component in the quantum computing system, and in the quantum chip, the quantum bit is one of the important factors to measure the performance of the quantum computer.

[0003] With the pursuit of quantum computing performance, there is a demand to integrate more superconducting quantum bits in quantum chips. As the number of quantum bits in quantum chips increases, the number of signal transmission lines and various circuit elements in quantum chips will also increase.

[0004] Since the preparation and testing of quantum bits may lead to quantum bit failure, each quantum chip needs to be tested and characterized for its parameters before it is officially put into use, including whether the quantum bit is qualified and the quantum bit frequency. As the number of quantum bits increases, it takes longer to measure the parameters of each quantum chip. Utility Model Content

[0005] In order to improve the efficiency of detecting chip-related parameters, the utility model provides a quantum bit test circuit, a layout structure, a quantum chip and a quantum computer.

[0006] In order to achieve the above purpose, the utility model provides the following technical solutions:

[0007] On the one hand, the utility model provides a quantum bit test circuit, including a quantum bit, a resonant cavity and a reading signal line coupled in sequence on a signal transmission line, the quantum bit including a first input end for inputting a test signal that at least covers the quantum bit frequency and the resonant cavity frequency through coupling, and the quantum bit frequency and the resonant cavity frequency have different numerical values.

[0008] In the quantum bit test circuit as described above, further, the absolute value of the difference between the quantum bit frequency and the resonant cavity frequency is greater than a set value.

[0009] The quantum bit test circuit as described above further includes a vector network analyzer, wherein the output end of the vector network analyzer for generating a test signal is connected to the first input end, and the input end for obtaining a test result is connected to a port for reading a signal line.

[0010] The quantum bit test circuit as described above further comprises a plurality of quantum bits and resonant cavities, each quantum bit is coupled to a corresponding resonant cavity, and all the resonant cavities are coupled to the read signal line.

[0011] In the quantum bit test circuit as described above, further, all components for realizing the coupling are coupling capacitors or coupling inductors.

[0012] The quantum bit test circuit as described above, further, the quantum bit also includes a second input end, and the second input end is used to adjust the quantum bit frequency.

[0013] In the quantum bit test circuit as described above, further, the second input terminal is suspended or grounded, so that the quantum bit frequency is a constant value.

[0014] On the other hand, the utility model provides a layout structure, including: the quantum bit test circuit as described above.

[0015] On the other hand, the utility model provides a quantum chip, comprising: the quantum bit test circuit as described above, wherein the quantum bit test circuit is made using the above-mentioned layout structure.

[0016] On another aspect, the utility model provides a quantum computer, comprising the above-mentioned quantum chip.

[0017] The beneficial effects of the utility model are:

[0018] The quantum bit in the quantum bit test circuit of the utility model includes a first input end that couples and inputs a test signal that at least covers the quantum bit frequency and the resonant cavity frequency. The test signal can drive the quantum bit to work, and also resonate the resonant cavity with the read signal line to transmit the quantum bit signal to the read signal line, and finally realize the signal reading. The test circuit only needs to connect one input port to quickly judge the quality of the quantum bit and obtain relevant information about the resonant cavity frequency and the quantum bit frequency.

[0019] A layout structure, a quantum chip and a quantum computer provided by the utility model have the same beneficial effects, which will not be described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 A schematic diagram of the structure of a quantum bit test circuit provided by an embodiment of the utility model;

[0021] Figure 2 This is the transmission curve diagram of the output signal of the quantum bit test circuit.

[0022] In the reference numerals:

[0023] 1. Quantum bit; 11. Josephson junction; 12. Cross capacitor; 2. Resonant cavity; 3. Read signal line; 41. First coupling capacitor; 42. Second coupling capacitor; 43. Third coupling capacitor; 44. Fourth coupling capacitor; 5. First input terminal; 6. Test signal input terminal; 7. Second input terminal. DETAILED DESCRIPTION

[0024] In order to enable those skilled in the art to better understand the technical solutions in the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of this application. The embodiments described below with reference to the drawings are exemplary and are only used to explain the present application, and cannot be interpreted as limitations on the present application.

[0025] In the description of the present invention, it should be understood that the terms "center", "up", "down", "left", "right", etc. indicate directions or positional relationships based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore should not be understood as a limitation on the present invention.

[0026] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present utility model, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0027] As one of the important components in quantum computers, the quantum chip needs to be tested for various parameters before it can be used as a finished product. In order to maintain the superconducting properties of the superconducting materials in the superconducting quantum chip, the quantum chip needs to be placed in a low temperature environment close to absolute zero during testing and use, so that the quantum circuits in the quantum chip are in a completely superconducting state and induce the Josephson effect, thereby achieving quantum entanglement and achieving the purpose of quantum computing.

[0028] In order to make the quantum circuit in a completely superconducting state, the low-temperature environment close to absolute zero is currently provided by a dilution refrigerator. In order to make the mixing chamber where the quantum chip is placed close to zero, it currently takes nearly 40 hours for the dilution refrigerator to be turned on and close to zero. In addition, when the quantum chip needs to be taken out after detection, it takes nearly 24 hours for the dilution refrigerator to be opened and the internal equipment can be taken out from the extremely low temperature. Before turning on the dilution refrigerator, in order to induce the Josephson effect, the quantum bits need to be manipulated. Therefore, different components of the measurement and control system used to manipulate the quantum bits are installed in different temperature zones of the dilution refrigerator, and this process will also take a lot of time. In detail, since each quantum bit requires a corresponding measurement and control part, for example, the measurement and control part needs to input the XY control signal corresponding to the quantum bit of each quantum chip to the XY control port for driving the corresponding quantum bit to work and energy level transition, and input the Z control signal for adjusting the quantum bit frequency to the corresponding Z control port. It can be seen that the connection and installation of the quantum chip and the measurement and control system in the dilution refrigerator require a huge workload. The larger the number of quantum bits, the more time it takes to install and test. If the quantum chip has a very high yield rate, it is a better choice to place it directly in a dilution refrigerator for testing. However, since the size of the Josephson junction in the quantum chip is 200-300nm, the success rate of the Josephson junction preparation has extremely high technical requirements, and the current preparation conditions cannot fully guarantee that the quantum bit qualification rate reaches a certain value. After the unqualified quantum bits and the corresponding measurement and control parts are installed in the dilution refrigerator and the dilution refrigerator is turned on, the test is turned on until the temperature zone of the dilution refrigerator located in the chip part is close to zero degrees. Then, due to unsatisfactory test results, it takes a lot of time to wait until the dilution refrigerator can be opened and the quantum chip can be removed and replaced. Due to the small internal space of the dilution refrigerator, when there are more quantum bits, the workload of each installation and removal is also very large, and it is easy to cause damage to the equipment or parts in the process.

[0029] In order to save the measurement time of quantum chips, the performance test of quantum chips mainly includes two categories: preliminary test and formal test. The preliminary test is set at room temperature and is mainly used to test whether the signal of the quantum bit can be obtained. When the quantum bit signal can be obtained, the components that characterize the quantum bit and the signal transmission line including the quantum bit are in good condition, and the relevant information of the resonant cavity frequency and the quantum bit frequency can also be obtained. Compared with the formal test, the preliminary test does not need to consider the test accuracy, but it can first exclude some unqualified quantum bits, which greatly reduces the workload of the formal test.

[0030] In order to achieve the most basic preliminary screening before the quantum chip is actually used for bit gates, the test circuit of the quantum chip is currently moved directly to the room temperature environment. The working principle based on the existing test circuit is as follows: by inputting a read signal to one end of the read signal line, inputting an XY control signal to the XY control end, and inputting a Z control signal to the Z control end, the read signal resonates with the corresponding resonant cavity frequency and enters the quantum bit corresponding to the resonant cavity, the XY control signal drives the quantum bit to work, and the signal carrying the quantum bit information returns to the read signal line through the resonant cavity, and is collected and acquired through the other end of the read signal line. Simply put, the resonant cavity signal is characterized by the read signal line. After determining the resonant cavity, the coupling between the resonant cavity and the quantum bit is used to disperse the state of the quantum bit and indirectly obtain the quantum bit frequency. For these basic information of quantum bits, the data of the read signal line needs to be processed to obtain them. In addition, it cannot be obtained immediately, and the performance of the resonant cavity must be characterized first. In addition, testing each quantum chip requires connecting the XY control terminal, the Z control terminal, and the reading signal line terminal to realize the test. When there are more quantum bits in the quantum chip, the measurement time of the quantum chip is still relatively long. Moreover, due to the large number of external connections, it is easy to extend the connection time of the test line and increase the probability of connection errors, which not only affects the measurement results, but may also cause damage to the chip.

[0031] In order to solve the above problems, Figure 1 As shown: An embodiment of the present application discloses a quantum bit test circuit, including a quantum bit 1, a resonant cavity 2 and a reading signal line 3 coupled in sequence on a signal transmission line, the quantum bit 1 including a first input terminal 5 for coupling input of a test signal that at least covers the quantum bit frequency and the resonant cavity frequency, and the quantum bit frequency and the resonant cavity frequency have different numerical values.

[0032] In the present application, the test signal of the quantum bit test circuit only needs to be input through the first input terminal 5. Compared with the prior art that requires connecting the port for inputting the read signal and the port for the XY control signal, the present application multiplexes the XY control terminal to input the test signal that at least covers the quantum bit frequency and the resonant cavity frequency, thereby reducing the connection time of the circuit, and there is no need to simultaneously adjust the waveform of the read signal and the waveform of the XY control signal, which also reduces the debugging time during detection. Therefore, the present quantum bit test circuit can improve the efficiency of detecting chip-related parameters.

[0033] The present application couples the input of a test signal that at least covers the quantum bit frequency and the resonant cavity frequency through the first input terminal 5, wherein the test signal is a waveform signal within a set frequency range, and each frequency in the set frequency range corresponds to a sine wave signal, and the quantum bit frequency and the resonant cavity frequency are within the set frequency range. When the frequency of the test signal is equal to the quantum bit frequency, the waveform of the output signal on the read signal line 3 reaches a peak value; when the test signal is equal to the resonant cavity frequency, the waveform of the output signal on the read signal line 3 reaches another peak value. When two obvious peaks appear in the output response waveform of the quantum bit 1, it means that the corresponding quantum bit 1 is in good condition, and the corresponding quantum bit frequency and resonant cavity frequency can be quickly obtained through the output response waveform.

[0034] Furthermore, the absolute value of the difference between the qubit frequency and the resonant cavity frequency is greater than a set value. The present application sets the absolute value of the difference between the qubit frequency and the resonant cavity frequency to be greater than a set value, thereby ensuring the distance between two obvious peaks in the output response waveform and avoiding mutual interference, so as to more accurately obtain information on the qubit frequency and the resonant cavity frequency. The set value described in the present application is 500M, the qubit frequency of the present application ranges from 4 to 5 GHz, and the resonant cavity frequency ranges from 7 to 7.4 GHz.

[0035] In order to achieve that the absolute value of the difference between the qubit frequency and the resonant cavity frequency is greater than the set value, and to be able to distinguish the peak corresponding to the qubit 1 and the peak corresponding to the resonant cavity 2 in the waveform of the output signal, the internal structure of the qubit 1 and the resonant cavity 2 is set in a manner that can achieve that the qubit frequency and the resonant cavity frequency are within the corresponding area. In more detail, the qubit 1 includes a Josephson junction 11 and a ground capacitor, wherein the Josephson junction 11 is one or more, and the multiple Josephson junctions 11 can be arranged in series or in parallel, and the other end of the Josephson junction 11 is connected to the ground, wherein the Josephson junction 11 is equivalent to a first inductor, and the ground capacitor is equivalent to a first capacitor. The target frequency of the qubit 1 can be obtained according to the first inductor and the first capacitor. Optionally, the ground capacitor is a cross structure, and the ground capacitor is a cross capacitor 12 formed by the cross structure and the ground. The resonant cavity 2 can be a half-wavelength coaxial resonant cavity 2 or a quarter-wavelength coaxial resonant cavity 2. Taking the quarter-wavelength coaxial resonant cavity 2 as an example, the quarter-wavelength coaxial resonant cavity 2 is composed of a coaxial line with one end short-circuited and one end open-circuited, wherein the coaxial line is equivalent to the second inductor, and the coaxial line and the peripheral ground are equivalent to the second capacitor. The target frequency of the resonant cavity 2 can be obtained according to the second inductor and the second capacitor. The present application first determines the target frequency of the quantum bit 1 and the resonant cavity 2, and reversely designs the Josephson junction 11 and the capacitance to ground of the quantum bit 1, the cavity structure of the resonant cavity 2, and the capacitance to ground and the ground condition of the resonant cavity structure, thereby providing a theoretical basis for the test signal to cover the quantum bit frequency and the resonant cavity frequency.

[0036] In one of the embodiments, the test circuit also includes a vector network analyzer, the output end of the vector network analyzer (not shown in the figure) generating a test signal is connected to the first input end 5, and the input end for obtaining the test result is connected to the port of the read signal line 3. The present application outputs a signal for testing the quantum bit frequency and the resonant cavity frequency through a vector network analyzer, and receives and analyzes the output signal of the test circuit, which not only reduces the use of equipment on the entire test circuit, but also avoids the inconsistency between the equipment providing the test signal and the equipment receiving the output signal of the test circuit, resulting in systematic errors in the measurement results. In addition, the number of input signals that need to be adjusted during the test is reduced. The present application only needs to adjust one signal at the first input end 5, and does not need to adjust multiple input signals at the same time, which also reduces the workload of the test, thereby improving the test efficiency.

[0037] In one embodiment, the test circuit includes a plurality of quantum bits 1 and a resonant cavity 2, each quantum bit 1 is coupled to a corresponding resonant cavity 2, and all the resonant cavities 2 are coupled to the read signal line 3. In the present application, the multiple quantum bits 1 and the resonant cavity 2, the quantum bit test circuit saves the test time to a greater extent compared with the test circuit in the prior art. The output end of the vector network analyzer generating the test signal is sequentially connected to the first input end 5 of the corresponding quantum bit 1. Compared with one quantum bit 1 corresponding to multiple connection ports, the present application reduces the workload of the test to the greatest extent, thereby improving the test efficiency.

[0038] In one embodiment, all the components for realizing the coupling are coupling capacitors or coupling inductors, and the setting of the coupling capacitors or coupling inductors realizes AC signal transmission on the basis of isolating DC signals and eliminating DC noise signals. Taking the coupling components as an example, the coupling capacitors include a first coupling capacitor 41 connected to the first input terminal 5, a second coupling capacitor 42 connecting the quantum bit 1 and the resonant cavity 2, and a third coupling capacitor 43 connecting the resonant cavity 2 and the read signal line 3, wherein the other end of the first coupling capacitor 41 serves as a test signal input terminal 6. In the present application, the test signal input terminal 6 replaces the function of the XY control terminal and the read signal line 3 in the prior art to input the read signal. In addition, the coupling capacitor also includes a fourth coupling capacitor 44, which is used to couple the test circuits of adjacent quantum bits. In other embodiments, the fourth coupling capacitor 44 can be replaced by an adjustable coupler quantum bit.

[0039] In one embodiment, the qubit 1 further includes a second input terminal 7, and the second input terminal 7 is used to adjust the qubit frequency. When the qubit frequency needs to be changed, the second input terminal 7 inputs an AC signal to generate an alternating magnetic field to act on the qubit 1, thereby changing the qubit frequency.

[0040] In another embodiment, the second input terminal 7 is suspended or grounded, so that the qubit frequency is a constant value. The second input terminal 7 is suspended or grounded, so that no AC signal is generated in the second input terminal 7, and no alternating magnetic field is generated to act on the qubit 1, so that the tested quantum frequency is the frequency corresponding to the structure of the qubit 1 itself.

[0041] Based on the above-mentioned embodiment of the quantum bit test circuit, the working principle is as follows: the quantum bit test circuit obtains a test signal from the first input terminal 5, the test signal passes through the quantum bit 1 and the resonant cavity 2, and finally obtains an output signal carrying the information of the quantum bit 1 and the resonant cavity from the read signal line 3. In one case, the output curve of the output signal is as follows Figure 2As shown, the two peaks represent the quantum bit information and the resonant cavity information respectively. When the target frequency of quantum bit 1 is less than the target frequency of resonant cavity 2, the left peak represents the quantum bit information, and the right peak represents the resonant cavity information. When the target frequency of quantum bit 1 is greater than the target frequency of resonant cavity 2, the left peak represents the resonant cavity information, and the right peak represents the quantum bit information. Due to technical limitations and production errors, there is a difference between the target frequency of quantum bit 1 and resonant cavity 2 and the measured frequency of the corresponding quantum bit 1 and resonant cavity 2. When the absolute value of the difference is within the set range, it is preliminarily judged that quantum bit 1 and resonant cavity 2 are in good condition. Based on the target frequency of quantum bit 1 and resonant cavity 2, the quantum bit frequency and resonant cavity frequency obtained by the waveform test corresponding to the output signal. Based on this scheme, the information is collected by using a vector network analyzer. Through one measurement, the quality of quantum bit 1 can also be quickly and preliminarily judged, and the quantum bit frequency and the reading cavity frequency information can be quickly and intuitively obtained at the same time.

[0042] On the other hand, the utility model provides a layout structure, including: the quantum bit test circuit as described above.

[0043] On the other hand, the utility model provides a quantum chip, comprising: the quantum bit test circuit as described above, wherein the quantum bit test circuit is made using the above-mentioned layout structure.

[0044] On another aspect, the utility model provides a quantum computer, comprising the above-mentioned quantum chip.

[0045] Regarding the technical effects of the layout structure, quantum chip and quantum computer described in the above embodiments, reference can be made to other embodiments of this specification for comparative explanation and no further details will be given here.

[0046] In the description of this specification, the description with reference to the terms "some embodiments" or "examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiments or examples are included in at least one embodiment or example of the utility model. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification.

[0047] The above are only preferred embodiments of the present invention and do not limit the present invention in any way. Any technician in the relevant technical field, without departing from the scope of the technical solution of the present invention, may make any equivalent replacement or modification to the technical solution and technical content disclosed in the present invention, which shall be deemed as the content of the technical solution of the present invention and still fall within the protection scope of the present invention.

Claims

1. A quantum bit test circuit, characterized in that: The invention comprises a quantum bit, a resonant cavity and a reading signal line which are sequentially coupled on a signal transmission line, wherein the quantum bit comprises a first input end for inputting a test signal which at least covers the quantum bit frequency and the resonant cavity frequency through coupling, and the quantum bit frequency and the resonant cavity frequency have different numerical values.

2. The quantum bit test circuit according to claim 1, characterized in that: The absolute value of the difference between the quantum bit frequency and the resonant cavity frequency is greater than a set value.

3. The quantum bit test circuit according to claim 1, characterized in that: It also includes a vector network analyzer, wherein an output end of the vector network analyzer for generating a test signal is connected to the first input end, and an input end for obtaining a test result is connected to a port for reading a signal line.

4. The quantum bit test circuit according to claim 1, characterized in that: It includes multiple quantum bits and resonant cavities, each quantum bit is coupled to a corresponding resonant cavity, and all the resonant cavities are coupled to the read signal line.

5. The quantum bit test circuit according to claim 4, characterized in that: All components for achieving the coupling are coupling capacitors or coupling inductors.

6. The quantum bit test circuit according to claim 1, characterized in that: The qubit also includes a second input end, which is used to adjust the qubit frequency.

7. The quantum bit test circuit according to claim 6, characterized in that: The second input terminal is suspended or grounded, so that the quantum bit frequency is a constant value.

8. A layout structure, characterized in that: include: A quantum bit test circuit as described in any one of claims 1 to 7.

9. A quantum chip, characterized in that: include: A quantum bit test circuit as described in any one of claims 1 to 7, wherein the quantum bit test circuit is made using a layout structure as described in claim 8.

10. A quantum computer, characterized in that: Comprising a quantum chip as described in claim 9.

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