Radio frequency switch mode control circuit

Abstract

The utility model discloses a radio frequency switch mode control circuit, and relates to the field of radio frequency switch circuits, a Vdd terminal is respectively connected to a signal regulator and a level shifter, and modulation voltage is introduced; the signal regulator rectifies the input modulation voltage and outputs a shaping voltage; the level converter is connected with the rectified output of the signal regulator and outputs a clock signal after demodulation; the MIPIcore decodes and outputs a mipi control signal based on the rectified output, a clock signal and a CTRL terminal input signal; the clock counter is used for counting and outputting a chip selection signal based on a clock signal, and the output chip selection signal is connected with a chip selection end of the data selector; and two input ends of the data selector respectively receive a mipi control signal and a signal input by the CTRL terminal, and output a radio frequency switch control signal according to a chip selection signal. The scheme is compatible with the existing universal 2T switch chip, and the function of freely switching the MIPI control mode and the GPIO control mode is achieved.

Description

Technical Field

[0001] The present application relates to the field of radio frequency circuits, and in particular to a radio frequency switch mode control circuit. Background Art

[0002] With the continuous development of technology, the demand for RF front-end equipment (such as power amplifiers, active antenna tuners, low noise amplifiers and antenna switches) is increasing. For equipment manufacturers, controlling all RF front-end equipment will be a huge challenge.

[0003] The control routing of the RF front-end switch chip is generally controlled by MIPI bus; at the same time, GPIO control routing also exists on some RF front-end terminal chips. The MIPI control method requires a power line VIO and two signal control lines SCLK and SDATA, and the GPIO control method requires a power line VDD and several VCTRL signal control lines.

[0004] Generally, RF switch chips are at least single-pole double-throw, that is, one transmit and one receive, and the mainstream packaging form generally uses a small package QFN with only 6 pins and adopts GPIO control. The distribution of the 6 pins is as follows Figure 1 As shown in the figure, the high and low level output of the CTRL control signal can only output the control of RF1on / RF2off and RF1off / RF2on. For the application of low power consumption requirements, the chip does not have a power down state. For some system applications, the control state of RF1 / RF2 being off at the same time (high isolation) or RF1 / RF2 being on at the same time is also missing, that is, the lack of control state causes limitations on system applications. Utility Model Content

[0005] The present application provides a radio frequency switch mode control circuit and control method to solve the problem that the control state of multiple radio frequency switch circuits is not high and the system application is limited. The Vdd terminal and CTRL terminal of the QFN under the GIPO control mode are reused; the radio frequency switch mode control circuit includes a signal conditioner, a level converter, a MIPI decoding core for the MIPI protocol slave end, a clock counter and a data selector;

[0006] Introducing a modulation voltage through a Vdd terminal, and connecting the Vdd terminal to a signal regulator and a level converter respectively; the signal regulator rectifies the input modulation voltage and outputs a shaped voltage;

[0007] The level converter is connected to the rectified output of the signal conditioner and outputs a demodulated clock signal based on the input modulation voltage and the shaped voltage;

[0008] The MIPI decoding core is connected to the rectifier output of the signal regulator, receives the clock signal output by the level converter, and receives the signal input by the CTRL terminal, and decodes and outputs the mipi control signal based on the MIPI protocol;

[0009] The clock counter receives the clock signal output by the level converter, counts and outputs a chip select signal according to the clock signal, and the output chip select signal is connected to the chip select terminal of the data selector;

[0010] The two input ends of the data selector receive the mipi control signal and the signal input by the CTRL terminal respectively, and output the RF switch control signal according to the chip selection signal.

[0011] Specifically, when the RF circuit is switched to the GIPO control mode, the modulation voltage directly input to the Vdd terminal is a DC Vdd voltage signal, and a filter capacitor Cin is connected to the Vdd port, the positive electrode of the filter capacitor Cin is directly connected to the Vdd terminal, and the negative electrode is grounded;

[0012] The CTRL terminal inputs the CTRL control signal for switching the RF path.

[0013] Specifically, when the RF circuit is switched to the MIPI control mode, the VIO voltage is input to the positive electrode of the diode D1, and the negative electrode output is connected to the Vdd terminal;

[0014] The positive electrode of the filter capacitor Cin is directly connected to the Vdd terminal, and the negative electrode is connected to the SCLK clock signal;

[0015] The input of the Vdd terminal is the modulation voltage after the SCLK clock signal carrier is modulated;

[0016] The CTRL terminal is connected to the SDATA data signal.

[0017] Specifically, when the RF circuit is switched to the MIPI control mode, the shaped voltage Vint output by the signal conditioner is a DC voltage, and Vint is greater than the VIO voltage;

[0018] The level converter demodulates a valid SCLK clock signal based on the rising edge and falling edge of the shaped voltage Vint, and sends the signal to the MIPI decoding core and the clock counter.

[0019] Specifically, when the radio frequency circuit is switched to the GIPO control mode, the level converter outputs an invalid clock signal.

[0020] Specifically, the clock counter counts the clock based on the rising edge or falling edge of the demodulated clock signal, and outputs a chip select signal according to the clock count value and a set target value;

[0021] When the clock count value is not higher than the target value, the output chip select signal is low, indicating that the current control mode is GPIO; when the clock count value is higher than the target value, the output chip select signal is high, indicating that the current control mode is MIPI.

[0022] Specifically, the MIPI decoding core is also provided with an enable EN terminal. When the control mode is the GPIO control mode, the EN terminal outputs a high level by default; when the control mode is the MIPI control mode and EN outputs a high level, the internal circuit power supply is turned on; when the control mode is the MIPI control mode and EN outputs a low level, the internal circuit power supply is turned off.

[0023] Specifically, when the output chip select signal is at a high level, the data selector selects the mipi control signal output; when the output chip select signal is at a low level, the data selector selects the CTRL signal output input by the CTRL terminal.

[0024] The beneficial effects brought by the technical solution provided by the embodiment of the present application include at least: on the basis of the pin pin of the GPIO control mode adopted in the original QFN packaging mode, the present application keeps the RF1 terminal, RF2 terminal, GND terminal and ANT terminal unchanged, and selects to reuse the CTRL terminal and Vdd terminal. On the basis of compatibility with GPIO, a diode and a filter capacitor are used to modulate the SCLK signal carrier into the VIO voltage to achieve the function of sharing a Vdd terminal, and the circuit introduces a signal regulator and a level converter to filter and modulate the modulation voltage, demodulate the SCLK signal and send it to the MIPIcore for decoding. For the state judgment of the circuit itself, the number of SCLK clocks specified by the command frame in the mipi protocol is used to judge, and the control signal is output in combination with the selector chip selection. This scheme introduces the MIPI control method on the basis of the original GPIO, is compatible with the GPIO control method of the existing general 2T switch chip, and the control method expands the application limitations of the GPIO control method, has a strong engineering significance, and the product is universal and competitive. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 A schematic diagram showing the pinout of the GPIO control method in the QFN package;

[0026] Figure 2 This is a connection diagram of the GPIO control pin lead-out port;

[0027] Figure 3 It is a schematic diagram of the SP2T packaging structure in the related art;

[0028] Figure 4 The schematic diagram of the pin lead-out terminal in the composite control mode is shown;

[0029] Figure 5 This is a connection diagram of the MIPI control pin lead-out port;

[0030] Figure 6 It is the RF switch mode control circuit under MIPI control mode;

[0031] Figure 7 It is the RF switch mode control circuit in GPIO control mode;

[0032] Figure 8 Lists the timing diagram of SCLK and SDATA signals under MIPI control. DETAILED DESCRIPTION

[0033] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0034] The term "multiple" as used herein refers to two or more than two. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the related objects are in an "or" relationship.

[0035] Figure 1 The schematic diagram shows the pin lead-out of the GPIO control method under the QFN package. Figure 2 This is a connection diagram of the pin lead-out port in GPIO control mode. In GPIO control mode, pin1 is used to lead out the RF2 end, pin2 is used to lead out the GND end, pin3 is used to lead out the RF1 end, pin4 is used to lead out the Vdd end, pin5 is used to lead out the RFin end, that is, to connect to the RF antenna ANT, and pin6 is used to lead out the CTRL end. At this time, the switch circuit can control the RF path from RF1 to ANT and the RF path from RF2 to ANT. Vdd and GND are responsible for power supply and grounding respectively, and the CTRL end is responsible for inputting control signals to control the specific RF path.

[0036] At present, there are mainstream RF switch SP2T packages such as Figure 3As shown in the figure, the device itself contains only 6 pins, but it needs to use two additional Vdd power supplies. In this mode, it only contains one RF path, and pin3 needs to be multiplexed as SCLK and one VDD power supply, and pin2 is multiplexed as VIO power supply and another VDD power supply, and pin4 is multiplexed as SDATA and CTRL. When adding two RF signals, the 6 pins are not enough to meet the actual application, and they cannot be compatible with single power supply VIO and dual power supply input at the same time, and cannot be switched.

[0037] Because the above-mentioned mode is single, in order to solve the limitations of the GPIO control mode, a composite controlled 2T RF switch is now provided, which is compatible with both GPIO and MIPI control modes. The pin4 pin in the GPIO control mode is connected to the Vdd signal, and the pin6 pin is connected to the CTRL signal. In addition to using the RFin, RF1, RF2 and GND pin terminals in the MIPI control mode, VIO signals, SDATA signals and SCLK signals are also required, that is, at least 6 pins are required for input. In order to solve this problem, the present application connects the pin4 pin in the MIPI control mode to the input VIO and SCLK signals at the same time, and the pin6 pin is connected to the input SDATA signal. This MIPI control connection method combines the VIO and SCLK signals and multiplexes them into the pin4 pin, that is, the clock signal carrier represented by SCLK is modulated to the VIO power supply. While the external input is powered normally, the internal circuit modulates and extracts the SCLK valid signal. After being input to the internal circuit, it is demodulated. This connection method does not add additional terminals and is perfectly compatible with the number of pins in the GPIO control mode.

[0038] Figure 4 The figure shows the schematic diagram of the pin lead-out terminal in the composite control mode. Figure 5 This is a connection diagram of the pin lead-out port of the MIPI control mode, that is, the pin4 and pin6 of the chip adopt the multiplexing mode, and only the input or output of the two pins in different modes need to be controlled. When the working mode is changed from GPIO control to MIPI control, the CTRL signal of the CTRL terminal of the pin6 pin is switched to the SDATA signal, and the Vdd signal of the Vdd terminal of the pin4 pin is switched to the SCLK and VIO signals. Because the VIO input is for power supply, and the SCLK input is a clock signal, if you want to combine the two and input them to the Vdd terminal, you must carry the clock information carrier to the voltage. Figure 5 In the example, the VIO signal input is connected to the diode D1, and the ground terminal of the filter capacitor Cin is changed to the input terminal of SCLK. Due to the unidirectional conductivity of the diode, the voltage flowing through the diode D1 is positive, and the SCLK signal passing through the filter capacitor Cin is superimposed on the filtered forward voltage to achieve signal carrier modulation. Assuming the diode voltage drop is VD , the voltage signal of SCLK is divided into low level and high level, and the voltage after the filter capacitor is charged is VIO-V D ; So the Vdd voltage after carrier modulation is expressed as follows:

[0039] V H =2*VIO-V D ; V L =VIO-V D ;

[0040] Where VIO is the power supply voltage; V D is the diode voltage drop; V H is the high level value of the modulation voltage, V L It is the low level value of the modulation voltage. After carrier modulation, Vdd changes according to the original SCLK signal cycle, which not only realizes the power supply function, but also contains the clock information of SCLK.

[0041] In order to realize the above-mentioned mode switching function, the present application provides a radio frequency switch mode control circuit, see Figure 5 As shown, it includes a diode D, a modulation capacitor Cin, a signal regulator, a level converter level shift, a decoding core mipi core for the MIPI protocol slave end, a clock counter Num count and a data selector MUX.

[0042] The circuit structure introduces the modulation voltage Vdd through the Vdd terminal, and the Vdd terminal is connected to the signal regulator and the level shifter respectively. The signal regulator rectifies the input modulation voltage Vdd and outputs the shaped voltage Vint. The shaping here is mainly to filter out the high-order harmonics of Vdd to obtain a relatively accurate voltage signal, which is convenient for subsequent clock counting.

[0043] like Figure 6 As shown, for the modulation voltage Vdd, as described in the previous example, when the RF circuit is switched to the GIPO control mode, the modulation voltage directly input to the Vdd terminal is a DC Vdd voltage signal, and a filter capacitor Cin is connected to the Vdd port, the positive electrode of the filter capacitor Cin is directly connected to the Vdd terminal, and the negative electrode is grounded; the CTRL terminal inputs the CTRL control signal for switching the RF path.

[0044] like Figure 7As shown in the figure, when the RF circuit is switched to MIPI control mode, the VIO voltage is input to the positive electrode of the diode D1, and the negative electrode is output to the Vdd terminal. The positive electrode of the filter capacitor Cin is directly connected to the Vdd terminal, and the negative electrode is connected to the SCLK clock signal. The Vdd terminal inputs the modulation voltage after carrier modulation based on the SCLK clock signal, and the CTRL terminal is connected to the SDATA data signal.

[0045] In some embodiments, the VIO voltage is generally a DC voltage of 1.6V to 2V. Taking 1.8V as an example, the voltage after the diode voltage drop is 1.8V-0.7V=1.1V, and the voltage after the Cin capacitor is charged is 1.1V. The SCLK signal connected to the capacitor is the same as the VIO power supply input, so the low level of the clock signal is set to 0, the high level is set to VIO, and the SDATA signal can be set in the same way. In this way, the carrier-post-Vdd means adding the VIO voltage to the clock signal, and its high level is 1.8V+1.1V=2.9V, and the low level is 1.1V.

[0046] The level shift converter connects the rectifier output of the signal regulator and outputs the demodulated clock signal based on Vdd and Vint. For the GIPO control mode, the Vdd terminal inputs the Vdd DC voltage, the negative pole of Cin is grounded, and there is no additional signal input, so the level shift outputs an invalid clock signal. Similarly, the two signals sent to the MIPI decoding core (invalid SCLK and SDATA signals) cannot be correctly decoded according to the mipi protocol.

[0047] For the MIPI control mode, the signal regulator filters out high-frequency components and outputs Vint. Vint is not only input into the level converter level shift for analysis, but also sent to the MIPI decoding core for power supply. The level converter level shift receives Vint and Vdd voltages and performs voltage conversion. The two signals are used for power supply and signal decoding respectively. The effective SCLK clock signal is demodulated according to the rising and falling edges to facilitate subsequent clock counting. For the convenience of calculation, the modulated SCLK signal can be output by the difference method. Taking the aforementioned Vdd or Vint as an example, the low voltage of the output SCLK signal is set to 0, and the high voltage is set to 2.9V-1.1V=1.8V.

[0048] For the clock counter Num count, it can demodulate and count the clock according to the rising edge and falling edge, and output a chip select signal according to the clock count value and the set target value. The clock counter counts the clock based on the rising edge and / or falling edge of the demodulated clock signal, and outputs a chip select signal according to the clock count value and the set target value. In some embodiments, when the clock count value is not higher than the target value, the output chip select signal is low, indicating that the current control mode is GPIO; when the clock count value is higher than the target value, the output chip select signal is high, indicating that the current control mode is MIPI.

[0049] It is particularly noted that the clock counter, signal regulator and level converter in all embodiments of the present application are common circuit structures, and a general circuit structure or a self-design can be used to implement the corresponding functions, and the specific details are not described in detail. MIPIcore is the processing core in the MIPI control mode, and the present application uses the core to perform MIPI control, and its internal details are not described in detail.

[0050] The target value of the clock signal is determined by the Slave Address and / or Command Payload bits of the SDATA signal and the number of SCLK cycles. For details, see Figure 8 The timing diagram of the SCLK and SDATA signals under MIPI control is listed. In some embodiments, the target value can also be set to 2 or 8 values.

[0051] For the clock counter Num count, when the clock count value is not higher than the target value, the output chip select signal is low, indicating that the current control mode is GPIO; when the clock count value is higher than the target value, the output chip select signal is high, indicating that the current control mode is MIPI.

[0052] The MIPI decoding core is also provided with an enable EN terminal. When the control mode is the GPIO control mode, the MIPI decoding core is essentially unable to decode according to invalid SCLK and SDATA signals, and the EN terminal outputs a high level by default; when the control mode is the MIPI control mode and EN outputs a high level, the internal circuit power supply is turned on; when the control mode is the MIPI control mode and EN outputs a low level, the internal circuit power supply is turned off, that is, the power down state that cannot be achieved in the GPIO control mode is realized.

[0053] For the data selector MXU, when the output chip select signal Cont_sel is at a high level, MXU selects the mipi control signal Ctrl_mipi output; when Cont_sel is at a low level, MXU selects the CTRL signal output input by the CTRL terminal (sent into the chip).

[0054] Based on the above-mentioned RF switch mode control circuit, the present application also provides a RF switch mode control method, the method comprising:

[0055] S1, receives the modulation voltage input from the Vdd terminal through the level converter, and receives the shaped voltage Vint output by the signal regulator;

[0056] S2, the level converter demodulates and outputs a clock signal based on the shaped voltage Vint and the modulation voltage, and sends the clock signal to the MIPI decoding core and the clock counter;

[0057] S3, the MIPI decoding core receives the clock signal and the input signal of the CTRL terminal, and decodes and outputs the mipi control signal based on the MIPI protocol;

[0058] S4, the clock counter analyzes the demodulated output clock signal, counts the clock signal according to the rising edge and the falling edge, and outputs a chip select signal based on the clock count value;

[0059] S5, the data selector receives the mipi control signal and the signal input from the CTRL terminal, and selects the mipi control signal or the CTRL signal of the CTRL terminal based on the chip select signal; when the chip select signal outputs a high level, the mipi control signal is selected and output, and when the chip select signal outputs a low level, the mipi control signal is selected and output.

[0060] In this solution, different control solutions all need to use the RF1 terminal, RF2 terminal, GND terminal and ANT terminal. The difference is that the Vdd terminal and CTRL terminal need to switch input in different states. When the chip select signal outputs a high level and the EN terminal of the MIPI decoding core outputs a low level, the chip switches to the power down state to achieve low power consumption.

[0061] In this embodiment, Num count uses the number of SCLK clocks specified in the command frame of the mipi protocol, which is at least 12 bits. After the number of Num count reading clocks is greater than 12, it is determined that the output Cont_sel is high, that is, the MIPI control and GPIO control identification functions are realized. Cont_sel is determined to be high, indicating that the current MIPI control mode is used, and the internal state control signal Ctrl_int receives the MIPI core output signal Ctrl_mipi to realize independent control of the internal state. At the same time, the MIPI core outputs the EN signal to open and close the internal circuit to achieve low-power application requirements, and expand the number of application states controlled by GPIO.

[0062] In summary, this application uses the GPIO control method in the original QFN packaging mode, keeps the RF1 terminal, RF2 terminal, GND terminal and ANT terminal unchanged, and chooses to reuse the CTRL terminal and Vdd terminal. On the basis of compatibility with GPIO, a diode and a filter capacitor are used to modulate the SCLK signal carrier into the VIO voltage to achieve the role of sharing a Vdd terminal, and the circuit introduces a signal regulator and a level converter to filter and modulate the modulation voltage, demodulate the SCLK signal and send it to the MIPIcore for decoding. For the state judgment of the circuit itself, the number of SCLK clocks specified in the command frame in the mipi protocol is used to judge, and the selector chip selects the output control signal. This solution introduces the MIPI control method on the basis of the original GPIO, and is compatible with the GPIO control method of the existing general 2T switch chip. The control method expands the application limitations of the GPIO control method, has a strong engineering significance, and the product is universal and competitive.

[0063] The preferred embodiments of the present invention are described above; it should be understood that the present invention is not limited to the above-mentioned specific implementation modes, and the devices and structures not described in detail should be understood to be implemented in a common manner in the art; any technician familiar with the art can make many possible changes and modifications without departing from the technical solution of the present invention, or modify them into equivalent embodiments with equivalent changes, which does not affect the essential content of the present invention; therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention are still within the scope of protection of the technical solution of the present invention.

Claims

1. A radio frequency switch mode control circuit, characterized in that: The Vdd terminal and CTRL terminal of the QFN under the GIPO control mode are reused; the RF switch mode control circuit includes a signal conditioner, a level converter, a MIPI decoding core for the MIPI protocol slave end, a clock counter and a data selector; Introducing a modulation voltage through a Vdd terminal, and connecting the Vdd terminal to a signal regulator and a level converter respectively; the signal regulator rectifies the input modulation voltage and outputs a shaped voltage; The level converter is connected to the rectified output of the signal conditioner and outputs a demodulated clock signal based on the input modulation voltage and the shaped voltage; The MIPI decoding core is connected to the rectifier output of the signal regulator, receives the clock signal output by the level converter, and receives the signal input by the CTRL terminal, and decodes and outputs the mipi control signal based on the MIPI protocol; The clock counter receives the clock signal output by the level converter, counts and outputs a chip select signal according to the clock signal, and the output chip select signal is connected to the chip select terminal of the data selector; The two input ends of the data selector receive the mipi control signal and the signal input by the CTRL terminal respectively, and output the RF switch control signal according to the chip selection signal.

2. The radio frequency switch mode control circuit according to claim 1, characterized in that: When the RF circuit is switched to the GIPO control mode, the modulation voltage directly input to the Vdd terminal is a DC Vdd voltage signal, and a filter capacitor Cin is connected to the Vdd port, the positive electrode of the filter capacitor Cin is directly connected to the Vdd terminal, and the negative electrode is grounded; The CTRL terminal inputs the CTRL control signal for switching the RF path.

3. The radio frequency switch mode control circuit according to claim 1, characterized in that: When the RF circuit is switched to MIPI control mode, the VIO voltage is input to the positive electrode of the diode D1, and the negative electrode output is connected to the Vdd terminal; The positive electrode of the filter capacitor Cin is directly connected to the Vdd terminal, and the negative electrode is connected to the SCLK clock signal; The input of the Vdd terminal is the modulation voltage after the SCLK clock signal carrier is modulated; The CTRL terminal is connected to the SDATA data signal.

4. The radio frequency switch mode control circuit according to claim 3, characterized in that: When the RF circuit is switched to the MIPI control mode, the shaped voltage Vint output by the signal conditioner is a DC voltage, and Vint is greater than the VIO voltage; The level converter demodulates a valid SCLK clock signal based on the rising edge and falling edge of the shaped voltage Vint, and sends the signal to the MIPI decoding core and the clock counter.

5. The radio frequency switch mode control circuit according to claim 3, characterized in that: When the radio frequency circuit is switched to the GIPO control mode, the level converter outputs an invalid clock signal.

6. The radio frequency switch mode control circuit according to claim 4 or 5, characterized in that: The clock counter counts the clock based on the rising edge or falling edge of the demodulated clock signal, and outputs a chip select signal according to the clock count value and a set target value; When the clock count value is not higher than the target value, the output chip select signal is low, indicating that the current control mode is GPIO; when the clock count value is higher than the target value, the output chip select signal is high, indicating that the current control mode is MIPI.

7. The radio frequency switch mode control circuit according to claim 6, characterized in that: The MIPI decoding core is also provided with an enable EN terminal. When the control mode is the GPIO control mode, the EN terminal outputs a high level by default; when the control mode is the MIPI control mode and EN outputs a high level, the internal circuit power supply is turned on; when the control mode is the MIPI control mode and EN outputs a low level, the internal circuit power supply is turned off.

8. The radio frequency switch mode control circuit according to claim 6, characterized in that: When the output chip select signal is at a high level, the data selector selects the mipi control signal output; when the output chip select signal is at a low level, the data selector selects the CTRL signal output input by the CTRL terminal.

Images