Array substrate, display panel and display device
By multiplexing the light-shielding electrode into source/drain in the transistor of the electronic paper array substrate, and increasing the spacing between them and the gate, the poor display problems such as ghosting and crosstalk in the electronic paper reader are solved, and a better display effect is achieved.
Patent Information
- Application Number
- CN202420153821.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-01-22
- Publication Date
- 2025-03-04
- Estimated Expiration
- 2034-01-22
AI Technical Summary
Existing electronic paper readers are prone to poor displays such as ghosting and crosstalk, and the main factor is the parasitic capacitance between the gate metal and the source and drain metal.
By multiplexing the light-shielding electrode into a source/drain electrode in the transistor of the array substrate, and increasing the spacing between the gate and the light-shielding electrode through the first insulating layer, the parasitic capacitance is reduced.
It reduces the coupling effect of parasitic capacitance, reduces poor display such as ghosting and crosstalk, and improves the display effect.
Smart Images
Figure CN222561889U_ABST
Abstract
Description
Technical Field
[0001] The present application belongs to the field of display technology, and specifically relates to an array substrate, a display panel and a display device. Background Art
[0002] E-paper displays are primarily reflective displays with no backlight and display images by reflecting ambient light, providing a viewing experience similar to traditional paper.
[0003] In the electronic paper industry, when electronic paper is used as a reader, the electronic paper transistor mainly adopts a bottom gate structure, and it is usually necessary to add a shielding layer to the array substrate to prevent the transistor channel from being exposed to light and generating a large leakage current. With the widespread application of electronic paper, people are increasingly demanding the quality of e-book display images. At present, some electronic paper readers are prone to display defects such as ghosting and crosstalk, and an important factor causing these defects is the parasitic capacitance between the gate metal and the source and drain metal, so how to reduce the parasitic capacitance is a problem that should be solved at present. Utility Model Content
[0004] The purpose of the present application is to provide an array substrate, a display panel and a display device, which can reduce the coupling effect of parasitic capacitance, reduce display defects such as ghosting and crosstalk, and improve the display effect.
[0005] In a first aspect, the present application provides an array substrate, comprising a substrate and a transistor disposed on the substrate, wherein the transistor comprises a gate and an active layer, wherein the gate insulating layer is disposed between the gate and the active layer, the gate insulating layer covers the gate, the active layer is disposed on a side of the gate insulating layer away from the substrate, and an orthographic projection of the active layer on the substrate at least partially overlaps with an orthographic projection of the gate on the substrate; the transistor further comprises:
[0006] A first electrode is provided on a side of the gate insulating layer away from the base substrate, and the first electrode is overlapped with one end of the active layer;
[0007] A light-shielding electrode, wherein a first insulating layer is provided between the light-shielding electrode and the first electrode, the first insulating layer is provided on a side of the gate insulating layer away from the base substrate, and the first insulating layer covers the first electrode and the active layer, a via hole is provided on the first insulating layer, and the light-shielding electrode is overlapped at the other end of the active layer through the via hole, and the orthographic projection of the light-shielding electrode on the base substrate at least partially overlaps with the orthographic projection of the first electrode on the base substrate.
[0008] In an exemplary embodiment of the present application, the array substrate further includes:
[0009] A second insulating layer is provided on a side of the first insulating layer away from the base substrate, and the second insulating layer covers the light shielding electrode, and a through hole is provided on the second insulating layer;
[0010] A pixel electrode is disposed on a side of the second insulating layer away from the base substrate, and the pixel electrode is connected to the light shielding electrode through the through hole.
[0011] In an exemplary embodiment of the present application, the array substrate further includes:
[0012] A second insulating layer, disposed on a side of the first insulating layer away from the base substrate, the second insulating layer covers the light shielding electrode, and a through hole is disposed on the second insulating layer;
[0013] A pixel electrode is provided on a side of the second insulating layer away from the base substrate, and the pixel electrode is connected to the first electrode through the through hole.
[0014] In an exemplary embodiment of the present application, in a direction from the pixel electrode to the base substrate, an opening area of the via hole gradually decreases.
[0015] In an exemplary embodiment of the present application, the via hole leaks out a portion of the active layer;
[0016] The transistor includes a channel region, and the length of the channel region can be adjusted according to the position of the via hole.
[0017] In an exemplary embodiment of the present application, the through hole sequentially penetrates the second insulating layer and the first insulating layer, and the opening area of the through hole gradually increases in the direction from the base substrate to the pixel electrode.
[0018] In an exemplary embodiment of the present application, the array substrate includes a plurality of sub-pixels arranged in an array, each of the sub-pixels includes a first transistor and a second transistor, and the pixel electrode is connected to one of the first transistor and the second transistor.
[0019] In an exemplary embodiment of the present application, when the pixel electrode is connected to the light shielding electrode through the through hole, the first electrode is provided between the first transistor and the second transistor;
[0020] The first electrode includes a first part, a second part and a third part, the first part is connected to the third part through the second part, the first part is overlapped with one end of the active layer in the first transistor, the third part is overlapped with one end of the active layer in the second transistor, and the orthographic projection of the second part on the substrate has no overlap with the orthographic projection of the light-shielding electrode on the substrate.
[0021] A second aspect of the present application provides a display panel, comprising an opposite substrate and any one of the above array substrates, wherein the opposite substrate is arranged opposite to the array substrate.
[0022] A third aspect of the present application provides a display device, including:
[0023] Power module;
[0024] In the display panel described above, the power module is used to provide driving power to the display panel to drive the display panel to perform image display.
[0025] The array substrate, display panel and display device of the present application have the following beneficial effects:
[0026] The array substrate includes a substrate and a transistor, and the transistor includes a gate, a gate insulating layer, an active layer, a first electrode, a first insulating layer and a light-shielding electrode, the first electrode is one of the source / drain electrodes of the transistor, and the light-shielding electrode is the other of the source / drain electrodes of the transistor, and the light-shielding electrode and the first electrode are located in different layers, and a first insulating layer is provided between the light-shielding electrode and the first electrode. That is to say, the present application reuses the light-shielding electrode as the source / drain electrode of the transistor, and the light-shielding electrode is provided on the side of the first insulating layer away from the substrate, that is: the first insulating layer increases the distance between the gate and the light-shielding electrode, so that the parasitic capacitance between the two is reduced, and the coupling effect of the parasitic capacitance is reduced, thereby reducing display defects such as ghosting and crosstalk, and improving the display effect.
[0027] In addition, the light-shielding electrode can also prevent large leakage currents from being generated by light.
[0028] Other features and advantages of the present application will become apparent from the following detailed description, or may be learned in part by the practice of the present application.
[0029] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS
[0030] The drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present application, and together with the specification are used to explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0031] Figure 1 A schematic diagram showing a structure in which a plurality of sub-pixels are formed on a substrate provided in Embodiment 1, 2, 3 or 4 of the present application is shown;
[0032] Figure 2 A schematic cross-sectional structure diagram of the connection between the pixel electrode and the light shielding electrode provided in the first embodiment of the present application is shown;
[0033] Figure 3 A schematic cross-sectional structure diagram of the connection between the pixel electrode and the first electrode provided in the second embodiment of the present application is shown;
[0034] Figure 4 A schematic cross-sectional structure diagram of a sub-pixel provided with two transistors according to the third embodiment of the present application is shown;
[0035] Figure 5 A schematic cross-sectional structure diagram of a sub-pixel provided with two transistors according to a fourth embodiment of the present application is shown;
[0036] Figure 6 A schematic diagram showing the structure of a display panel provided in Embodiment 5 of the present application is shown;
[0037] Figure 7 The structure of the display device provided in the sixth embodiment of the present application is shown.
[0038] Description of reference numerals:
[0039] 1. Display device; 10. Display panel; 100. Array substrate; 110. Base substrate; 120. Transistor; 120a. First transistor; 120b. Second transistor; 121. Gate; 122. Active layer; 123. First electrode; 1231. First part; 1232. Second part; 1233. Third part; 124. Shading electrode; 125. Channel region; 130. Gate insulating layer; 140. First insulating layer; 141. Via hole; 150. Second insulating layer; 160. Pixel electrode; 170. Through hole; 200. Opposite substrate; 300. Display medium layer; 20. Power module. DETAILED DESCRIPTION
[0040] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this application will be more comprehensive and complete and fully convey the concept of the example embodiments to those skilled in the art.
[0041] In this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.
[0042] In this application, unless otherwise clearly specified and limited, the terms "assembly", "connection" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.
[0043] In addition, described feature, structure or characteristic can be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present application. However, those skilled in the art will appreciate that the technical scheme of the present application can be put into practice without one or more of the specific details, or other methods, components, devices, steps, etc. can be adopted. In other cases, known methods, devices, realizations or operations are not shown or described in detail to avoid blurring the various aspects of the application.
[0044] Embodiment 1
[0045] See also Figure 1 As shown, the first embodiment of the present application provides an array substrate 100, which includes a base substrate 110 and a plurality of array-arranged sub-pixels (not shown in the figure) disposed on the base substrate 110, and each sub-pixel includes a transistor 120.
[0046] The base substrate 110 may be a glass substrate, but is not limited thereto, and may also be a substrate made of other materials, such as PI material, etc.
[0047] Specifically, see Figure 2 As shown, the transistor 120 may include a gate 121, an active layer 122, a first electrode 123 and a light-shielding electrode 124. A gate insulating layer 130 may be arranged between the gate 121 and the active layer 122 to insulate the gate 121 and the active layer 122 from each other; and the first electrode 123 and the light-shielding electrode 124 may be overlapped with the source and drain doping regions of the active layer 122, respectively. Specifically, the corresponding connection relationship between the first electrode 123 and the light-shielding electrode 124 and the source and drain doping regions of the active layer 122 may be determined according to whether the transistor 120 is N-type or P-type.
[0048] For example, Figure 2As shown, in an embodiment of the present application, the transistor 120 may be a bottom gate type, that is, a gate 121 may be first formed on a base substrate 110; then, a gate insulating layer 130 is formed on the base substrate 110, and the gate insulating layer 130 covers the gate 121; then, an active layer 122 is formed on a side of the gate insulating layer 130 away from the base substrate 110, that is, the active layer 122 is located on a side of the gate 121 away from the base substrate 110, and the active layer 122 overlaps with the positive projection of the gate 121 on the base substrate 110. For example, the orthographic projection of the gate electrode 121 on the base substrate 110 may be located within the orthographic projection of the active layer 122 on the base substrate 110; the first electrode 123 may be formed after the active layer 122 is formed, and at least a portion of the first electrode 123 may overlap on a doped region of the source and drain doped regions of the active layer 122; then, a first insulating layer 140 is formed on the base substrate 110, the first insulating layer 140 covers the gate insulating layer 130, the active layer 122 and the first electrode 123, and a via 141 is formed on the first insulating layer 140; finally, a light-shielding electrode 124 is formed above the first insulating layer 140, and the light-shielding electrode 124 overlaps on another doped region of the source and drain doped regions of the active layer 122 through the via 141 on the first insulating layer 140.
[0049] Among them, the first electrode 123 is the source or drain of the transistor 120, and the light shielding electrode 124 is the drain or source of the transistor 120; that is, the light shielding electrode 124 is reused as the drain or source of the transistor 120, and the light shielding electrode 124 and the first electrode 123 are located in different layers, and there is a first insulating layer 140 between the light shielding electrode 124 and the first electrode 123, and the distance between the gate 121 and the light shielding electrode 124 can be increased through the first insulating layer 140. In addition, the parasitic capacitance between the gate 121 and the source / drain is reduced, the coupling effect of the parasitic capacitance is reduced, the display problems such as ghosting and crosstalk are reduced, and the display effect is improved.
[0050] It should be noted that if Figure 2 As shown, the orthographic projection of the light-shielding electrode 124 on the base substrate 110 at least partially overlaps with the orthographic projection of the first pole 123 on the base substrate 110; that is, part of the light-shielding electrode 124 can shield the channel region 125 between the first pole 123 and the light-shielding electrode 124, thereby preventing light from irradiating the channel region 125 of the transistor 120 and generating a large leakage current.
[0051] That is to say, Figure 2 As shown, a channel region 125 of the transistor 120 is formed between the light-shielding electrode 124 and the first electrode 123 , and the light-shielding electrode 124 is used to shield the channel region 125 to prevent the channel region 125 from being exposed to light and generating a large leakage current.
[0052] In addition, if Figure 2 As shown, the array substrate 100 also includes a second insulating layer 150 and a pixel electrode 160. The second insulating layer 150 is arranged on the side of the first insulating layer 140 away from the base substrate 110, and the second insulating layer 150 covers the light-shielding electrode 124. A through hole 170 is provided on the second insulating layer 150. The pixel electrode 160 is arranged on the side of the second insulating layer 150 away from the base substrate 110, and is electrically connected to the first electrode 123 or the light-shielding electrode 124 through the through hole 170 on the second insulating layer 150.
[0053] In the embodiments of the present application, Figure 2 As shown, the pixel electrode 160 can be electrically connected to the light shielding electrode 124 through a through hole 170 structure penetrating the second insulating layer 150. That is, the light shielding electrode 124 is the drain of the transistor 120, and the first electrode 123 is the source of the transistor 120.
[0054] like Figure 2 As shown, the light-shielding electrode 124 located on the first insulating layer 140 is connected to one end of the active layer 122 through a via 141 structure penetrating the first insulating layer 140, and the orthographic projection of the light-shielding electrode 124 on the base substrate 110 and the orthographic projection of the first pole 123 on the base substrate 110 have an overlapping area, so that the light-shielding electrode 124 can be used to shield the channel region 125 between the light-shielding electrode 124 and the first pole 123 to prevent external light from irradiating the channel region 125 and generating a large leakage current, thereby ensuring the display effect.
[0055] It should be noted that if Figure 2 As shown, in the direction from the pixel electrode 160 to the base substrate 110, the area of the through hole 170 gradually decreases to ensure that the pixel electrode 160 can be stably electrically connected to the shading electrode 124 and is not prone to breakage, thereby ensuring the continuity of the pixel electrode 160 and further ensuring the display effect.
[0056] In addition, if Figure 2 As shown, in the direction from the pixel electrode 160 to the base substrate 110 , the area of the via hole 141 gradually decreases to ensure that the light shielding electrode 124 can be stably overlapped on one end of the active layer 122 and is not prone to breakage, thereby ensuring the continuity of the light shielding electrode 124 .
[0057] It is worth mentioning that the maximum opening area of the via hole 141 is smaller than the minimum opening area of the through hole 170 .
[0058] In the embodiment of the present application, the channel region 125 is the portion of the light-shielding electrode 124 overlapping the active layer 122 and the portion of the first pole 123 overlapping the active layer 122, and the length of the channel region 125 is the distance between the light-shielding electrode 124 overlapping the active layer 122 and the first pole 123 overlapping the active layer 122; that is, by changing the position of the via 141 and changing the position where the light-shielding electrode 124 overlaps the active layer 122, the distance between the light-shielding electrode 124 and the first pole 123 can be changed, and the length of the channel region 125 can be changed, thereby realizing the development of short channel transistor 120 devices to achieve narrow frame, high resolution and high pixel density display.
[0059] That is to say, the present application scheme utilizes the light-shielding electrode 124 as the source or drain of the transistor 120, and the light-shielding electrode 124 and the first electrode 123 are located in different layers, and a first insulating layer 140 is provided between the light-shielding electrode 124 and the first electrode 123, so as to increase the distance between the light-shielding electrode 124 and the gate 121, reduce the parasitic capacitance between the gate 121 and the light-shielding electrode 124, reduce the coupling effect of the parasitic capacitance, and reduce display problems such as ghosting and crosstalk.
[0060] In addition, by changing the position of the via 141, the length of the channel region 125 between the light shielding electrode 124 and the first electrode 123 can be adjusted, thereby realizing the development of a short channel transistor 120 device to achieve narrow frame, high resolution and high pixel density display.
[0061] Embodiment 2
[0062] The difference between the second embodiment of the present application and the first embodiment is that Figure 3 As shown, the pixel electrode 160 is electrically connected to the first electrode 123 .
[0063] The pixel electrode 160 can be electrically connected to the first electrode 123 through the through hole 170 that sequentially penetrates the second insulating layer 150 and the first insulating layer 140. At this time, the first electrode 123 is the drain of the transistor 120, the light shielding electrode 124 is the source, and the orthographic projection of the light shielding electrode 124 on the base substrate 110 and the orthographic projection of the first electrode 123 on the base substrate 110 have an overlapping portion, so as to shield the channel region 125 between the light shielding electrode 124 and the first electrode 123, avoid the channel region 125 from generating a large leakage current, and ensure the display effect.
[0064] Embodiment 3
[0065] The difference between the third embodiment of the present application and the first embodiment is that Figure 4 As shown, each sub-pixel in the third embodiment of the present application includes two transistors 120, namely a first transistor 120a and a second transistor 120b, and the two transistors 120 are arranged adjacent to each other.
[0066] The first electrode 123 is disposed between the first transistor 120a and the second transistor 120b to reduce the space occupied by the first electrode 123 and reduce the cost of the material of the first electrode 123. One end of the first electrode 123 is overlapped with one end of the active layer 122 in the first transistor 120a, and the other end of the first electrode 123 is overlapped with one end of the active layer 122 in the second transistor 120b.
[0067] For example, Figure 4 As shown, the first electrode 123 includes a first part 1231, a second part 1232 and a third part 1233, the first part 1231 is connected to the third part 1233 through the second part 1232, the first part 1231 is overlapped on one end of the active layer 122 in the first transistor 120a, the third part 1233 is overlapped on one end of the active layer 122 in the second transistor 120b, the second part 1232 is located between the first part 1231 and the third part 1233, and the orthographic projection of the second part 1232 on the substrate 110 does not overlap with the orthographic projection of the shading electrode 124 on the substrate 110, so as to avoid the problem of parasitic capacitance between the shading electrode 124 and the first electrode 123.
[0068] It is worth mentioning that the pixel electrode 160 is electrically connected to the light shielding electrode 124 of the first transistor 120a and the second transistor 120b through the through hole 170. In other words, the pixel electrode 160 can be electrically connected to the light shielding electrode 124 of the first transistor 120a or the light shielding electrode 124 of the second transistor 120b.
[0069] Embodiment 4
[0070] The difference between the fourth embodiment of the present application and the second embodiment is that Figure 5 As shown, each sub-pixel in the fourth embodiment of the present application includes two transistors 120, namely a first transistor 120a and a second transistor 120b, and the two transistors 120 are arranged adjacent to each other.
[0071] See also Figure 5As shown, the light-shielding electrode 124 is continuous and uninterrupted, and the light-shielding electrode 124 is located between the first electrodes 123 of two adjacent transistors 120, that is, the light-shielding electrode 124 is located between the first electrode 123 of the first transistor 120a and the first electrode 123 of the second transistor 120b; and the orthographic projection of the light-shielding electrode 124 on the substrate 110 has an overlapping area with the orthographic projection of the first electrode 123 of the first transistor 120a on the substrate 110, and the orthographic projection of the light-shielding electrode 124 on the substrate 110 has an overlapping area with the orthographic projection of the first electrode 123 of the second transistor 120b on the substrate 110, so as to prevent light from irradiating the channel region 125 and generating a large leakage current.
[0072] It is worth mentioning that the pixel electrode 160 is electrically connected to the first electrode 123 of one of the first transistor 120a and the second transistor 120b through the through hole 170. In other words, the pixel electrode 160 can be electrically connected to the first electrode 123 of the first transistor 120a or the first electrode 123 of the second transistor 120b.
[0073] Embodiment 5
[0074] Embodiment 5 of the present application provides a display panel 10, such as Figure 6 As shown, it includes a counter substrate 200 and an array substrate 100 described in any one of the first to fourth embodiments, wherein a display medium layer 300 formed by a plurality of micro liquid capsules may be provided between the counter substrate 200 and the array substrate 100, wherein the micro liquid capsule is a sealed sphere and white particles, black particles and a transparent dispersion medium are encapsulated inside, wherein the white particles and the black particles have different charges, and the white particles and the black particles are immersed in the transparent dispersion medium and can move freely. The transistor 120 in any array substrate 100 in the first to fourth embodiments drives the white particles and the black particles to move in the transparent dispersion medium. The light shielding electrode 124 is used to block external light from being transmitted through the counter substrate 200 through the white particles and the black particles to the channel region 125.
[0075] Embodiment 6
[0076] Embodiment 6 of the present application provides a display device 1, such as Figure 7 As shown, the display device 1 includes a power module 20 and a display panel 10 in the fifth embodiment, and the power module 20 is used to provide driving power to the display panel 10 to drive the display panel 10 to perform image display, that is, to provide driving power to the gate 121, the first electrode 123 and the light shielding electrode 124.
[0077] In the description of this specification, the description with reference to the terms "some embodiments", "exemplarily", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.
[0078] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application. Therefore, any changes or modifications made in accordance with the claims and description of the present application should fall within the scope of the patent of this application.
Claims
1. An array substrate, comprising a base substrate and a transistor disposed on the base substrate, wherein the transistor comprises a gate and an active layer, a gate insulating layer is disposed between the gate and the active layer, the gate insulating layer covers the gate, the active layer is disposed on a side of the gate insulating layer away from the base substrate, and an orthographic projection of the active layer on the base substrate at least partially overlaps with an orthographic projection of the gate on the base substrate; characterized in that: The transistor further comprises: A first electrode is provided on a side of the gate insulating layer away from the base substrate, and the first electrode is overlapped with one end of the active layer; A light-shielding electrode, wherein a first insulating layer is provided between the light-shielding electrode and the first electrode, the first insulating layer is provided on a side of the gate insulating layer away from the base substrate, and the first insulating layer covers the first electrode and the active layer, a via hole is provided on the first insulating layer, and the light-shielding electrode is overlapped at the other end of the active layer through the via hole, and the orthographic projection of the light-shielding electrode on the base substrate at least partially overlaps with the orthographic projection of the first electrode on the base substrate.
2. The array substrate according to claim 1, characterized in that: The array substrate further includes: A second insulating layer, disposed on a side of the first insulating layer away from the base substrate, the second insulating layer covers the light shielding electrode, and a through hole is disposed on the second insulating layer; A pixel electrode is disposed on a side of the second insulating layer away from the base substrate, and the pixel electrode is connected to the light shielding electrode through the through hole.
3. The array substrate according to claim 1, characterized in that: The array substrate further includes: A second insulating layer, disposed on a side of the first insulating layer away from the base substrate, the second insulating layer covers the light shielding electrode, and a through hole is disposed on the second insulating layer; A pixel electrode is provided on a side of the second insulating layer away from the base substrate, and the pixel electrode is connected to the first electrode through the through hole.
4. The array substrate according to claim 2 or 3, characterized in that: In the direction from the pixel electrode to the base substrate, the opening area of the via hole gradually decreases.
5. The array substrate according to claim 4, characterized in that: The via hole leaks part of the active layer; The transistor includes a channel region, and the length of the channel region can be adjusted according to the position of the via hole.
6. The array substrate according to claim 3, characterized in that: The through hole passes through the second insulating layer and the first insulating layer in sequence, and the opening area of the through hole gradually increases in the direction from the base substrate to the pixel electrode.
7. The array substrate according to claim 2 or 3, characterized in that: The array substrate includes a plurality of sub-pixels arranged in an array, each of the sub-pixels includes a first transistor and a second transistor, and the pixel electrode is connected to one of the first transistor and the second transistor.
8. The array substrate according to claim 7, characterized in that: When the pixel electrode is connected to the light shielding electrode through the through hole, the first electrode is arranged between the first transistor and the second transistor; The first electrode includes a first part, a second part and a third part, the first part is connected to the third part through the second part, the first part is overlapped with one end of the active layer in the first transistor, the third part is overlapped with one end of the active layer in the second transistor, and the orthographic projection of the second part on the substrate has no overlap with the orthographic projection of the light-shielding electrode on the substrate.
9. A display panel, characterized in that: It comprises an opposing substrate and the array substrate according to any one of claims 1 to 8, wherein the opposing substrate is arranged opposite to the array substrate.
10. A display device, characterized in that: include: Power module; The display panel as claimed in claim 9, wherein the power module is used to provide driving power to the display panel to drive the display panel to perform image display.