Word line selection circuit, memory array and flash memory

Abstract

The utility model relates to the technical field of memories, in particular to a word line selection circuit, a memory array and a flash memory, the word line selection circuit comprises: a replacement determination module, the first input end and the second input end of which respectively input the first flag bit information and the second flag bit information of a selected redundant word line; the first input end of the redundancy control module is connected with the output end of the replacement determination module, the second input end of the redundancy control module inputs the address of the operation word line, and the third input end of the redundancy control module inputs the replacement address of the selected redundancy word line; and the output end of the comparator is connected with the address decoding circuit of the storage array and the address decoding circuit of the redundant array and is used for outputting replacement selection signals. The word line selection circuit provided by the utility model can solve the problems of complex control logic in the existing redundancy replacement process and complex circuit structure for redundancy replacement, and has the advantages of simple circuit structure and control logic, quick response and accurate judgment.

Description

Technical Field

[0001] The present application relates to the field of memory technology, and in particular to a word line selection circuit, a memory array, and a flash memory. Background Art

[0002] A memory array is an array of memory cells and is the key component of flash memory for storing data information. During the use of a memory array, it is usually necessary to decode the memory cell addresses in the memory array to perform operations such as erase, read, or write.

[0003] During the manufacturing process of flash memory, it is necessary to perform operations on the flash memory for functional testing. However, during the manufacturing process, memory cells often have defects or functional abnormalities. As a result, when the memory decodes the address of the defective or functionally abnormal cell during the functional test, it cannot correctly perform operations based on the defective or functionally abnormal cell. This causes the memory to fail the functional test and be scrapped, which in turn leads to reduced flash memory yield, increased production costs, and waste of production resources. To address this problem, some flash memories provide multiple redundant word lines composed of redundant cells. When performing operations on defective or functionally abnormal cells, the redundant word lines are used to replace the word lines containing the defective or functionally abnormal cells. The existing redundant replacement process generally requires first determining the mapping relationship between the address of the word line containing the defective or functionally abnormal cell and the address of the redundant word line to identify the redundant word line to be replaced. Then, the voltage applied to the word line containing the replaced memory cell is canceled, and the voltage required for the operation is configured for the redundant word line so that the redundant cells in the redundant word line can replace the defective or functionally abnormal cell to perform the operation. This leads to complex control logic and complex circuit structure for redundant replacement.

[0004] There is currently no effective technical solution to the above problems. Utility Model Content

[0005] The purpose of the present application is to provide a word line selection circuit, a memory array and a flash memory, aiming to solve the problem that the existing redundant replacement process control logic is complex and the circuit structure for redundant replacement is complex.

[0006] In a first aspect, the present application provides a word line selection circuit for use in a flash memory. The flash memory has a storage array and a redundant array. Each redundant word line in the redundant array is configured with a first flag bit and a second flag bit. The first flag bit stores first flag bit information for marking an available state of the corresponding redundant word line, and the second flag bit stores second flag bit information for marking an occupied state of the corresponding redundant word line. The word line selection circuit includes:

[0007] a replacement determination module, wherein a first input terminal and a second input terminal are respectively input with first flag bit information and second flag bit information of a selected redundant word line, and an output terminal is used to output a redundancy enable signal representing a usage status of the selected redundant word line;

[0008] The redundancy control module has a first input terminal connected to the output terminal of the replacement determination module, a second input terminal inputting the address of the operation word line, a third input terminal inputting the replacement address of the selected redundant word line, and an output terminal connected to the address decoding circuit of the memory array and the address decoding circuit of the redundant array and configured to output a replacement selection signal.

[0009] The word line selection circuit provided in the present application can conveniently determine whether a redundant replacement has occurred based on the first flag bit and the second flag bit of the redundant word line, and can output a replacement selection signal according to the judgment result to shield the address decoding circuit of the word line where the replaced storage unit is located and configure the voltage required for operation for the selected redundant word line, thereby easily realizing word line selection, and has the advantages of simple circuit structure and control logic, rapid response and accurate judgment.

[0010] Optionally, the replacement determination module includes:

[0011] The AND gate has one input terminal inputting the first flag information, another input terminal inputting the inverted second flag information, and an output terminal connected to the input terminal of the redundancy control module and outputting a redundancy enable signal.

[0012] Optionally, the address decoding circuit of the memory array includes a plurality of word line decoding circuits, each word line decoding circuit including:

[0013] Address matcher;

[0014] A multiplexer, wherein a first input terminal is connected to the address matcher, a second input terminal is input with an inverted GND signal, and a control terminal is input with a replacement selection signal;

[0015] The first word line driver module has a first input terminal and a second input terminal connected to the output terminal of the multiplexer, a third input terminal inputting an operating voltage, a fourth input terminal inputting a negative power supply voltage, and an output terminal connected to the operating word line and used for outputting the operating voltage or the negative power supply voltage.

[0016] In this embodiment, the present application sets up a multiplexer and a first word line driver module, which can apply a negative power supply voltage to the operating word line when the level of the replacement selection signal is high, so that the storage cells in the operating word line do not perform the corresponding operation, and can apply the operating voltage to the operating word line when the level of the replacement selection signal is low, so that the storage cells that need to perform the operation perform the operation normally.

[0017] Optionally, each word line decoding circuit further includes:

[0018] The first level conversion module is configured such that the output terminal of the multiplexer is connected to the first input terminal and the second input terminal of the first word line driving module via the first level conversion module.

[0019] In this embodiment, the present application provides a first level conversion module, which can convert the level of the signal output by the multiplexer into a level available to the input end of the first word line driver module, thereby enabling the first word line driver module to operate normally.

[0020] Optionally, the first input end of the first level conversion module is connected to the output end of the multiplexer through a first NOT gate, the second input end is connected to the output end of the multiplexer, the first output end is connected to the first input end of the first word line driver module, and the second output end is connected to the second input end of the first word line driver module.

[0021] Optionally, the address decoding circuit of the redundant array includes:

[0022] The second word line driver module has a first input terminal and a second input terminal inputting a replacement selection signal, a third input terminal inputting an operating voltage, a fourth input terminal inputting a negative power supply voltage, and an output terminal connected to the selected redundant word line and used for outputting an operating voltage or a negative power supply voltage.

[0023] Optionally, the address decoding circuit of the redundant array further includes:

[0024] The second level conversion module replaces the selection signal and inputs it into the first input terminal and the second input terminal of the second word line driving module through the second level conversion module.

[0025] Optionally, the replacement selection signal is input into the first input terminal of the second level conversion module through the third NOT gate and the fourth NOT gate, and is input into the second input terminal of the second level conversion module through the third NOT gate, and the first output terminal and the second output terminal of the second level conversion module are connected to the first input terminal and the second input terminal of the second word line driver module.

[0026] In a second aspect, the present application provides a memory array comprising any one of the above word line selection circuits.

[0027] The memory array provided in the present application can conveniently determine whether a redundant replacement has occurred based on the first flag bit and the second flag bit of the redundant word line, and can output a replacement selection signal based on the judgment result to shield the address decoding circuit of the word line where the replaced memory cell is located and configure the voltage required for operation for the selected redundant word line, thereby easily realizing word line selection, and has the advantages of simple circuit structure and control logic, rapid response and accurate judgment.

[0028] In a third aspect, the present application provides a flash memory comprising any one of the above word line selection circuits or the above storage array.

[0029] The flash memory provided in the present application can conveniently determine whether a redundant replacement has occurred based on the first flag bit and the second flag bit of the redundant word line, and can output a replacement selection signal based on the judgment result to shield the address decoding circuit of the word line where the replaced storage unit is located and configure the voltage required for operation for the selected redundant word line, thereby easily realizing word line selection, and has the advantages of simple circuit structure and control logic, rapid response and accurate judgment.

[0030] As can be seen from the above, the present application provides a word line selection circuit, a memory array, and a flash memory, wherein the word line selection circuit of the present application can conveniently determine whether a redundant replacement has occurred based on the first flag bit and the second flag bit of the redundant word line, and can output a replacement selection signal according to the judgment result to shield the address decoding circuit of the word line where the replaced memory cell is located and configure the voltage required for operation for the selected redundant word line, thereby easily realizing word line selection, and having the advantages of simple circuit structure and control logic, rapid response, and accurate judgment. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 A schematic diagram of the structure of a word line selection circuit provided in an embodiment of the present application.

[0032] Figure 2 A structural diagram of a replacement determination module provided in an embodiment of the present application.

[0033] Figure 3 A schematic structural diagram of an address decoding circuit for a storage array provided in an embodiment of the present application.

[0034] Figure 4 A schematic diagram of the structure of an address decoding circuit of a redundant array provided in an embodiment of the present application.

[0035] Explanation of reference numerals: 1. Replacement determination module; 10. Storage array; 11. AND gate; 101. Multiplexer; 102. First word line driver module; 103. First level conversion module; 104. First NOT gate; 105. Address matcher; 106. Second NOT gate; 2. Redundancy control module; 20. Redundant array; 201. Second word line driver module; 202. Second level conversion module; 203. Third NOT gate; 204. Fourth NOT gate. DETAILED DESCRIPTION

[0036] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. The components of the embodiments of the present application generally described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application for protection, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work fall within the scope of protection of the present application.

[0037] It should be noted that similar reference numerals and letters represent similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings. At the same time, in the description of this application, the terms "first", "second", etc. are only used to distinguish the description and should not be understood as indicating or implying relative importance.

[0038] First, as Figure 1 As shown, the present application provides a word line selection circuit, which is applied to a flash memory. The flash memory has a storage array 10 and a redundant array 20. Each redundant word line in the redundant array 20 is configured with a first flag bit and a second flag bit. The first flag bit stores first flag bit information for marking the available state of the corresponding redundant word line, and the second flag bit stores second flag bit information for marking the occupied state of the corresponding redundant word line. The word line selection circuit includes:

[0039] A replacement determination module 1, wherein the first input terminal and the second input terminal respectively input the first flag bit information and the second flag bit information of the selected redundant word line, and the output terminal is used to output a redundancy enable signal representing the usage status of the selected redundant word line;

[0040] The redundancy control module 2 has a first input connected to the output of the replacement determination module 1, a second input inputting the address of the operation word line, a third input inputting the replacement address of the selected redundant word line, and an output connected to the address decoding circuit of the memory array 10 and the address decoding circuit of the redundant array 20 and configured to output a replacement selection signal.

[0041] Specifically, in Figure 1 In the embodiment, Good_flag is the first flag information, monitor is the second flag information, Redun_en is the redundancy enable signal, Input_addr is the address of the operation word line, Bad_addr is the replacement address of the selected redundant word line, match is the replacement selection signal, XDEC is the address decoding circuit of the memory array 10, and RDEC is the address decoding circuit of the redundant array 20.

[0042] More specifically, the operating word line is the word line where the memory cells that need to be operated are located in the memory array 10 .

[0043] More specifically, the redundant array 20 includes a plurality of redundant word lines, each of which includes a plurality of redundant cells. A redundant cell is a cell that can replace a memory cell that needs to be operated. When a memory cell that needs to be operated has a defect or malfunctions, replacing the memory cell that needs to be operated based on the redundant cell can enable the flash memory to smoothly perform the required operation.

[0044] More specifically, the replacement selection signal is used to control the address decoding circuit of the operating word line in the memory array 10 not to apply an operating voltage to the operating word line based on the selected redundant word line and the operating word line that replaces it, and to control the address decoding circuit of the selected redundant word line to apply an operating voltage to the redundant word line, so that the redundant cells in the selected redundant word line perform the operation instead of the memory cells that need to be operated.

[0045] More specifically, the available state of the redundant word line indicates whether the redundant word line has defects, the occupied state of the redundant word line indicates whether the redundant word line has replaced the operating word line, and the used state of the redundant word line indicates whether the redundant word line has normally replaced the operating word line for use.

[0046] More specifically, in the present application, the value of the first flag bit information is 1 when the corresponding redundant word line has no defects, and is 0 when the corresponding redundant word line has defects; the value of the second flag bit information is 0 when the corresponding redundant word line has replaced the operating word line, and is 1 when the corresponding redundant word line has not replaced the operating word line.

[0047] More specifically, the second input terminal of the redundancy control module 2 inputs the address of the operation word line, and the third input terminal inputs the replacement address of the selected redundant word line, so that the redundancy control module 2 can accurately make the redundant unit in the selected redundant word line replace the storage unit that needs to be operated to perform the operation.

[0048] More specifically, since a redundant word line may have defects or malfunctions, it is necessary to first determine that the selected redundant word line can normally replace the operating word line before the redundant cells in the selected redundant word line are caused to replace the memory cells in the operating word line to perform operations. Furthermore, there may be a situation where the operating word line is normal but the flash memory mistakenly causes the redundant cells to replace the memory cells in the operating word line to perform operations. Therefore, it is necessary to first determine that the selected redundant word line has replaced the operating word line before the redundant cells in the selected redundant word line are caused to replace the memory cells in the operating word line to perform operations. The first input terminal of the redundancy control module 2 of the present application is connected to the output terminal of the replacement determination module 1. Only when the selected redundant word line can normally replace the operating word line and has replaced the operating word line, the redundant cells in the selected redundant word line are caused to replace the memory cells that need to be operated to perform operations, thereby ensuring that the flash memory smoothly performs the required operations. The word line selection circuit provided in the present application can conveniently determine whether a redundant replacement has occurred based on the first flag bit and the second flag bit of the redundant word line, and can output a replacement selection signal according to the judgment result to shield the address decoding circuit of the word line where the replaced storage unit is located and configure the voltage required for operation for the selected redundant word line, thereby easily realizing word line selection, and has the advantages of simple circuit structure and control logic, rapid response and accurate judgment.

[0049] like Figure 2 As shown, in some preferred embodiments, the replacement determination module 1 includes:

[0050] The AND gate 11 has one input terminal inputting the first flag information and another input terminal inputting the inverted second flag information, and an output terminal connected to the input terminal of the redundancy control module 2 and outputting a redundancy enable signal.

[0051] Specifically, when the selected redundant word line has no defects and has replaced the operating word line, the value of the redundant enable signal output by the AND gate 11 is 1, indicating that the redundant word line has normally replaced the operating word line for use; when the selected redundant word line has defects or the operating word line has not been replaced, the value of the redundant enable signal output by the AND gate 11 is 0, indicating that the redundant word line has not normally replaced the operating word line for use. Therefore, in this embodiment, the present application provides a replacement determination module 1 including the AND gate 11, which outputs a redundant enable signal with a value of 1 only when the selected redundant word line can normally replace the operating word line and has replaced the operating word line, thereby enabling the flash memory to smoothly execute the required operations.

[0052] like Figure 3 As shown, in some preferred embodiments, the address decoding circuit of the memory array 10 includes a plurality of word line decoding circuits, each word line decoding circuit including:

[0053] Address matcher 105;

[0054] The multiplexer 101 has a first input terminal connected to the address matcher 105, a second input terminal inputting an inverted GND signal, and a control terminal inputting a replacement selection signal;

[0055] The first word line driver module 102 has a first input terminal and a second input terminal connected to the output terminal of the multiplexer 101, a third input terminal inputting an operating voltage, a fourth input terminal inputting a negative power supply voltage, and an output terminal connected to the operating word line and used to output an operating voltage or a negative power supply voltage.

[0056] Specifically, each word line decoding circuit corresponds to a word line in the memory array 10 .

[0057] More specifically, the address matcher 105 includes a multi-input NAND gate, whose input terminal inputs a plurality of judgment information, and the judgment information is used to indicate whether the corresponding address bit of the operating word line is consistent with the corresponding word line of the address matcher 105 .

[0058] More specifically, in Figure 3 In the figure, VPP is the operating voltage, VEE is the negative power supply voltage, WL is the operating word line, and Addr <3> 、Addr <2> 、Addr <1> and Addr <0> All of them are judgment information.

[0059] More specifically, in Addr <3> 、Addr <2> 、Addr <1> and Addr <0> When both are 1, that is, the address bit of the operating word line is completely consistent with the address bit of the corresponding word line of the address matcher 105, the output of the address matcher 105 is 0.

[0060] More specifically, the operating voltage is a voltage required to operate a memory cell in a word line that needs to perform an operation.

[0061] More specifically, for a word line decoding circuit whose address bits of the corresponding word line are completely consistent with the address bits of the operating word line, during the redundant replacement process, the address matcher 105 is triggered and inputs a signal with a value of 0 to the multiplexer 101. Under this premise, when the value of the replacement selection signal is 1, the multiplexer 101 outputs an inverted GND signal, and the first word line driver module 102 applies a negative power supply voltage to the operating word line; when the value of the replacement selection signal is 0, the multiplexer 101 outputs a signal with a value of 0, and the first word line driver module 102 applies the operating voltage to the operating word line.

[0062] It should be noted that, for the word line decoding circuit whose address bits of the corresponding word line are not completely consistent with the address bits of the operating word line, since the address matcher 105 is not triggered during the redundant replacement process, when the value of the replacement selection signal is 1, the multiplexer 101 outputs a signal with a value of 1, and the first word line driver module 102 applies the negative power supply voltage to the operating word line.

[0063] In this embodiment, the present application provides a multiplexer 101 and a first wordline driver module 102, which can apply a negative power supply voltage to the operating wordline when the value of the replacement selection signal is 1, causing the memory cells in the operating wordline to not perform the corresponding operation, and can apply an operating voltage to the operating wordline when the value of the replacement selection signal is 0, causing the memory cells that need to perform the operation to perform the operation normally. Preferably, a GND signal is input to the second input terminal of the multiplexer 101 through a second NOT gate 106.

[0064] In some preferred embodiments, each word line decoding circuit further includes:

[0065] The first level conversion module 103 , the output end of the multiplexer 101 is connected to the first input end and the second input end of the first word line driving module 102 through the first level conversion module 103 .

[0066] In this embodiment, the present application sets a first level conversion module 103 to convert the level of the signal output by the multiplexer 101 into a level available to the input end of the first word line driver module 102, thereby enabling the first word line driver module 102 to operate normally.

[0067] In some preferred embodiments, the first input end of the first level conversion module 103 is connected to the output end of the multiplexer 101 through the first NOT gate 104, the second input end is connected to the output end of the multiplexer 101, the first output end is connected to the first input end of the first word line driver module 102, and the second output end is connected to the second input end of the first word line driver module 102.

[0068] Specifically, the operation of the first word line driver module 102 usually requires the input of two electrical signals with opposite level states. Therefore, in this embodiment, the present application provides a first level conversion module 103 with two input terminals and two output terminals, which can input two electrical signals with opposite level states to the first word line driver module 102, thereby enabling the first word line driver module 102 to operate normally.

[0069] like Figure 4 As shown, in some preferred embodiments, the address decoding circuit of the redundant array 20 includes:

[0070] The second word line driving module 201 has a first input terminal and a second input terminal inputting a replacement selection signal, a third input terminal inputting an operating voltage, a fourth input terminal inputting a negative power supply voltage, and an output terminal connected to the selected redundant word line and used for outputting an operating voltage or a negative power supply voltage.

[0071] Specifically, in Figure 4 , RWL is the selected redundant word line.

[0072] More specifically, the second wordline driver module 201 applies an operating voltage to the selected redundant wordline when a replacement select signal with a value of 1 is input, and applies a negative power supply voltage to the selected redundant wordline when an address of the operating wordline is input. Therefore, in this embodiment, the present application provides the second wordline driver module 201, which can apply an operating voltage to the selected redundant wordline when the replacement select signal has a value of 1, causing the redundant cells in the selected redundant wordline to perform a corresponding operation, and can apply a negative power supply voltage to the selected redundant wordline when the replacement select signal has a value of 0, causing the redundant cells in the selected redundant wordline to not perform a corresponding operation. This can thereby cooperate with the multiplexer 101 and the first wordline driver module 102 to cause the redundant cells in the selected redundant wordline to perform an operation instead of the memory cells that require operation.

[0073] In some preferred embodiments, the address decoding circuit of the redundant array 20 further includes:

[0074] The second level conversion module 202 replaces the selection signal and inputs it into the first input terminal and the second input terminal of the second word line driving module 201 through the second level conversion module 202 .

[0075] In this embodiment, the present application provides a second level conversion module 202 to convert the level of the replacement selection signal into a level available to the input end of the second word line driving module 201, thereby enabling the first word line driving module 102 to operate normally.

[0076] In some preferred embodiments, the replacement selection signal is input to the first input terminal of the second level conversion module 202 through the third NOT gate 203 and the fourth NOT gate 204, and is input to the second input terminal of the second level conversion module through the third NOT gate 203. The first output terminal and the second output terminal of the second level conversion module 202 are connected to the first input terminal and the second input terminal of the second word line driver module 201.

[0077] Specifically, the operation of the second word line driver module 201 usually requires the input of two electrical signals with opposite level states. Therefore, in this embodiment, the present application provides a second level conversion module 202 with two input terminals and two output terminals, which can input two electrical signals with opposite level states to the second word line driver module 201, thereby enabling the second word line driver module 201 to operate normally.

[0078] In a second aspect, the present application provides a memory array comprising any one of the above word line selection circuits.

[0079] The memory array of the present application can conveniently determine whether a redundant replacement has occurred based on the first flag bit and the second flag bit of the redundant word line, and can output a replacement selection signal according to the judgment result to shield the address decoding circuit of the word line where the replaced memory cell is located and configure the voltage required for operation for the selected redundant word line, thereby easily realizing word line selection, and has the advantages of simple circuit structure and control logic, rapid response and accurate judgment.

[0080] In a third aspect, the present application provides a flash memory comprising any one of the above word line selection circuits or the above storage array.

[0081] The flash memory of the present application can conveniently determine whether a redundant replacement has occurred based on the first flag bit and the second flag bit of the redundant word line, and can output a replacement selection signal according to the determination result to shield the address decoding circuit of the word line where the replaced storage unit is located and configure the voltage required for operation for the selected redundant word line, thereby easily realizing word line selection, and has the advantages of simple circuit structure and control logic, rapid response and accurate judgment.

[0082] In summary, the present application provides a word line selection circuit, a memory array, and a flash memory, wherein the word line selection circuit of the present application can conveniently determine whether a redundant replacement has occurred based on the first flag bit and the second flag bit of the redundant word line, and can output a replacement selection signal according to the judgment result to shield the address decoding circuit of the word line where the replaced memory cell is located and configure the voltage required for operation for the selected redundant word line, thereby easily realizing word line selection, and having the advantages of simple circuit structure and control logic, rapid response, and accurate judgment.

[0083] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", etc., indicating directions or positional relationships, are based on the directions or positional relationships shown in the accompanying drawings and are intended only to facilitate the description of the present invention and simplify the description. They do not indicate or imply that the devices or elements referred to must have a specific direction, be constructed and operate in a specific direction, and therefore should not be understood as limiting the present invention. In the description of the present invention, "multiple" means two or more, unless otherwise clearly and specifically defined.

[0084] In the description of this utility model, it should be noted that, unless otherwise expressly specified or limited, the terms "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; mechanical connections, electrical connections, or mutual communication; direct connections or indirect connections through an intermediate medium; and internal communication between two components or interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in this utility model based on specific circumstances.

[0085] In the present invention, unless otherwise expressly specified or limited, a first feature being "above" or "below" a second feature may include the first and second features being in direct contact, or may include the first and second features being in contact not directly but through another feature between them. Moreover, a first feature being "above," "above," and "above" a second feature may include the first feature being directly above or obliquely above the second feature, or may simply mean that the first feature is higher in level than the second feature. A first feature being "below," "below," and "below" a second feature may include the first feature being directly below or obliquely below the second feature, or may simply mean that the first feature is lower in level than the second feature.

[0086] The disclosure above provides many different embodiments or examples for realizing different structures of the present invention. In order to simplify the disclosure of the present invention, the components and settings of specific examples are described above. Of course, they are merely examples and are not intended to limit the present invention. In addition, the present invention may repeat reference numbers and / or reference letters in different examples. Such repetition is for the purpose of simplicity and clarity and does not in itself indicate the relationship between the various embodiments and / or settings discussed. In addition, the present invention provides examples of various specific processes and materials, but a person of ordinary skill in the art will recognize the application of other processes and / or the use of other materials.

[0087] Throughout this specification, reference to terms such as "one embodiment," "certain embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples" means that a specific feature, structure, material, or characteristic described in conjunction with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0088] The above descriptions are only some embodiments of the present invention. For those skilled in the art, several modifications and improvements can be made without departing from the inventive concept of the present invention, and these all fall within the scope of protection of the present invention.

Claims

1. A word line selection circuit, characterized in that: The invention is applied to a flash memory, wherein the flash memory has a storage array (10) and a redundant array (20), each redundant word line in the redundant array (20) is configured with a first flag bit and a second flag bit, the first flag bit stores first flag bit information for marking an available state of the corresponding redundant word line, and the second flag bit stores second flag bit information for marking an occupied state of the corresponding redundant word line, and the word line selection circuit includes: A replacement determination module (1) has a first input terminal and a second input terminal respectively inputting first flag bit information and second flag bit information of a selected redundant word line, and an output terminal for outputting a redundant enable signal representing a usage status of the selected redundant word line; A redundancy control module (2) has a first input terminal connected to the output terminal of the replacement determination module (1), a second input terminal inputting the address of the operation word line, a third input terminal inputting the replacement address of the selected redundant word line, and an output terminal connected to the address decoding circuit of the storage array (10) and the address decoding circuit of the redundant array (20) and used for outputting a replacement selection signal.

2. The word line selection circuit according to claim 1, wherein: The replacement determination module (1) comprises: An AND gate (11) has one input terminal inputting first flag information, another input terminal inputting inverted second flag information, and an output terminal connected to the input terminal of the redundancy control module (2) and outputting a redundancy enable signal.

3. The word line selection circuit according to claim 1, wherein: The address decoding circuit of the storage array (10) includes a plurality of word line decoding circuits, each of the word line decoding circuits including: AddressMatcher(105); A multiplexer (101), wherein a first input terminal is connected to the address matcher (105), a second input terminal inputs an inverted GND signal, and a control terminal inputs a replacement selection signal; A first word line driving module (102) has a first input terminal and a second input terminal connected to the output terminal of the multiplexer (101), a third input terminal inputting an operating voltage, a fourth input terminal inputting a negative power supply voltage, and an output terminal connected to the operating word line and used for outputting the operating voltage or the negative power supply voltage.

4. The word line selection circuit according to claim 3, wherein: Each of the word line decoding circuits further comprises: A first level conversion module (103), wherein the output end of the multiplexer (101) is connected to the first input end and the second input end of the first word line driving module (102) through the first level conversion module (103).

5. The word line selection circuit according to claim 4, wherein: The first input end of the first level conversion module (103) is connected to the output end of the multiplexer (101) through a first NOT gate (104), the second input end is connected to the output end of the multiplexer (101), the first output end is connected to the first input end of the first word line driver module (102), and the second output end is connected to the second input end of the first word line driver module (102).

6. The word line selection circuit according to claim 2, wherein: The address decoding circuit of the redundant array (20) comprises: The second word line driving module (201) has a first input terminal and a second input terminal for inputting a replacement selection signal, a third input terminal for inputting an operating voltage, a fourth input terminal for inputting a negative power supply voltage, and an output terminal connected to the selected redundant word line and used for outputting an operating voltage or a negative power supply voltage.

7. The word line selection circuit according to claim 6, wherein: The address decoding circuit of the redundant array (20) further includes: A second level conversion module (202), wherein the replacement selection signal is input into the first input terminal and the second input terminal of the second word line driving module (201) through the second level conversion module (202).

8. The word line selection circuit according to claim 7, wherein: The replacement selection signal is input to the first input terminal of the second level conversion module (202) through the third NOT gate (203) and the fourth NOT gate (204), and is input to the second input terminal of the second level conversion module (202) through the third NOT gate (203). The first output terminal and the second output terminal of the second level conversion module (202) are connected to the first input terminal and the second input terminal of the second word line driving module (201).

9. A storage array, characterized in that: The method comprises the word line selection circuit according to any one of claims 1 to 8.

10. A flash memory, characterized in that: The method comprises the word line selection circuit according to any one of claims 1 to 8 or the memory array according to claim 9.

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