Watchdog circuit with mis-closing prevention function
By using an external crystal clock and multi-bit redundant logic control circuit design, the problem of watchdog circuits being susceptible to ESD events is solved, and the system is protected against accidental shutdown and the clock signal is restored to ensure stable system operation and data security.
Patent Information
- Application Number
- CN202423318637.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-31
- Publication Date
- 2025-12-09
- Estimated Expiration
- 2034-12-31
AI Technical Summary
Existing watchdog circuits are susceptible to electrostatic discharge (ESD) events, which can cause them to shut down erroneously, resulting in unstable clock signals and affecting system stability and data security.
An external crystal clock is used to control the watchdog module. Combined with a reset control circuit and a multi-bit redundant logic control circuit, filtering and a multi-bit comparator are used to ensure that the watchdog module does not shut down erroneously in the event of an ESD, thus achieving stable reset and clock signal recovery.
In the event of an ESD incident, the system can promptly resume normal operation, prevent accidental shutdown, and ensure data security and system stability.
Smart Images
Figure CN223650993U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of circuit design technology, specifically to a watchdog circuit with a function to prevent accidental shutdown. Background Technology
[0002] A watchdog timer circuit is a timer circuit used to monitor system operation and faults. It typically has one input and one output. The input is called the "feed," and the output is usually connected to a reset pin, typically a microcontroller. The watchdog's function is to periodically check the internal state of the chip. If an error occurs, it sends a restart signal to the chip. Therefore, a watchdog circuit ensures stable system operation and prevents system crashes or data loss due to software or hardware failures.
[0003] However, some unexpected events may cause the watchdog circuit to shut down unintentionally. For example, an electrostatic discharge (ESD) event could cause the watchdog circuit's enable to fail, leading to a system timeout if the expected feed signal is not received, thus triggering a reset. A system reset will interrupt the currently running tasks or state, potentially resulting in data loss or requiring unsaved work to be restarted.
[0004] Furthermore, currently, watchdog circuits commonly use PLL circuits to generate the input clock. These PLL circuits control the frequency and phase of the internal oscillation signal through an external reference signal, generating and maintaining a clock signal synchronized with the reference signal. However, when subjected to events such as ESD (Electronic Stress Discharge), the phase deviation and oscillation frequency of the PLL circuit become unstable, causing the output clock signal to fail to recover to normal in a timely manner, thus affecting the normal operation of the watchdog circuit.
[0005] Therefore, a watchdog circuit with anti-false shutdown function and a stable clock signal needs to be designed. Utility Model Content
[0006] This utility model provides a watchdog circuit with anti-accidental shutdown function, which is mainly used to solve the problems of existing watchdog circuits being prone to accidental shutdown and clock signal not being able to recover in time when subjected to event impacts, thereby achieving the effect of anti-accidental shutdown function and stable clock signal.
[0007] This utility model achieves the above objectives through the following technical solutions:
[0008] A watchdog circuit with anti-accidental shutdown function includes a reset control circuit, a logic control circuit, a multi-bit comparator circuit, and a watchdog module. The reset control circuit includes two-stage DFF flip-flops, both of which have their inputs connected to a high level. Their clock signals are both connected to an external crystal oscillator clock signal, and their reset terminals are both input to an asynchronous reset signal. When the asynchronous reset signal is removed, an asynchronous reset synchronization release signal is output to the reset terminal of the watchdog module after adding one clock cycle. The logic control circuit inputs a multi-bit setpoint configured by the system and, under the control of the crystal oscillator clock signal, outputs the multi-bit setpoint to the first input terminal of the multi-bit comparator circuit. The second input terminal of the multi-bit comparator circuit inputs a multi-bit constant, which is used to compare the multi-bit setpoint with the multi-bit constant, and outputs a comparison signal to the enable terminal of the watchdog module. The watchdog module's input terminal receives a periodic feed signal from the system master control module, which triggers an interrupt signal or a reset signal when the watchdog timer times out or the asynchronous reset synchronization release signal is input, causing the system to perform the corresponding interrupt or reset operation.
[0009] A further embodiment is that the reset control circuit also includes a glitch filtering circuit, which includes several D flip-flops connected in series. The clock signal terminals of the several D flip-flops are all input with a glitch filtering clock signal. The asynchronous reset signal is output after being delayed by the several D flip-flops, thereby eliminating jitter interference.
[0010] A further approach is to establish that the delay time of the asynchronous reset signal is related to the number of D flip-flops as follows:
[0011] t=N*T
[0012] Where N is the number of D flip-flops, and T is the period of the glitch-filtering clock signal.
[0013] A further approach is to use a multi-bit register in the logic control circuit. The multi-bit set value is input to the input terminal of the multi-bit register, and the crystal oscillator clock signal is input to its clock signal terminal. This is used to latch the multi-bit set value into the multi-bit register according to the rising or falling edge of the crystal oscillator clock signal.
[0014] A further embodiment is that the multi-bit comparator circuit selects a numerical comparator with a corresponding number of bits according to the number of bits of the multi-bit set value. The numerical comparator is used to compare the multi-bit set value with the multi-bit parameter step by step from high to low bits, and is provided with a cascaded signal terminal for inputting control signals, for outputting the comparison signal according to the comparison result and the control signal.
[0015] A further solution is that when the multi-bit setting value is equal to the value of the multi-bit parameter, the multi-bit comparator circuit outputs a comparison signal of 0, thereby disabling the watchdog module's enable.
[0016] A further approach is to use a 16-bit constant with multiple bit flips as the multi-bit parameter to improve the watchdog module's ability to prevent accidental shutdown when subjected to impact events.
[0017] A further embodiment is that the watchdog module includes a WDT control register and a watchdog counter. The WDT control register is used to set the timeout period and enable the watchdog. The watchdog counter is used to calculate the time from when the watchdog timer was last cleared to the present.
[0018] Therefore, this utility model has the following beneficial effects:
[0019] 1. The input clock path of the watchdog module of this utility model comes directly from an external crystal oscillator clock. Compared with the traditional solution that uses a clock generated by a PLL, it is not affected by internal oscillation during ESD events and can be controlled by an external crystal oscillator clock to enable the system to recover to normal in a timely manner.
[0020] 2. This utility model achieves reset control through a reset control circuit set outside the watchdog module. Compared with the traditional digital logic reset control scheme inside the watchdog module, it is not affected by internal oscillations during ESD events, thus enabling timely recovery to normal.
[0021] 3. This utility model realizes the watchdog enable control through logic control circuit. By adopting multi-bit redundant control, the watchdog module can only be disabled when multiple bits simultaneously meet the set multi-bit parameters. In the event of ESD and other events, it is almost impossible for multiple control bits to change to multi-bit parameter values at the same time. Therefore, there is no problem of the watchdog being turned off by mistake.
[0022] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments. Attached Figure Description
[0023] Figure 1 This is a schematic diagram of a watchdog circuit with anti-accidental shutdown function according to an embodiment of the present invention.
[0024] Figure 2 This is a circuit diagram of the burr filtering circuit of this utility model embodiment.
[0025] Figure 3 This is a schematic diagram of a multi-bit register according to an embodiment of the present invention.
[0026] Figure 4This is a schematic diagram of a numerical comparator implemented in this utility model. Detailed Implementation
[0027] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this utility model. All other embodiments obtained by those skilled in the art based on the described embodiments of this utility model without creative effort are within the scope of protection of this utility model.
[0028] An embodiment of a watchdog circuit with anti-accidental shutdown function
[0029] See Figure 1 This utility model relates to a watchdog circuit with anti-accidental shutdown function, comprising a reset control circuit 10, a logic control circuit 20, a multi-bit comparator circuit 30, and a watchdog module 40. The reset control circuit 10 includes two stages of DFF flip-flops, both with high-level inputs and external crystal clock signals connected to their clock terminals. Both stages have an asynchronous reset signal Rst_n input at their reset terminals. When the asynchronous reset signal Rst_n is removed, an asynchronous reset synchronization departure signal Rst_n_sync is output to the reset terminal of the watchdog module 40 after an additional clock cycle. The logic control circuit 20 is used to input system configuration... A multi-bit setpoint is generated and output to the first input terminal of the multi-bit comparator circuit 30 under the control of the crystal oscillator clock signal. A multi-bit constant is input to the second input terminal of the multi-bit comparator circuit 30 for comparing the multi-bit setpoint with the multi-bit constant, and a comparison signal is output to the enable terminal of the watchdog module 40. The input terminal of the watchdog module 40 is periodically fed a watchdog signal by the system main control module, which is used to trigger the interrupt signal WDG_INT or the reset signal WDG_WRST to make the system perform the corresponding interrupt or reset operation when the watchdog timer times out or the asynchronous reset synchronous withdrawal signal Rst_n_sync is input.
[0030] Specifically, in this embodiment, when an asynchronous reset is performed, the asynchronous reset signal Rst_n flips from 1 to 0. At this time, the two DFF flip-flops are immediately reset, meaning the output asynchronous reset synchronization release signal Rst_n_sync is immediately pulled down to a low level to reset the system. It can be seen that the reset action is not controlled by the crystal oscillator clock signal at this time, thus enabling asynchronous reset. When the reset is released, the asynchronous reset signal Rst_n flips from 0 to 1. At this time, the reset of the two DFF flip-flops is canceled, and they begin normal operation. However, the input high-level signal takes two cycles to reach the output. The asynchronous reset signal Rst_n, with a two-cycle delay, is sufficient to eliminate the metastability caused by the reset and ensure that the reset signal perceived by the system is on the edge of the crystal oscillator clock signal. Therefore, the reset release behavior is controlled by the crystal oscillator clock signal, enabling synchronous release.
[0031] Specifically, in this embodiment, the input clock path of the watchdog module 40 comes directly from an external crystal oscillator clock. In the event of an ESD, it is not affected by the internal oscillation and the system can be restored to normal in a timely manner by controlling the external crystal oscillator clock.
[0032] In this embodiment, the reset control circuit 10 further includes a glitch filtering circuit, which includes a plurality of D flip-flops connected in series. The clock signal terminals of the plurality of D flip-flops are all input to the glitch filtering clock signal. The asynchronous reset signal Rst_n is output after being delayed by the plurality of D flip-flops, thereby eliminating jitter interference.
[0033] Specifically, in this embodiment, jitter when inputting the asynchronous reset signal Rst_n may cause the chip to perform multiple reset actions, introducing uncertainty and error into the system. By eliminating the jitter interference of the asynchronous reset signal Rst_n, the reliability and stability of the asynchronous reset signal Rst_n are guaranteed.
[0034] In this embodiment, the relationship between the delay time of the asynchronous reset signal Rst_n and the number of the D flip-flops is as follows:
[0035] t=N*T
[0036] Where N is the number of D flip-flops, and T is the period of the glitch-filtering clock signal.
[0037] Specifically, the glitch filtering circuit in this embodiment is only an example and not the only filtering method. For example, glitch can be filtered out by using a delay device. The delay time of the delay device is set to achieve the filtering time. If glitch below 100ns needs to be filtered out, a 100ns delay device is introduced, which can completely eliminate jitter interference.
[0038] In this embodiment, the logic control circuit 20 uses a multi-bit register. The multi-bit setting value is input at the input terminal of the multi-bit register, and the crystal oscillator clock signal is input at its clock signal terminal. The multi-bit setting value is latched in the multi-bit register according to the rising or falling edge of the crystal oscillator clock signal.
[0039] In this embodiment, the multi-bit comparator circuit 30 selects a numerical comparator with a corresponding number of bits according to the number of bits of the multi-bit set value. The numerical comparator is used to compare the multi-bit set value with the multi-bit parameter step by step from high to low bits, and is provided with a cascaded signal terminal for inputting control signals, for outputting the comparison signal according to the comparison result and the control signal.
[0040] In this embodiment, when the multi-bit setting value is equal to the value of the multi-bit parameter, the multi-bit comparator circuit 30 outputs a comparison signal of 0, thereby disabling the watchdog module 40.
[0041] In this embodiment, the multi-bit parameter is a 16-bit bit constant with multiple bit flips to improve the watchdog module 40's ability to prevent accidental shutdown when subjected to an impact event.
[0042] Specifically, in this embodiment, the configuration value cfg of the multi-bit register is set to specify the 16-bit constant rnd = 16'B0101001011001101. At this time, the watchdog module 40 can only be turned off when the multi-bit register value is configured as cfg=16'B 0101001011001101.
[0043] Specifically, this embodiment employs multi-bit redundancy control, ensuring that the watchdog module 40 can only disable the watchdog when multiple bits simultaneously meet the set multi-bit parameters. In the event of ESD or other shocks, it is almost impossible for multiple control bits to simultaneously change to multi-bit parameter values, thus eliminating the problem of the watchdog being accidentally turned off.
[0044] In this embodiment, the watchdog module 40 includes a WDT control register and a watchdog counter. The WDT control register is used to set the timeout period and enable the watchdog. The watchdog counter is used to calculate the time from when the watchdog timer was last cleared to the present.
[0045] The above embodiments are merely preferred embodiments of this utility model and should not be construed as limiting the scope of protection of this utility model. Any non-substantial changes and substitutions made by those skilled in the art based on this utility model shall fall within the scope of protection claimed by this utility model.
Claims
1. A watchdog circuit with anti-accidental shutdown function, characterized in that, include: The system comprises a reset control circuit, a logic control circuit, a multi-bit comparator circuit, and a watchdog module. The reset control circuit includes two DFF flip-flops, both with high-level inputs and clock signals connected to an external crystal oscillator. Both flip-flops input an asynchronous reset signal, which, when the asynchronous reset signal is removed, adds one clock cycle and outputs an asynchronous reset synchronization release signal to the watchdog module's reset terminal. The logic control circuit inputs a multi-bit setpoint configured by the system and, under the control of the crystal oscillator clock signal, outputs the multi-bit setpoint to the first input of the multi-bit comparator circuit. The second input of the multi-bit comparator circuit inputs a multi-bit constant, which is used to compare the multi-bit setpoint with the multi-bit constant, and outputs a comparison signal to the watchdog module's enable terminal. The watchdog module's input is periodically fed a "feed" signal by the system's main control module, which triggers an interrupt or reset signal when the watchdog timer times out or the asynchronous reset synchronization release signal is input, causing the system to perform the corresponding interrupt or reset operation.
2. The watchdog circuit with anti-accidental shutdown function according to claim 1, characterized in that: The reset control circuit also includes a glitch filtering circuit, which includes several D flip-flops connected in series. The clock signal terminals of the several D flip-flops are all input with a glitch filtering clock signal. The asynchronous reset signal is output after being delayed by the several D flip-flops to eliminate jitter interference.
3. The watchdog circuit with anti-accidental shutdown function according to claim 2, characterized in that: The relationship between the delay time of the asynchronous reset signal and the number of the D flip-flops is as follows: t=N*T Where N is the number of D flip-flops, and T is the period of the glitch-filtering clock signal.
4. The watchdog circuit with anti-accidental shutdown function according to claim 1, characterized in that: The logic control circuit employs a multi-bit register. The multi-bit set value is input to the input terminal of the multi-bit register, and the crystal clock signal is input to its clock signal terminal. The multi-bit set value is latched into the multi-bit register according to the rising or falling edge of the crystal clock signal.
5. The watchdog circuit with anti-accidental shutdown function according to claim 1, characterized in that: The multi-bit comparator circuit selects a numerical comparator with a corresponding number of bits according to the number of bits of the multi-bit set value. The numerical comparator is used to compare the multi-bit set value with the multi-bit parameter step by step from high to low bits, and is provided with a cascaded signal terminal for inputting control signals, for outputting the comparison signal according to the comparison result and the control signal.
6. The watchdog circuit with anti-accidental shutdown function according to claim 5, characterized in that: When the multi-bit setting value is equal to the value of the multi-bit parameter, the multi-bit comparator circuit outputs a comparison signal of 0, thereby disabling the watchdog module's enable.
7. The watchdog circuit with anti-accidental shutdown function according to claim 6, characterized in that: The multi-bit parameter is a 16-bit bit constant with multiple bit flips, which improves the watchdog module's ability to prevent accidental shutdown when subjected to impact events.
8. The watchdog circuit with anti-accidental shutdown function according to claim 1, characterized in that: The watchdog module includes a WDT control register and a watchdog counter. The WDT control register is used to set the timeout period and enable the watchdog. The watchdog counter is used to calculate the time from when the watchdog timer was last cleared to the present.