Logic circuit for increasing common-mode transient immunity of OOK modulation and demodulation digital isolator

Abstract

The utility model discloses a logic circuit for increasing the common-mode transient immunity of an OOK modulation and demodulation digital isolator, the logic circuit comprises a transmitting terminal TX and a receiving terminal RX, the receiving terminal RX comprises a cross-coupled common-gate pre-drive amplifier composed of a plurality of transistors, the common-gate pre-drive amplifier amplifies signals sent by the transmitting terminal TX, and the common-gate pre-drive amplifier is used for amplifying the signals sent by the receiving terminal TX; the envelope comparator is used for comparing the output voltage of the common-gate pre-drive amplifier and outputting a corresponding high-level signal or a low-level signal; the forward common-mode voltage change rate detection circuit is a transistor MN5, the transistor MN5 is connected with the common-gate pre-drive amplifier, and the transistor MN5 is switched on or switched off by an output voltage signal of the transmitting end TX; the negative common-mode voltage change rate detection circuit is a transistor MP5, the transistor MP5 is connected with the common-gate pre-drive amplifier, and the transistor MP5 is switched on or switched off by an output voltage signal of the common-gate pre-drive amplifier; and the logic circuit is used for comparing an output signal of the output end of the envelope comparator, an output signal of the positive common-mode voltage change rate detection circuit and an output signal of the negative common-mode voltage change rate detection circuit, and outputting a logic processing result.

Description

Technical Field

[0001] This application belongs to the field of digital isolators for OOK modulation and demodulation, specifically referring to a logic circuit that increases the common-mode transient immunity of digital isolators for OOK modulation and demodulation. Background Technology

[0002] On-Off Keying (OOK) modulation and demodulation is a simple binary modulation method that controls the presence or absence of a signal by switching a circuit on and off, thereby enabling data transmission. OOK modulation and demodulation technology is mainly used in wireless communication systems. Its basic principle is to transmit information by changing the presence or absence of a signal. When the transmitting end needs to send a bit, it turns the signal on for a period of time; when it does not need to send a bit, the signal remains off. Because capacitively isolated digital isolators have two completely independent grounds, the voltage difference between these two grounds changes transiently in practical applications. If the transient rate of change of the voltage difference between the two grounds exceeds a certain limit, it will disrupt the normal transmission of digital signals. This limit is the common-mode transient immunity of the digital isolator, which is an important performance parameter of digital isolator products.

[0003] Common-mode transient immunity indicates the ability of an isolation circuit to suppress high-speed transient signals from passing through the isolation layer and disrupting the output state. It also reflects the sensitivity of the isolation circuit to fast transient signal interference. A higher common-mode transient immunity rating means that the isolation circuit or device can guarantee that the output (OUT) does not malfunction when a common-mode voltage with a higher rise or fall rate impacts the isolation barrier under its defined test conditions. Utility Model Content

[0004] To overcome the shortcomings of the prior art, this application provides a logic circuit that increases the common-mode transient immunity of a digital isolator with OOK modulation and demodulation, which can improve the common-mode transient immunity of the logic circuit.

[0005] This invention provides a logic circuit for increasing the common-mode transient immunity of a digital isolator with OOK modulation and demodulation. The logic circuit includes a transmitter TX and a receiver RX, which are connected to each other. The transmitter TX sends a voltage signal to the receiver RX.

[0006] The receiving end RX includes:

[0007] A cross-coupled common-gate pre-driver amplifier composed of multiple transistors amplifies the signal transmitted by the transmitter TX. The common-gate pre-driver amplifier includes transistors MN1, MN2, MN3, and MN4. Transistors MN1 and MN4 share a common gate, and transistors MN2 and MN3 share a common gate. Transistors MN1, MN2, MN3, and MN4 are all connected to the input power supply VDD2 of the receiver RX and the ground terminal GND2 of the receiver RX.

[0008] An envelope comparator is provided, the input of which is connected to the output of the common-gate pre-driver amplifier. The envelope comparator compares the output voltage of the common-gate pre-driver amplifier and outputs a corresponding high-level signal or low-level signal.

[0009] A forward common-mode voltage change rate detection circuit, wherein the forward common-mode voltage change rate detection circuit is a transistor MN5, the transistor MN5 is connected to the common-gate pre-drive amplifier, and the transistor MN5 is turned on or off by the output voltage signal of the transmitter TX;

[0010] A negative common-mode voltage change rate detection circuit, wherein the negative common-mode voltage change rate detection circuit is a transistor MP5, the transistor MP5 is connected to the common-gate pre-drive amplifier, and the transistor MP5 is turned on or off by the output voltage signal of the common-gate pre-drive amplifier;

[0011] A logic circuit is provided, the input of which is connected to the output of the envelope comparator, the positive common-mode voltage change rate detection circuit, and the negative common-mode voltage change rate detection circuit. The logic circuit compares the output signal of the envelope comparator, the output signal of the positive common-mode voltage change rate detection circuit, and the output signal of the negative common-mode voltage change rate detection circuit, and outputs the logic processing result.

[0012] According to the logic circuit provided in this application for increasing the common-mode transient immunity of a digital isolator for OOK modulation and demodulation, the body transistor MN1, the transistor MN2, the transistor MN3, the transistor MN4 and the transistor MN5 are all NMOS transistors, and the transistor MP5 is a PMOS transistor.

[0013] According to the logic circuit provided in this application for increasing the common-mode transient immunity of the digital isolator for OOK modulation and demodulation, the input voltage VDD1 of the transmitting end TX is different from the ground end GND1, and the input voltage VDD2 of the receiving end RX is different from the ground end GND2.

[0014] According to the logic circuit provided in this application for increasing the common-mode transient immunity of the digital isolator for OOK modulation and demodulation, a first high-voltage capacitor C1 and a second high-voltage capacitor C2 are also connected between the transmitter TX and the receiver RX.

[0015] Wherein, one end of the first high-voltage capacitor C1 is connected to the first output terminal of the transmitter TX, and the other end of the first high-voltage capacitor C1 is connected to the first input terminal of the receiver RX, and inputs the voltage signal INP_RX; one end of the second high-voltage capacitor C2 is connected to the second output terminal of the transmitter TX, and the other end of the second high-voltage capacitor C2 is connected to the second input terminal of the receiver RX, and inputs the voltage signal INN_RX.

[0016] According to the logic circuit provided in this application for increasing the common-mode transient immunity of the digital isolator for OOK modulation and demodulation, the common-gate pre-drive amplifier further includes transistor MP1, transistor MP2, first resistor R1 and second resistor R2.

[0017] The gates of transistors MN2 and MN3 are both connected to the input power supply VDD2 of the receiver RX. The source of transistor MN3 is connected to the source of transistor MN1, and the drain of transistor MN3 is connected to the gate of transistor MN3.

[0018] The source of transistor MN2 is connected to the source of transistor MN4, and the drain of transistor MN2 is connected to the drain of transistor MP2.

[0019] The gates of both transistors MN1 and MN4 are connected to the input power supply VDD2 of the receiver RX, and the drain of transistor MN1 is connected to the drain of transistor MP1.

[0020] The drain of transistor MN4 is connected to the gate of transistor MN4;

[0021] The gate of transistor MP1 is connected to the drain of transistor MP1, and the source of transistor MP1 is connected to the input power supply VDD2 of the receiving terminal RX.

[0022] The gate of transistor MP2 is connected to the drain of transistor MP2, and the source of transistor MP2 is connected to the input power supply VDD2 of the receiver RX.

[0023] One end of the first resistor R1 is connected to the electrical connection node between the source of transistor MN3 and the source of transistor MN1, and the other end of the first resistor R1 is connected to the ground terminal GND2 of the receiving terminal RX; the electrical connection node between the source of transistor MN3 and the source of transistor MN1 also receives the input voltage signal INP_RX.

[0024] One end of the second resistor R2 is connected to the electrical node connecting the source of transistor MN2 and the source of transistor MN4, and the other end of the second resistor R2 is connected to the ground terminal GND2 of the receiving terminal RX; the electrical node connecting the source of transistor MN2 and the source of transistor MN4 also receives the input voltage signal INN_RX;

[0025] The electrical connection between the drain of transistor MN1 and the drain of transistor MP1 is the first output terminal of the common gate pre-driver amplifier, and the electrical connection between the drain of transistor MN2 and the drain of transistor MP2 is the second output terminal of the common gate pre-driver amplifier.

[0026] According to the logic circuit provided in this application for increasing the common-mode transient immunity of a digital isolator for OOK modulation and demodulation, transistors MP1 and MP2 are PMOS transistors.

[0027] According to the logic circuit provided in this application for increasing the common-mode transient immunity of a digital isolator for OOK modulation and demodulation, the first input terminal of the envelope comparator is connected to the first output terminal of the common-gate pre-driver amplifier, and the second input terminal of the envelope comparator is connected to the second output terminal of the common-gate pre-driver amplifier.

[0028] According to the logic circuit provided in this application for increasing the common-mode transient immunity of a digital isolator with OOK modulation and demodulation, the gate of transistor MN5 is connected to the input voltage signal INN_RX, the source of transistor MN5 is connected to the ground terminal GND2 of the receiver RX, and the drain of transistor MN5 is connected to the input power supply VDD2 of the receiver RX.

[0029] According to the logic circuit provided in this application for increasing the common-mode transient immunity of a digital isolator for OOK modulation and demodulation, the gate of transistor MP5 is connected to the first output terminal of the common-gate pre-driver amplifier, the source of transistor MP5 is connected to the input power supply VDD2 of the receiver RX, and the drain of transistor MP5 is connected to the ground terminal GND2 of the receiver RX.

[0030] According to the logic circuit provided in this application for increasing the common-mode transient immunity of a digital isolator for OOK modulation and demodulation, the first input terminal of the logic circuit is connected to the source of the transistor MP5, the second input terminal of the logic circuit is connected to the output terminal of the envelope comparator, and the third input terminal of the logic circuit is connected to the source of the transistor MN5.

[0031] The output signal of the logic circuit is VOUT.

[0032] The beneficial effects of this utility model are as follows: This application provides a logic circuit for increasing the common-mode transient immunity of a digital isolator with OOK modulation and demodulation. Based on the characteristics of the digital isolator with OOK modulation and demodulation, a set of positive common-mode voltage change rate detection circuits and negative common-mode voltage change rate detection circuits are added. When the change rate of common-mode voltage or common-mode current in the logic circuit exceeds a set threshold, the positive or negative common-mode voltage change rate detection circuit is turned on, thereby discharging the common-mode current and reducing the impact on the input signal of the amplifier at the receiving end RX, or reducing the impact on the de-driver at the transmitting end TX, thus ensuring normal signal transmission. Moreover, since the response speed of the positive and negative common-mode voltage change rate detection circuits is much higher than that of the modulation and demodulation path, during the change of common-mode voltage or common-mode current in the circuit, the output signal of the positive or negative common-mode voltage change rate detection circuit takes effect first, thereby preventing the output of the logic circuit from changing and maintaining the output (VOUT) of the logic circuit unchanged, effectively improving the common-mode transient immunity of the digital isolator. Attached Figure Description

[0033] The technical solution and other beneficial effects of this application will become apparent from the following detailed description of specific embodiments in conjunction with the accompanying drawings.

[0034] Figure 1 A schematic diagram of the logic circuit for increasing the common-mode transient immunity of the digital isolator for OOK modulation and demodulation provided in this application. Detailed Implementation

[0035] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0036] In the description of this application, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0037] The following disclosure provides many different embodiments or examples for implementing different structures of this application. To simplify the disclosure, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, various specific examples of processes and materials are provided in this application, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0038] The present invention will now be further described in conjunction with the accompanying drawings and specific embodiments.

[0039] On-Off Keying (OOK) modulation and demodulation is a simple binary modulation method that controls the presence or absence of a signal by switching a circuit on and off, thereby enabling data transmission. OOK modulation and demodulation technology is mainly used in wireless communication systems, and its basic principle is to transmit information by changing the presence or absence of a signal. Based on the characteristics of OOK modulation and demodulation, this application provides a logic circuit to increase the common-mode transient immunity of a digital isolator in OOK modulation and demodulation.

[0040] Figure 1 A schematic diagram of the logic circuit for increasing the common-mode transient immunity of the digital isolator for OOK modulation and demodulation provided in this application.

[0041] like Figure 1As shown, the logic circuit provided in this application mainly includes a transmitter TX and a receiver RX. The transmitter TX and the receiver RX are connected, and the transmitter TX sends a voltage signal to the receiver RX. The receiver RX processes the voltage signal sent by the transmitter TX and outputs a corresponding output (VOUT).

[0042] The receiving end RX includes:

[0043] A cross-coupled common-gate pre-driver amplifier composed of multiple transistors amplifies the signal transmitted by the transmitter TX. The common-gate pre-driver amplifier includes transistors MN1, MN2, MN3, and MN4. Transistors MN1 and MN4 share a common gate, and transistors MN2 and MN3 share a common gate. Transistors MN1, MN2, MN3, and MN4 are all connected to the input power supply VDD2 of the receiver RX and the ground terminal GND2 of the receiver RX.

[0044] An envelope comparator COMP is connected to the output of the common-gate pre-driver amplifier. The envelope comparator COMP compares the output voltage of the common-gate pre-driver amplifier and outputs a corresponding high-level signal or low-level signal.

[0045] A forward common-mode voltage change rate detection circuit, wherein the forward common-mode voltage change rate detection circuit is a transistor MN5, the transistor MN5 is connected to the common-gate pre-drive amplifier, and the transistor MN5 is turned on or off by the output voltage signal of the transmitter TX.

[0046] A negative common-mode voltage change rate detection circuit, wherein the negative common-mode voltage change rate detection circuit is a transistor MP5, the transistor MP5 is connected to the common-gate pre-drive amplifier, and the transistor MP5 is turned on or off by the output voltage signal of the common-gate pre-drive amplifier.

[0047] The logic circuit has its input terminals connected to the output terminals of the envelope comparator COMP, the positive common-mode voltage change rate detection circuit, and the negative common-mode voltage change rate detection circuit. The logic circuit compares the output signals of the envelope comparator COMP, the positive common-mode voltage change rate detection circuit, and the negative common-mode voltage change rate detection circuit, and outputs the logic processing result.

[0048] The input voltage VDD1 of the transmitting end TX is different from that of the ground terminal GND1, and the input voltage VDD2 of the receiving end RX is different from that of the ground terminal GND2. That is, the transmitting end TX belongs to the voltage domain of VDD1 to GND1, while the receiving end RX belongs to the voltage domain of VDD2 to GND2.

[0049] When a high common-mode voltage change rate or common-mode current change rate occurs in the logic circuit, a positive common-mode voltage change occurs when the voltage of the ground terminal GND1 of the transmitting end TX suddenly increases relative to the voltage of the ground terminal GND2 of the receiving end RX; or a negative common-mode voltage change occurs when the voltage of the ground terminal GND1 of the transmitting end TX suddenly decreases relative to the voltage of the ground terminal GND2 of the receiving end RX. Since the response speed of the positive common-mode voltage change rate detection circuit and the negative common-mode voltage change rate detection circuit is much higher than the response speed of the modulation and demodulation main path, the output signal of the positive common-mode voltage change rate detection circuit or the negative common-mode voltage change rate detection circuit takes effect first, thereby preventing the output of the logic circuit from changing and maintaining the output (VOUT) of the logic circuit unchanged.

[0050] Specifically, in this embodiment, the body tube MN1, the transistor MN2, the transistor MN3, the transistor MN4 and the transistor MN5 are all NMOS transistors, and the transistor MP5 is a PMOS transistor.

[0051] like Figure 1 As shown, a first high-voltage capacitor C1 and a second high-voltage capacitor C2 are connected between the transmitting end TX and the receiving end RX. One end of the first high-voltage capacitor C1 is connected to the first output terminal of the transmitting end TX, and the other end is connected to the first input terminal of the receiving end RX, inputting a voltage signal INP_RX. One end of the second high-voltage capacitor C2 is connected to the second output terminal of the transmitting end TX, and the other end is connected to the second input terminal of the receiving end RX, inputting a voltage signal INN_RX. The voltage difference between the ground terminal GND1 of the transmitting end TX and the ground terminal GND2 of the receiving end RX is mainly applied across the first high-voltage capacitor C1 and the second high-voltage capacitor C2.

[0052] In this embodiment, as Figure 1 As shown, the common-gate pre-drive amplifier also includes transistor MP1, transistor MP2, a first resistor R1, and a second resistor R2.

[0053] Specifically, the gates of transistors MN2 and MN3 are both connected to the input power supply VDD2 of the receiver RX, the source of transistor MN3 is connected to the source of transistor MN1, and the drain of transistor MN3 is connected to the gate of transistor MN3.

[0054] The source of transistor MN2 is connected to the source of transistor MN4, and the drain of transistor MN2 is connected to the drain of transistor MP2.

[0055] The gates of both transistors MN1 and MN4 are connected to the input power supply VDD2 of the receiver RX, and the drain of transistor MN1 is connected to the drain of transistor MP1.

[0056] The drain of transistor MN4 is connected to the gate of transistor MN4.

[0057] The gate of transistor MP1 is connected to the drain of transistor MP1, and the source of transistor MP1 is connected to the input power supply VDD2 of the receiver RX.

[0058] The gate of transistor MP2 is connected to the drain of transistor MP2, and the source of transistor MP2 is connected to the input power supply VDD2 of the receiver RX.

[0059] One end of the first resistor R1 is connected to the electrical connection node between the source of transistor MN3 and the source of transistor MN1, and the other end of the first resistor R1 is connected to the ground terminal GND2 of the receiving terminal RX; the electrical connection node between the source of transistor MN3 and the source of transistor MN1 also receives the input voltage signal INP_RX.

[0060] One end of the second resistor R2 is connected to the electrical node connecting the source of transistor MN2 and the source of transistor MN4, and the other end of the second resistor R2 is connected to the ground terminal GND2 of the receiving terminal RX; the electrical node connecting the source of transistor MN2 and the source of transistor MN4 also receives the input voltage signal INN_RX.

[0061] The electrical connection between the drain of transistor MN1 and the drain of transistor MP1 is the first output terminal of the common gate pre-driver amplifier, and the electrical connection between the drain of transistor MN2 and the drain of transistor MP2 is the second output terminal of the common gate pre-driver amplifier.

[0062] In this configuration, transistors MP1 and MP2 are both PMOS transistors. The current flowing through the gate of transistor MN2 and the gate of transistor MN3 together form current source I1, which controls the on / off state of transistors MN2 and MN3. The current flowing through the gate of transistor MN1 and the gate of transistor MN4 together form current source I2, which controls the on / off state of transistors MN1 and MN4.

[0063] The first input terminal of the envelope comparator COMP is connected to the first output terminal of the common gate pre-driver amplifier, and the second input terminal of the envelope comparator COMP is connected to the second output terminal of the common gate pre-driver amplifier.

[0064] In the forward common-mode voltage change rate detection circuit, the gate of transistor MN5 is connected to the input voltage signal INN_RX, the source of transistor MN5 is connected to the ground terminal GND2 of the receiving terminal RX, and the drain of transistor MN5 is connected to the input power supply VDD2 of the receiving terminal RX.

[0065] In the negative common-mode voltage change rate detection circuit, the gate of transistor MP5 is connected to the first output terminal of the common-gate pre-drive amplifier, the source of transistor MP5 is connected to the input power supply VDD2 of the receiver RX, and the drain of transistor MP5 is connected to the ground terminal GND2 of the receiver RX.

[0066] The current flowing through the source of transistor MP5 forms current source I3, and the current flowing through the source of transistor MN5 forms current source I4. Current source I3 and transistor MP5 together constitute the negative common-mode voltage change rate detection circuit, and current source I4 and transistor MN5 together constitute the positive common-mode voltage change rate detection circuit.

[0067] The first input terminal A1 of the logic circuit is connected to the source of the transistor MP5, the second input terminal A2 of the logic circuit is connected to the output terminal of the envelope comparator COMPCOMP, and the third input terminal A3 of the logic circuit is connected to the source of the transistor MN5; the output signal of the logic circuit is VOUT.

[0068] The working principle of the logic circuit provided in this embodiment is as follows:

[0069] When there is no high common-mode voltage or common-mode current change rate in the circuit, i.e., when the logic circuit of the OOK modulation and demodulation digital isolator is working normally, when the receiver RX receives the carrier signal transmitted by the transmitter TX, the logic circuit, through the processing of the common-gate pre-driver amplifier and the envelope comparator COMP, outputs a high level, thereby controlling the logic circuit to output a high level. Conversely, when the receiver RX does not receive the carrier signal transmitted by the transmitter TX, the logic circuit, through the processing of the common-gate pre-driver amplifier and the envelope comparator COMP, outputs a low level, thereby controlling the logic circuit to output a low level.

[0070] When there is no high common-mode voltage change rate or common-mode current change rate in the circuit, i.e., when the logic circuit of the OOK modulation and demodulation digital isolator is working normally, transistor MP5 is in the off state. The negative common-mode voltage change rate detection circuit, composed of current source I3 and transistor MP5, outputs a high level and does not affect the normal modulation and demodulation function of the logic circuit. When transistor MN5 is in the off state, the positive common-mode voltage change rate detection circuit, composed of current source I4 and transistor MN5, outputs a low level and does not affect the normal modulation and demodulation function of the logic circuit.

[0071] When the voltage at ground terminal GND1 of the transmitting end TX suddenly increases relative to the voltage at ground terminal GND2 of the receiving end RX, i.e., a positive common-mode voltage change occurs, the common-mode current flows from the transmitting end TX into the receiving end RX through the first high-voltage capacitor C1 and the second high-voltage capacitor C2. Consequently, the voltages of the input voltage signals INP_RX and INN_RX increase simultaneously. The common-mode current in the logic circuit increases with the increase of the common-mode change rate. The larger the common-mode current, the higher the voltages of the input voltage signals INP_RX and INN_RX. When the voltages of the input voltage signals INP_RX and INN_RX rise to a certain level, i.e., when the common-mode change rate exceeds a preset value, the transistor MN5 is turned on. The outputs of the current source I4 and the transistor MN5 change from low level to high level. This high-level signal controls the logic circuit output to maintain its original output state, thereby preventing the logic circuit output from changing due to the change in the main path output of the envelope comparator COMP, thus keeping the logic circuit output (VOUT) unchanged.

[0072] When there is no positive common-mode voltage change, or the positive common-mode voltage change is small and does not exceed the preset value, the transistor MN5 is in the off state, and the positive common-mode voltage change rate detection circuit will not affect the normal modulation and demodulation function of the logic circuit.

[0073] During the positive common-mode voltage change, the output of the negative common-mode voltage change rate detection circuit, which is composed of the current source I3 and the transistor MP5, is unaffected, and the negative common-mode voltage change rate detection circuit will not affect the normal modulation and demodulation function of the logic circuit.

[0074] When the voltage at ground terminal GND1 of the transmitting end TX suddenly decreases relative to the voltage at ground terminal GND2 of the receiving end RX, i.e., a negative common-mode voltage change occurs, the common-mode current flows from the receiving end RX into the transmitting end TX through the first high-voltage capacitor C1 and the second high-voltage capacitor C2. At this time, the common-mode current is provided by the ground terminal GND2 of the receiving end RX through the first resistor R1 and the second resistor R2. Consequently, the voltages of the input voltage signals INP_RX and INN_RX decrease simultaneously and fall below the ground terminal GND2 of the receiving end RX; the output voltage of the common-gate pre-driver amplifier also decreases. The common-mode current in the logic circuit increases with the increase of the common-mode change rate. The larger the common-mode current, the lower the voltages of the input voltage signals INP_RX and INN_RX, and the lower the output voltage of the common-gate pre-driver amplifier. When the voltages of the input voltage signals INP_RX and INN_RX decrease to a certain level, i.e., when the common-mode change rate exceeds a preset value, the transistor MP5 is turned on. The outputs of the current source I3 and the transistor MP5 change from high level to low level. This low-level signal controls the logic circuit output to maintain its original output state, thereby preventing the logic circuit output from changing due to the change in the main path output of the envelope comparator COMPCOMP, thus keeping the logic circuit output (VOUT) unchanged.

[0075] When there is no negative common-mode voltage change, or the negative common-mode voltage change is small and does not exceed the preset value, the transistor MP5 is in the off state, and the negative common-mode voltage change rate detection circuit will not affect the normal modulation and demodulation function of the logic circuit.

[0076] During the negative common-mode voltage change, the output of the positive common-mode voltage change rate detection circuit, which is composed of the current source I4 and the transistor MN5, is unaffected, and the positive common-mode voltage change rate detection circuit will not affect the normal modulation and demodulation function of the logic circuit.

[0077] This application provides a logic circuit for increasing the common-mode transient immunity of a digital isolator with OOK modulation and demodulation. Based on the characteristics of the OOK modulation and demodulation digital isolator, a set of positive and negative common-mode voltage change rate detection circuits are added. When the rate of change of the common-mode voltage or common-mode current in the logic circuit exceeds a set threshold, the positive or negative common-mode voltage change rate detection circuit is turned on, thereby discharging the common-mode current and reducing the impact on the input signal of the amplifier at the receiving end RX, or reducing the impact on the de-driver at the transmitting end TX, thus ensuring normal signal transmission. Moreover, since the response speed of the positive and negative common-mode voltage change rate detection circuits is much higher than that of the modulation and demodulation path, during the change of the common-mode voltage or common-mode current in the circuit, the output signal of the positive or negative common-mode voltage change rate detection circuit takes effect first, thereby preventing the output of the logic circuit from changing and maintaining the output (VOUT) of the logic circuit unchanged, effectively improving the common-mode transient immunity of the digital isolator.

[0078] Although preferred embodiments of the present invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the present invention. Finally, it should be noted that in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or terminal device that includes said element.

[0079] The above provides a detailed description of a logic circuit for increasing the common-mode transient immunity of a digital isolator for OOK modulation and demodulation, as provided in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A logic circuit for increasing the common-mode transient immunity of a digital isolator for OOK modulation and demodulation, characterized in that, The logic circuit includes a transmitter TX and a receiver RX, the transmitter TX and the receiver RX are connected, and the transmitter TX sends a voltage signal to the receiver RX. The receiving end RX includes: A cross-coupled common-gate pre-driver amplifier composed of multiple transistors amplifies the signal transmitted by the transmitter TX. The common-gate pre-driver amplifier includes transistors MN1, MN2, MN3, and MN4. Transistors MN1 and MN4 share a common gate, and transistors MN2 and MN3 share a common gate. Transistors MN1, MN2, MN3, and MN4 are all connected to the input power supply VDD2 of the receiver RX and the ground terminal GND2 of the receiver RX. An envelope comparator is provided, the input of which is connected to the output of the common-gate pre-driver amplifier. The envelope comparator compares the output voltage of the common-gate pre-driver amplifier and outputs a corresponding high-level signal or low-level signal. A forward common-mode voltage change rate detection circuit, wherein the forward common-mode voltage change rate detection circuit is a transistor MN5, the transistor MN5 is connected to the common-gate pre-drive amplifier, and the transistor MN5 is turned on or off by the output voltage signal of the transmitter TX; A negative common-mode voltage change rate detection circuit, wherein the negative common-mode voltage change rate detection circuit is a transistor MP5, the transistor MP5 is connected to the common-gate pre-drive amplifier, and the transistor MP5 is turned on or off by the output voltage signal of the common-gate pre-drive amplifier; A logic circuit is provided, the input of which is connected to the output of the envelope comparator, the positive common-mode voltage change rate detection circuit, and the negative common-mode voltage change rate detection circuit. The logic circuit compares the output signal of the envelope comparator, the output signal of the positive common-mode voltage change rate detection circuit, and the output signal of the negative common-mode voltage change rate detection circuit, and outputs the logic processing result.

2. The logic circuit for increasing the common-mode transient immunity of a digital isolator for OOK modulation and demodulation according to claim 1, characterized in that, The body tube MN1, the transistor MN2, the transistor MN3, the transistor MN4 and the transistor MN5 are all NMOS transistors, and the transistor MP5 is a PMOS transistor.

3. The logic circuit for increasing the common-mode transient immunity of a digital isolator for OOK modulation and demodulation according to claim 1, characterized in that, The input voltage VDD1 of the transmitting end TX is different from the ground terminal GND1, and the input voltage VDD2 of the receiving end RX is different from the ground terminal GND2.

4. The logic circuit for increasing the common-mode transient immunity of a digital isolator for OOK modulation and demodulation according to claim 1, characterized in that, A first high-voltage capacitor C1 and a second high-voltage capacitor C2 are also connected between the transmitter TX and the receiver RX. Wherein, one end of the first high-voltage capacitor C1 is connected to the first output terminal of the transmitter TX, and the other end of the first high-voltage capacitor C1 is connected to the first input terminal of the receiver RX, and inputs the voltage signal INP_RX; one end of the second high-voltage capacitor C2 is connected to the second output terminal of the transmitter TX, and the other end of the second high-voltage capacitor C2 is connected to the second input terminal of the receiver RX, and inputs the voltage signal INN_RX.

5. The logic circuit for increasing the common-mode transient immunity of a digital isolator for OOK modulation and demodulation according to claim 4, characterized in that, The common-gate pre-drive amplifier also includes transistor MP1, transistor MP2, first resistor R1, and second resistor R2; The gates of transistors MN2 and MN3 are both connected to the input power supply VDD2 of the receiver RX. The source of transistor MN3 is connected to the source of transistor MN1, and the drain of transistor MN3 is connected to the gate of transistor MN3. The source of transistor MN2 is connected to the source of transistor MN4, and the drain of transistor MN2 is connected to the drain of transistor MP2. The gates of both transistors MN1 and MN4 are connected to the input power supply VDD2 of the receiver RX, and the drain of transistor MN1 is connected to the drain of transistor MP1. The drain of transistor MN4 is connected to the gate of transistor MN4; The gate of transistor MP1 is connected to the drain of transistor MP1, and the source of transistor MP1 is connected to the input power supply VDD2 of the receiving terminal RX. The gate of transistor MP2 is connected to the drain of transistor MP2, and the source of transistor MP2 is connected to the input power supply VDD2 of the receiver RX. One end of the first resistor R1 is connected to the electrical connection node between the source of transistor MN3 and the source of transistor MN1, and the other end of the first resistor R1 is connected to the ground terminal GND2 of the receiving terminal RX; the electrical connection node between the source of transistor MN3 and the source of transistor MN1 also receives the input voltage signal INP_RX. One end of the second resistor R2 is connected to the electrical node connecting the source of transistor MN2 and the source of transistor MN4, and the other end of the second resistor R2 is connected to the ground terminal GND2 of the receiving terminal RX; the electrical node connecting the source of transistor MN2 and the source of transistor MN4 also receives the input voltage signal INN_RX; The electrical connection point between the drain of transistor MN1 and the drain of transistor MP1 is the first output terminal of the common gate pre-driver amplifier, and the electrical connection point between the drain of transistor MN2 and the drain of transistor MP2 is the second output terminal of the common gate pre-driver amplifier.

6. The logic circuit for increasing the common-mode transient immunity of a digital isolator for OOK modulation and demodulation according to claim 5, characterized in that, The transistors MP1 and MP2 are PMOS transistors.

7. The logic circuit for increasing the common-mode transient immunity of a digital isolator for OOK modulation and demodulation according to claim 5, characterized in that, The first input terminal of the envelope comparator is connected to the first output terminal of the common gate pre-driver amplifier, and the second input terminal of the envelope comparator is connected to the second output terminal of the common gate pre-driver amplifier.

8. The logic circuit for increasing the common-mode transient immunity of a digital isolator for OOK modulation and demodulation according to claim 7, characterized in that, The gate of transistor MN5 is connected to the input voltage signal INN_RX, the source of transistor MN5 is connected to the ground terminal GND2 of the receiving terminal RX, and the drain of transistor MN5 is connected to the input power supply VDD2 of the receiving terminal RX.

9. The logic circuit for increasing the common-mode transient immunity of a digital isolator with OOK modulation and demodulation according to claim 8, characterized in that, The gate of transistor MP5 is connected to the first output terminal of the common gate pre-driver amplifier, the source of transistor MP5 is connected to the input power supply VDD2 of the receiver RX, and the drain of transistor MP5 is connected to the ground terminal GND2 of the receiver RX.

10. The logic circuit for increasing the common-mode transient immunity of a digital isolator for OOK modulation and demodulation according to claim 9, characterized in that, The first input terminal of the logic circuit is connected to the source of the transistor MP5, the second input terminal of the logic circuit is connected to the output terminal of the envelope comparator, and the third input terminal of the logic circuit is connected to the source of the transistor MN5. The output signal of the logic circuit is VOUT.

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