SOC internal power-on and power-off detection circuit
By designing an internal power-on/off detection circuit for the SOC and utilizing a voltage divider module and a hysteresis comparator structure, the problem of inaccurate detection in existing SOC power-on detection circuits under slow power-on and low voltage environments is solved. Stable PMU status detection and ripple immunity are achieved, making it suitable for SOC detection under various voltage conditions.
Patent Information
- Application Number
- CN202423269525.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-30
- Publication Date
- 2026-01-02
- Estimated Expiration
- 2034-12-30
AI Technical Summary
Existing SOC power-on detection circuits cannot generate a reasonable signal during slow power-on, cannot be used in low-voltage environments, and cannot be set to a fixed voltage value for detection. They cannot meet the power-on requirements of on-chip LDO detection in SOCs, and also have ripple and glitches issues.
A power-on/off detection circuit for an internal SOC was designed, including a voltage divider module and a detection module. Utilizing a hysteresis comparator structure composed of a MUX selector, comparator, and inverter, the circuit achieves accurate detection of the PMU's startup and shutdown states through multiple resistor voltage dividers and selectable threshold detection, exhibiting anti-ripple and anti-interference capabilities.
It achieves selectivity and stability of detection threshold, can accurately detect the start-up and shutdown status of PMU under various voltage environments, has anti-ripple and anti-interference characteristics, and is suitable for SOC detection under different voltage conditions.
Smart Images
Figure CN223756808U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to the field of integrated circuit especially relates to a SOC internal power -on and power -off detection circuit. BACKGROUND
[0002] In system on chip (System on Chip, abbreviated as SOC) design, a definite PMU start completion signal is the important guarantee of system stability. Because it ensures that SOC starts to work under the premise of obtaining stable power supply, thereby avoid the system collapse or data loss caused by unstable power supply and other problems. The common power-on detection circuit structure is as follows:
[0003] Figure 1 The common first power-on detection circuit structure is shown in the figure, Figure 1 Vp point is connected to the detected power supply through pull-up resistor R1, and s_porb signal is 0 before Vp reaches threshold voltage. After Vp reaches threshold voltage, the inverter formed by PM1 and NM1 and the BUFFER composed of inverter I1 can output s_porb=1, indicating that PMU starts to complete. However, Figure 1 The structure shown in the figure cannot generate reasonable signals when power is slowly turned on.
[0004] Figure 2 The common second power-on detection circuit structure is shown in the figure, Figure 2 Vp reaches threshold voltage, s_porb signal is 0. Under the condition that VDD gradually increases, PM4 is turned on, VP is charged to VDD, so that s_porb=1 is output, and the chip works normally, thereby achieving the function of power-on detection. However, due to the series use of MOS diodes, the minimum starting voltage of VDD is an integer multiple of the threshold value of MOS devices, which cannot be used in low-voltage environment. At the same time, the above structure cannot set a fixed voltage value for detection, and cannot set different power-on and power-off threshold values. It does not meet the use requirements of SOC on-chip detection LDO power-on.
[0005] Figure 3 The common third power-on detection circuit structure is shown in the figure, Figure 3 V_DET is the detected voltage, a suitable voltage V_comp is divided through the voltage division of resistor R1 and resistor R2, and compared with reference voltage Vref by comparator. When the voltage V_comp is greater than Vref, the output S_PORB=1; when the voltage V_comp is less than Vref, the output S_PORB=0. However, this structure has a problem. Because the voltage output by PMU basically exists ripple, it will fluctuate around dc value or appear burr, at this time, the output of S_PORB will fluctuate, and the state of the detected voltage at this time cannot be correctly presented. Utility model content
[0006] The technical problem to be solved by the embodiment of the utility model lies in providing a SOC internal power-on and power-off detection circuit to accurately obtain PMU starting state and closing state.
[0007] In order to solve the above technical problem, the embodiment of the utility model provides a SOC internal power-on and power-off detection circuit, which comprises a voltage division module and a detection module, the detection module comprises a MUX selector, a comparator and four inverters, the voltage division module is composed of three or more than three resistors connected in series, the voltage division module is connected with a detected voltage end, the MUX selector comprises two inputs and two selection ends, the two inputs of the MUX selector are connected with two resistors respectively, the output end of the MUX selector is connected with the positive electrode of the input end of the comparator, the output end of the comparator outputs signals through four inverters connected in series, and the two selection ends of the MUX selector are connected with two ends of the third inverter along the transmission direction of the output signal of the comparator.
[0008] Further, the MUX selector is composed of a pmos switch, an nmos switch or a cmos switch.
[0009] Further, the comparator is composed of a mos tube or a bjt tube.
[0010] The utility model has the advantages that, compared with the prior power-on detection circuit, the utility model has the selectivity of detection threshold value, and has certain anti-ripple and anti-interference characteristics. BRIEF DESCRIPTION OF DRAWINGS
[0011] Figure 1 It is the structure diagram of the prior first power-on detection circuit.
[0012] Figure 2 It is the structure diagram of the prior second power-on detection circuit.
[0013] Figure 3 It is the structure diagram of the prior third power-on detection circuit.
[0014] Figure 4 It is the structure block diagram of the SOC internal power-on and power-off detection circuit of the embodiment of the utility model. DETAILED DESCRIPTION
[0015] It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict, and the present application will be further described in detail in combination with the drawings and specific embodiments.
[0016] In the embodiments of the present application, if there is a directional indication (such as up, down, left, right, front, back, etc.), it is only used to explain the relative position relationship, movement condition, etc. between components in a certain specific posture (as shown in the drawings), and if the specific posture changes, the directional indication will also change accordingly.
[0017] In addition, in the present application, the description of "first", "second", etc. is only for the purpose of description, and cannot be understood as indicating or implying the relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features limited by "first" and "second" can explicitly or implicitly include at least one of the features.
[0018] Please refer to Figure 4 The SOC internal power-on and power-off detection circuit in the embodiments of the present application comprises a voltage dividing module and a detection module.
[0019] The detection module comprises a MUX (Multiplexer) selector, a comparator and four inverters. The detection module of the present application is similar to a hysteresis comparator. The voltage dividing module is composed of three or more resistors connected in series. The voltage dividing module is connected to the detected voltage end. The MUX selector comprises two inputs and two selection ends. The two inputs of the MUX selector are connected to the two resistors in turn. For example, the voltage dividing module is composed of resistors R1, R2 and R3 connected in series. The resistor R1 is connected to the detected voltage V_DET. The two inputs of the MUX selector are connected between the resistor R1 and the resistor R2 and between the resistor R2 and the resistor R3 respectively.
[0020] The output end of the MUX selector is connected to the positive input end of the comparator. The output end of the comparator outputs a signal through four inverters connected in series. The two selection ends of the MUX selector are connected to the two ends of the third inverter along the transmission direction of the comparator output signal. That is, the first inverter of the four inverters connected in series is connected to the output end of the comparator, and the fourth inverter outputs the PMU start completion signal.
[0021] The present application can perform power-on and power-off detection with selectable threshold value for the internal voltage of the SOC, so as to accurately obtain the PMU start state and the off state.
[0022] As an implementation manner, the MUX selector is composed of a pmos switch, an nmos switch or a cmos switch, or other elements or modules with gating function.
[0023] As an implementation, the comparator is composed of mos tubes or bjt (bipolar transistor) tubes.
[0024] The working principle of the utility model is: the utility model divides the voltage into VTH_R of first power-on and VTH_F of first power-off through multiple resistors for the detected voltage V_DET.The circuit of the utility model starts to work, S_B=1, IN_B is gated.When V_DET continuously increases, VTH_R>Vref, the comparator output S_PORB=1.At power-off, S_A=1 at this time, IN_A is gated, first detect VTH_F, when VTH_F<Vref, the comparator output S_PORB=0.Because the utility model adopts hysteresis comparator structure, the ripple of PMU output voltage and burr will not affect S_PORB.
[0025] Although the embodiments of the utility model have been shown and described, it can be understood by those skilled in the art that various changes, modifications, replacements and variations can be made to these embodiments without departing from the principles and spirits of the utility model, the scope of the utility model is defined by the appended claims and their equivalent scope.
Claims
1. A SOC internal power-on / off detection circuit, comprising a voltage division module and a detection module, characterized in that, The detection module comprises a MUX selector, a comparator and four inverters, the voltage dividing module is composed of three or more resistors connected in series, the voltage dividing module is connected to the voltage terminal to be detected, the MUX selector comprises two inputs and two selection terminals, the two inputs of the MUX selector are connected to the two resistors respectively, the output terminal of the MUX selector is connected to the positive input terminal of the comparator, the output terminal of the comparator is connected to the input terminal of the four inverters connected in series, and the two selection terminals of the MUX selector are connected to the two terminals of the third inverter along the transmission direction of the output signal of the comparator.
2. The SOC internal power-up / down detection circuit of claim 1, wherein, The MUX selector is composed of a pmos switch, an nmos switch or a cmos switch.
3. The SOC internal power-up / down detection circuit of claim 1, wherein, The comparator is composed of a mos tube or a bjt tube.