Dynamic signal acquisition circuit based on FPGA kernel

Abstract

The utility model discloses a dynamic signal acquisition circuit based on an FPGA kernel, and belongs to the technical field of signal acquisition. Comprising a field programmable gate array (FPGA) which is connected with a first synchronous dynamic random access memory (SDRAM), an ARM processor and a plurality of analog-to-digital converters (ADC). The input end of the analog-to-digital converter ADC is connected with the output end of the signal conditioning board; the input end of the signal conditioning board is connected with the dynamic acceleration sensor, the strain sensor and the displacement sensor and receives signals output by the sensors; the ARM processor is connected with a nonvolatile storage device FLASH and a second synchronous dynamic random access memory SDRAM; and the field programmable gate array FPGA is used for filtering and converting the acquired data and transmitting the data to the ARM processor. According to the utility model, synchronous acquisition, synchronous processing, synchronous analysis and synchronous transmission can be realized; the signal conditioning circuit adopts a modular design and can be compatible with sensors of various dynamic signals.

Description

TECHNICAL FIELD

[0001] The utility model relates to signal acquisition technical field especially, it relates to a dynamic signal acquisition circuit based on FPGA kernel. BACKGROUND

[0002] In the industrial equipment state monitoring, mechanical vibration analysis and engineering test field, the dynamic signal acquisition system bears the core task of multi-source heterogeneous sensor data synchronous acquisition. The traditional dynamic signal acquisition device adopts MCU or DSP architecture, and its sequential execution characteristic leads to timing deviation when collecting multi-channel signals, especially in the system above 32 channels, the synchronization error between channels can reach microseconds, which seriously affects the analysis accuracy of phase-sensitive signals. SUMMARY

[0003] The utility model discloses a dynamic signal acquisition circuit based on FPGA kernel, which overcomes the defects of the prior art.

[0004] The utility model discloses a dynamic signal acquisition circuit based on FPGA kernel, which overcomes the defects of the prior art.

[0005] Preferably, the field programmable gate array FPGA is further connected with a gigabit network port and a first RS485 interface.

[0006] Preferably, the ARM processor is further connected with a state light, a hundred megabit network port and a second RS485 interface.

[0007] Preferably, the power module comprises a switch, the input end of the switch is connected with a 9-36V external power supply, and the output end of the switch is connected with a power supply conditioning circuit.

[0008] The utility model has the advantages of:

[0009] 1) synchronous acquisition, synchronous processing, synchronous analysis and synchronous transmission can be realized; the signal conditioning circuit adopts modular design and can be compatible with various dynamic signal sensors. BRIEF DESCRIPTION OF DRAWINGS

[0010] Figure 1 The principle block diagram of the clock signal circuit of the dynamic signal acquisition circuit based on the FPGA kernel is shown in Fig. 5.

[0011] Figure 2 The principle block diagram of the clock signal circuit of the dynamic signal acquisition circuit based on the FPGA kernel is shown in Fig. 5.

[0012] Figure 3 The principle block diagram of the clock signal circuit of the dynamic signal acquisition circuit based on the FPGA kernel is shown in Fig. 5.

[0013] Figure 4 The principle block diagram of the clock signal circuit of the dynamic signal acquisition circuit based on the FPGA kernel is shown in Fig. 5. DETAILED DESCRIPTION

[0014] The technical scheme of the present application will be described clearly and completely in combination with the embodiments. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all the other embodiments obtained by the person skilled in the art without creative labor are within the protection scope of the present application.

[0015] Referring to Figures 1-4 The present application provides a technical scheme: a dynamic signal acquisition circuit based on FPGA kernel, comprising a field programmable gate array FPGA, the field programmable gate array FPGA connects a first synchronous dynamic random access memory SDRAM, an ARM processor and a plurality of analog-to-digital converters ADC; the input end of the analog-to-digital converter ADC is connected with the output end of the signal conditioning board; the input end of the signal conditioning board is connected with a dynamic acceleration sensor, a strain sensor and a displacement sensor and receives the output signals thereof; the ARM processor is connected with a nonvolatile storage device FLASH and a second synchronous dynamic random access memory SDRAM; the field programmable gate array FPGA is used for filtering and converting the collected data and transmitting to the ARM processor.

[0016] In this embodiment, the dynamic signal acquisition circuit based on FPGA kernel design mainly collects the sensing devices such as dynamic acceleration sensor, strain sensor and displacement sensor installed on the highway bridge, and uploads the collected data to the information system through network communication. The whole system measures, collects, processes and analyzes the parameters such as the environment of the bridge, the load action, the dynamic structure response and the characteristics of the bridge, and performs early warning and evaluation on the state of the bridge. After the multi-channel sensor signals enter the acquisition circuit, they are pre-processed by the signal conditioning circuit, and then the data is collected by 8-channel synchronous ADC. The data collected by ADC is given to FPGA parallel port, and FPGA processes the collected data by filtering and conversion. FPGA converts the data into UDP protocol through logic programming and transmits the data to the host computer through gigabit network. At the same time, the data can also be transmitted to the ARM end through the FSMC interface. The data obtained by the ARM end is the processed data, and the ARM can directly perform subsequent characteristic value, communication and control work.

[0017] The dynamic signal acquisition circuit based on FPGA kernel design can realize synchronous acquisition, synchronous processing, synchronous analysis and synchronous transmission of multi-channel sensors, and can also perform edge computing on the ARM end to process the characteristic values and upload them to the platform. This circuit can realize local real-time display, processing, analysis and evaluation of the bridge site without the help of local industrial computer to obtain data processing, and remote platform characteristic value early warning.

[0018] When starting, FPGA generates a soft reset signal through systemreset. The soft reset signal first passes through PLL_rst phase-locked loop logic, which generates a PLL reset signal to PLL_ADC and PLL. When all the phase-locked loop output clocks are latched, sys_ctrl outputs the soft reset signal of the system. The soft reset signal of the system resets the ad7770 logic, adc_Control logic and RTL8211_UDP logic for unified configuration. After reset, wait for the start collection instruction. When starting collection, ad7770 logic drives the external analog-to-digital conversion chip for collection. The data after collection is sent to RTL8211_UDP logic through adc_Control logic to complete data transmission.

[0019] FPGA function module description:

[0020] systemreset: system reset logic, generates system reset signal.

[0021] PLL_rst: phase-locked loop reset logic, generates a reset signal that can reset the system clock phase-locked loop.

[0022] PLL_ADC: system phase-locked loop logic, generates the clock signal required for the operation of the analog-to-digital converter.

[0023] PLL: system phase-locked loop logic, generates the clock signal required for the system to run.

[0024] sys_ctrl: according to the system reset logic and the latch signal of the phase-locked loop reset logic, generates the reset signal of the internal function logic gate.

[0025] ad7770: external analog-to-digital converter driving logic.

[0026] adc_Control: controls the external analog-to-digital converter to complete data acquisition.

[0027] RTL8211_UDP: gigabit Ethernet drive logic.

[0028] clk_sel: sampling rate switching logic, generates the corresponding main clock signal according to different sampling rate requirements.

[0029] In some embodiments, the field programmable gate array (FPGA) is further connected with a gigabit network port and a first RS485 interface.

[0030] In some embodiments, the ARM processor is further connected with a status light, a 100M network port and a second RS485 interface.

[0031] In some embodiments, a power module is further included, and the power module includes a switch, an input end of the switch is connected with a 9-36V external power supply, and an output end of the switch is connected with a power supply conditioning circuit.

[0032] The above only describes preferred embodiments of the present application, and it should be understood that the present application is not limited to the forms disclosed herein, and should not be considered as excluding other embodiments, but can be used in various other combinations, modifications and environments, and can be modified within the scope of the concepts described herein, through the above teachings or related technical or knowledge. Any modification and change made by the person skilled in the art without departing from the spirit and scope of the present application shall be within the protection scope of the claims of the present application.

Claims

1. A dynamic signal acquisition circuit based on FPGA kernel, characterized in that: The application relates to a signal acquisition and processing system, which comprises a field programmable gate array (FPGA) connected with a first synchronous dynamic random access memory (SDRAM), an ARM processor and a plurality of analog-to-digital converters (ADCs); the input end of the ADC is connected with the output end of a signal conditioning board; the input end of the signal conditioning board is connected with a dynamic acceleration sensor, a strain sensor and a displacement sensor and receives the output signals of the sensors; the ARM processor is connected with a nonvolatile storage device (FLASH) and a second SDRAM; the FPGA is used for filtering and converting the collected data and transmitting the data to the ARM processor. The FPGA is further connected with a gigabit network port and a first RS485 interface.

2. The dynamic signal acquisition circuit based on FPGA kernel according to claim 1, characterized in that: The ARM processor is further connected with a state light, a 100M network port and a second RS485 interface.

3. The dynamic signal acquisition circuit based on FPGA kernel according to claim 1, characterized in that: The application further comprises a power module, which comprises a switch; the input end of the switch is connected with a 9-36V external power supply; and the output end of the switch is connected with a power conditioning circuit.

4. The dynamic signal acquisition circuit based on FPGA kernel according to any one of claims 1-3, characterized in that: ​

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