High-voltage MOS terminal protection structure with high avalanche tolerance

Abstract

The utility model relates to the technical field of transistor protection, and discloses a high-voltage MOS terminal protection structure with high avalanche tolerance, which comprises a high-voltage MOS device, the high-voltage MOS device is provided with a cellular area and a terminal protection area, the cellular area is also provided with a shield grid used for reducing on-resistance and increasing breakdown voltage, and the terminal protection area is provided with a terminal protection area. The longitudinal section of the shield grid is arranged in a trapezoid shape, the field limiting rings with the gradually-decreased spacing can widen the width of a depletion region, improve the transverse voltage endurance capability of the MOS device, reduce the peak value of an edge electric field, transfer the peak point of an electric field through a slope field plate and eliminate a grid angle distortion electric field, and the shield grid reconstructs the electric field to be distributed in a trapezoid shape and optimizes a longitudinal electric field. Therefore, the breakdown voltage of the MOS device is improved, and the avalanche trigger threshold is remarkably improved; through the design of the drain buffer layer, a large amount of high-energy carrier kinetic energy can be absorbed, the channel thermal shock can be reduced, the local temperature peak value can be reduced, the two metal layers are utilized to assist heat dissipation, double-path heat conduction is realized, and the avalanche tolerance is improved.

Description

Technical Field

[0001] This utility model relates to the field of transistor protection technology, specifically a high-voltage MOS termination protection structure with high avalanche tolerance. Background Technology

[0002] Transistor protection refers to a systematic protection measure that uses a three-pronged approach of structural design, circuit protection, and packaging technology to prevent permanent damage to transistors under abnormal operating conditions. This prevents transistors from being damaged under abnormal operating conditions such as overvoltage, overcurrent, and overheating, ensuring their reliability and lifespan, improving the stability and safety of electronic systems, and avoiding system failures caused by transistor failure.

[0003] A search revealed that patent application number CN201420726171.8 discloses a trench-type MOS device and its terminal protection structure that effectively improves the electric field line distribution in the terminal protection zone and enhances the performance and reliability of the terminal protection structure. The device includes a semiconductor substrate, an active region disposed in the middle, and a terminal protection zone disposed on the periphery. At least one voltage divider ring and a stop ring located outside the voltage divider ring are disposed in the terminal protection zone. The voltage divider ring includes an annular voltage divider trench. A second conductivity type deep well region is disposed on the upper part of the first conductivity type epitaxial layer. The voltage divider trench penetrates the second conductivity type deep well region from top to bottom, and the bottom of the trench is located in the first conductivity type epitaxial layer. The voltage divider trench is filled with an insulating medium of the same material as the insulating dielectric layer.

[0004] Traditional transistor protection structures rely on a single field limiting ring or right-angle field plate, which leads to electric field concentration at the edge curvature and a large electric field strength at the bottom of the gate oxide, making it prone to ionization distortion. Furthermore, a single field limiting ring cannot regulate the lateral potential, resulting in deviations in current distribution. The lack of a drain buffer layer prevents effective absorption of avalanche carrier kinetic energy, resulting in low avalanche tolerance and causing local overheating of the MOS device, which in turn leads to breakdown. Therefore, we need to propose a high-voltage MOS termination protection structure with high avalanche tolerance. Utility Model Content

[0005] The purpose of this invention is to provide a high-voltage MOS terminal protection structure with high avalanche tolerance. Through the design of a composite field limiting ring, a ramp field plate, and a trapezoidal shielding gate, the field limiting rings with decreasing spacing widen the depletion region, improving the lateral withstand voltage of the MOS device and reducing the peak value of the edge electric field. The ramp field plate transfers the peak electric field point, eliminating the gate corner distortion electric field. Furthermore, the shielding gate reconstructs the electric field into a trapezoidal distribution, optimizing the longitudinal electric field, thereby increasing the breakdown voltage of the MOS device and significantly improving the avalanche trigger threshold. The drain buffer layer design absorbs a large amount of high-energy carrier kinetic energy, reducing channel thermal shock and local temperature peaks. The two metal layers assist in heat dissipation, achieving dual-path heat conduction and improving avalanche tolerance, thus solving the problems mentioned in the background art.

[0006] To achieve the above objectives, this utility model provides the following technical solution: a high avalanche tolerance high-voltage MOS termination protection structure, comprising a high-voltage MOS device, wherein a cell region and a termination protection zone are provided on the high-voltage MOS device, an insulating dielectric layer is provided on the surface of the high-voltage MOS device, a first metal layer is deposited on the cell region, a second metal layer is deposited on the termination protection zone, a shielding gate for reducing on-resistance and increasing breakdown voltage is also provided in the cell region, the longitudinal cross-section of the shielding gate is trapezoidal, a composite field limiting ring for widening the depletion region, dispersing the electric field intensity, and avoiding edge concentrated breakdown is provided at the edge of the termination protection zone, and a sloping field plate covered with a sloped oxide layer is also provided at the edge of the termination protection zone.

[0007] Preferably, the bottom of the high-voltage MOS device is provided with N - Drift region and N + Substrate region, the N - Drift region and N + A drain buffer layer with a thickness of 2-5 μm is disposed between the substrate regions.

[0008] Preferably, the surface of the upper cell region of the high-voltage MOS device is provided with an ohmic contact hole that penetrates the insulating dielectric layer, and the first metal layer is located inside the ohmic contact hole.

[0009] Preferably, the high-voltage MOS device has an ohmic contact hole two that penetrates the insulating dielectric layer on the surface of the terminal protection zone, and the second metal layer is located inside the ohmic contact hole two.

[0010] Preferably, the surface of the cell region of the high-voltage MOS device is further provided with cell trenches, and the shielding gate is located inside the cell trenches.

[0011] Preferably, the surface of the high-voltage MOS device is further provided with a plurality of single-cell trenches, the interior of which is equipped with conductive polycrystalline silicon and an oxide layer.

[0012] Preferably, a protective trench is provided at the edge of the terminal protection zone, and the composite field limiting ring is located inside the protective trench.

[0013] Preferably, the composite field limiting ring comprises multiple field limiting rings arranged in a straight line, and the spacing between two adjacent field limiting rings decreases in order to avoid electric field distortion.

[0014] Compared with the prior art, the beneficial effects of this utility model are:

[0015] 1. This utility model, through the design of composite field limiting rings, ramp field plates, and trapezoidal shielding gates, can widen the depletion region by using field limiting rings with decreasing spacing, thereby improving the lateral breakdown voltage capability of MOS devices and reducing the peak value of the edge electric field. The ramp field plate transfers the peak point of the electric field, eliminates the gate corner distortion electric field, and reconstructs the electric field into a trapezoidal distribution through the shielding gate, optimizing the longitudinal electric field, thereby improving the breakdown voltage of MOS devices and significantly increasing the avalanche trigger threshold.

[0016] 2. This utility model, through the design of the drain buffer layer, can absorb a large amount of high-energy carrier kinetic energy, reduce channel thermal shock, reduce local temperature peaks, and utilize two metal layers to assist in heat dissipation, thereby achieving dual-path heat conduction and improving avalanche tolerance. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the structure of this utility model;

[0018] Figure 2 This is an exploded view of the present invention.

[0019] In the diagram: 1. High-voltage MOS device; 2. N - Drift zone; 3, N + 4. Substrate region; 5. Drain buffer layer; 6. First metal layer; 7. Ohmic contact hole one; 8. Second metal layer; 9. Ohmic contact hole two; 10. Shielding gate; 11. Cell trench; 22. Composite field limiting ring; 33. Protective trench; 44. Conductive polysilicon; 55. Single cell trench; 66. Oxide layer; 77. Sloping field plate; 88. Insulating dielectric layer. Detailed Implementation

[0020] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0021] Please see Figure 1-2This utility model provides a technical solution: a high avalanche tolerance high voltage MOS termination protection structure, including a high voltage MOS device 1, a cell region and a termination protection zone are provided on the high voltage MOS device 1, an insulating dielectric layer 11 is provided on the surface of the high voltage MOS device 1, a first metal layer 5 is deposited in the cell region, a second metal layer 6 is deposited in the termination protection zone, and a shielding gate 7 is also provided in the cell region to reduce the on-resistance and increase the breakdown voltage. The longitudinal cross section of the shielding gate 7 is trapezoidal. Through the structural design of the shielding gate 7 being wider at the top and narrower at the bottom, the longitudinal electric field distribution can be optimized, the electric field strength at the bottom of the gate oxide can be weakened, and the two metal layers are directly connected to the source of the MOS device, shielding the high electric field coupling between the gate and the drain.

[0022] A composite field limiting ring 8 is provided at the edge of the terminal protection zone to widen the depletion zone, disperse the electric field intensity, and avoid edge-concentrated breakdown. A sloping field plate 10 covered with an inclined oxide layer is also provided at the edge of the terminal protection zone.

[0023] The composite field limiting ring 8 includes multiple field limiting rings arranged in a straight line. To avoid electric field distortion, the spacing between two adjacent field limiting rings decreases.

[0024] Taking four field limiting rings in the composite field limiting ring 8 as an example, the spacing between the first and second field limiting rings is 10μm, the spacing between the second and third field limiting rings is 7μm, and the spacing between the third and fourth field limiting rings is 5μm. This can widen the depletion region and simultaneously improve the lateral breakdown voltage capability of the MOS device.

[0025] The inclined angle of the ramp field plate 10 is 55°, which can push the electric field peak from the gate corner to the end of the ramp field plate 10. The ramp field plate 10 can suppress the electric field concentration in the terminal protection zone of the MOS device.

[0026] The bottom of high-voltage MOS device 1 is provided with N - Drift zones 2 and N + Substrate region 3, N - Drift zones 2 and N + A drain buffer layer 4 is disposed between the substrate regions 3. The thickness of the drain buffer layer 4 is 2-5 μm, and the doping concentration of the drain buffer layer 4 is 1×10⁻⁶. 17 cm -3 It absorbs the kinetic energy of avalanche carriers.

[0027] The combined effect of the slope field plate 10 and the drain buffer layer 4 significantly improves the avalanche failure energy threshold.

[0028] An ohmic contact hole 51 penetrating the insulating dielectric layer 11 is formed on the surface of the cell region of the high-voltage MOS device 1, and the first metal layer 5 is located inside the ohmic contact hole 51.

[0029] The high-voltage MOS device 1 has an ohmic contact hole 61 that penetrates the insulating dielectric layer 11 on the surface of the terminal protection zone, and the second metal layer 6 is located inside the ohmic contact hole 61.

[0030] Both the first metal layer 5 and the second metal layer 6 are aluminum-copper alloy layers or aluminum-silicon-copper alloy layers, and the first metal layer 5 and the second metal layer 6 are not in contact.

[0031] The surface of the cell region of the high-voltage MOS device 1 is also provided with cell trenches 71, and the shielding gate 7 is located inside the cell trenches 71.

[0032] Compared to the traditional triangular shielding grid 7, the trapezoidal shielding grid 7 structure in this application can transform the electric field into a trapezoidal distribution, reduce Rds, and optimize the longitudinal electric field.

[0033] The surface of the high-voltage MOS device 1 is also provided with multiple unit cell trenches 91, and conductive polysilicon 9 is installed inside the unit cell trenches 91. An oxide layer 92 is disposed inside the unit cell trenches 91. The conductive polysilicon 9 is designed to share the cell current.

[0034] A protective trench 81 is provided at the edge of the terminal protection zone, and the composite field limiting ring 8 is located inside the protective trench 81.

[0035] This application uses the design of trapezoidal shielding grid 7 to reconstruct the longitudinal electric field distribution and reduce the peak electric field; the design of composite field limiting ring 8 to widen the depletion region and significantly reduce the electric field concentration at the curvature; the design of ramp field plate 10 to transfer the peak electric field point and eliminate the electric field distortion at the grid corner; and the design of drain buffer layer 4 to absorb the kinetic energy of high-energy carriers and reduce channel thermal shock.

[0036] In summary, the trapezoidal shielding gate 7 homogenizes the longitudinal electric field, and the composite field limiting ring 8 disperses the transverse electric field, thereby improving the uniformity of the electric field across the entire region of the MOS device and effectively preventing breakdown.

[0037] Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the present invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A high-voltage MOS termination protection structure with high avalanche tolerance, characterized in that: The device includes a high-voltage MOS device (1), which has a cell region and a terminal protection zone. An insulating dielectric layer (11) is disposed on the surface of the high-voltage MOS device (1). A first metal layer (5) is deposited on the cell region, and a second metal layer (6) is deposited on the terminal protection zone. The cell region is also provided with a shielding gate (7) for reducing the on-resistance and increasing the breakdown voltage. The longitudinal cross-section of the shielding gate (7) is trapezoidal. A composite field limiting ring (8) is disposed at the edge of the terminal protection zone for widening the depletion region, dispersing the electric field intensity, and avoiding edge-concentrated breakdown. A sloping field plate (10) covered with a sloping oxide layer is also disposed at the edge of the terminal protection zone.

2. The high avalanche tolerant high voltage MOS termination protection structure according to claim 1, wherein: The bottom of the high-voltage MOS device (1) is provided with N - drift region (2) and N + substrate region (3), the N - drift region (2) and N + substrate region (3) is provided with a drain buffer layer (4), the thickness of the drain buffer layer (4) is 2-5 μm.

3. The high avalanche tolerant high voltage MOS termination protection structure of claim 1, wherein: The high-voltage MOS device (1) has an ohmic contact hole (51) that penetrates the insulating dielectric layer (11) on the surface of the cell region, and the first metal layer (5) is located inside the ohmic contact hole (51).

4. The high avalanche tolerance high voltage MOS termination protection structure according to claim 1, characterized in that: The high-voltage MOS device (1) has an ohmic contact hole (61) that penetrates the insulating dielectric layer (11) on the surface of the terminal protection zone, and the second metal layer (6) is located inside the ohmic contact hole (61).

5. The high avalanche tolerance high voltage MOS termination protection structure according to claim 1, characterized in that: The surface of the cell region of the high-voltage MOS device (1) is also provided with cell trenches (71), and the shielding gate (7) is located inside the cell trenches (71).

6. The high avalanche tolerance high voltage MOS termination protection structure according to claim 1, characterized in that: The surface of the high-voltage MOS device (1) is also provided with a plurality of single-cell trenches (91), and conductive polysilicon (9) is installed inside the single-cell trenches (91). An oxide layer (92) is provided inside the single-cell trenches (91).

7. The high avalanche tolerance high voltage MOS termination protection structure according to claim 1, characterized in that: A protective trench (81) is provided at the edge of the terminal protection zone, and the composite field limiting ring (8) is located inside the protective trench (81).

8. The high avalanche tolerance high voltage MOS termination protection structure according to claim 1, characterized in that: The composite field limiting ring (8) includes multiple field limiting rings arranged in a straight line. To avoid electric field distortion, the spacing between two adjacent field limiting rings decreases.

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