Package substrate and package structure

Abstract

The application provides a packaging substrate, which comprises an insulating layer, a first circuit layer, a second circuit layer and an electrical connection structure. The first circuit layer and the second circuit layer are respectively arranged on opposite sides of the insulating layer, and the electrical connection structure connects the first circuit layer and the second circuit layer. The insulating layer is provided with a first slot and a second slot, the first circuit layer is provided with a first wire slot, and the first wire slot is communicated with the first slot. The second circuit layer comprises a first conductive area and a second conductive area, the first conductive area is arranged in communication with the first slot, and the second conductive area is arranged in communication with the second slot. The electrical connection structure comprises a bonding pad and a conductive body connected with the bonding pad, the conductive body penetrates the second slot and is connected with the second conductive area. The thickness of the first conductive area is smaller than the thickness of the second conductive area to form a containing space communicated with the first slot, and the cross-sectional width of the containing space is larger than the cross-sectional width of the first slot. In addition, the application also provides a packaging structure.

Description

Technical Field

[0001] This application relates to the field of electronic packaging, and more particularly to a packaging substrate and packaging structure. Background Technology

[0002] Molding is a process in which encapsulating resin is injected into a mold under high temperature and pressure and cured to form a shape that covers the chip and adheres to a carrier substrate. With the continuous development of the semiconductor industry, chip integration is becoming increasingly sophisticated, requiring more reliable packaging within a smaller space. However, the reduction in space dimensions increases the difficulty of molding, making it prone to delamination between the carrier substrate and the encapsulating resin due to interfacial stress or decreased adhesive strength. Utility Model Content

[0003] In view of this, this application provides a packaging substrate to improve the bonding strength with the packaging resin in the plastic packaging process.

[0004] In addition, it is necessary to provide a packaging structure for the above-mentioned packaging substrate.

[0005] An encapsulation substrate includes an insulating layer, a first circuit layer, a second circuit layer, and an electrical connection structure. The first circuit layer and the second circuit layer are respectively disposed on opposite sides of the insulating layer. The electrical connection structure is embedded in the insulating layer and connects the first circuit layer and the second circuit layer. The insulating layer has a first slot and a second slot. The first circuit layer has a first groove that connects to the first slot. The second circuit layer includes a first conductive region and a second conductive region. The first conductive region connects to the first slot, and the second conductive region connects to the second slot. The electrical connection structure includes a pad and a conductor connecting to the pad. The conductor passes through the second slot and connects to the second conductive region. The thickness of the first conductive region is less than the thickness of the second conductive region, thereby forming an accommodating space on the side of the first conductive region facing the first circuit layer. The accommodating space connects to the first slot, and the cross-sectional width of the accommodating space is greater than the cross-sectional width of the first slot.

[0006] An encapsulation structure includes: an encapsulation substrate as described above, electronic components disposed on pads; and a package body disposed on the electronic components, a portion of which is filled into a first groove, a first slot, and an accommodating space.

[0007] In this application, a first groove, a first slot communicating with the first groove, and an accommodating space communicating with the first slot are provided on the packaging substrate. The accommodating space is located on the side of the first conductive area of ​​the second circuit layer facing the first circuit layer, and its cross-sectional width is greater than that of the first slot. During the subsequent molding process, the encapsulating resin can flow from the first circuit layer side into the first slot through the first groove and further fill the accommodating space. After the encapsulating resin cures to form a package, the package is embedded in the stepped cavity formed by the first groove, the first slot, and the accommodating space, forming a stable interlocking structure and increasing the interface bonding area, thereby improving the bonding strength between the package and the packaging substrate, reducing interface stress concentration, suppressing delamination, and improving packaging reliability. Attached Figure Description

[0008] Figure 1 This is a cross-sectional schematic diagram of a peelable substrate provided in an embodiment of this application.

[0009] Figure 2 for Figure 1 The diagram shows a cross-sectional view of a first electroplated layer on one side of a peelable substrate.

[0010] Figure 3 for Figure 2 The diagram shows a cross-sectional view of the first electroplated layer after the first photosensitive pattern has been applied.

[0011] Figure 4 for Figure 3 The diagram shows a cross-sectional view of the first electroplated layer after the first electrical connection structure has been installed.

[0012] Figure 5 for Figure 4 The diagram shows a cross-section of the first photosensitive pattern after the third photosensitive pattern has been set.

[0013] Figure 6 To remove Figure 5 The diagram shows the first electrical connection structure and a cross-sectional view of part of the first circuit layer.

[0014] Figure 7 For separation Figure 6 The diagram shows a cross-sectional view of the second intermediate obtained after the first and second copper layers.

[0015] Figure 8 To remove Figure 7 The diagram shows a cross-sectional view of the third intermediate formed by the first photosensitive pattern, the third photosensitive pattern, and the second copper layer of the second intermediate.

[0016] Figure 9 for Figure 8 The diagram shows a cross-sectional view of a packaging substrate formed by providing a first solder resist layer and a second solder resist layer on the third intermediate.

[0017] Figure 10 This is a cross-sectional schematic diagram of the packaging structure provided in one embodiment of this application.

[0018] Explanation of main component symbols Packaging substrate: 100; Peelable substrate: 10; First side plate: 11; Core board: 12; Second side plate: 13; Blind via: 14; First slot: 111; Second slot: 112; First copper foil layer: 113; First insulating layer: 114; Second circuit layer: 115; First conductive area: 115a; Second conductive area: 115b; Accommodating space: 116; Core layer: 121; First copper layer: 122; Second copper layer: 123; Second copper foil layer: 131; Second insulating layer: 132; Third circuit layer: 133; First electroplated layer: 20; Second electroplated layer: 22; First photosensitive pattern: 30; Second photosensitive pattern: 31; First electrical connection structure: 40. First pad: 401; First conductor: 402; Second electrical connection structure: 41; Second pad: 411; Second conductor: 412; Third photosensitive pattern: 50; Fourth photosensitive pattern: 51; First intermediate: 52; Second intermediate: 60; Third intermediate: 61; First circuit layer: 21; First wire groove: 211; Second wire groove: 212; First solder resist layer: 62; First window: 621; Second solder resist layer: 63; Second window: 631; Package structure: 200; Electronic component: 201; Package body: 202; Body: 203; Pin: 204; Cross-sectional width: W1, W2, W3, W4, W5, W6; Thickness direction: A. Detailed Implementation

[0019] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0020] It should be noted that when a component is considered to be "connected" to another component, it can be directly connected to the other component or may also exist in an intervening component. When a component is considered to be "set on" another component, it can be directly set on the other component or may also exist in an intervening component.

[0021] Please see Figures 1 to 10 This application provides a method for manufacturing a packaging substrate 100, including the following steps: S1: Please see Figure 1A peelable substrate 10 is provided, which has a thickness direction A. Viewed in cross-section along thickness direction A, the peelable substrate 10 includes a first side plate 11, a core plate 12, and a second side plate 13 stacked sequentially. The first side plate 11 is provided with a plurality of first slots 111 and a plurality of second slots 112. In planar projection, the plurality of second slots 112 are arranged in a matrix, and four first slots 111 are evenly distributed at the four corners of this matrix.

[0022] In this embodiment, the core board 12 includes a core layer 121, two first copper layers 122, and two second copper layers 123. The two first copper layers 122 are respectively disposed on opposite sides of the core layer 121. The two second copper layers 123 are respectively disposed on the side of the first copper layers 122 facing away from the core layer 121. An adhesive layer (not shown) is disposed between the first copper layers 122 and the second copper layers 123, allowing the first copper layers 122 and the second copper layers 123 to be peeled off. Specifically, the adhesive layer may be a release adhesive material, such as a heat-releasable adhesive, an ultraviolet (UV) releasable adhesive, or a chemically releasable adhesive; preferably, it may be one or a combination of acrylic, modified epoxy, polyimide, polyolefin, or polyester resins. When preset thermal / optical / chemical triggering conditions are applied to the adhesive layer, its adhesive strength selectively decreases, thereby achieving controllable peeling of the first copper layer 122 and the second copper layer 123. The peeling interface is flat with little residue, reducing the impact on the copper layer patterns on both sides and facilitating subsequent processing.

[0023] In this embodiment, the first side plate 11 includes a first copper foil layer 113, a first insulating layer 114, and a second circuit layer 115 stacked sequentially. The second circuit layer 115 has the same thickness throughout. The second side plate 13 includes a second copper foil layer 131, a second insulating layer 132, and a third circuit layer 133 stacked sequentially. The third circuit layer 133 has the same thickness throughout. The peelable substrate 10 is also provided with blind vias 14, which connect the first insulating layer 114 and the second insulating layer 132, with a portion of the first insulating layer 114 filling the blind vias 14. Thus, the first insulating layer 114 filling the blind vias 14 forms a "resin rivet" structure between the two insulating layers, increasing the effective bonding area at the interface and providing an additional shear bearing path, which is beneficial to improving the bonding strength of the first side plate 11, the second side plate 13, and the core board 12, and reducing the risk of subsequent peeling and warping between layers.

[0024] S2: Please see Figure 2 A first electroplated layer 20 is formed on the first copper foil layer 113, and the first electroplated layer 20 is attached to the inner wall of the first groove 111 and the inner wall of the second groove 112. One side of the first electroplated layer 20 is connected to the second circuit layer 115.

[0025] In this embodiment, step S2 further includes: depositing a second electroplating layer 22 on the second copper foil layer 131, the second electroplating layer 22 covering the second copper foil layer 131.

[0026] S3: Please see Figure 3 A first photosensitive pattern 30 is formed on the first electroplated layer 20, and the first photosensitive pattern 30 has multiple first openings 301 and multiple second openings 302 formed through it. The first openings 301 are set corresponding to the first grooves 111, and the second openings 302 are set corresponding to the second grooves 112. At the same time, a second photosensitive pattern 31 is formed on the second electroplated layer 22.

[0027] In this embodiment, the cross-sectional width W1 of the first opening 301 is greater than the cross-sectional width W2 of the first slot 111; the cross-sectional width W3 of the second opening 302 is greater than the cross-sectional width W4 of the second slot 112.

[0028] S4: Please see Figure 4 Please see Figure 4 A first electrical connection structure 40 is formed by electroplating within the first opening 301 and the first slot 111. The first electrical connection structure 40 includes a first pad 401 and a first conductor 402 connected to the first pad 401. The first pad 401 is formed in the first opening 301, and the first conductor 402 is formed in the first slot 111. The end of the first conductor 402 away from the first pad 401 is connected to the second circuit layer 115.

[0029] Simultaneously, a second electrical connection structure 41 is formed by electroplating within the second opening 302 and the second slot 112. The second electrical connection structure 41 includes a second pad 411 and a second conductor 412 connected to the second pad 411. The second pad 411 is formed in the second opening 302, and the second conductor 412 is formed in the second slot 112. The end of the second conductor 412 away from the second pad 411 is connected to the second circuit layer 115.

[0030] S5: Please see Figure 5 A third photosensitive pattern 50 is set on the first photosensitive pattern 30. The third photosensitive pattern 50 is provided with a third opening 501. The first pad 401 is set corresponding to the third opening 501.

[0031] Simultaneously, a fourth photosensitive pattern 51 is set on the second photosensitive pattern 31. The simultaneous formation of the third photosensitive pattern 50 and the fourth photosensitive pattern 51 on both sides helps to maintain the symmetry of process load and heat input on both sides of the core board 12, reduces warpage and suppresses stress unevenness, thereby improving process stability and product yield.

[0032] S6: Please see Figure 6The etching process removes the first electrical connection structure 40 and a portion of the second circuit layer 115 to obtain the first intermediate body 52. ​​Specifically, the etching solution first etches away the first pad 401, a portion of the first electroplated layer 20 corresponding to the first pad 401, and the first copper foil layer 113, exposing the first opening 301; then, the etching solution etches away the first conductor 402 and the first electroplated layer 20 corresponding to the first conductor 402, exposing the first trench 111; finally, the etching solution etches away a portion of the second circuit layer 115 to form an accommodating space 116. Thus, the second circuit layer 115 can be divided into a first conductive region 115a and a second conductive region 115b, with the first conductive region 115a connected to the first trench 111 and the second conductive region 115b connected to the second trench 112. The thickness of the first conductive region 115a is less than the thickness of the second conductive region 115b, thereby forming an accommodating space 116 on the side of the first conductive region 115a facing the first circuit layer 21. The accommodating space 116 is connected to the first slot 111, and the cross-sectional width of the accommodating space 116 is greater than the cross-sectional width of the first slot 111.

[0033] S7: Trim the edges of the first intermediate body 52, removing the edge portion of the first intermediate body 52, including the blind hole 14, so that the external dimensions and edge quality of the first intermediate body 52 meet the preset tolerance and flatness requirements.

[0034] In this embodiment, step S7 further includes: removing edge burrs, residual electroplating layer and residual adhesive from the first intermediate 52, reducing the risk of resin overflow, crack initiation or stress concentration caused by edge blind holes 14 during subsequent peeling, lamination, solder resist coating and molding processes, thereby reducing the risk of edge defects extending into the effective area.

[0035] S8: Please see Figure 7 The core board 12 is separated, causing the first copper layer 122 and the second copper layer 123 to peel off from each other, thus obtaining the second intermediate 60. Specifically, by heating the first intermediate 52, the bonding strength of the adhesive layer between the first copper layer 122 and the second copper layer 123 is reduced, ultimately achieving the separation of the first copper 122 from the second copper layer 123.

[0036] The second intermediate body 60 includes a second copper layer 123, a second circuit layer 115, a first insulating layer 114, a first electroplating layer 20, a first photosensitive pattern 30, and a third photosensitive pattern 50 stacked sequentially. The second intermediate body 60 is provided with a first slot 111 and an accommodating space 116 communicating with the first slot 111.

[0037] S9: Please see Figure 7 and Figure 8The first photosensitive pattern 30, the third photosensitive pattern 50, and the second copper layer 123 are removed, and the first copper foil layer 113 and the first electroplated layer 20 are etched to form the first circuit layer 21, thereby obtaining the third intermediate 61. The first circuit layer 21 is provided with a first groove 211 and a second groove 212. The first groove 211 connects to the first slot 111, and the first insulating layer 114 is exposed at the bottom of the second groove 212.

[0038] S9: Please see Figure 9 A first solder resist layer 62 and a second solder resist layer 63 are respectively provided on opposite sides of the third intermediate 61 to obtain a packaging substrate 100.

[0039] In this embodiment, the first solder resist layer 62 is disposed on the side of the first circuit layer 21 away from the first insulating layer 114, and part of the first solder resist layer 62 is filled into the second wire groove 212. The first pad 401 is flush with the first solder resist layer 62, so that the first pad 401 is exposed in the first solder resist layer 62.

[0040] The second solder resist layer 63 is disposed on the side of the second circuit layer 115 opposite to the first insulating layer 114. The first solder resist layer 62 is provided with a first opening 621, which corresponds to the first wire groove 211. The second solder resist layer 63 is provided with a second opening 631, and the side of the second conductive area 115b opposite to the first insulating layer 114 is exposed at the bottom of the second opening 631.

[0041] Compared with the prior art, the manufacturing method of the packaging substrate 100 provided in this application has the following advantages: (i) The first groove 211, the first slot 111, and the accommodating space 116 are connected in sequence, and the cross-sectional width of the accommodating space 116 is greater than that of the first slot 111. After the encapsulating resin is cured, an interlocking structure is formed in the substrate, which significantly increases the effective bonding area and provides a shear / peel bearing path, thereby reducing the stress concentration at the interface, suppressing the delamination, warping and edge cracking of the substrate 100, and improving the encapsulation reliability.

[0042] (ii) A first conductive region 115a and a second conductive region 115b with a thickness difference are provided in the second circuit layer 115, and an accommodating space 116 is formed on the side of the first conductive region 115a as a stress buffer. At the same time, the first conductor 402 is connected to the second conductive region 115b through the second slot 112, so that the electrical connection path and the resin anchoring path are independent of each other, reducing the risk of thermo-mechanical coupling and metal fatigue at the first pad 401 and the first conductor 402, and improving the welding strength and thermal cycling stability.

[0043] (iii) The simultaneous photosensitive / electroplating / etching steps on both sides maintain symmetrical thermal and mechanical loads, reducing board warping and registration errors. Blind vias 14 are filled with insulating resin to form "resin rivets," improving the lamination bonding strength between the first side plate 11, the second side plate 13, and the core board 12. Solder mask openings expose the solder pads flush, improving solder wetting and coplanarity. The surrounding / spaced arrangement of the slotted array helps to evenly distribute stress and improve process stability and finished product yield.

[0044] Please see Figure 9 An embodiment of this application also provides a packaging substrate 100, including an insulating layer (i.e., a first insulating layer 114, the same below), a first circuit layer 21, a second circuit layer 115, and an electrical connection structure (i.e., a first electrical connection structure 40, the same below). The first circuit layer 21 and the second circuit layer 115 are respectively disposed on opposite sides of the insulating layer, and the electrical connection structure is embedded in the insulating layer, connecting the first circuit layer 21 and the second circuit layer 115.

[0045] The insulating layer (first insulating layer 114, the same below) is provided with a first slot 111 and a second slot 112. The first circuit layer 21 is provided with a first wire groove 211 and a second wire groove 212. The first wire groove 211 is connected to the first slot 111, and part of the second wire groove 212 is connected to the second slot 112.

[0046] The second circuit layer 115 includes a first conductive region 115a and a second conductive region 115b. The first conductive region 115a is connected to the first slot 111, and the second conductive region 115b is connected to the second slot 112.

[0047] The electrical connection structure includes a pad (i.e., the first pad 401, the same below) and a conductor connecting the pad (i.e., the first conductor 402, the same below). The conductor passes through a portion of the second wire groove 212 and the second slot 112 and is connected to the second conductive area 115b.

[0048] The thickness of the first conductive region 115a is less than the thickness of the second conductive region 115b, thereby forming an accommodating space 116 on the side of the first conductive region 115a facing the first circuit layer 21. The accommodating space 116 is connected to the first slot 111, and the cross-sectional width W5 of the accommodating space 116 is greater than the cross-sectional width W2 of the first slot 111.

[0049] In this embodiment, the cross-sectional width W6 of the first groove 211 is greater than the cross-sectional width W2 of the first slot 111. Thus, combined with the fact that the cross-sectional width of the accommodating space 116 is also greater than the cross-sectional width of the first slot 111, a "wide-narrow-wide" through-cavity is formed along the thickness direction, roughly forming an "I"-shaped channel. On the one hand, this facilitates the smooth entry of the encapsulating resin from the first circuit layer 21 side and its expansion within the accommodating space 116, improving venting and filling, and reducing the risk of air bubbles and voids; on the other hand, the narrow neck in the middle facilitates the curing of the encapsulated body 202 (see...). Figure 10 (The same below) forms a reverse snap-fit ​​structure, which enhances the anti-peeling and anti-pull-out capabilities, thereby improving the bonding strength and reliability between the package 202 and the package substrate 100.

[0050] In this embodiment, a plurality of second slots 112 are disposed between two adjacent first slots 111. Furthermore, the plurality of first slots 111 are evenly distributed around the plurality of second slots 112. Thus, in planar projection, an ordered array is formed with the second slot 112 area as the core and surrounded by the first slots 111. The first slots 111, together with the first groove 211 and the accommodating space 116, constitute a multi-directional adhesive injection and anchoring channel, allowing the encapsulating resin to flow in circumferentially and fully fill the space.

[0051] In this embodiment, the packaging substrate 100 further includes a first solder resist layer 62 and a second solder resist layer 63. The first solder resist layer 62 is disposed on the side of the first circuit layer 21 away from the insulating layer, and a portion of the first solder resist layer 62 is filled into another portion of the second wire groove 212. The second solder resist layer 63 is disposed on the side of the second circuit layer 115 away from the insulating layer.

[0052] In this embodiment, the first solder resist layer 62 is provided with a first window 621, which corresponds to the first wire groove 211. The second pad 411 is flush with the first solder resist layer 62 and is exposed in the first solder resist layer 62. The second solder resist layer 63 is provided with a second window 631, and the side of the second conductive area 115b facing away from the insulating layer is exposed at the bottom of the second window 631.

[0053] Please see Figure 10 An embodiment of this application also provides a packaging structure 200, including a packaging substrate 100, an electronic component 201, and a package body 202. The electronic component 201 is disposed on a pad. The package body 202 is disposed on the electronic component 201, and a portion of the package body 202 is filled into a first groove 211, a first slot 111, and an accommodating space 116.

[0054] In this embodiment, the electronic component 201 includes a body 203 and pins 204, with the pins 204 soldered to pads. A gap exists between the body 203 and the packaging substrate 100, and a filler 205 is provided in this gap. The filler 205 can be used to fill the gap and form a stress buffer / sealing layer, providing support and positioning for the body 203 and limiting its displacement during molding, handling, and heating.

[0055] In addition, those skilled in the art may make other changes within the spirit of this application. Of course, all such changes made in accordance with the spirit of this application should be included within the scope of protection claimed in this application.

Claims

1. A packaging substrate, characterized in that, It includes an insulating layer, a first circuit layer, a second circuit layer, and an electrical connection structure. The first circuit layer and the second circuit layer are respectively disposed on opposite sides of the insulating layer. The electrical connection structure is embedded in the insulating layer and connects the first circuit layer and the second circuit layer. The insulating layer is provided with a first slot and a second slot, and the first circuit layer is provided with a first wire groove, which is connected to the first slot. The second circuit layer includes a first conductive region and a second conductive region, wherein the first conductive region is connected to the first slot and the second conductive region is connected to the second slot. The electrical connection structure includes a pad and a conductor connected to the pad, the conductor passing through the second slot and connected to the second conductive area; The thickness of the first conductive region is less than the thickness of the second conductive region, thereby forming an accommodating space on the side of the first conductive region facing the first circuit layer. The accommodating space is connected to the first slot, and the cross-sectional width of the accommodating space is greater than the cross-sectional width of the first slot.

2. The packaging substrate as described in claim 1, characterized in that, The cross-sectional width of the first groove is greater than the cross-sectional width of the first slot.

3. The packaging substrate as described in claim 1, characterized in that, Multiple second slots are provided between two adjacent first slots.

4. The packaging substrate as described in claim 3, characterized in that, Multiple first slots are evenly distributed around multiple second slots.

5. The packaging substrate as described in claim 3, characterized in that, It also includes a first solder resist layer and a second solder resist layer. The first solder resist layer is disposed on the side of the first circuit layer away from the insulating layer. The first circuit layer also includes a second wire groove. Part of the insulating layer is exposed in the second wire groove, and part of the first solder resist layer is filled in the second wire groove. The second solder resist layer is disposed on the side of the second circuit layer away from the insulating layer.

6. The packaging substrate as described in claim 5, characterized in that, The first solder resist layer is provided with a first window, which corresponds to the first wire groove. The solder pad is flush with the first solder resist layer and is exposed in the first solder resist layer.

7. The packaging substrate as described in claim 5, characterized in that, The second solder resist layer is provided with a second window, and the side of the second conductive area away from the insulating layer is exposed at the bottom of the second window.

8. A packaging structure, characterized in that, include: The packaging substrate as described in any one of claims 1 to 7, Electronic components, the electronic components being disposed on the pads; A package is disposed on the electronic component, and a portion of the package is filled into the first slot, the first groove, and the accommodating space.

9. The packaging structure as described in claim 8, characterized in that, The electronic component includes a body and pins, the pins being soldered to the pads.

10. The packaging structure as described in claim 9, characterized in that, There is a gap between the body and the packaging substrate, and the gap is filled with a filler.

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