NEW GATE STRUCTURES FOR SETTING THE LIMIT VOLTAGE AND METHOD

Abstract

Device comprising: a substrate (110); an interface layer (210) formed above the substrate (110), wherein the interface layer (210) has a dipole-penetrated section (210A); a gate dielectric layer (430) formed above the interface layer (210); and a metal gate electrode formed above the gate dielectric layer (430), wherein the dipole-penetrated section (210A) comprises yttrium oxide Y2O3, niobium oxide Nb2O5, titanium oxide TiO5, boron oxide B2O3, phosphorus pentoxide P2O5 or phosphorus trioxide P2O3.

Description

BACKGROUND

[0001] The semiconductor integrated circuit (IC) industry has grown exponentially. Technological advances in IC materials and design have produced generations of ICs, each generation featuring smaller and more complex circuitry than the previous one. As IC development progressed, functional density (i.e., the number of connected devices per chip area) generally increased, while geometric size (i.e., the smallest component (or trace) that can be produced using a manufacturing process) decreased. This scale-down process generally offers benefits by increasing production efficiency and reducing associated costs. However, this scale-down has also increased the complexity of IC processing and manufacturing.

[0002] For example, the limiting voltage in conventional devices can be adjusted by increasing the thickness of different exit metals of a gate electrode. However, with ongoing downscaling, increasing the thickness of these different exit metals becomes impractical and / or can lead to various manufacturing problems.

[0003] Therefore, while conventional methods for determining the limit voltages are generally appropriate, they are not satisfactory in all aspects.

[0004] Publication US 2014 / 0264626A1 describes gate structures with a dielectric base layer, a dielectric layer, a cover layer, and an electrode material over a substrate. A metallic layer containing lanthanum or aluminum is applied, which diffuses into the dielectric layers during a tempering process.

[0005] Document US 2015 / 0104933A1 describes the formation of dipoles between two dielectric layers of a gate structure.

[0006] Document US 2012 / 0049297A1 describes a gate structure with dielectric layers and a gate electrode consisting of metallic layers. Different lanthanum concentration distributions are found in the dielectric layers.

[0007] Document US 2015 / 0 035 073 A1 describes gate structures with dielectric layers.

[0008] Document US 2019 / 0318967A1 describes gate structures with a dielectric boundary layer, a gate dielectric layer, a blocking layer, and a superimposed dipole layer. Dipole doping is driven from the dipole layer into the gate dielectric layer using a annealing process.

[0009] Document US 2011 / 0 127 616 A1 describes the manufacturing of gate structures.

[0010] Document DE 11 2011 101 277 B4 describes the manufacture of gate structures.

[0011] The invention is defined by the main claim and the dependent claims. Further embodiments of the invention are described by the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The following detailed description is best understood with the help of the accompanying drawings. It should be noted that, according to industry standard practice, various features are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity. Fig. 1A is a perspective view of an IC device according to various aspects of this revelation. Fig. 1B is a top view of an IC device according to various aspects of this revelation. Fig. Figures 2A to 21A, 2B to 21B, 2C to 21C, 2D to 21D, 2E to 21E and 2F to 21F and 22 to 23 are cross-sectional views of different embodiments of an IC device at different stages of manufacture according to different aspects of this disclosure. Fig. Figure 24 is a flowchart illustrating a process for manufacturing a semiconductor device according to various aspects of this disclosure. DETAILED DESCRIPTION

[0013] The following disclosure provides many different embodiments or examples of the implementation of various features of the disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, only examples and are not to be understood as limiting. For example, forming a first feature or a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and it may also include embodiments in which further features can be formed between the first and second features, so that the first and second features do not have to be in direct contact. Furthermore, this disclosure may repeat reference numbers and / or letters from the various examples.This repetition serves for simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations explained.

[0014] Furthermore, this disclosure may repeat reference numbers and / or letters from the various examples. This repetition serves for simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations described. Furthermore, the formation of a feature on, connected with, and / or coupled to another feature in this subsequent disclosure may include embodiments in which the features are formed in direct contact, and may also include embodiments in which further features can be formed between the features, so that the features need not be in direct contact. Furthermore, spatially relative terms such as "lower," "upper," "horizontal," "vertical," "on," "above," "below," "underneath," "upward," "downward," "above," "below," etc., and their derivatives (e.g., "horizontal," "downward," "upward," etc.) are used.) for the simplicity of this disclosure of the relationship of one feature to another. The spatially relative terms are intended to cover different orientations of the device comprising the features. Furthermore, when a number or range of numbers is designated by "about," "approximately," and the like, the term is intended to include numbers that lie within a suitable range containing the designated number, such as the range of + / - 10% around the described number, or at other values ​​as a person skilled in the art will understand. For example, the term "about 5 nm" encompasses the dimensional range from 4.5 nm to 5.5 nm.

[0015] This disclosure relates generally to semiconductor devices, and more specifically to field-effect transistors (FETs), such as planar FETs, three-dimensional fin-conductor FETs (FinFETs), or gate-all-around devices (GAA devices). One aspect of this disclosure involves forming a dipole layer directly on an interface layer in a gate structure, and then using multiple interface layer structuring processes to achieve different threshold voltages for different devices. This improves the flexibility in setting the threshold voltage and reduces the gate resistance compared to conventional devices, as explained in more detail below.

[0016] Fig. 1A and Fig. Figure 1B illustrates a three-dimensional perspective view or a top view of a section of an integrated circuit device (IC device) 90. The IC device 90 may be an intermediate device manufactured during the processing of an IC, or a section thereof, which may include static random-access memory (SRAM) and / or other logic circuits, passive components such as resistors, capacitors, and inductors, and active components such as p-FETs (PFETs), n-FETs (NFETs), FinFETs, metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor transistors (CMOS transistors), bipolar transistors, high-voltage transistors, high-frequency transistors, and / or other memory cells. This disclosure is not limited to a specific number of devices or device regions or to specific device configurations unless otherwise claimed.For example, although IC device 90 as illustrated is a three-dimensional FinFET device, the concepts of this disclosure may also apply to planar FET devices or GAA devices.

[0017] With reference to Fig. In Figure 1A, the IC device 90 comprises a substrate 110. The substrate 110 can comprise an elemental (single-element) semiconductor, such as silicon, germanium, and / or other suitable materials; a compound semiconductor, such as silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, and / or other suitable materials; an alloy semiconductor, such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, and / or other suitable materials. The substrate 110 can be a single-layer material having a uniform composition. Alternatively, the substrate 110 can comprise multiple layers of material having similar or different compositions suitable for fabricating the IC device. In one example, the substrate 110 can be a silicon-on-insulator (SOI) substrate having a semiconductor silicon layer formed on a silicon oxide layer.In another example, the substrate 110 can comprise a conductive layer, a semiconductor layer, a dielectric layer, other layers, or combinations thereof. Various doped regions, such as source / drain regions, can be formed in or on the substrate 110. Depending on the design requirements, the doped regions can be doped with n-type dopants, such as phosphorus or arsenic, and / or p-type dopants, such as boron. The doped regions can be formed directly on the substrate 110, in a p-well structure, an n-well structure, a dual-well structure, or using a raised structure. Doped regions can be formed by implantation of dopant atoms, on-site doped epitaxial growth, and / or other suitable techniques.

[0018] Three-dimensional active regions 120 are formed on the substrate 110. The active regions 120 are elongated, fin-like structures that project upwards from the substrate 110. Thus, the active regions 120 can subsequently be referred to interchangeably as fins 120 or fin structures 120. The fin structures 120 can be fabricated using suitable processes, including photolithography and etching. The photolithography process can include forming a photoresist layer over the substrate 110, exposing the photoresist to form a structure, performing firing processes after exposure, and developing the photoresist to form a masking element (not shown) including the resist. The masking element is then used to etch cutouts in the substrate 110, leaving the fin structures 120 on the substrate 110.The etching process can include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. In some embodiments, the fin structure 120 can be formed by dual or multiple structuring processes. In general, dual or multiple structuring processes combine photolithography and self-aligning processes, which allows the creation of structures that, for example, have spacings smaller than would otherwise be possible using a single direct photolithography process. For example, a layer can be formed over a substrate and structured using a photolithography process. Spacers are formed along the structured layer using a self-aligning process. The layer is then removed, and the remaining spacers or spikes can then be used to structure the fin structures 120.

[0019] The IC device 90 also includes source / drain features 122 formed over the fins 120. The source / drain features 122 may include epilayers that are epitaxially formed on the fin structures 120.

[0020] The IC device 90 further comprises insulating structures 130 formed over the substrate 110. The insulating structures 130 electrically isolate different components of the IC device 90. The insulating structures 130 can comprise silicon oxide, silicon nitride, silicon oxynitride, fluoride-doped silicate glass (FSG), a dielectric with a low k-value, and / or other suitable materials. In some embodiments, the insulating structures 130 can include shallow trench insulating features (STI structures). In one embodiment, the insulating structures 130 are formed by etching trenches into the substrate 110 during the formation of the fin structures 120. The trenches can then be filled with an insulating material described above, followed by a chemical-mechanical planarization (CMP) process.Other insulation structures, such as field oxide, local oxidation of silicon (LOCOS), and / or other suitable structures, can also be implemented as the insulation structures 130. Alternatively, the insulation structures 130 can comprise a multilayer structure, which may, for example, include one or more thermal oxide lining layers.

[0021] The IC device 90 also includes gate structures 140 formed over and in engagement with the fins 120 on three sides in a channel region of each fin 120. The gate structures 140 can be dummy gate structures (e.g., comprising an oxide gate dielectric and a polysilicon gate electrode) or can be high-k metal gate structures comprising a high-k gate dielectric and a metal gate electrode, the high-k metal gate structures being formed by replacing the dummy gate structures. Although not shown here, the gate structure 140 can include further material layers, such as an interface layer over the fins 120, a cover layer, other suitable layers, or combinations thereof.

[0022] With reference to Fig. In 1B, several fins 120 are arranged longitudinally along the X-direction, and several gate structures 140 are arranged longitudinally along the Y-direction, i.e., generally perpendicular to the fins 120. In numerous embodiments, the IC device 90 includes further features such as gate spacers arranged along side walls of the gate structures 140, hard mask layer(s) arranged over the gate structures 140, and numerous other features.

[0023] Fig. 2A to 2F to Fig. Figures 21A to 21F illustrate diagrammatic fragmentary cross-sectional side views of a section of an IC device 90 at various stages of manufacture according to different embodiments of this disclosure. For example, they illustrate Fig. 2A to 21A diagrammatic fragmentary cross-sectional side views of a gate structure 200A manufactured according to an embodiment corresponding to an N-transistor having an ultra-low threshold voltage (hereinafter referred to as N-uLVT). Fig. Figures 2A to 21A illustrate diagrammatic fragmentary cross-sectional side views of a Gate 200B structure fabricated according to an embodiment corresponding to an N-transistor having a low threshold voltage (hereinafter referred to as N-LVT). Fig. Figures 2C to 21C illustrate diagrammatic fragmentary cross-sectional side views of a gate structure 200C fabricated according to an embodiment corresponding to an N-transistor having a standard cutoff voltage (hereinafter referred to as N-SVT). It is understood that the cutoff voltage of the N-uLVT is lower than the cutoff voltage of the N-LVT, and vice versa.

[0024] This illustrates Fig. 2D to 21D diagrammatic fragmentary cross-sectional side views of a 200D gate structure fabricated according to an embodiment corresponding to a P-transistor having a standard limit voltage (hereinafter referred to as P-SVT). Fig. Figures 2E to 21E illustrate diagrammatic fragmentary cross-sectional side views of a gate structure 200E manufactured according to an embodiment corresponding to a P-transistor having a low threshold voltage (hereinafter referred to as P-LVT). Fig. Figures 2F to 21F illustrate diagrammatic fragmentary cross-sectional side views of a 200F gate structure fabricated according to an embodiment corresponding to a P-transistor having an ultra-low threshold voltage (hereinafter referred to as P-uLVT). It is understood that, since the PFET devices have negative threshold voltages, the magnitude or absolute value of the P-uLVT threshold voltage is less than the magnitude or absolute value of the P-LVT threshold voltage, and vice versa.

[0025] It is understood that in some embodiments, the gate structures 200A to 200F can be formed on the same wafer and / or be sections of the same IC chip. Thus, at least some of the manufacturing processes described below can be performed simultaneously on all gate structures 200A to 200F. In FinFET embodiments, the gate structures 200A to 200F can also each be connected via fin structures (e.g., the fin structures 120 from [reference missing]). Fig. 1A to 1B) are formed such that the gate structures 200A to 200F each wrap around a section of the fin structures. For example, the gate structures 200A to 200F can wrap around channel regions of the fin structures, thus placing source and drain regions of the fin structure between them.

[0026] In the manufacturing stage from Fig. Gate structures 200A to 200F each comprise an interface layer (hereinafter referred to interchangeably as IL) 210, which extends over a section of the substrate 110 (for example, over the fin structures 120). Fig. 1A is formed. In some embodiments, IL 210 comprises silicon oxide. In other embodiments, IL 210 may comprise another suitable type of dielectric. IL 210 has a thickness of 220 (measured in the Z direction). Fig. 1A). In some embodiments, the thickness 220 lies in a range between approximately 0.3 nm and approximately 1.5 nm.

[0027] Still referring to Fig. In gate structures 200A to 200F, a hard mask layer 230 is formed over the IL 210. In some embodiments, the hard mask layer 230 comprises titanium nitride. In some embodiments, the hard mask layer 230 is formed by an atomic layer deposition (ALD) process with approximately 20 to 50 deposition cycles and in a temperature range between approximately 400°C and 450°C. Such a deposition process can form the hard mask layer 230 with a thickness 235 in a range between approximately 1.0 nm and approximately 2.5 nm. This range for the thickness 235 is not chosen arbitrarily but is specifically configured to effectively establish a distance or gap between the IL 210 and the dipole layer to be formed over it. As will be explained in more detail below, such a distance helps to set the limit voltage of the N-SVT and P-uLVT transistors.

[0028] A structured photoresist layer 240 is formed above the hard mask layer 230 in gate structures 200C and 200F, corresponding to embodiments N-SVT and P-uLVT, respectively, but not above the hard mask layer 230 in gate structures 200A to 200B and 200D to 200E. In some embodiments, the structured photoresist layer 240 may comprise a photosensitive material and an antireflective material. The structured photoresist layer 240 can be used to structure the underlying hard mask layer 230.

[0029] Now, with reference to Fig. In gate structures 3A to 3F, a photolithography process is performed to pattern the hard mask layer 230. The patterned photoresist layer 240 can protect the underlying portions of the hard mask layer 230 while the exposed portions of the hard mask layer 230 are removed. In this way, the remaining portions of the hard mask layer 230 are formed over the IL 210 in gate structures 200C and 200F, but not over the IL 210 in gate structures 200A to 200B and 200D to 200E. As explained in more detail below, this disclosure leaves the hard mask layer 230 that remains in gate structures 200C and 200F to serve as an additional diffusion barrier or to increase the distance between the IL 210 and a dipole layer that is formed over it in a subsequent fabrication process.After structuring the hard mask layer 230, the structured photoresist layer 240 is removed, for example, using a photoresist ash or stripping process.

[0030] Now, with reference to Fig. In gate structures 200A to 200F, a hard mask layer 260 is formed over the IL 210. In some embodiments, the hard mask layer 260 may comprise the same material (or a substantially similar material) as the hard mask layer 230. For example, the hard mask layer 260 may comprise titanium nitride. In other embodiments, the hard mask layer 230 may comprise a different type of material. In some embodiments, the hard mask layer 260 is formed by an ALD process with approximately 20 to approximately 50 deposition cycles and in a temperature range between approximately 400°C and approximately 450°C. Such a deposition process can form the hard mask layer 260 with a thickness 265 in the range between approximately 1.0 nm and approximately 2.5 nm.This area for thickness 265 is not chosen arbitrarily, but is specifically configured to effectively set a distance or gap between the IL 210 and the dipole layer to be formed above it. As explained in more detail below, such a distance helps to set the cutoff voltage of the N-LVT, N-SVT, P-LVT, and P-uLVT transistors.

[0031] A structured photoresist layer 270 is formed above the hard mask layer 230 in gate structures 200B to 200C and 200E to 200F, corresponding to embodiments N-LVT, N-SVT, P-LVT, and P-uLVT, respectively, but not above the hard mask layer 260 in gate structures 200A and 200D, corresponding to embodiments N-uLVT and P-SVT. In some embodiments, the structured photoresist layer 270 may comprise a photosensitive material and an antireflective material. The structured photoresist layer 240 may be used to structure the underlying hard mask layer 230.

[0032] Now, with reference to Fig. In gate structures 5A to 5F, a photolithography process is performed to pattern the hard mask layer 260. The patterned photoresist layer 270 can protect the underlying sections of the hard mask layer 260 while removing the exposed sections. In this way, the remaining sections of the hard mask layer 260 are positioned over the IL 210 in gate structures 200D to 200C and 200E to 200F, but not over the IL 210 in gate structures 200A to 200D. Once again, this revelation leaves behind the hard mask layer 230, which remains in the gate structures 200B to 200C and 200E to 200F, to serve as another additional diffusion barrier, or to further increase a distance between the IL 210 and the dipole layer that is formed on top of it in a later manufacturing process.The varying distances between the IL 210 and the dipole layer help to set different cutoff voltages for these different transistors. After the hard mask layer 260 is structured, the structured photoresist layer 270 is removed, for example, using a photoresist ash or stripping process.

[0033] Now, with reference to Fig. 6A to 6F, a dipole deposition process 290 is carried out to deposit a dipole layer 300 on each of the gate structures 200A to 200F. More precisely, the dipole layer 300 is deposited directly on the IL 210 in the gate structures 200A and 200D (corresponding to the embodiments N-uLVT and P-SVT, respectively), and the dipole layer 300 is deposited directly on the hard mask layer 260 in the gate structures 200B to 200C and 200E to 200F (corresponding to the embodiments N-LVT, N-SVT, P-LVT, and P-uLVT, respectively).

[0034] In some embodiments, the dipole layer 300 may comprise a dipole material suitable for N devices (also referred to as N-dipole material), which, as non-limiting examples, may include a metal oxide material such as lanthanum oxide (La₂O₃), yttrium oxide (Y₂O₃), magnesium oxide (MgO), strontium oxide (SrO), or combinations thereof. The metal oxide species in the metal oxide material form dipole moments with the species (e.g., silicon oxide) of IL 210, thereby generating differentials in electrical potential of the overall gate structures 200A to 200F. In this disclosure, such differentials can influence the work function of the gate structures 200A to 200F, and therefore the limiting voltage Vt, without affecting the type(s) and / or number of work function metal layers (to be formed in subsequent fabrication processes) of the gate structures 200A to 200F.For NFET devices such as gate structures 200A to 200C, the N-dipole material can decrease the threshold voltage Vt. For PFET devices such as gate structures 200D to 200F, the N-dipole material can increase the threshold voltage Vt. In alternative embodiments where a P-dipole material is used to implement dipole layer 300, the threshold voltage Vt is increased for NFET devices such as gate structures 200A to 200C, but decreased for PFET devices such as gate structures 200D to 200F.

[0035] In some embodiments, the dipole deposition process 290 includes an ALD process. In some embodiments, the ALD process includes La(fAMD)3 or La(thd)3 and O3 as precursors. The ALD process allows precise control of the thickness 310 of the deposited dipole layer 300. In some embodiments, the thickness 310 is in a range between approximately 0.5 nm and approximately 1.5 nm.

[0036] It should be noted that, since the dipole layer 300 is deposited directly on the upper surface of the IL 210 for gate structures 200A and 200D, the dipole layer 300 has the strongest effect on the IL 210 for gate structures 200A and 200D. Meanwhile, for gate structures 200B and 200E, the dipole layer 300 is separated from the IL 210 by the hard mask layer 260, which, as explained above, has a thickness of 265 mm. Thus, the dipole layer 300 has a lesser effect on the IL 210 for gate structures 200B and 200E. Finally, the dipole layer 300 for the gate structures 200C and 200F is separated from the IL 210 by the hard mask layer 260 and the hard mask layer 230, which can have a combined thickness of 330 (e.g., a sum of the thicknesses 235 and 265 as explained above). Since the combined thickness 330 is greater than the thickness 265, the dipole layer 300 can have the least effect on the IL 210 for the gate structures 200C and 200F.

[0037] The multiple structuring processes explained above result in different distances or separations between the IL 210 and the dipole layer 300 for the different transistor types. For N-uLVT and P-SVT transistors, there is no separation between the dipole layer 300 and the IL 210, and thus the dipole layer 300 can have the strongest effect on the IL 210 for these transistors. For N-LVT and P-LVT transistors, there is an intermediate separation (caused by the presence of the hard mask layer 260) between the dipole layer 300 and the IL 210, and thus the dipole layer 300 can have an intermediate effect on the IL 210 for these transistors. For the N-SVT and P-uLVT transistors, there is a relatively large separation between the dipole layer 300 and the IL 210, and thus the dipole layer 300 can have the weakest effect on the IL 210 for these transistors.

[0038] Now, with reference to Fig. 7A to 7F, a dipole insertion process 350 is performed on the gate structures 200A to 200F. In some embodiments, the dipole insertion process 350 can include a thermal process, such as an annealing process. In some embodiments, the annealing process can be performed at an annealing temperature between approximately 600 degrees Celsius and approximately 800 degrees Celsius using nitrogen gas. Such a high annealing temperature causes the metal ions in the dipole layers 300 to penetrate (or react with) the IL 210. The metal ions can increase the polarity of the IL 210 and can therefore be used to adjust the limiting voltage Vt of the gate structures 200A to 200F. The dipole penetration can be Fig. 7A to 7F are optically represented as dipole-penetrated sections 210A of the IL 210.

[0039] As explained above, for the NFETs, the gate structures 200A, 200B, and 200C each exhibit different levels of separation between the IL 210 and the dipole layer 300, with gate structure 200A having the least separation between its IL 210 and its dipole layer 300, and gate structure 200C having the greatest separation between its IL 210 and its dipole layer 300. Consequently, the IL 210 of gate structure 200A can exhibit a greater amount of dipole penetration than the IL 210 of gate structure 200B, and vice versa. Similarly, for the PFETs, the IL 210 of the 200D gate structure can have a greater amount of dipole penetration than the IL 210 of the 200E gate structure, and the IL 210 of the 200E gate structure can have a greater amount of dipole penetration than the IL 210 of the 200F gate structure.

[0040] The differences in dipole penetration can be represented by the different depths to which the dipole-penetrated sections 210A extend into the IL 210. For example, the dipole-penetrated sections 210A of gate structures 200A to 200C can have depths of 370 to 372, and the dipole-penetrated sections 210A of gate structures 200D to 200F can each have depths of 380 to 382. The depths 370 to 372 and 380 to 382 can also be referred to as the thicknesses of the dipole-penetrated sections 210A. In some embodiments, the depths 370 to 372 and 380 to 382 can each be in a range between approximately 0.2 nm and approximately 0.3 nm.

[0041] Due to the presence of hard mask layer 260 in gate structures 200B and 200E, and the presence of hard mask layers 260 and 230 in gate structures 200C and 200F, depth 370 is greater than depth 371, which is greater than depth 372, and depth 380 is greater than depth 381, which is greater than depth 382. Mathematically, depth 370 is greater than depth 371, which is greater than depth 372, and depth 380 is greater than depth 381, which is greater than depth 382.Again, this is because the absence of a hard mask layer between the IL 210 and the dipole layer 300 in gate structures 200A and 200D allows the metal ions of the dipole layer 300 to be driven deepest into the IL 210, and the presence of the hard mask layer 260 between the IL 210 and the dipole layer 300 in gate structures 200B and 200E allows the metal ions of the dipole layer 300 to be driven less deep into the IL 210, and the presence of both hard mask layers 260 and 230 between the IL 210 and the dipole layer 300 in gate structures 200C and 200F allows the metal ions of the dipole layer 300 to be driven least deep into the IL 210. The different depths 370 to 372 allow for different settings of the limit voltages Vt for the gate structures 200A to 200C.Likewise, the different depths 380 to 382 allow for different settings of the limit voltages Vt for the gate structures 200D to 200F.

[0042] It is understood that within each dipole-penetrated section 210A, the concentration of the dipole material (e.g., the metal ions) can increase as it approaches the dipole layer 300. In other words, the concentration of the dipole material can reach a peak at an interface between the dipole layer 300 and the dipole-penetrated section 210A and then gradually decreases as the distance from the interface (or the upper surface of the dipole-penetrated section) increases (e.g., as it penetrates deeper towards the substrate 110).

[0043] It should be noted that depth 370 can be equal to depth 380, but does not have to be; depth 371 can be equal to depth 381, but does not have to be; and depth 372 can be equal to depth 382, ​​but does not have to be. Furthermore, the values ​​of depths 372 and 382 can approach 0 in some embodiments. In other words, the hard mask layers 230 and 260 essentially block or prevent the penetration of material from the dipole layer 300 into the IL 210.

[0044] It is also understood that in some embodiments, the differences between gate structures 200A to 200C (and gate structures 200D to 200F) regarding the effectiveness of dipole driving may be manifested by the different concentration levels of the dipole material (e.g., metal ions) in the dipole-penetrated sections 210A of IL 210, instead of or in addition to the different depths 370 to 372 and 380 to 382. In other words, the dipole metal ion concentration in the dipole-penetrated section 210A of gate structure 200A may exceed the dipole metal ion concentration in the dipole-penetrated section 210A of gate structure 200B, and the dipole metal ion concentration in the dipole-penetrated section 210A of gate structure 200B may exceed the dipole metal ion concentration in the dipole-penetrated section 210A of gate structure 200B. Exceed 200°C.Similarly, the dipole metal ion concentration in the dipole-penetrated section 210A of gate structure 200D can exceed the dipole metal ion concentration in the dipole-penetrated section 210A of gate structure 200E, and the dipole metal ion concentration in the dipole-penetrated section 210A of gate structure 200E can exceed the dipole metal ion concentration in the dipole-penetrated section 210A of gate structure 200F. In some embodiments, the differences between the dipole metal ion concentration levels between gate structures 200A and 200F can exist regardless of whether the differences between depths 370 to 372 are present (or whether the differences between depths 380 to 382 are present), or vice versa.

[0045] Now, with reference to Fig. In embodiments 8A to 8F, a dipole removal process 400 is carried out to remove the remaining sections of the dipole layers 300, for example, the sections of the dipole layer 300 that contain IL 210 or do not react with it. In some embodiments, the dipole removal process 400 includes an etching process, such as a wet etching process, a dry etching process, or a combination thereof. In some embodiments, an etchant used in such an etching process may include hydrochloric acid (HCl), alkali (NH4), an oxidizing agent, or another suitable etchant.

[0046] Now, with reference to Fig. 9A to 9F, a layer removal process 410 is performed to remove the hard mask layers 260 and 230. In some embodiments, the hard mask layer removal process 410 includes an etching process, such as a wet etching process. After performing the hard mask layer removal process 410, the dipole-penetrated sections 210A of IL 210 are exposed for all transistors discussed herein.

[0047] With reference to Fig. In 10A to 10F, a gate dielectric deposition process 420 is carried out to form a gate dielectric layer 430 over the dipole-penetrated sections 210A of IL 210. In some embodiments, the gate dielectric deposition process 420 includes an ALD process to precisely control the thickness of the deposited gate dielectric layer 430. In some embodiments, the ALD process is carried out using between 20 and 40 deposition cycles and in a temperature range between approximately 200°C and approximately 300°C. In some embodiments, the ALD process uses HfCl4 and / or H2O as precursors and / or adds LaCl3 as a lanthanum doping source. Such an ALD process can form the gate dielectric layer with a thickness 440 that can be in the range between approximately 1.0 nm and approximately 2.0 nm.

[0048] In some embodiments, the gate dielectric layer 430 comprises a material with a high k-value, which can refer to dielectrics that have a high dielectric constant greater than that of silicon oxide (k ≈ 3.9). Examples of dielectrics with a high k-value include HfO₂, HfSiO₂, HfSiON₂, HfTaO, HfTiO₂, HfZrO₂, ZrO₂, Al₂O₃, HfO₂-Al₂O₃, TiO₂, Ta₂O₅, La₂O₃, Y₂O₃, or combinations thereof. In other embodiments, the gate dielectric layer 430 may comprise a material without a high k-value, such as silicon oxide.

[0049] It is understood that, since the lower surface of the gate dielectric layer 430 forms an interface with the dipole-penetrated section 210A of the IL below, a certain amount of dipole material (e.g., metal ions) can diffuse from the dipole-penetrated section 210A into the gate dielectric layer 430. Thus, the lower section of the gate dielectric layer 430 can have a higher content of dipole material than the rest of the gate dielectric layer 430.

[0050] Now, with reference to Fig. In embodiments 11A to 11F, several deposition processes 450 are performed to form a protective layer 460 over the gate dielectric layer 430, and a cover layer 470 over the protective layer 460. In some embodiments, the deposition processes 450 include ALD processes. In some embodiments, the protective layer 460 comprises TiN, and the cover layer 470 comprises TiSiN or SiO2. In some embodiments, the protective layer 460 or the cover layer 470 may have a thickness in the range of approximately nm to approximately 2.0 nm.

[0051] Now, with reference to Fig. 12A to 12F, an annealing process 480 is performed. In some embodiments, the annealing process 480 may include an in-place post-metal annealing process (iPMA process). The annealing process 480 improves the quality of the gate dielectric layer 430. The protective layer 460 and / or the cover layer 470 can help prevent oxygen diffusion into the gate dielectric layer 430 during the annealing process 480, since the gate dielectric layer 430 would otherwise be exposed to an oxygen-containing environment during the annealing process 480 if the protective layer 460 and the cover layer 470 had not been formed. Oxygen diffusion in the gate dielectric layer 430 could degrade the quality of the gate dielectric layer 430, and therefore the formation of the protective layers 460 and 470 helps to reduce such unwanted oxygen diffusion, thus improving the quality of the gate dielectric layer 430.

[0052] It is understood that the tempering process can cause further diffusion of the dipole material from the dipole-penetrated section 210A to the gate dielectric layer 430. Thus, the gate dielectric layer 430 can also have a dipole-penetrated section 430A on or near its lower surface. The presence of the dipole-penetrating section 430A at the bottom of the gate dielectric layer 430 can also be one of the unique physical properties of the gate structures fabricated according to the embodiments of this disclosure.

[0053] Now, with reference to Fig. In embodiments 13A to 13F, a deposition process 500 is carried out to form a cover layer 510 over the cover layer 470. In some embodiments, the deposition process 500 comprises an ALD process. In some embodiments, the cover layer 510 comprises silicon oxide or titanium silicon nitride.

[0054] Now, with reference to Fig. A tempering process 520 is performed on components 14A to 14F, which further improves the quality of the gate dielectric layer 430. Again, the tempering process 520 can be carried out in an oxygen-containing environment. Similar to the cover layer 470 and the protective layer 460, the cover layer 510 prevents oxygen from diffusing into the gate dielectric layer 430. This improves the quality of the gate dielectric layer 430.

[0055] Now, with reference to Fig. In sections 15A to 15F, the cover layers 510 and 470 and the protective layer 460 are removed, for example, by using one or more etching processes. At this stage of the manufacturing process, the gate dielectric layers 430 (which are of good quality due at least in part to the performance of the tempering process 480 and 520) are disclosed.

[0056] Now, with reference to Fig. In each of the gate structures 200A to 200F, a phosphorus exit metal layer 530 is formed over the gate dielectric layer 430. The phosphorus exit metal layer 530 can be formed using an ALD, CVD, PVD, or combination thereof deposition process. In some embodiments, the phosphorus exit metal layer 530 can be formed in an ALD process using TiCl4 and / or NH3 as a precursor. In some embodiments, the phosphorus exit metal layer 530 comprises titanium nitride (TiN). In other embodiments, the phosphorus exit metal layer 530 can comprise a different type of exit metal material, such as TaN or WCN. In some embodiments, the phosphorus exit metal layer 530 can be formed to have a thickness in the range of approximately 1.0 nm to approximately 2.5 nm.

[0057] A structured photoresist layer 540 is formed over the phosphorus exit metal layer 530 in gate structures 200D to 200F, corresponding to the P-SVT, P-LVT, and P-uLVT embodiments, respectively, but not over the phosphorus exit metal layer 530 in gate structures 200A to 200C, corresponding to the N-uLVT, N-LVT, and N-SVT embodiments, respectively. In some embodiments, the structured photoresist layer 540 may comprise a photosensitive material and an antireflective material. The structured photoresist layer 540 can be used to structure the underlying phosphorus exit metal layer 530.

[0058] Now, with reference to Fig. In gate structures 17A to 17F, a lithography process 560 is performed to pattern the phosphorus exit metal layer 530. The patterned photoresist layer 540 can protect the underlying portions of the phosphorus exit metal layer 530 while the exposed portions of the phosphorus exit metal layer 530 are removed. In this way, the remaining portions of the phosphorus exit metal layer 530 are formed above the gate dielectric layer 430 in gate structures 200D to 200F, but not above the gate dielectric layer 430 in gate structures 200A to 200C. After the phosphorus exit metal layer 530 has been patterned, the patterned photoresist layer 540 is removed, for example, using a photoresist ash or stripping process. The remaining P-work function metal layer 530 serves as a section of the gate electrode for the gate structures 200D to 200F to adjust their work function.

[0059] Now, with reference to Fig. Several deposition processes 600 were carried out on gate structures 18A to 18F to form an N-exit work metal structure for gate structures 200A to 200F. For example, the N-exit work metal structure can include a protective layer 610 formed over the gate dielectric layer 430 for gate structures 200A to 200C and over the P-exit work metal layer 530 for gate structures 200D to 200F, an N-exit work metal layer 620 formed over the protective layer 610, and a protective layer 630 formed over the N-exit work metal layer 620. The protective layer 610 can prevent oxidation of the N-exit work metal layer 620 by the gate dielectric layer 430. In some embodiments, the protective layer 610 of the gate structures 200D to 200F is thicker than the protective layer 610 of the gate structures 200A to 200C, which prevents the protective layer 610 from oxidizing more effectively.The protective layer 630 significantly prevents or reduces oxygen diffusion into the N-exit work metal layer 620 from above. The N-exit work metal layer 620 serves as a section of the gate electrode for the gate structures 200A to 200C for adjusting their work function.

[0060] In some embodiments, the protective layer 610 and the protective layer 630 can each comprise TiN, and the N exit work metal layer 620 can comprise titanium aluminum carbide (TiAlC). Thus, the N exit work metal structure can comprise a sandwich-like structure in which the N exit work metal layer 620 is sandwiched between two protective layers 610 and 630. In other embodiments, the N exit work metal layer 620 can comprise a different type of aluminum-based exit work metal, such as TiAl, TaAl, or TaAlC. The oxygen content in the N exit work metal structure is less than approximately 1%. A cover layer 650 can also be formed over the protective layer 630. In some embodiments, the cover layer 650 can comprise silicon oxide.

[0061] In some embodiments, the protective layer 610, the N exit work metal layer 620, the protective layer 630, and the cover layer 650 can all be formed in a single on-site process within the same tool using a high-vacuum system. For example, the protective layer 610 can be formed in a first chamber of the tool using an ALD process. The wafer, comprising the gate structures 200A to 200F, can then be transferred (essentially under vacuum conditions) to a second chamber of the tool, with the N exit work metal layer 620 being formed in a separate ALD process. Silic gas penetration (SiH4 penetration) can also be used to prevent oxidation of the N exit work metal layer 620. Therefore, the wafer, which includes the gate structures 200A to 200F, will be transferred to a third chamber of the tool (again essentially under vacuum conditions), with the protective layer 630 being formed in a different ALD process.The 650 cover layer can also be formed in the third chamber of the tool.

[0062] Now, with reference to Fig. In 19A to 19F, several deposition processes 670 are performed to form an adhesive layer 680 over the cover layer 650, and to form a filler metal layer 690 over the adhesive layer 680. In some embodiments, the deposition processes 670 may include ALD, CVD, PVD, or combinations thereof. In some embodiments, the adhesive layer 680 may comprise TiN or TaN, and the filler metal layer 690 may comprise tungsten (W), cobalt (Co), ruthenium (Ru), or iridium (Ir). In some embodiments, the filler metal layer 690 may be formed by first forming a fluorine-free tungsten (FFW) over the cover layer 680, followed by forming a low-fluorine tungsten (LFW) over the FFW, and then forming tungsten over the LFW. The filler metal layer 690 serves as the main conduction section of the gate electrode of gate structures 200A to 200F. In some embodiments, the adhesive layer 680 can have a thickness in a range between approximately 1.0 nm and approximately 1.0 nm.2.5 nm and the FFW can be formed, lying in a range between approximately 2.0 nm and approximately 4.0 nm.

[0063] Fig. 2A to 2F to Fig. 19A to 19F correspond to a first embodiment of this disclosure. A second embodiment of this disclosure is described in Fig. Figures 20A to 20F are illustrated. For the sake of simplicity, clarity, and consistency, similar components between the first and second embodiments are labeled identically, and the associated descriptions for these similar components can be omitted below.

[0064] One difference between the first embodiment and the second embodiment is that the gate structures 200A to 200F in the second embodiment do not have a protective layer 610. Thus, the N-exit metal layer 620 is formed directly on the gate dielectric layer 430 for gate structures 200A to 200C, the N-exit metal layer 620 is formed directly on the P-exit metal layer 530 for gate structures 200D to 200F, and the P-exit metal layer 530 is formed directly on the gate dielectric layer 430 for gate structures 200D to 200F.

[0065] Another difference between the first embodiment and the second embodiment is that a P-dipole layer (instead of the N-dipole layer) is formed over the IL 210. In some embodiments, the P-dipole layer may comprise aluminum oxide (Al₂O₃), niobium oxide (Nb₂O₅), titanium oxide (TiO₅), boron oxide (B₂O₃), phosphorus pentoxide (P₂O₅), or phosphorus trioxide (P₂O₃). A dipole insertion process similar to the dipole insertion process 350 (see Fig. 7A to 7F) is implemented in the second embodiment to form the dipole-penetrated sections 210A of the IL 210.

[0066] Another difference between the first embodiment and the second embodiment is that the content of dipole material is lowest in gate structures 200A and 200D and highest in gate structures 200C and 200F, which is the opposite of the first embodiment. For example, for the in Fig. The NFETs shown in sections 20A to 20C have dipole-penetrated sections 210A of the IL 210 depths 710, 711 and 712 for the gate structures 200A, 200B and 200C respectively. For the in Fig. The PFETs shown in 20D to 20F have dipole-penetrated sections 210A of the IL 210 with depths of 720, 721, and 722 for the gate structures 200D, 200E, and 200F, respectively. While in the first embodiment, depth 370 > depth 371 > depth 372, in the second embodiment, depth 710 < depth 711 < depth 712. Similarly, while in the first embodiment, depth 380 > depth 381 > depth 382, ​​in the second embodiment, depth 720 < depth 721 < depth 722.

[0067] Alternatively, the differences in dipole material content in IL-210 can manifest as differences in concentration levels. For example, for the in Fig. For the NFETs shown in 20A to 20C, the IL 210 of gate structure 200A exhibits the lowest concentration level of the P-dipole material, the IL 210 of gate structure 200C can exhibit the highest concentration level of the P-dipole material, and the IL 210 of gate structure 200B can exhibit an intermediate concentration level of the P-dipole material. For the in Fig. In the PFETs shown from 20D to 20F, the IL 210 of gate structure 200D has the lowest concentration level of the P-dipole material, the IL 210 of gate structure 200F can have the highest concentration level of the P-dipole material, and the IL 210 of gate structure 200E can have an intermediate concentration level of the P-dipole material.

[0068] The differences in dipole material content between gate structures 200A to 200F can be achieved by configuring the distances between the P-dipole layer and the IL 210, for example by selectively forming hard mask layers (e.g., similar to hard mask layers 230 and 260) over different gate structures 200A to 200F. For example, two hard mask layers (similar to hard mask layers 230 and 260) can be formed. Fig. 6C and Fig. 6F) for the gate structures 200A and 200D, a hard mask layer (similar to the hard mask layer 260 from Fig. 6B and Fig. 6E) for the gate structures 200B and 200E, and no hard mask layers can be formed for the gate structures 200C and 200F.

[0069] Due to these differences explained above between the first embodiment and the second embodiment, the gate structures 200A to 200F of the second embodiment may be able to set the limit voltage differently than the gate structures 200A to 200F of the first embodiment.

[0070] Fig. Figures 21A to 21F illustrate a third embodiment of this disclosure. For the sake of simplicity, clarity, and consistency, similar components between the first, second, and third embodiments are labelled identically, and the associated descriptions for these similar components may be omitted below.

[0071] With reference to Fig. In the third embodiment, gate structures 200A to 200C can be substantially similar to gate structures 200A to 200C of the first embodiment. For example, the dipole-penetrated sections 210A of IL 210 can comprise N-dipole materials, with gate structure 200A having the highest content of N-dipole material, gate structure 200C having the lowest content, and gate structure 200B having an immediate content of N-dipole material. This can be manifested, for example, as depth 370 > depth 371 > depth 372. Likewise, in the third embodiment, as in the first embodiment, the protective layer 610 is formed between the gate dielectric layer 430 and the N exit metal layer 620 for gate structures 200A to 200C.

[0072] The gate structures 200D to 200F of the third embodiment can be substantially similar to the gate structures 200D to 200F of the second embodiment. For example, the dipole-penetrated sections 210A of the IL 210 can comprise P-dipole materials, with gate structure 200F having the highest content of P-dipole material, gate structure 200D having the lowest content, and gate structure 200E having an immediate content of P-dipole material. This can be manifested, for example, as depth 722 > depth 721 > depth 720. Furthermore, in the third embodiment, as in the second embodiment, the P-exit metal layer 530 is formed directly on the gate dielectric layer 430 for gate structures 200D to 200F.

[0073] It is noted that in the first and second embodiments, the NFETs and PFETs have different exit work metals but the same type of dipole layers (e.g., both with an N-dipole material or both with a P-dipole material). In contrast, in the third embodiment, the NFETs and PFETs have the same exit work metals (e.g., layers 530, 620, and 630) but different types of dipole materials. For example, the NFETs made of Fig. 21A to 21C the N-dipole materials and the NFETs from Fig. 21D to 21F feature the P-dipole materials.

[0074] Fig. Figure 22 illustrates a diagrammatic fragmentary cross-sectional view of a section of the IC device 90 according to embodiments of the disclosure. Again, for the sake of clarity and consistency, similar elements are shown in Fig. 2A to 2F to 21A to 21F in Fig. 22 are labelled the same.

[0075] Now, with reference to Fig. 22 the section of the IC device 90 the above with reference to Fig. Figures 1A to 1B describe the fin structure 120. The section of the IC device 90 also includes an interlayer dielectric (ILD) 750 formed over the fin structure 120. In some embodiments, the ILD 750 may comprise a dielectric, such as silicon oxide, silicon nitride, silicon oxynitride, TEOS-formed oxide, PSG, BPSG, a low-k dielectric, another suitable dielectric, or combinations thereof. Examples of low-k dielectrics include FSG, carbon-doped silicon oxide, Black Diamond® (Applied Materials of Santa Clara, California), xerogel, aerogel, amorphous fluorinated carbon, parylene, BCB, SiLK (Dow Chemical, Midland, Michigan), polyimide, another low-k dielectric, or combinations thereof.

[0076] Section 90 of the IC device further comprises gate structures, for example, an NFET gate structure 760 and a PFET gate structure 770. The NFET gate structure 760 can be manufactured according to any embodiment of the gate structures 200A / 200B / 200C described above, and the PFET gate structure 770 can be manufactured according to any embodiment of the gate structures 200D / 200E / 200F described above. The NFET gate structure 760 and the PFET gate structure 770 are each located above and wrapped around the fin structure 120. The NFET gate structure 760 and the PFET gate structure 770 are also separated from each other by sections of the ILD 750.

[0077] The NFET gate structure 760 and the PFET gate structure 770 each comprise the IL 210. As explained above, the IL 210 contains a dipole-penetrated section 210A, which is formed by creating the dipole layer directly above the top surface of the IL 210, followed by a annealing process to drive the dipole material into the IL 210. The IL 210 for the NFET gate structure 760 and the IL 210 for the PFET gate structure 770 can be constructed approximately according to the first embodiment and the second embodiment described above with reference to Fig. 2A to 2F to 20A to 20F, which are explained, comprise the same type of dipole materials. IL 210 for the NFET gate structure 760 and IL 210 for the PFET gate structure 770 can be described, for example, according to the third embodiment described above with reference to Fig. Sections 21A to 21F are explained, and also include different types of dipole materials.

[0078] The NFET gate structure 760 and the PFET gate structure 770 also include the gate dielectric layer (which may be a high k-value dielectric layer) 430, formed over the IL 210. It should be noted that, due to the diffusion of dipole material from the IL 210 into the gate dielectric layer 430, the gate dielectric layer 430 may have a dipole-penetrated section 430A at or near its lower surface.

[0079] The NFET gate structure 760 and the PFET gate structure 770 further comprise one or more exit metal layers 780 formed above the gate dielectric layer 430. The exit metal layers 780 may comprise one or more of the various layers 610 to 680 described above. The exit metal layers 780 for the NFET gate structure 760 and the exit metal layers 780 for the PFET gate structure 770 may comprise different types or numbers of layers, for example, according to the first embodiment and the second embodiment described above with reference to Fig. Figures 2A to 2F to 20A to 20F are explained. The exit work metal layers 780 for the NFET gate structure 760 and the exit work metal layers 780 for the PFET gate structure 770 can also comprise the same types and numbers of layers, for example, according to the third embodiment explained above with reference to Figures 21A to 21F. The filler metal 690 explained above is formed over the exit work metal layer 780 and over the ILD 750. A CMP process can be performed to planarize the top surface of the filler metal 690.

[0080] In conventional devices, the thicknesses of the exit-work metal layers 780 may need to be manipulated to adjust the gate voltage. For example, different thicknesses of the exit-work metal layers 780 can lead to different gate voltage values. However, as the exit-work metal layers 780 become thicker, there is less space for the filler metal 690. In other words, the gate fill window is reduced, which can lead to a higher than optimal gate resistance. In contrast, this disclosure can achieve gate voltage adjustment via dipole doping and mask structuring to cause different amounts of dipole material to penetrate the interface layer for different types of devices. Therefore, it is not necessary to adjust the thickness of the exit-work metal layers 780 to achieve different gate voltages according to this disclosure.As a result, the gate filling window is not unduly shortened or reduced, and there is sufficient space for the formation of the filling material 690. In this way, the gate resistance of the IC device 90 is reduced compared with the gate resistance of conventional devices.

[0081] It is understood that at least sections of the NFET gate structure 760 and PFET gate structure 770 can be formed using the gate replacement process explained above. Due to the gate replacement process, the exit work metal layer 780 is formed to partially fill a trench, resulting in the exit work metal layer 780 having a "U-shaped" cross-sectional profile. It is understood that in some embodiments, such as the high k-value embodiments last described, the gate dielectric layer 430 (or IL 210) may also be formed to have a similar U-shaped cross-sectional profile.

[0082] Fig. Figure 23 illustrates a diagrammatic cross-sectional side view of a section of an IC device 800 manufactured according to embodiments of this disclosure, wherein the IC device 800 is a gate-all-around device (GAA device) and may hereinafter be referred to as a GAA device 800. It is understood that the GAA device 800 may be an NFET in some embodiments or a PFET in other embodiments.

[0083] With reference to Fig. 23 The cross-sectional view of the GAA device 800 is taken along an XZ plane, with the X direction (the same X direction as in Fig. 1A) the horizontal direction and the Z-direction (the same Z-direction as in Fig. 1A) the vertical direction. The GAA device 800 comprises a fin structure 810, which may be similar to the fin structure 120 explained above. In some embodiments, the fin structure 810 comprises silicon. The GAA device 800 comprises source / drain features 820, which are similar to the source / drain features 122 explained above. In embodiments where the GAA device 800 is an NFET, the source / drain features 820 comprise silicon phosphorus (SiP). In embodiments where the GAA device 800 is a PFET, the source / drain features 820 comprise silicon germanium (SiGe).

[0084] The GAA device 800 comprises several channels, for example channels 830 to 333, as shown in Fig. Figure 23 shows that channels 830 to 833 each comprise a semiconductor material, for example, silicon or a silicon compound. Channels 830 to 833 are nanostructures (e.g., having sizes on the order of a few nanometers) and can each have an elongated shape extending in the X direction. In some embodiments, channels 830 to 833 can each have a nanowire shape, a nanosheet shape, a nanotube shape, etc. The cross-sectional profile of the nanowire, nanosheet, or nanotube can be round / circular, square, rectangular, hexagonal, elliptical, or a combination thereof.

[0085] In some embodiments, the lengths (e.g., measured in the X direction) of channels 830 to 833 may differ from one another. For example, the length of channel 830 may be shorter than the length of channel 831, which may be shorter than the length of channel 832, which may be shorter than the length of channel 833. In some embodiments, the individual channels 830 to 833 may not have uniform thicknesses. For example, the two ends of each of the channels 830 to 833 may be thicker than a middle section of each of the channels 830 to 833. Thus, each of the channels 830 to 833 may have a "dogbone" shape.

[0086] In some embodiments, the distance (e.g., measured in the Z-direction) between channels 830 to 833 (from each channel to adjacent channels) lies in a range between approximately 8 nanometers (nm) and approximately 12 nm. In some embodiments, the thickness (e.g., measured in the Z-direction) of each of channels 830 to 833 lies in a range between approximately 5 nm and approximately 8 nm. In some embodiments, the width (e.g., measured in the Y-direction) is... Fig. 1A measured) each of channels 830 to 833 in a range between approximately 15 nm and approximately 150 nm.

[0087] Several interface layers (ILs) 840 are formed on the upper and lower surfaces of the channels 830 to 833. The ILs 840 can be substantially similar to the IL 210 explained above. For example, according to embodiments of this disclosure, a dipole layer can be formed directly on the ILs 840 during the manufacture of the GAA device 800. Subsequently, a dipole insertion process such as the dipole insertion process 350, described above with reference to Fig. As explained in sections 7A to 7F, the process is carried out to drive the metal ions of the dipole material into the ILs 840. Accordingly, each IL 840 can have a dipole-penetrated section similar to the dipole-penetrated section 210A explained above. For simplicity, these dipole-penetrated sections are referred to in Fig. 23 not specifically illustrated. Nevertheless, it is understood that different types of GAA devices (e.g., uLVT vs. LVT vs. SVT) may exhibit different levels of dipole material in the ILs 840, which may manifest as different depths of the dipole-penetrated sections or different concentration levels of the dipole material within the ILs 840.

[0088] The GAA device 800 also includes gate structures arranged above and between the channels 830 to 833. The gate structures may include gate dielectric layers 850, which may be similar to the gate dielectric layer 430 explained above. In some embodiments, the gate dielectric layers 850 include a gate dielectric with a high k-value. It is understood that the gate dielectric layers 850 may also have dipole-penetrated sections near their interfaces with the ILs 840. However, these dipole-penetrated sections are not specifically illustrated herein for the sake of simplicity. The gate structures further include one or more exit-work metal layers 860, which may comprise one or more of the various layers 610 to 680 explained above.In embodiments where the GAA device 800 is an NFET, the one or more exit work metal layers 860 comprise N exit work metal layers, such as TiAlC. In embodiments where the GAA device 800 is an NFET, the one or more exit work metal layers 860 comprise P exit work metal layers, such as TiN.

[0089] The gate structures also include filler metals 880, which can be similar to the filler metal 690 described above. In the section of the gate structure formed over channels 830 to 833, the filler metal 880 is formed over one or more exit work metal layers 860. The one or more exit work metal layers 860 are U-shaped and wrap around the filler metal 880, and the gate dielectric layer 850 is also U-shaped and wraps around the one or more exit work metal layers 860. In sections of the gate structures formed between channels 830 to 833, the filler metal 880 is circumferentially surrounded by the one or more (in cross-sectional view) exit work metal layers 860, which are then circumferentially surrounded by the gate dielectric layer 850.It is understood that the gate structures may include an adhesive layer formed between the one or more exit working layers 860 and the filler metal 880 to increase adhesion. However, for the sake of simplicity, such an adhesive layer is not specifically illustrated herein.

[0090] The GAA device 800 also includes gate spacers 890 and inner spacers 900, which are arranged on the side walls of the gate dielectric layer 850. The inner spacers 900 are also arranged between the channels 830 to 833. The gate spacers and the inner spacers 900 can comprise a dielectric, for example, a material with a low k-value such as SiOCN, SiON, SiN, or SiOC.

[0091] The GAA device 800 further comprises source / drain contacts 920 formed over the source / drain features 820. The source / drain contacts 920 may comprise a conductive material such as cobalt, copper, aluminum, tungsten, or combinations thereof. The source / drain contacts 920 are surrounded by barrier layers, for example, barrier layers 930 and 940, which help to prevent or reduce the diffusion of materials to and from the source / drain contacts 920. In some embodiments, the barrier layer 930 comprises TiN, and the barrier layer 940 comprises SiN. A silicide layer 960 may also be formed between the source / drain features 820 and the source / drain contacts 920 to reduce the source / drain contact resistance. In some embodiments, the silicide layer 960 may comprise a metal silicide material, such as cobalt silicide.

[0092] The GAA device 800 further comprises an interlayer dielectric (ILD) 980, which is similar to the ILD 750 discussed above. The ILD 980 provides electrical insulation between the various components of the GAA device 800, as explained above, such as between the gate structures and the source / drain contacts 920.

[0093] Further details regarding the manufacture of GAA devices are disclosed in US Patent No. 10,164,012 entitled “Semiconductor Device and Manufacturing Method Thereof”, granted on December 25, 2018, and in US Patent No. 10,361,278 entitled “Method of Manufacturing a Semiconductor Device and a Semiconductor Device”, granted on July 23, 2019, the disclosures of which are hereby incorporated by reference in their entirety.

[0094] Fig.Figure 24 is a flowchart illustrating a process 1000 for fabricating a semiconductor structure. The process 1000 includes a step 1010 for forming a mask layer over a first interface layer (IL) for a first gate structure and over a second IL for a second gate structure.

[0095] The procedure 1000 includes a step 1020 for structuring the mask layer to remove a section of the mask layer that is formed over the first IL.

[0096] Method 1000 includes a step 1030 for forming a dipole layer. A first section of the dipole layer is formed directly on the first IL. A second section of the dipole layer is formed on a remaining section of the mask layer that is arranged over the second IL.

[0097] The process 1000 includes a step 1040 for carrying out a dipole insertion process to drive a material of the dipole layer into the first IL and the second IL.

[0098] In some embodiments, the dipole insertion process forms a first dipole-penetrated section in the first IL and a second dipole-penetrated section in the second IL. The first dipole-penetrated section has a first depth. The second dipole-penetrated section has a second depth. The first depth is greater than the second depth.

[0099] In some embodiments, after the dipole insertion process has been carried out: the first IL has a first concentration level of the dipole layer material, the second IL has a second concentration level of the dipole layer material, and the first concentration level is larger than the second concentration level.

[0100] In some embodiments, the dipole insertion process includes a tempering process, which is carried out in a temperature range between approximately 600 degrees Celsius and 800 degrees Celsius and with a nitrogen gas.

[0101] It is understood that the process 1000 may include further steps that are performed before, during, or after steps 1010-1040. For example, process 1000 may include a step of removing the dipole layer and the remaining portion of the mask layer after performing the dipole insertion process. Process 1000 may also include a step of forming a gate dielectric layer directly on the first and second ILs. Process 1000 may also include a step of forming one or more exit-work metal layers over the gate dielectric layer. Process 1000 may also include a step of forming a filler metal over the one or more exit-work metal layers.In some embodiments, the formation of one or more exit work metal layers comprises: forming a first exit work metal layer over the gate dielectric layer; forming a second exit work metal layer over the first exit work metal layer; and forming a third exit work metal layer over the second exit work metal layer. In some embodiments, the first exit work metal layer and the third exit work metal layer have the same material composition, and the second exit work metal layer has a different material composition than the first and third exit work metal layers. In some embodiments, the first exit work metal layer, the second exit work metal layer, and the third exit work metal layer are formed in place using the same deposition tool.Other steps include the formation of vias, contacts or metal layers, etc.

[0102] In summary, this disclosure involves forming dipole layers directly on the interface layers and performing tempering processes to cause the dipole materials to diffuse through or into the interface layers. Different types of devices (e.g., uLVT vs. LVT vs. SVT) employ different lithography and structuring processes to generate varying amounts of dipole materials that penetrate their respective interface layers. For example, a first type of device can form the dipole layer directly on the interface layer, resulting in the greatest dipole concentration / depth in the interface layer for this first type of device. A second type of device can form a mask layer between the dipole layer and the interface layer, and the presence of this mask layer results in a lower dipole concentration / depth in the interface layer for this second type of device.A third type of device can incorporate a thicker mask layer (compared to the second type) between the dipole layer and the interface layer. The presence of this thicker mask layer results in an even lower dipole concentration / depth in the interface layer for this third type of device. The varying dipole concentrations / depths in the interface layer for different device types allow for different threshold voltages to be achieved. Furthermore, the dipole material can be N-type in some embodiments and P-type in others, which also influences the threshold voltage.

[0103] Based on the above explanations, it can be seen that this disclosure offers advantages over conventional source / drain vias. However, it is understood that not all advantages are explained herein, and that no particular advantage is required for any embodiment. One advantage is that this disclosure allows greater flexibility in setting the threshold voltage. For example, the formation of the dipole layer above the interface layer allows the dipole material to penetrate the interface layer. The amount of dipole material in the interface layer influences the transistor's threshold voltage. Therefore, dipole doping of the interface layer provides freedom in setting the transistor's threshold voltage. Furthermore, for different types of devices (e.g., uLVT vs. LVT vs.SVT devices employ various structuring processes to allow different amounts of dipole material to penetrate the interface layers of the respective devices. Again, since the amount of dipole material in the interface layer influences the interface voltage, these different types of devices can be configured to achieve different interface voltages suitable or desirable for their respective applications, further optimizing the flexibility of interface voltage adjustment. Interface voltage adjustment is further optimized by the fact that either an N-dipole material or a P-dipole material can be implemented.

[0104] Another advantage is the reduced gate resistance. More specifically, conventional limiting voltage methods rely on adjusting the thickness of the exit-work metal layers to achieve different limiting voltages. A thicker exit-work metal results in a smaller gate filling window (e.g., for the formation of tungsten as part of the metal gate electrode for a high k-value gate structure), which increases the gate resistance. In contrast, this discovery does not require manipulating the thickness of the exit-work metal layers to achieve different limiting voltages. Consequently, the gate filling window is larger (e.g., more space for the tungsten to fill the gate electrode), which reduces the gate resistance compared to conventional gate structures. Other advantages include compatibility with existing manufacturing processes and the ease and low cost of implementation.

[0105] The advanced lithography process, method, and materials described above can be used in many applications, including fin-type field-effect transistors (FinFETs). For example, the fins can be structured to create a relatively close spacing between features, for which the above disclosure is well suited. Furthermore, the spacers used to form the fins of FinFETs, also known as mandrels, can be processed according to the above disclosure.

[0106] One aspect of this disclosure comprises a semiconductor device. The semiconductor device includes a substrate, an interface layer formed over the substrate, a gate dielectric layer formed over the interface layer, and a metal gate electrode formed over the gate dielectric layer. The interface layer has a dipole-penetrated section.

[0107] Another aspect of this disclosure includes a semiconductor device. The semiconductor device comprises a first gate structure comprising a first interface layer, a first gate dielectric layer arranged above the first interface layer, and a first gate electrode arranged above the first gate dielectric layer. The semiconductor device also comprises a second gate structure comprising a second interface layer, a second gate dielectric layer arranged above the second interface layer, and a second gate electrode arranged above the second gate dielectric layer. The first interface layer comprises a different quantity of dipole material than the second interface layer.

[0108] Another aspect of this disclosure includes a method for manufacturing a semiconductor device. The method comprises: forming a mask layer over a first interface layer (IL) for a first gate structure and over a second IL for a second gate structure; structuring the mask layer to remove a portion of the mask layer formed over the first IL; forming a dipole layer, wherein a first portion of the dipole layer is formed directly on the first IL, and wherein a second portion of the dipole layer is formed on a remaining portion of the mask layer arranged over the second IL; and performing a dipole insertion process to insert a dipole layer material into the first IL and the second IL.

Claims

[1] Device comprising: a substrate (110); an interface layer (210) formed above the substrate (110), wherein the interface layer (210) has a dipole-penetrated section (210A); a gate dielectric layer (430) formed above the interface layer (210); and a metal gate electrode formed above the gate dielectric layer (430), wherein the dipole-penetrated section (210A) comprises yttrium oxide Y2O3, niobium oxide Nb2O5, titanium oxide TiO5, boron oxide B2O3, phosphorus pentoxide P2O5 or phosphorus trioxide P2O3. [2] Device according to claim 1, wherein a maximum concentration of a dipole material within the dipole-penetrated section (210A) decreases as the distance from an upper surface of the dipole-penetrated section (210A) increases. [3] Device according to claim 1 or 2, wherein a lower section of the gate dielectric layer (430) comprises a dipole material which is diffused from the interface layer (210). [4] Device according to one of the preceding claims, wherein: the metal gate electrode comprises an exit working metal component and a filler metal component formed above the exit working metal component; and the exit work metal component comprises an exit work metal layer (620), which is inserted between a first protective layer (610) and a second protective layer (630). [5] Device according to claim 4, wherein the exit working metal layer (620) comprises TiAlC and wherein the first protective layer (610) and the second protective layer (630) each comprise TiN. [6] Device according to any of the preceding claims, wherein the device comprises a FinFET device or a gate all-around device. [7] Device comprising: a first gate structure (200) comprising a first interface layer (210), a first gate dielectric layer (430) arranged above the first interface layer (210), and a first gate electrode arranged above the first gate dielectric layer (430); and a second gate structure (200) comprising a second interface layer (210), a second gate dielectric layer (430) arranged above the second interface layer (210), and a second gate electrode arranged above the second gate dielectric layer (430); wherein the first interface layer (210) comprises a different quantity of a dipole material than the second interface layer (210), wherein the dipole material comprises yttrium oxide Y2O3, niobium oxide Nb2O5, titanium oxide TiO5, boron oxide B2O3, phosphorus pentoxide P2O5 or phosphorus trioxide P2O3. [8] Device according to claim 7, wherein: a peak concentration of the dipole material in the first interface layer (210) occurs at an interface between the first interface layer (210) and the first gate dielectric layer (430); or a peak concentration of the dipole material in the second interface layer (210) occurs at an interface between the second interface layer (210) and the second gate dielectric layer (430). [9] Device according to claim 7 or 8, wherein: a first section (210A) of the first interface layer (210) comprises the dipole material, wherein the first section (210A) has a first depth or a first dipole concentration plane; and a second section (210A) of the second interfacial layer (210) comprises the dipole material, wherein the second section (210A) has a second depth that differs from the first depth, or a second concentration level that differs from the first dipole concentration level. [10] Device according to any one of the preceding claims 7 to 9, wherein: the first gate structure (200) is associated with a first limiting voltage; and the second gate structure (200) is associated with a second limiting voltage that differs from the first limiting voltage. [11] Device according to any one of the preceding claims 7 to 10, wherein the dipole material is a first dipole material and wherein the device further comprises: a third gate structure (200) comprising a third interface layer (210), a third gate dielectric layer (430) arranged above the third interface layer (210), and a third gate electrode arranged above the third gate dielectric layer (430); and a fourth gate structure (200) comprising a fourth interface layer (210), a fourth gate dielectric layer (430) arranged above the fourth interface layer (210), and a fourth gate electrode arranged above the fourth gate dielectric layer (430); where: the third interface layer (210) comprises a different quantity of a second dipole material than the fourth interface layer (210); the first gate structure (200) and the second gate structure (200) are components of N-transistors; and the third gate structure (200) and the fourth gate structure (200) are components of P-transistors. [12] Device according to claim 11, wherein the first dipole material and the second dipole material are both N-dipole materials or both P-dipole materials. [13] Device according to claim 11, wherein: the first dipole material comprises an N-dipole material; and the second dipole material comprises a P-dipole material. [14] Procedures, including: Forming a mask layer (230, 260) over a first interface layer, IL, (210) for a first gate structure (200) and over a second IL (210) for a second gate structure (200); Structuring the mask layer (230, 260) to remove a section of the mask layer (230, 260) formed over the first IL (210); Forming a dipole layer (300), wherein a first section of the dipole layer (300) is formed directly on the first IL (210) and wherein a second section of the dipole layer (300) is formed on a remaining section of the mask layer (230, 260) arranged above the second IL (210); and Performing a dipole insertion process (350) to insert a material of the dipole layer (300) into the first IL (210) and the second IL (210), wherein the dipole layer (300) comprises yttrium oxide Y2O3, niobium oxide Nb2O5, titanium oxide TiO5, boron oxide B2O3, phosphorus pentoxide P2O5 or phosphorus trioxide P2O3. [15] The method of claim 14, wherein: the dipole insertion process (350) forms a first dipole-penetrated section (210A) in the first IL (210) and a second dipole-penetrated section (210A) in the second IL (210); the first dipole-penetrated section (210A) has a first depth; the second dipole-penetrated section (210A) has a second depth; and the first depth is greater than the second depth. [16] Method according to claim 14 or 15, wherein after performing the dipole insertion process (350): the first IL (210) has a first concentration of the material of the dipole layer (300); the second IL (210) has a second concentration of the material of the dipole layer (300); and the first concentration value is greater than the second concentration value. [17] Method according to any one of the preceding claims 14 to 16, wherein the dipole insertion process (350) comprises a tempering process which is carried out in a temperature range between approximately 600 degrees Celsius and 800 degrees Celsius and with a nitrogen gas. [18] Method according to any one of the preceding claims 14 to 17, further comprising: Removal of the dipole layer (300) and removal of the remaining section of the mask layer (230, 260) after performing the dipole insertion process (350); Forming a gate dielectric layer (430) directly on the first IL (210) and the second IL (210); Forming one or more exit work metal layers (530, 620, 780, 860) over the gate dielectric layer (430); and Formation of a filler metal (690) over one or more exit working metal layers (530, 620, 780, 860). [19] Method according to claim 18, wherein forming the one or more exit working metal layers (530, 620, 780, 860) comprises: Formation of a first exit work metal layer (530, 620, 780, 860) over the gate dielectric layer (430); Formation of a second exit work metal layer (530, 620, 780, 860) over the first exit work metal layer (530, 620, 780, 860); and Forming a third exit work metal layer (530, 620, 780, 860) over the second exit work metal layer (530, 620, 780, 860); wherein: the first exit metal layer (530, 620, 780, 860) and the third exit metal layer (530, 620, 780, 860) have the same material compositions; and the second exit metal layer (530, 620, 780, 860) has a different material composition than the first exit metal layer (530, 620, 780, 860) and the third exit metal layer (530, 620, 780, 860). [20] Method according to claim 19, wherein the first exit work metal layer (530, 620, 780, 860), the second exit work metal layer (530, 620, 780, 860) and the third exit work metal layer (530, 620, 780, 860) are formed in situ using the same deposition tool.

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