Etching stop layer for forming storage arrangement

Abstract

Methods for manufacturing an integrated chip, comprising: Forming (2402) a storage device (108) over a substrate (102); Forming (2412) an etch stop layer (116) over the storage device (108); Forming (2414) an interlayer dielectric layer (104c), ILD layer, over the etch stop layer (116) and laterally surrounding the storage device (108); Performing one or more structuring processes to define a first trench (1904a) extending from a top surface of the ILD layer (104c) to expose a top surface of the etch stop layer (116), comprising performing the one or more structuring processes: Performing (2418) a first structuring process on the ILD layer (104c) to form a first intermediate trench (1704a) above the storage device (108), wherein the first intermediate trench (1704a) is separated from the etch stop layer (116) by the ILD layer (104c); and Performing (2422) a second structuring process on the ILD layer (104c) to increase the depth of the first trench (1904a) and to define the first trench (1904a); Performing (2424) a removal process to remove an exposed portion of the etch stop layer (116); and Formation (2426) of a conductive material within the first trench (1904a) after carrying out the removal process.

Description

BACKGROUND

[0001] Many modern electronic devices incorporate electronic memory for storing data. Electronic memory can be volatile or non-volatile. Volatile memory stores data when power is applied, while non-volatile memory can store data even when power is removed. Magnetoresistive random-access memory (MRAM) is a promising candidate for a next-generation non-volatile memory technology. MRAM devices use magnetic tunnel junctions (MTJs) to store data in a way that enables high-speed, low-power data access.

[0002] US 2017 / 0 092 847 A1 discloses a method for fabricating a random access memory device, comprising forming a memory structure on a substrate, wherein a first cap layer for covering a surface of the memory structure and a second cap layer are formed on the first cap layer using a plasma under different conditions. US 2018 / 0 309 053 A1 discloses a method for fabricating a magnetic memory device, comprising forming an encapsulation layer having a thickness on a lower electrode and an upper electrode, wherein the upper electrode is spaced from the lower electrode by at least the thickness.The document US 2019 / 0 148 637 A1 discloses a method for forming a semiconductor device, comprising depositing an insulating layer over a semiconductor substrate and etching the insulating layer to form a plurality of trenches for receiving a first conductive material. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Aspects of the present disclosure are best understood by reference to the following detailed description when taken in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not drawn to scale. Indeed, the dimensions of the various features may be exaggerated or reduced as desired for clarity of explanation. Fig. 1 shows a cross-sectional view of some embodiments of an integrated chip with an etch stop layer suitable for improving a process window and reducing the cost of manufacturing a memory device. Fig. 2 shows a cross-sectional view of some additional embodiments of an integrated chip with an etch stop layer as disclosed herein. Fig. 3 shows a cross-sectional view of some additional embodiments of an integrated chip with an etch stop layer as disclosed herein. Fig. 4 shows a cross-sectional view of some additional embodiments of an integrated chip with an etch stop layer as disclosed herein. Fig. 5 shows cross-sectional views of some additional embodiments of an integrated chip with an etch stop layer as disclosed herein. Fig. 6-23 show cross-sectional views of some embodiments of a method for fabricating an integrated chip having an etch stop layer suitable for improving a process for fabricating a memory device. Fig. 24 shows a flowchart of some embodiments of a method for manufacturing an integrated chip with an etch stop layer suitable for improving a process for manufacturing a memory device. DETAILED DESCRIPTION

[0004] The following disclosure provides many different embodiments or examples of implementing various features of the provided subject matter. To simplify the present disclosure, specific examples of components and arrangements are described below. These are, of course, only examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, but may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Further, reference numerals may be repeated throughout the various examples of the present disclosure.This repetition is for the purpose of simplicity and clarity and does not, in itself, prescribe any relationship between the various embodiments and / or configurations discussed herein.

[0005] Furthermore, for convenience, spatially relative terms such as "below," "under," "downward," "above," "above," "upward," and the like may be used herein to describe the relationship of one element or feature to one or more other elements or features as illustrated in the drawings. The spatially relative terms are intended to encompass various orientations of the device during use or operation, in addition to the orientation illustrated in the drawings. The device may be oriented differently (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may also be interpreted accordingly.

[0006] Magnetic tunnel junction (MTJ) devices (e.g., magnetoresistive random access memory (MRAM) devices) include a magnetic tunnel junction (MTJ) disposed vertically within a back-end-of-line (BEOL) metal stack between a bottom electrode and a top electrode. The MTJ has a pinned layer and a free layer vertically separated by a tunnel barrier layer. A magnetic orientation of the pinned layer is static (i.e., fixed), while a magnetic orientation of the free layer is capable of switching between a parallel configuration and an antiparallel configuration relative to that of the pinned layer. The parallel configuration provides a low-resistance state that digitally stores data as a first data state (e.g., a logic "0").The anti-parallel configuration provides a high-impedance state that digitally stores data as a second data state (e.g., a logical “1”).

[0007] The top electrode of an MTJ device is typically connected to an overlying interconnect wire via a top electrode via. The top electrode via can be formed by etching a via opening into an interlayer dielectric (ILD) layer above the top electrode and subsequently filling the via opening with a conductive material. The via opening can be etched according to a patterned masking layer, so the size of a top electrode via is generally defined by the characteristics of a photolithography system.

[0008] As the size of MTJ devices has decreased, it has become increasingly difficult to place (land) a top electrode via on a top electrode. It has been recognized that landing an (intermediate) interconnect wire on the top electrode can be done more easily and can increase a process window and / or reduce the manufacturing costs of MTJ devices. To establish good electrical contact between the top electrode and an overlying interconnect wire, the interconnect wire can be formed within a trench etched into an ILD layer so that it extends along opposite sides of the top electrode. However, if the trench extends along opposite sides of the top electrode, the ILD layer can be over-etched, which can damage an MTJ beneath the top electrode (e.g.,Etching can damage a magnesium oxide layer within an MTJ) and lead to MTJ device failure and reduced yield.

[0009] The present disclosure, in some embodiments, relates to a method of manufacturing an integrated chip that uses an etch stop layer to prevent damage to an MTJ device during fabrication of the integrated chip. The method includes forming an MTJ device over a substrate. An etch stop layer is formed over the MTJ device, and a top ILD layer is formed over the etch stop layer. Subsequently, one or more etch processes are performed on the top ILD layer to define a trench exposing a portion of the etch stop layer directly over the MTJ device. Then, an additional removal process (e.g., a wet etch process or a wet cleaning process) is performed to remove the exposed portion of the etch stop layer before a conductive material is formed within the trench.By using separate processes to expose and remove the etch stop layer, a top interconnect wire can be formed on an MTJ device without significantly damaging an MTJ of the MTJ device.

[0010] Fig. 1 shows a cross-sectional view of some embodiments of an integrated chip 100 with an etch stop layer suitable for improving a process window and / or reducing the cost of manufacturing a memory device.

[0011] The integrated chip 100 includes a memory device 108 disposed within a dielectric structure 104 over a substrate 102. The dielectric structure 104 includes a plurality of stacked interlayer dielectric (ILD) layers. In some embodiments, the plurality of stacked ILD layers may include one or more lower ILD layers 104L disposed between the memory device 108 and the substrate 102 and one or more upper ILD layers 104U surrounding the memory device 108. In some embodiments, the one or more lower ILD layers 104L surround a lower interconnect 106 disposed beneath the memory device 108.

[0012] The memory device 108 includes a bottom electrode 110, a data storage structure 112 disposed over the bottom electrode 110, and a top electrode 114 disposed over the data storage structure 112. In some embodiments, the memory device 108 may include a magnetic tunnel junction (MTJ) device. In such embodiments, the data storage structure 112 may include a magnetic tunnel junction (MTJ). In some embodiments, the bottom electrode 110 and the top electrode 114 include a conductive material such as copper, aluminum, titanium, tantalum, titanium nitride, titanium nitride, tantalum nitride, or the like.

[0013] An etch stop layer 116 is disposed over one or more lower ILD layers 104L and the memory device 108. The upper ILD layer 104U or upper ILD layers 104U are disposed over the etch stop layer 116. The etch stop layer 116 separates the memory device 108 vertically and laterally from the one or more upper ILD layers 104U. A top interconnect wire 118 is disposed within the one or more upper ILD layers 104U at a location above the memory device 108. The top interconnect wire 118 extends laterally past opposite sidewalls of the memory device 108 and extends vertically below a top surface of the memory device 108 such that the top interconnect wire 118 laterally surrounds the memory device 108.In some embodiments, an (intermediate) interconnect via 120 is disposed on the upper interconnect wire 118 and is recessed from one or more sidewalls of the upper interconnect wire 118 by a non-zero distance.

[0014] The etch stop layer 116 is suitable for mitigating damage to the memory device 108 during one or more etch processes used to form the upper interconnect wire 118 within the one or more upper ILD layers 104U. By mitigating the damage to the memory device 108, the upper interconnect wire 118 may be formed to extend past opposite sidewalls of the memory device 108, thereby improving a process window (e.g., overlay defects, critical dimension defects (CD defects), etc.) of the memory device 108 and providing a good electrical connection between the upper electrode 114 and the upper interconnect wire 118. Furthermore, the contact of the upper interconnect wire 118 with the upper electrode 114 may also reduce the number of photomasks used to manufacture the integrated chip 100 (e.g.,by removing photomasks used to form a top electrode via, performing etch-back processes, etc.), thereby reducing the manufacturing cost of the integrated chip 100.

[0015] Fig. 2 shows some additional embodiments of an integrated chip 200 with an etch stop layer suitable for preventing damage to a memory device.

[0016] The integrated chip 200 includes a memory device 108 disposed within a dielectric structure 104 disposed over a substrate 102. In some embodiments, the dielectric structure 104 includes one or more lower ILD layers 104L and one or more upper ILD layers 104U. The one or more lower ILD layers 104L laterally surround one or more lower interconnect layers 203. In some embodiments, the one or more lower interconnect layers 203 include conductive contacts 204, interconnect wires 206, and interconnect vias 208. The one or more upper ILD layers 104U laterally surround the memory device 108.In some embodiments, the one or more lower ILD layers 104L and / or the one or more upper ILD layers 104U may include one or more of silicon dioxide, SiCOH, borophosphate silicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), undoped silicate glass (USG), or the like. In some embodiments, the one or more lower interconnect layers 203 may include one or more of copper, aluminum, tungsten, ruthenium, or the like.

[0017] The one or more lower interconnect layers 203 are configured to couple the memory device 108 to an access device 202 disposed within the substrate 102. In some embodiments, the access device 202 may comprise a MOSFET (metal-oxide-semiconductor field-effect transistor) device. In some embodiments, the MOSFET device may comprise a planar FET having a gate structure 202c laterally disposed between a source region 202a and a drain region 202b. In some embodiments, the gate structure 202c may comprise a gate electrode separated from the substrate 102 by a gate dielectric. In some embodiments, the source region 202a is coupled to a source line SL, and the gate structure 202c is coupled to a word line WL. In other embodiments, the access device 202 may comprise a FinFET, a nanostructure FET (iea gate-all-around FET) or the like. In still other embodiments, the access device 202 may comprise a HEMT (high electron mobility transistor), a BJT (bipolar junction transistor), a JFET (junction gate field effect transistor), or the like.

[0018] A bottom insulation structure 210 is disposed over the one or more bottom ILD layers 104L. The bottom insulation structure 210 has sidewalls defining an opening extending through the bottom insulation structure 210. In various embodiments, the bottom insulation structure 210 may include one or more of silicon nitride, silicon dioxide, silicon carbide, or the like. A bottom electrode via 212 is disposed between the sidewalls of the bottom insulation structure 210. The bottom electrode via 212 extends from one of the bottom interconnect layers 203 to a top surface of the bottom insulation structure 210. In some embodiments, the bottom electrode via 212 may include one or more elements of titanium, titanium nitride, tantalum, tantalum nitride, or the like.

[0019] The memory device 108 is disposed on the bottom electrode via 212. In some embodiments, the memory device 108 includes a bottom electrode 110 separated from a top electrode 114 by a data storage structure 112. In some embodiments, the bottom electrode 110 and the top electrode 114 may include a metal such as tantalum, titanium, tantalum nitride, titanium nitride, platinum, nickel, hafnium, zirconium, ruthenium, iridium, or the like.

[0020] In some embodiments, the data storage structure 112 includes a magnetic tunnel junction (MTJ). In such embodiments, the data storage structure 112 may include a pinned layer 112a separated from a free layer 112c by a dielectric tunnel barrier 112b. The pinned layer 112a has a fixed magnetization, while the free layer 112c has a magnetization that can be changed during operation (through the tunneling magnetoresistance (TMR) effect) to be either parallel (i.e., in a "P" state) or antiparallel (i.e., in an "AP" state) relative to the magnetization of the pinned layer 112a. In some embodiments, the pinned layer 112a may include cobalt, iron, boron, nickel, ruthenium, iridium, platinum, or the like.In some embodiments, the dielectric tunnel barrier 112b may include magnesium oxide, aluminum oxide, nickel oxide, gadolinium oxide, tantalum oxide, molybdenum oxide, titanium oxide, tungsten oxide, or the like. In some embodiments, the free layer 112c may include cobalt, iron, boron, iron cobalt, nickel cobalt, cobalt iron boride, iron boride, iron platinum, iron palladium, or the like.

[0021] In some embodiments, one or more sidewall spacers 214 may be disposed along sidewalls of the data storage structure 112 and the top electrode 114. In some embodiments, the top electrode 114 protrudes outwardly from a top surface of the one or more sidewall spacers 214. In some embodiments, the one or more sidewall spacers 214 may include an oxide (e.g., silicon-rich oxide), a nitride (e.g., silicon nitride), a carbide (e.g., silicon carbide), or the like.

[0022] An etch stop layer 116 is disposed over the lower insulation structure 210 and the memory device 108. The etch stop layer 116 extends along sidewalls of the lower electrode 110 and the one or more sidewall spacers 214. In some embodiments, the one or more sidewall spacers 214 may extend vertically above a top surface of the etch stop layer 116. In some embodiments, the etch stop layer 116 may include a metal oxide, a metal nitride, or the like. For example, in some embodiments, the etch stop layer 116 may include aluminum oxide, aluminum nitride, or the like. In some embodiments, the etch stop layer 116 may have a thickness in a range between about 0.5 nm (5 angstroms (Å)) and about 5 nm (50 Å), between about 1 nm (10 Å) and about 3 nm (30 Å), or between other suitable values.

[0023] A top interconnect wire 118 is disposed within the one or more top ILD layers 104U and coupled to the top electrode 114. The top interconnect wire 118 extends laterally past opposite sidewalls of the top electrode 114. In some embodiments, the top interconnect wire 118 may extend further beyond the opposite sidewalls of the etch stop layer 116. In some embodiments, the top interconnect wire 118 may extend along sidewalls of both the top electrode 114 and the sidewall spacers 214. In some embodiments, the top interconnect wire 118 may contact a top surface of the etch stop layer 116 along an interface underlying a top surface of the top electrode 114. In some embodiments, the top interconnect wire 118 may include aluminum, copper, tungsten, or the like.In some embodiments, the upper interconnect wire 118 is additionally coupled to a bit line BL.

[0024] Fig. 3 shows some additional embodiments of an integrated chip 300 with an etch stop layer disclosed herein.

[0025] The integrated chip 300 includes a substrate 102 having an embedded memory region 302 and a logic region 304. A dielectric structure 104 is disposed over the substrate 102. The dielectric structure 104 includes a plurality of stacked ILD layers 104a-104d. In some embodiments, two or more adjacent stacked ILD layers 104a-104d may be separated from each other by an etch stop layer 306a-306b. In various embodiments, the etch stop layers 306a-306b may include a nitride (e.g., silicon nitride), a carbide (e.g., silicon carbide), or the like.

[0026] The embedded memory region 302 includes an access device 202 disposed on and / or within the substrate 102. The access device 202 is coupled to a plurality of lower interconnect layers 203 disposed within a plurality of lower ILD layers 104a-104b. A lower isolation structure 210 is disposed over the plurality of lower ILD layers 104a-104b. In some embodiments, the lower isolation structure 210 may comprise two or more stacked dielectric materials. For example, the lower isolation structure 210 may include a first dielectric layer 210a and a second dielectric layer 210b over the first dielectric layer 210a. In some embodiments, the first dielectric layer 210a may include silicon-rich oxide, silicon carbide, silicon nitride, or the like.In some embodiments, the second dielectric layer 210b may include silicon carbide, silicon nitride, or the like.

[0027] A bottom electrode via 212 extends through the bottom isolation structure 210, between one of the plurality of bottom interconnect layers 203 and a memory device 108 overlying the bottom isolation structure 210. The memory device 108 is disposed within a first top ILD layer 104c on the bottom isolation structure 210. In some embodiments, one or more sidewall spacers 214 are disposed on opposite sides of the memory device 108. An etch stop layer 116 is disposed on the bottom isolation structure 210 and extends along opposite sides of the memory device 108 and the one or more sidewall spacers 214.In some embodiments, the etch stop layer 116 may have a first top surface 116U that is recessed by a first distance 308 below a top surface of the one or more sidewall spacers 214 and / or recessed by a second distance 310 below a horizontal surface 104H of the first top ILD layer 104c. The recessed first top surface 116U of the etch stop layer 116 is due to a selectivity of a wet cleaning chemical or etchant used to remove the etch stop layer 116. For example, during the fabrication of the integrated chip 300, a dry etchant may etch the first top ILD layer 104c and expose a top surface of the etch stop layer 116. A wet cleaning chemical or etchant may be used to subsequently remove exposed surfaces of the etch stop layer 116 and to leave the etch stop layer 116 exposed.In some embodiments, the first distance 308 may be between about 5 nm and about 40 nm, between about 10 nm and about 30 nm, or between other suitable values. In some embodiments, the second distance 310 may be between about 5 nm and about 50 nm, between about 10 nm and about 40 nm, or between other suitable values.

[0028] The logic region 304 includes a transistor device 312 arranged on and / or within the substrate 102. The transistor device 312 is coupled to a plurality of interconnect layers 314-318b surrounded by the dielectric structure 104. The plurality of interconnect layers 314-318b includes a conductive contact 314, interconnect wires 316a-316c, and / or interconnect vias 318a-318b. In some embodiments, the plurality of interconnect layers 314-318b includes an interconnect via 318a and an interconnect wire 316b within the first upper ILD layer 104c. The interconnect via 318a is laterally separated from the memory device 108 and the interconnect wire 316b is laterally separated from a top interconnect wire 118 on the memory device 108.In some embodiments, the interconnect wire 316b extends from the top surface of the first upper ILD layer 104c to a location vertically offset by a distance 320 from the horizontal surface 104H of the first upper ILD layer 104c. In other embodiments (not shown), the interconnect wire 316b extends from a top surface of the first upper ILD layer 104c to a location substantially aligned with the horizontal surface 104H. In some embodiments, the interconnect via 318a extends vertically from below a bottom surface of the etch stop layer 116 to above a top surface of the etch stop layer 116. In some embodiments, the plurality of interconnect layers 314-318b may include one or more of copper, tungsten, aluminum, or the like.

[0029] In some embodiments, the etch stop layer 116 may have a sidewall 116s facing the interconnect via 318a. The sidewall 116s is laterally offset by a non-zero distance 317 from a sidewall of the lower isolation structure 210 and / or a sidewall of the first upper ILD layer 104c facing the interconnect via 318a. The lateral offset of the sidewall 116s of the etch stop layer 116 causes the interconnect via 318a to have protrusions 319 protruding outwardly from a sidewall of the interconnect via 318a between the first upper ILD layer 104c and the lower isolation structure 210.The lateral backshift is due to lateral removal of the etch stop layer 116 caused by a wet cleaning chemical or etchant used to remove a portion of the etch stop layer 116 during fabrication of the integrated chip 300.

[0030] Fig. 4 shows some additional embodiments of an integrated chip 400 with an etch stop layer as disclosed herein.

[0031] The integrated chip 400 includes a memory device 108 disposed over a substrate 102. The memory device 108 is coupled to a bottom interconnect 106 via a bottom electrode via 212 extending through a bottom isolation structure 210. In some embodiments, the memory device 108 includes a data storage structure 112 disposed between a bottom electrode 110 and a top electrode 114. In some embodiments, the top electrode 114 may have a greater height along a center of the top electrode 114 than along outer edges of the top electrode 114. In some embodiments, the top surface 114U of the top electrode 114 may have a substantially round profile.

[0032] An etch stop layer 116 and a top isolation structure 402 separate the bottom isolation structure 210 from one or more top ILD layers 104U surrounding the memory device 108. In some embodiments, the top isolation structure 402 comprises one or more stacked dielectric materials. For example, the top isolation structure 402 may include one or more of a carbide, a nitride, an oxide, or the like. In some embodiments, the top isolation structure 402 may be disposed above the etch stop layer 116. In other embodiments (not shown), the top isolation structure 402 may be disposed below the etch stop layer 116.

[0033] In some embodiments, the bottom electrode 110, the data storage structure 112, and the top electrode 114 have tapered sidewalls. For example, the tapered sidewalls of the bottom electrode 110 cause a bottom surface of the bottom electrode 110 to have a greater width than a top surface of the bottom electrode 110. In some embodiments, the etch stop layer 116 has a sidewall angled at an angle α greater than 90° relative to a top surface of the etch stop layer 116.

[0034] In some embodiments, the etch stop layer 116 has a first upper surface 116U1 that is vertically offset (e.g., upward or downward) from a top surface 402U of the upper isolation structure 402. In some embodiments, the first upper surface 116U1 of the etch stop layer 116 may be disposed along a first side of the memory device 108, and a second upper surface 116U2 of the etch stop layer 116 may be disposed along an opposite second side of the memory device 108. In some embodiments, the first upper surface 116U1 and the second upper surface 116U2 may be disposed at different heights above the substrate 102 due to process variations in the removal of the etch stop layer 116 during the fabrication of the integrated chip 400.In some embodiments, the first top surface 116U1 may be separated from the second top surface 116U2 by a vertical distance 404 that is between about 5 nm and about 20 nm, between about 5 nm and about 10 nm, or between other similar values.

[0035] Fig. 5 shows some additional embodiments of an integrated chip 500 with an etch stop layer as disclosed herein.

[0036] The integrated chip 500 includes a plurality of memory devices 108a-108b arranged on a substrate 102. The plurality of memory devices 108a-108b each includes a data storage structure 112 arranged between a bottom electrode 110 and a top electrode 114. In some embodiments, the plurality of memory devices 108a-108b are laterally surrounded by one or more sidewall spacers 214. The plurality of memory devices 108a-108b are also laterally surrounded by one or more upper ILD layers 104U. The one or more upper ILD layers 104U are separated from the substrate 102 by one or more lower ILD layers 104L and a lower isolation structure 210. A plurality of lower interconnects are arranged within the one or more lower ILD layers 104L.

[0037] In some embodiments, the plurality of lower interconnects include active interconnects 502 and dummy interconnects 504. The active interconnects 502 extend between an underlying interconnect 506 and a bottom electrode via 212. The dummy interconnects 504 are disposed laterally between the active interconnects 502 and have a bottom surface completely covered by one or more lower ILD layers 104L. In some embodiments, the lower isolation structure 210 also extends continuously past the opposite sides of the dummy interconnects 504. In some embodiments, the dummy interconnects 504 each have a height less than the height of the active interconnects 502. In some embodiments, the dummy interconnects 504 each have a width less than a width of the active interconnects 502.

[0038] In some embodiments, the active interconnects 502 include a conductive core 502a and a barrier layer 502b surrounding the conductive core 502a. The barrier layer 502b separates the conductive core 502a from the one or more lower ILD layers 104L and is configured to prevent the diffusion of atoms of the conductive core 502a into the one or more lower ILD layers 104L. In some embodiments, the dummy interconnects 504 further include a conductive core 504a and a barrier layer 504b surrounding the conductive core 504a. In some embodiments, the bottom electrode via 212 further includes a barrier layer 212a and a conductive core 212b.

[0039] A plurality of upper interconnect wires 118a-118b are disposed on the plurality of storage devices 108a-108b. In some embodiments, the plurality of upper interconnect wires 118a-118b include a conductive core 119a and a barrier layer 119b separating the conductive core 119a from the one or more upper ILD layers 104U. The plurality of upper interconnect wires 118a-118b extend continuously from directly above the plurality of storage devices 108a-108b to along one or more sides of the plurality of storage devices 108a-108b. In some embodiments, the upper interconnect wire 118 has a lowermost location that lies vertically below a top surface of the data storage structure 112. In some embodiments, the lowermost location is located vertically above the etch stop layer 116 and laterally outward of the sidewall spacers 214.

[0040] Fig. 6-23 show cross-sectional views 600-2300 of some embodiments of a method for manufacturing an integrated chip with an etch stop layer suitable for improving the manufacture of a memory device. Although Fig. 6-23 with reference to a method, it should be noted that the Fig. The structures shown in Figures 6-23 are not limited to such a procedure, but can be independent structures that are independent of the procedure.

[0041] As shown in cross-sectional view 600 in Fig. 6, a substrate 102 is provided. In various embodiments, the substrate 102 may be any type of semiconductor body (e.g., silicon, SiGe, SOI, etc.), such as a semiconductor wafer and / or one or more dies on a wafer, as well as any other type of semiconductor layers and / or epitaxial layers associated therewith. In some embodiments, the substrate 102 includes an embedded memory region 302 and a logic region 304. In some embodiments, an access device 202 is formed within the embedded memory region 302, and a transistor device 312 is formed within the logic region 304. In some embodiments, the access device 202 and / or the transistor device 312 may comprise a MOSFET.In some such embodiments, the access device 202 and / or the transistor device 312 may comprise a planar FET formed by depositing a gate dielectric film and a gate electrode film over the substrate 102. The gate dielectric film and the gate electrode film are then patterned to form a gate dielectric and a gate electrode. The substrate 102 may then be implanted to form a source region and a drain region within the substrate 102 on opposite sides of the gate electrode. In other embodiments, the access device 202 and / or the transistor device 312 may comprise a FinFET, a nanostructure FET (i.e., a gate-all-around FET), or the like. In yet other embodiments, the access device 202 and / or the transistor device 312 may comprise a HEMT, a BJT, a JFET, or the like.

[0042] In some embodiments, one or more lower interconnect layers 303 and 313 may be formed within one or more lower ILD layers 104L formed over the substrate 102. In some embodiments, the one or more lower ILD layers 104L may include a first lower ILD layer 104a and a second lower ILD layer 104b. In some embodiments, the one or more lower interconnect layers 303 and 313 may include a first plurality of lower interconnect layers 303 disposed within the embedded memory region 302 and a second plurality of lower interconnect layers 313 disposed within the logic region 304. In some embodiments, one or more lower interconnect layers 303 and 313 may include one or more conductive contacts, an interconnect wire, and / or an interconnect via.The one or more lower interconnect layers 303 and 313 may be formed by forming a lower ILD layer of the one or more lower ILD layers 104a-104b over the substrate 102, selectively etching the lower ILD layer to define a via opening and / or a trench within the lower ILD layer, forming a conductive material (e.g., copper, aluminum, etc.) within the via opening and / or the trench, and performing a planarization process (e.g., a chemical mechanical planarization process) to remove excess conductive material over the lower ILD layer.

[0043] As shown in cross-sectional view 700 in Fig. 7, a lower isolation structure 210 is formed over the one or more lower ILD layers 104L. In some embodiments, the lower isolation structure 210 comprises a plurality of different stacked dielectric materials. For example, in some embodiments, the lower isolation structure 210 comprises a first dielectric layer 210a and a second dielectric layer 210b over the first dielectric layer 210a. In some embodiments, the first dielectric layer 210a may include silicon-rich oxide, silicon carbide, silicon nitride, or the like. In some embodiments, the second dielectric layer 210b may include silicon carbide, silicon nitride, or the like.In some embodiments, the lower insulating structure 210 may be formed by one or more deposition processes (such as a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, a plasma-enhanced CVD (PE-CVD) process, or the like).

[0044] As shown in cross-sectional view 800 in Fig. 8, a bottom electrode via 212 is formed within the bottom insulation structure 210. The bottom electrode via 212 extends through the bottom insulation structure 210 to the plurality of first bottom interconnect layers 303. In some embodiments, the bottom electrode via 212 may be formed by selectively patterning the bottom insulation structure 210 to form an opening 802 that extends through the bottom insulation structure 210 and exposes a top surface of the plurality of first bottom interconnect layers 303. One or more conductive materials are then formed within the opening 802 and over a top surface of the bottom insulation structure 210. In some embodiments, the one or more conductive materials may include a diffusion barrier layer and / or an overlying metal layer.In some embodiments, the diffusion barrier layer and / or the metal layer may be formed by a deposition process (e.g., a PVD process, CVD process, PE-CVD process, or the like). In some embodiments, a planarization process (e.g., a chemical mechanical planarization (CMP) process) may be performed after the deposition processes to remove excess material of the diffusion barrier layer and / or the metal layer above the lower insulation structure 210.

[0045] As shown in cross-sectional view 900 in Fig. 9, a memory device stack 902 is formed over the bottom isolation structure 210 and the bottom electrode via 212. The memory device stack 902 includes a bottom electrode layer 904, one or more data storage layers 906 over the bottom electrode layer 904, and a top electrode layer 908 over the one or more data storage layers 906. In some embodiments, the bottom electrode layer 904, the one or more data storage layers 906, and the top electrode layer 908 may be formed by a deposition process (e.g., PVD process, CVD process, PE-CVD process, or the like).

[0046] In some embodiments, the bottom electrode layer 904 and / or the top electrode layer 908 may include a metal such as titanium, tantalum, titanium nitride, tantalum nitride, or the like. In some embodiments, the one or more data storage layers 906 may include a magnetic reference layer 906a, a tunneling layer 906b, and a magnetically free layer 906c. In some embodiments, the magnetic reference layer 906a may include cobalt, iron, boron, nickel, ruthenium, iridium, platinum, or the like. In some embodiments, the tunneling layer 906b may include magnesium oxide, aluminum oxide, nickel oxide, gadolinium oxide, tantalum oxide, molybdenum oxide, titanium oxide, tungsten oxide, or the like. In some embodiments, the magnetically free layer 906c may include cobalt, iron, boron, iron cobalt, nickel cobalt, cobalt iron boride, iron boride, iron platinum, iron palladium, or the like.

[0047] As shown in the cross-sectional view 1000 in Fig. 10, a first patterning process is performed on the upper electrode layer (908 in Fig. 9) and the one or more data storage layers (906 in Fig. 9) to form a top electrode 114 and a data storage structure 112. In some embodiments, the first patterning process exposes the top electrode layer (908 in Fig. 9) and the one or more data storage layers (906 in Fig. 9) selectively according to a hard mask layer 1004 (e.g., titanium, titanium nitride, tantalum, silicon nitride, silicon carbide, etc.) to a first etchant 1002. In some embodiments, the first etchant 1002 may include a dry etchant (e.g., with a fluorine- or chlorine-based etch chemistry). In some embodiments, the data storage structure 112 may include a magnetic tunnel junction (MTJ).

[0048] After the first patterning process is complete, one or more sidewall spacers 214 are formed along sidewalls of the top electrode 114 and the data storage structure 112. In various embodiments, the one or more sidewall spacers 214 may include silicon nitride, silicon dioxide, silicon oxynitride, and / or the like. In some embodiments, the one or more sidewall spacers 214 may be formed by forming a spacer layer 1006 over the substrate 102. The spacer layer 1006 is then exposed to an etchant (e.g., a dry etchant), thereby removing the spacer layer 1006 from horizontal surfaces.Removing the spacer layer 1006 from horizontal surfaces leaves a portion of the spacer layer 1006 along opposite sidewalls of the top electrode 114 and the data storage structure 112 as one or more sidewall spacers 214.

[0049] As shown in cross-sectional view 1100 in Fig. 11, a second patterning process is performed on the lower electrode layer (904 in Fig. 10) to define a memory device 108 having a data storage structure 112 between a bottom electrode 110 and the top electrode 114. In some embodiments, the second patterning process exposes the bottom electrode layer (904 in Fig. 10) selectively exposes a second etchant 1102 in areas not covered by the hard mask layer 1004 and the one or more sidewall spacers 214. In some embodiments, the second etchant 1102 may include a dry etchant (e.g., with a fluorine- or chlorine-based etch chemistry). In some embodiments, the hard mask layer 1004 may be removed after the second patterning process is complete.

[0050] As shown in the cross-sectional view 1200 in Fig. As shown in Figure 12, an etch stop layer 116 is formed over the lower isolation structure 210 and the memory device 108. The etch stop layer 116 is formed to extend continuously along a top surface of the lower isolation structure 210 and along sidewalls and a top surface of the memory device 108. In some embodiments, the etch stop layer 116 may include a metal oxide, a metal nitride, or the like. For example, the etch stop layer 116 may be made of aluminum oxide, aluminum nitride, or the like. In some embodiments, the etch stop layer 116 may be formed by a deposition process (e.g., PVD process, CVD process, PE-CVD process, or the like).

[0051] As shown in the cross-sectional view 1300 in Fig. 13, a first upper ILD layer 104c is formed over the etch stop layer 116. In some embodiments, the first upper ILD layer 104c may be formed by a deposition process (e.g., PVD, CVD, PE-CVD, ALD, or the like). In some embodiments, the first upper ILD layer 104c may include a bump 1302 protruding outward from a top surface 105 at a location that lies directly above the memory device 108 due to the topography of the memory device 108. In some embodiments (not shown), an upper isolation structure (e.g., the upper isolation structure 402 in Fig. 4) comprising one or more stacked dielectric materials may be formed on the etch stop layer 116 before the first upper ILD layer 104c is formed. In some embodiments, the one or more dielectric materials may include a nitride, a carbide, an oxide, or the like.

[0052] As shown in the cross-sectional view 1400 in Fig. As illustrated in Figure 14, a first planarization process (e.g., a CMP process) is performed on the first upper ILD layer 104c. The first planarization process is performed along a line 1402 to remove a portion of the first upper ILD layer 104c including the bump 1302 and to define a substantially planar upper surface extending over the memory device 108. In some embodiments, the first planarization process may include a chemical mechanical polishing (CMP) process.

[0053] As shown in the cross-sectional view 1500 in Fig. 15, a hard mask structure 1502 is formed over the first upper ILD layer 104c. The hard mask structure 1502 is then patterned to have sidewalls defining a first opening 1504a over the memory device 108 and a second opening 1504b within the logic region 304. In some embodiments, the hard mask structure 1502 may comprise a multi-layer hard mask structure including a first hard mask layer 1506, a second hard mask layer 1508 over the first hard mask layer 1506, and a third hard mask layer 1510 over the second hard mask layer 1508. In some embodiments, the first hard mask layer 1506 may include a dielectric material such as silicon dioxide, silicon nitride, silicon carbide, or the like. In some embodiments, the second hard mask layer 1508 may include an anti-reflective coating.In some embodiments, the third hard mask layer 1510 may include a metal such as titanium, titanium nitride, or the like. In some embodiments, the first opening 1504a and the second opening 1504b may be defined by sidewalls of the third hard mask layer 1510, and the first hard mask layer 1506 and the second hard mask layer 1508 may extend continuously between the sidewalls of the third hard mask layer 1510.

[0054] As shown in the cross-sectional view 1600 in Fig. 16, a third patterning process is performed to define a via opening 1602 within the first upper ILD layer 104c in the logic region 304. The via opening 1602 extends through the hard mask pattern 1502 to within the first upper ILD layer 104c. In some embodiments, the via opening 1602 is defined by sidewalls and a bottom surface of the first upper ILD layer 104c. In some embodiments, the first upper ILD layer 104c has a non-zero thickness 1604 below the via opening 1602. In some embodiments, the third patterning process selectively exposes the first upper ILD layer 104c to a third etchant 1606 in areas not covered by the hard mask pattern 1502. In some embodiments, the third etchant 1606 may be a dry etchant (e.g.,with a chlorine-based etch chemistry, a fluorine-based etch chemistry, or the like).

[0055] As shown in the cross-sectional view 1700 in Fig. 17, a fourth patterning process is performed to define a first interconnect trench 1704a within the first upper ILD layer 104c in the embedded memory region 302 and a second interconnect trench 1704b within the first upper ILD layer 104c in the logic region 304. The fourth patterning process further increases the depth of the via opening 1602 such that the via opening 1602 exposes a top surface of the etch stop layer 116 within the logic region 304, wherein the first upper ILD layer 104c separates the first interconnect trench 1704a from the etch stop layer 116 within the embedded memory region 302.

[0056] In some embodiments, the fourth patterning process selectively exposes the first upper ILD layer 104c to a fourth etchant 1702 according to the first opening 1504a and the second opening 1504b of the hard mask structure 1502. In some embodiments, the fourth etchant 1702 may include a dry etchant (e.g., having a chlorine-based etch chemistry, a fluorine-based etch chemistry, or the like). In some embodiments, the first interconnect trench 1704a may be shallower than the second interconnect trench 1704b because the via opening 1602 allows more etchant to etch the second interconnect trench 1704b than the first interconnect trench 1704a.

[0057] As shown in the cross-sectional view 1800 in Fig. 18, a first wet removal process is performed to remove the etch stop layer 116 beneath the via opening 1602. In some embodiments, a first wet cleaning chemical or etchant 1802 is used for the first wet removal process, which has high selectivity between the etch stop layer 116 and the first upper ILD layer 104c. For example, the first wet cleaning chemical or etchant 1802 may remove the etch stop layer 116 more than ten times faster than the first upper ILD layer 104c. In various embodiments, the first wet cleaning chemical or etchant 1802 may include a copper corrosion fluid, an amine and / or fluoride-based mixture (e.g., ST250), hydrofluoric acid, or the like.In some embodiments (not shown), the first wet cleaning chemical or etchant 1802 may remove the etch stop layer 116 both vertically and laterally such that the etch stop layer 116 is laterally recessed from a sidewall of the first upper ILD layer 104c (e.g., as shown in FIG. Fig. 3 shown).

[0058] As shown in the cross-sectional view 1900 in Fig. 19, a fifth structuring process is performed. The fifth structuring process increases a depth of the first interconnect trench (1704a in Fig. 18) to form a first interconnect trench 1904a exposing a top surface of the etch stop layer 116 within the embedded memory region 302. The fifth patterning process further increases the depth of the second interconnect trench (1704b in Fig. 18) to form a second interconnect trench 1904b. In some embodiments, the fifth patterning process may cause a first interconnect trench 1904a to extend beneath a top surface of the memory device 108 such that the etch stop layer 116 is exposed along a top surface and sidewalls of the memory device 108. In some embodiments, the fifth patterning process selectively exposes the first top ILD layer 104c to a fifth etchant 1902 according to the first opening 1504a and the second opening 1504b of the hard mask structure 1502. In some embodiments, the fifth etchant 1902 may include a dry etchant (e.g., with a chlorine-based etch chemistry, a fluorine-based etch chemistry, or the like). In some embodiments (not shown), the fifth patterning process may be performed both through the first upper ILD layer 104c and through an upper isolation structure (e.g.the upper insulating structure 402 in . Fig. 4) etch.

[0059] As shown in the cross-sectional view 2000 in Fig. 20, a second wet removal process is performed to remove the etch stop layer 116 within the embedded memory region 302. In some embodiments, the second wet removal process uses a second wet cleaning chemical or etchant 2002 that has high selectivity between the etch stop layer 116 and the first upper ILD layer 104c. For example, the second wet cleaning chemical or etchant 2002 may remove the etch stop layer 116 more than ten times faster than the first upper ILD layer 104c. In various embodiments, the second wet cleaning chemical or etchant 2002 may include a copper corrosion fluid, an amine and / or fluoride-based mixture (e.g., ST250), hydrofluoric acid, or the like.In some embodiments (not shown), the second wet cleaning chemical or etchant 2002 may further laterally remove the etch stop layer 116 such that the etch stop layer 116 is laterally recessed from a sidewall of the lower isolation structure 210 and / or the first upper ILD layer 104c (as shown in FIG. Fig. 3).

[0060] As shown in the cross-sectional view 2100 in Fig. As shown in Figure 21, a conductive material 2102 is deposited within the first interconnect trench 1904a, the second interconnect trench 1904b, and the via opening 1602. In some embodiments, the conductive material 2102 may include aluminum, copper, tungsten, or the like.

[0061] As shown in the cross-sectional view 2200 in Fig. As illustrated in Figure 22, a second planarization process (e.g., a CMP process) is performed on the first upper ILD layer 104c. The second planarization process is performed along a line 2202 to remove the conductive material 2102 above the first upper ILD layer 104c. In some embodiments, the second planarization process may include a chemical mechanical polishing (CMP) process.

[0062] As shown in cross-sectional view 2300 in Fig. 23, one or more additional interconnect layers 322 are formed within a second upper ILD layer 104d over the first upper ILD layer 104c. In some embodiments, the one or more additional interconnect layers 322 may each be formed by a damascene process (e.g., single damascene process or double damascene process). The damascene process is performed by forming the second upper ILD layer 104d over the first upper ILD layer 104c, etching the second upper ILD layer 104d to form a via opening and / or a trench, and filling the via opening and / or trench with a conductive material. In some embodiments, the second upper ILD layer 104d may be deposited by a physical vapor deposition technique (e.g., PVD, CVD, PE-CVD, ALD, etc.) and the conductive material (e.g.,Tungsten, copper, aluminum or the like) can be formed by a deposition process and / or a plating process (e.g., electroplating, electroless plating, etc.).

[0063] Fig. 24 shows a flow diagram of some embodiments of a method 2400 for fabricating an integrated chip having an etch stop layer suitable for enhancing the formation of an MTJ device.

[0064] Although method 2400 is illustrated and described herein as a series of acts or events, it should be understood that the illustrated order of such acts or events is not to be construed in a limiting sense. For example, some acts may be performed in a different order and / or concurrently with other acts or events than those illustrated and / or described herein. Further, not all acts illustrated herein may be required to practice one or more aspects or embodiments of the description contained herein. Further, one or more of the acts illustrated herein may be performed in one or more separate acts and / or phases.

[0065] At 2402, transistor devices are formed within a logic region and an embedded memory region of a substrate. Fig. 6 shows a cross-sectional view 600 of some embodiments corresponding to operation 2402.

[0066] At 2404, first and second lower interconnects are formed within a lower interlayer dielectric (ILD) layer over the substrate. The first lower interconnect is formed within the embedded memory region, and the second lower interconnect is formed within the logic region. Fig. 6 shows a cross-sectional view 600 of some embodiments corresponding to operation 2404.

[0067] In 2406, a bottom electrode via is formed over the first bottom interconnect and within a bottom isolation structure overlying the bottom ILD layer. Fig. 7-8 show cross-sectional views 700-800 of some embodiments according to operation 2406.

[0068] At 2408, a memory device is formed over the bottom electrode via. The memory device includes a data storage structure disposed between a bottom electrode and a top electrode. Fig. 9-11 show cross-sectional views 900-1100 of some embodiments according to operation 2408.

[0069] At 2410, one or more sidewall spacers are formed along opposite sides of the data storage structure. Fig. 11 shows a cross-sectional view 1100 of some embodiments corresponding to operation 2410.

[0070] At 2412, an etch stop layer is formed over the memory device, the sidewall spacers, and the bottom isolation structure. Fig. 12 shows a cross-sectional view 1200 of some embodiments corresponding to operation 2412.

[0071] At 2414, an upper ILD layer is formed over the etch stop layer. Fig. 13-14 show cross-sectional views 1300-1400 of some embodiments corresponding to operation 2414.

[0072] At 2416, a patterning process is performed on the upper ILD layer to define a via opening within the logic area. Fig. 15-16 show cross-sectional views of 1500-1600 of some embodiments according to operation 2416.

[0073] At 2418, a patterning process is performed on the upper ILD layer to define a first intermediate trench within the logic region and a second intermediate trench within the embedded memory region. Fig. 17 shows a cross-sectional view of 1700 of some embodiments according to operation 2418.

[0074] At 2420, a first wet removal process is performed to remove a first portion of the etch stop layer exposed by the via opening and the second intermediate trench. Removing the first portion of the etch stop layer exposes the lower insulation structure directly above the second lower interconnect structure. Fig. 18 shows a cross-sectional view 1800 of some embodiments corresponding to operation 2420.

[0075] At 2422, a patterning process is performed to increase the depths of the first intermediate trench and the second intermediate trench to form a first trench and a second trench. The patterning process further removes the exposed portion of the lower isolation structure, forming an opening that exposes the second lower interconnect structure. The first trench exposes a second portion of the etch stop layer above the memory device. However, because the etch stop layer covers the memory device, the patterning process is prevented from damaging the memory device. Fig. 19 shows a cross-sectional view 1900 of some embodiments according to operation 2422.

[0076] At 2424, a second wet removal process is performed to remove the second portion of the etch stop layer. Fig. 20 shows a cross-sectional view 2000 of some embodiments according to operation 2424.

[0077] At 2426, a conductive material is formed within the via opening, the first trench, and the second trench. Fig. 21 shows a cross-sectional view 2100 of some embodiments according to operation 2426.

[0078] Thus, in some embodiments, the present disclosure relates to an integrated chip comprising an etch stop layer suitable for reducing damage to a memory device. The etch stop layer further improves a process window and / or reduces the cost of a manufacturing process of the memory device.

[0079] In some embodiments, the present disclosure relates to a method of fabricating an integrated chip. The method includes forming a memory device over a substrate; forming an etch stop layer over the memory device; forming an interlayer dielectric (ILD) layer over the etch stop layer and laterally surrounding the memory device; performing one or more patterning processes to define a first trench extending from a top surface of the ILD layer to expose a top surface of the etch stop layer; performing a removal process to remove an exposed portion of the etch stop layer; and forming a conductive material within the first trench after performing the removal process.wherein performing one or more patterning processes comprises: performing a first patterning process on the ILD layer to form a first intermediate trench above the memory device, wherein the first intermediate trench is separated from the etch stop layer by the ILD layer; and performing a second patterning process on the ILD layer to increase a depth of the first trench and define the first trench. In some embodiments, the removal process comprises a wet cleaning process or a wet etching process. In some embodiments, the method further comprises forming a via opening and an overlying second trench within the ILD layer, wherein the second trench and the via opening expose a second portion of the etch stop layer.before the second patterning process is performed. In some embodiments, the via opening exposes a second upper surface of the etch stop layer that lies laterally outside the memory device. In some embodiments, the method further comprises performing a second removal process to remove the second portion of the etch stop layer before the removal process is performed. In some embodiments, the second removal process comprises a wet cleaning process or a wet etching process. In some embodiments, the method further comprises forming an upper isolation structure along the upper surface and along the sidewalls of the etch stop layer; and forming the ILD layer over the upper isolation structure, wherein the one or more patterning processes etch through the upper isolation structure.to expose the top surface of the etch stop layer. In some embodiments, the etch stop layer has a first top surface along a first side of the memory device and a second top surface along a second side of the memory device opposite the first side after performing the removal process; and the first top surface and the second top surface are at different heights above the substrate.

[0080] In other embodiments, the present disclosure relates to a method of fabricating an integrated chip. The method includes forming a memory device over one or more lower interlayer dielectric (ILD) layers on a substrate, the memory device having a data storage structure disposed between a lower electrode and a top electrode; forming an etch stop layer over the top electrode; forming an upper ILD layer over the etch stop layer and laterally surrounding the memory device; forming a recess in the upper ILD layer, the recess extending from a top surface of the ILD layer to the etch stop layer; removing an exposed portion of the etch stop layer;and forming a top interconnect wire in the recess, wherein forming the recess comprises: performing a first patterning process on the ILD layer to form a first intermediate trench above the memory device, the first intermediate trench separated from the etch stop layer by the ILD layer; and performing a second patterning process on the ILD layer to increase a depth of the recess and define the recess. In some embodiments, the top ILD layer has a horizontally extending surface directly below the top interconnect wire and laterally outward from a top surface of the memory device;and the etch stop layer has a top surface recessed below the horizontally extending surface. In some embodiments, the method further comprises forming a bottom isolation structure over the one or more bottom ILD layers; forming a bottom electrode via within the bottom isolation structure, wherein the bottom electrode is formed over the bottom electrode via;and forming a via opening defined by sidewalls of the upper ILD layer, the etch stop layer, and the lower insulating structure. In some embodiments, the sidewalls of the etch stop layer defining the via opening are laterally recessed from the sidewalls of the lower insulating structure defining the via opening by a non-zero distance. In some embodiments, the etch stop layer includes a metal oxide or a metal nitride. In some embodiments, a first etchant is used to define the recess within the ILD layer, and a wet cleaning chemical is used to remove the etch stop layer, wherein the first etchant is different from the wet cleaning chemical.

[0081] In still other embodiments, the present disclosure relates to an integrated chip.The integrated chip comprises: a memory device disposed over a bottom interconnect within one or more bottom interlayer dielectric (ILD) layers over a substrate; a top ILD layer laterally surrounding the memory device; an etch stop layer separating the memory device and the one or more bottom ILD layers from the one or more top ILD layers, the etch stop layer having a top surface underlying a top surface of the memory device; and a top interconnect wire contacting sidewalls of the memory device over the etch stop layer, one or more sidewall spacers disposed on opposite sides of the memory device, and the etch stop layer extending along the opposite sides of the one or more sidewall spacers.In some embodiments, the integrated chip further comprises: a bottom isolation structure disposed over the one or more bottom ILD layers; a bottom electrode extending through the bottom isolation structure between the bottom interconnect and the memory device; and a top isolation structure separating the bottom isolation structure from the top ILD layer. In some embodiments, the top isolation structure has a top surface that is vertically offset from a top surface of the etch stop layer by a non-zero distance. In some embodiments, the top ILD layer has a horizontally extending surface that lies directly below the top interconnect wire and laterally outside the memory device; and the etch stop layer has a top surface that is recessed below the horizontally extending surface.In some embodiments, the etch stop layer has a first top surface along a first side of the memory device and a second top surface along a second side of the memory device opposite the first side, wherein the first top surface and the second top surface are arranged at different heights above the substrate.

Claims

[1] A method of manufacturing an integrated chip, comprising: Forming (2402) a memory device (108) over a substrate (102); Forming (2412) an etch stop layer (116) over the memory device (108); Forming (2414) an interlayer dielectric layer (104c), ILD layer, over the etch stop layer (116) and laterally surrounding the memory device (108); Performing one or more patterning processes to define a first trench (1904a) extending from a top surface of the ILD layer (104c) to expose a top surface of the etch stop layer (116), wherein performing the one or more patterning processes comprises: Performing (2418) a first patterning process on the ILD layer (104c) to form a first intermediate trench (1704a) above the memory device (108), wherein the first intermediate trench (1704a) is separated from the etch stop layer (116) by the ILD layer (104c); and performing (2422) a second patterning process on the ILD layer (104c) to increase a depth of the first trench (1904a) and to define the first trench (1904a); performing (2424) a removal process to remove an exposed portion of the etch stop layer (116); and Forming (2426) a conductive material within the first trench (1904a) after performing the removal process. [2] The method of claim 1, wherein the removal process comprises a wet cleaning process or a wet etching process. [3] The method of claim 1 or 2, further comprising: Forming one or more sidewall spacers (214) along the sidewalls of the memory device (108), wherein the etch stop layer (116) extends along opposite sides of the one or more sidewall spacers (214). [4] The method of claim 3, further comprising: Forming (2416) a via opening (1602) and an overlying second trench (1904b) within the ILD layer (104c), wherein the second trench (1904b) and the via opening (1602) expose a second portion of the etch stop layer (116) prior to performing the second patterning process. [5] The method of claim 4, wherein the via opening (1602) exposes a second upper surface of the etch stop layer (116) that is laterally outward of the memory device (108). [6] The method of claim 4 or 5, further comprising: Performing a second removal process to remove the second portion of the etch stop layer (116) prior to performing the removal process. [7] The method of claim 6, wherein the second removal process comprises a wet cleaning process or a wet etching process. [8] The method of any preceding claim, further comprising: Forming an upper insulation structure (402) along the upper surface and along the sidewalls of the etch stop layer (116); and Forming the ILD layer (104c) over the upper isolation structure (402), wherein the one or more patterning processes etch through the upper isolation structure to expose the upper surface of the etch stop layer (116). [9] Method according to one of the preceding claims, wherein the etch stop layer (116) has a first upper surface (116U1) along a first side of the memory device (108) and a second upper surface (116U2) along a second side of the memory device (108) opposite the first side after performing the removal process; and wherein the first upper surface (116U1) and the second upper surface (116U2) are at different heights above the substrate (102). [10] A method of manufacturing an integrated chip, comprising: Forming (2402) a memory device (108) over one or more lower interlayer dielectric layers (104a-104b), ILD layers, on a substrate (102), the memory device (108) comprising a data storage structure (112) disposed between a lower electrode (110) and an upper electrode (114); Forming (2412) an etch stop layer (116) over the upper electrode (114); Forming (2414) an upper ILD layer (104c) over the etch stop layer (116) and laterally surrounding the memory device (108); Forming a recess (1904a) within the upper ILD layer (104c), the recess extending from a top surface of the ILD layer to the etch stop layer (116), wherein forming a recess (1904a) within the upper ILD layer (104c) comprises: Performing (2418) a first patterning process on the ILD layer (104c) to form a first intermediate trench (1704a) above the memory device (108), wherein the first intermediate trench (1704a) is separated from the etch stop layer (116) by the ILD layer (104c); and performing (2422) a second patterning process on the ILD layer (104c) to increase a depth of the recess (1904a) and to define the recess (1904a); Removing (2424) an exposed portion of the etch stop layer (116); and Forming (2426) an upper interconnect wire (118) within the recess (1904a). [11] Method according to claim 10, wherein the upper ILD layer (104c) has a horizontally extending surface directly below the upper interconnect wire (118) and laterally outside a top surface of the memory device (108); and wherein the etch stop layer (116) has an upper surface recessed below the horizontally extending surface. [12] The method of claim 10 or 11, further comprising: Forming a lower isolation structure (210) over one or more lower ILD layers (104a-104b); Forming (2406) a bottom electrode via within the bottom insulating structure (210), wherein the bottom electrode (110) is formed over the bottom electrode via; and Forming (2416) a via opening (1602) defined by sidewalls of the upper ILD layer (104c), the etch stop layer (116) and the lower isolation structure (210). [13] The method of claim 12, wherein the sidewalls of the etch stop layer (116) defining the via opening (1602) are laterally recessed by a non-zero distance (317) from sidewalls of the lower insulation structure (210) defining the via opening (1602). [14] The method of any one of claims 10 to 13, wherein the etch stop layer (116) contains a metal oxide or a metal nitride. [15] The method of any one of claims 10 to 14, wherein a first etchant is used to define the recess (1904a) within the ILD layer (104c) and a wet cleaning chemical is used to remove the etch stop layer (116), the first etchant being different from the wet cleaning chemical. [16] Integrated chip comprising: a memory device (108) disposed over a lower interconnect (106) within one or more lower ILD layers (104a, 104b) over a substrate (102); an upper ILD layer (104c) laterally surrounding the memory device (108); an etch stop layer (116) separating the memory device (108) and the one or more lower ILD layers (104a, 104b) from the one or more upper ILD layers (10c), the etch stop layer (116) having a top surface underlying a top surface of the memory device (108); and an upper interconnect wire (118) contacting sidewalls of the memory device (108) above the etch stop layer (116), wherein one or more sidewall spacers (214) are disposed on opposite sides of the memory device (108) and the etch stop layer (116) extends along the opposite sides of the one or more sidewall spacers (214), further comprising: a lower isolation structure (210) disposed over the one or more lower ILD layers (104a, 104b); a lower electrode (212) extending through the lower insulation structure (210) between the lower interconnect (106) and the memory device (108); and an upper isolation structure (402) separating the lower isolation structure (210) from the upper ILD layer (104c). [17] The memory device (108) of claim 16, wherein the upper isolation structure (402) has a top surface that is vertically offset from a top surface of the etch stop layer (116) by a non-zero distance. [18] Storage device (108) according to one of claims 16 and 17, wherein the upper ILD layer (104c) has a horizontally extending surface located directly below the upper interconnect wire and laterally outside the memory device (108); and wherein the etch stop layer (116) has a top surface recessed below the horizontally extending surface. [19] The memory device (108) of any of claims 16 and 17, wherein the etch stop layer (116) has a first top surface (116U1) along a first side of the memory device (108) and a second top surface (116U2) along a second side of the memory device (108) opposite the first side, the first top surface and the second top surface being disposed at different heights above the substrate (102).

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