CURRENT MEASURING SYSTEM

Abstract

Current sensing system for a digital low-dropout regulator (LDO) for receiving a reference voltage and generating an output voltage, wherein the output voltage of the digital LDO depends on a first DAC code signal, wherein the current sensing system includes a current determination unit configured to receive the first DAC code signal and generate an output current signal using the first DAC code signal.

Description

[0001] The present disclosure relates to a current measurement system. More particularly, the present disclosure relates to a current measurement system for a digital low-dropout (LDO) regulator. BACKGROUND

[0002] Fig. Figure 1A shows a digital LDO 100 as is known in the art (Jun Liu et al., A Fully-Synthesizable 0.6V Digital LDO with Dual-Loop Control using Standard Digital Cells, 2016 14th IEEE International New Circuits and Systems Conference (NEWCAS), Vancouver, BC, Canada, 2016, pp. 1-4).

[0003] The LDO 100 includes a main comparator (102), the shift registers (104, 106), a counter (108), a buffer (110), the transistors (112, 114, 116, 118), a panic circuit (120) including the comparators (122, 124) and a logic block (126), a clock circuit (128) including a multiplexer (130) and a frequency scaler (132), and a capacitor Co with the equivalent series resistance (ESR) Ro.

[0004] The LDO 100 uses a coarse digital-to-analog converter (DAC) 134 and a fine DAC 136, each driven by an up-down counter 104, 106 and a timing scheme 128 that delays a response to a "panic" detected by the window comparator provided by the panic circuit 120.

[0005] The main control loop is the single comparator 102 (or 1-bit ADC), which compares a feedback voltage VFB derived from an output voltage VLDO with a target value VREF.

[0006] The operation of the up-down counters 104, 106 acts as an integration function on an error signal CMP, so that the stability of the control loop depends on the zero point of the external decoupling capacitor Co, which has an ESR denoted by Ro.

[0007] If a "panic" is detected, ie the output voltage VLDO has exceeded the range defined by the window comparator 120, the coarse and fine up-down counters 104, 106 are clocked at the full clock rate CLK, and the output current is driven to the new target value (either up or down) under the control of the main comparator output CMP.

[0008] Since the output of DACs 134, 136 are essentially current sources provided by transistors 112, 114, 116, 118, the output voltage VLDO is the integral of this current, resulting in a 90° phase shift of the control to the output voltage VLDO. This typically results in a limit cycle of the DAC code. Since capacitor Co has a certain ESR (indicated by Ro), the amplitude of the limit cycle decreases to a steady state. However, the fast clocking in "panic" mode is a limited period of time, which in this example is 32 clock cycles. When the fast "panic" clocking ends, fine circuit 136 operates at 1 / 32 of the clock speed.

[0009] The coarse and fine DAC outputs are controlled using a current mirror scheme. This has two advantages: 1. The switching process and dynamics of the LDO are kept constant and the performance is as expected. 2. The PSRR sensitivity of the output stage is reduced.

[0010] Fig. Figure 1B is a sketch of a current mirror scheme 138 for controlling the coarse and fine DAC outputs, as known from the prior art (Xiangyu Mao et al., A 1.2-A Calibration-Free Hybrid LDO With In-Loop Quantization and Auxiliary Constant Current Control Achieving High Accuracy and Fast DVS, IEEE Transactions on Circuits and Systems - I: Regular Papers, Vol. 69, No. 11, November 2022).

[0011] The current mirror scheme 138 includes transistors 140, current sources 142, a capacitor 144, an amplifier 146, and a sink buffer 148. SUMMARY

[0012] It is desirable to measure the output current of a digital LDO.

[0013] According to a first aspect of the disclosure, a current measurement system for a digital low-dropout regulator (LDO) is provided to receive a reference voltage and generate an output voltage, wherein the output voltage of the digital LDO depends on a first DAC code signal, the current measurement system comprising a current determination unit configured to receive the first DAC code signal and generate an output current signal using the first DAC code signal.

[0014] Optionally, the LDO comprises a comparison circuit configured to receive the reference voltage, receive a feedback voltage, wherein the feedback voltage depends on the output voltage, compare the reference voltage and the feedback voltage, and generate an error signal that depends on the comparison between the reference voltage and the feedback voltage, and a first digital-to-analog converter configured to receive the error signal and generate the first DAC code signal based on the error signal.

[0015] If necessary, the comparison circuit includes a main comparator or a 1-bit analog-to-digital converter.

[0016] Optionally, the first digital-to-analog converter comprises a first shift register configured to generate the first DAC code signal.

[0017] Optionally, the LDO comprises a comparison circuit configured to receive the reference voltage, receive a feedback voltage, wherein the feedback voltage depends on the output voltage, compare the reference voltage and the feedback voltage, and generate an error signal that depends on the comparison between the reference voltage and the feedback voltage, and a first digital-to-analog converter configured to receive the error signal and generate the first DAC code signal based on the error signal.

[0018] If necessary, the comparison circuit includes a main comparator or a 1-bit analog-to-digital converter.

[0019] Optionally, the first digital-to-analog converter comprises a first shift register configured to generate the first DAC code signal.

[0020] Optionally, each of the first buffer circuits comprises a first inverter.

[0021] Optionally, the digital LDO includes an output capacitor with an equivalent series resistance, wherein the first DAC signal is provided to the output capacitor to generate the output voltage.

[0022] Optionally, the current determination unit is configured to generate the output current signal by calculating an output current using the first DAC code signal and to provide the output current signal using the calculated output current.

[0023] Optionally, the current determination unit is configured to calculate the output current by multiplying the first DAC code signal by a first variable.

[0024] Optionally, the current measurement system comprises an average current determination unit configured to receive the output current signal and provide an average output current signal.

[0025] If necessary, the average current determination unit includes a low-pass filter.

[0026] If necessary, the low-pass filter includes an infinite impulse response (IIR) filter.

[0027] Optionally, the current measuring system includes a warning circuit that indicates when the output current exceeds a first output value or falls below a second threshold.

[0028] Optionally, the digital LDO comprises a panic circuit configured to detect when the feedback voltage exceeds a first voltage threshold or falls below a second voltage threshold and to control the first digital-to-analog converter to operate in a panic mode when the feedback voltage exceeds the first voltage threshold or falls below the second voltage threshold, and a clock circuit configured to provide a clock signal to the comparison circuit, to operate in a fast mode by providing the clock signal at a first frequency while operating in the panic mode, and to operate in a slow mode when not in the panic mode by providing the clock signal at a second frequency, the second frequency being lower than the first frequency, the clock circuit being configured to indicatewhen the output current exceeds the first threshold current value or falls below the second threshold current value when the clock circuit is operating in slow mode.

[0029] Optionally, the panic circuit is configured to output a panic signal in response to detecting the feedback voltage exceeding the first voltage threshold or falling below the second voltage threshold, wherein the panic signal is used to switch the first digital-to-analog converter into panic mode.

[0030] Optionally, the panic circuit comprises a first comparator configured to compare the feedback voltage with the first voltage threshold and a second comparator configured to compare the feedback voltage with the second voltage threshold.

[0031] Optionally, the panic circuit comprises a logic circuit configured to receive the outputs of the first and second comparators and to provide the panic signal when the first and second comparator outputs indicate that the feedback voltage has exceeded the first voltage threshold or has fallen below the second voltage threshold.

[0032] Optionally, the digital LDO comprises a counter circuit configured to receive the panic signal and the error signal, wherein the first digital-to-analog converter comprises a first shift register configured to generate the first DAC code signal, and the counter circuit is further configured to increment the first shift register while the first digital-to-analog converter operates in panic mode.

[0033] Optionally, the clock circuit comprises a multiplexer for receiving an input clock signal and a frequency scaling unit, wherein the clock circuit is configured to provide the input clock signal as the clock signal during the fast mode, and the frequency scaling unit is configured to reduce the frequency of the input clock signal when generating the clock signal during the slow mode.

[0034] Optionally, the current measurement system includes a first current mirror. Optionally, the first current mirror is configured to control coarse and fine DAC outputs.

[0035] Optionally, the digital LDO comprises a second digital-to-analog converter configured to receive the error signal and generate a second DAC code signal based on the error signal, wherein the output voltage is dependent on the second DAC code signal.

[0036] If necessary, the first digital-to-analog converter provides coarse control of the output voltage and the second digital-to-analog converter provides fine control of the output voltage.

[0037] Optionally, the current determination unit is configured to generate the output current signal using the second DAC code signal.

[0038] Optionally, the second digital-to-analog converter comprises a second shift register configured to generate the second DAC code signal.

[0039] If necessary, the second shift register includes an up-down counter.

[0040] Optionally, the second digital-to-analog converter comprises a plurality of second current sources, each of the second current sources acting as a bit of the second DAC code signal.

[0041] Optionally, each of the second current sources comprises a second transistor.

[0042] Optionally, the second shift register comprises a plurality of outputs, each output associated with a single bit of the second DAC code signal and coupled to a gate of one of the plurality of second current sources.

[0043] Optionally, the second digital-to-analog converter comprises a plurality of second buffer circuits, each output being coupled to the gate of one of the plurality of second current sources via a buffer circuit.

[0044] Optionally, each of the second buffer circuits comprises a second inverter.

[0045] Optionally, the digital LDO includes an output capacitor having an equivalent series resistance, wherein the first and second DAC signals are provided to the output capacitor to generate the output voltage.

[0046] Optionally, the current determination unit is configured to generate the output current signal by calculating an output current using the first DAC code signal and the second DAC code signal and to provide the output current signal using the calculated output current.

[0047] Optionally, the current determination unit is configured to calculate the output current by adding the sum of the multiplication of the first DAC code signal by a first variable and the multiplication of the second DAC code signal by a second variable.

[0048] According to a second aspect of the disclosure, a voltage regulator system is provided comprising a digital low-dropout regulator (LDO) for receiving a reference voltage and generating an output voltage, and a current measurement system comprising a current determination unit configured to receive a first DAC code signal, wherein an output voltage of the digital LDO depends on the first DAC code signal, and to generate an output current signal using the first DAC code signal.

[0049] It will be appreciated that the voltage regulator of the second aspect may include the features set forth in the first aspect and may include further features as described herein.

[0050] According to a third aspect of the disclosure, a method is provided for measuring a current from a digital low-dropout regulator (LDO) for receiving a reference voltage and generating an output voltage, wherein the output voltage of the digital LDO is dependent on a first DAC code signal, the method comprising receiving the first DAC code signal at a current determination unit and generating an output current signal using the first DAC code signal using the current determination unit.

[0051] It will be appreciated that the method of the third aspect may include features set out in the first aspect and / or the second aspect and may include further features as described herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] The disclosure is further described below by way of example and with reference to the accompanying drawings, in which: Fig. 1A a digital LDO as known in the art, Fig. Figure 1B is a sketch of a current mirror scheme for controlling coarse and fine DAC outputs, as is known in the art; Fig. 2A is a diagram of a current measurement system for a digital LDO according to a first embodiment of the present disclosure, Fig. 2B a sketch of the current measuring system with a special example of the LDO, Fig. 2C is a sketch of a specific embodiment of the LDO as shown in Fig. 2B; Fig. 3A is a diagram of a current measurement system according to a second embodiment of the present disclosure, Fig. 3B is a diagram of the current measuring system showing a specific embodiment of the average current determination unit, Fig. 3C is a diagram of a current measurement system according to a third embodiment of the present disclosure, Fig. 3D a timing diagram showing an example of the operation of the warning circuit, where the output current signal varies over time, Fig. 3E is a diagram of a current measurement system according to a fourth embodiment of the present disclosure; Fig. 4A is a sketch of a special embodiment of the LDO used with the current measuring system of Fig. 3C is used, according to a fifth embodiment of the present disclosure, Fig. 4B is a sketch of a specific embodiment of the LDO that can be used with a current measurement system of the present disclosure such as the current measurement system of Fig. 3C may be used, according to a sixth embodiment of the present disclosure; Fig. 5 is a sketch of a special embodiment of the LDO, which uses the current measuring system of Fig. 2A, according to a seventh embodiment of the present disclosure; Fig. 6 is a schematic diagram of a digital LDO and current measurement system according to an eighth embodiment of the present disclosure; Fig. 7A is a block diagram of an IIR filter as may be implemented within the current measurement system to provide the average output current signal, Fig. 7B is a sketch of the IIR filter including a comparator; and Fig. 8 is a diagram showing simulation results for a practical implementation of the IIR filter. DETAILED DESCRIPTION

[0053] Fig. Figure 2A is a diagram of a current measurement system 200 for a digital LDO 202, according to a first embodiment of the present disclosure. During operation, the digital LDO 202 receives a reference voltage Vref and generates an output voltage Vout. The output voltage Vout of the digital LDO 202 is dependent on a DAC code signal 204.

[0054] The current measurement system 200 includes a current determination unit 206 configured to receive the DAC code signal 204 and generate an output current signal 207 using the DAC code signal 204.

[0055] The current measurement system 200 may generate the output current signal 207 by performing a calculation using the DAC code signal 204 to calculate the output current, wherein the output current signal 207 is generated using the calculated output current.

[0056] The output current may also be referred to as load current, where load current is the current provided to a circuit component during operation of the LDO 202.

[0057] The output current can be calculated, for example, by multiplying the DAC code signal 204 by a variable that can be represented by the following equation: Iout=qq×v1 where lout is the output current, qq is the DAC code signal 204 and v1 is the variable.

[0058] For example, if it is known that each bit of the DAC code signal 216 indicates a current of 10 mA, the output current lout is provided when v1 = 10 mA.

[0059] Fig. 2B is a diagram of current measurement system 200 with a specific example of LDO 202, which includes a comparison circuit 208 configured to receive reference voltage Vref and a feedback voltage Vfb. Feedback voltage Vfb is dependent on the output voltage Vout of LDO 202. For example, in one specific embodiment, feedback voltage Vfb may be equal to output voltage Vout, and in another specific embodiment, feedback voltage Vfb may be a scaled-down version of output voltage Vout.

[0060] The operation of the comparison circuit 208 is to compare the reference voltage Vref and the feedback voltage Vfb and then generate an error signal 210 that depends on the comparison between the voltages Vref and Vfb. The comparison circuit 208 can comprise, for example, a main comparator or a 1-bit analog-to-digital converter. The error signal 210 can indicate the difference between the voltages Vref and Vfb.

[0061] The LDO 202 further includes a digital-to-analog converter (DAC) 212 that receives the error signal 210 and generates the DAC code signal 204 based on the error signal 210.

[0062] Fig. Figure 2C is a sketch of a specific embodiment of the LDO 202 as used in Fig. 2B and how it can be used with any of the current measurement systems described here, based on technical understanding.

[0063] The DAC 212 includes a shift register 214 configured to generate the DAC code signal 204. The shift register 214 may include an up-down counter.

[0064] The DAC 212 may include a plurality of current sources 216, 218, with each current source 216, 218 acting as a bit of the DAC code signal 204. It should be understood that two current sources 216, 218 are shown in the present embodiment, and that, as will be appreciated by those skilled in the art, other embodiments may include additional current sources. Current source 216 includes a transistor 220, and current source 218 includes a transistor 222.

[0065] The shift register 214 provides a plurality of outputs 219. Each output 219 is associated with a single bit of the DAC code signal 204 and is coupled to a gate of one of the transistors 220, 222.

[0066] The DAC 212 accepts a binary "word" (several bits with a scaled weight). The DAC 212 can, for example, perform binary-to-thermometer decoding: 001b=0000001101b=0000011⋅⋅100b=0001111⋅⋅111b=1111111

[0067] Thus, there is one output current source per bit of the DAC code signal 204. The thermometer is easier to control and adjust than binary-weighted current sources, but mathematically they are identical. The shift register 214 can generate a thermometer count, often referred to as a "walking one."

[0068] The DAC code signal 204 may be provided by the outputs 219 of the shift register 214. For example, if one output is 0 and the other output is 1, the DAC code signal 204 may have the value 01. In this example, the DAC code signal 204 may be a single signal indicating the value 01, or it may be formed from two distinct signals, one of which has the value 0 and the other the value 1, and together they form the DAC code signal 204. The bit values ​​may also be extracted from the current sources 216, 218 to provide the DAC code signal 204.

[0069] The DAC 212 includes buffer circuits 224, 226, with each of the outputs 219 coupled to a gate via one of the buffer circuits 224, 226. The buffer circuits 224, 226 may each include an inverter. In the present embodiment, the buffer circuit 224 includes an inverter 228, and the buffer circuit 226 includes an inverter 230.

[0070] The LDO 202 may include an output capacitor Co with an equivalent series resistance (ESR) Ro, wherein the DAC signal 204 is provided to the output capacitor Co to generate the output voltage Vout. Note that the resistance symbol indicated by Ro is an ESR of the capacitor Co and therefore does not represent a physical component implemented separately within the circuit.

[0071] Fig. 3A is a diagram of a current measurement system 300 according to a second embodiment of the present disclosure. The current measurement system 300 includes the current determination unit 206. The current measurement system 300 of the present embodiment further includes an average current determination unit 302 configured to receive the output current signal 207 and provide an average output current signal 304. The average output current signal 304 indicates the average output current of the LDO 202.

[0072] Fig. 3B is a diagram of current measurement system 300 showing a specific embodiment of average current determination unit 302. In the present embodiment, average current determination unit 302 includes a low-pass filter 306, wherein output current signal 207 is filtered by low-pass filter 306 to provide average output current signal 304. Low-pass filter 306 may include an infinite impulse response (IIR) filter 308.

[0073] Fig. 3C is a diagram of a current measurement system 310 according to a third embodiment of the present disclosure. The current measurement system 310 includes the current determination unit 206. The current measurement system 310 further includes an alarm circuit 312.

[0074] Fig. Figure 3D is a timing diagram illustrating an exemplary operation of circuit 312, with the output current signal (shown by curve 314) varying over time. The diagram shows two threshold current values ​​Th1, Th2.

[0075] During operation, if the output current lout exceeds the threshold Th1 (as illustrated by the output current signal rising above the threshold Th1 at time t1), the warning circuit 312 indicates that the output current lout has exceeded the threshold Th1. Similarly, if the output current falls below the threshold Th2, as shown, for example, at time t2, the warning circuit 312 indicates that the output current lout has fallen below the threshold Th2.

[0076] The warning circuit 312 may indicate that a threshold has been passed by providing an indication signal 313, which may be provided to the LDO 202, the current measurement system 310, or any other suitable circuit or system, wherein the receiving circuit or system responds accordingly to the indication that a threshold current has been passed.

[0077] Fig. 3E is a diagram of a current measurement system 316 according to a fourth embodiment of the present disclosure. The current measurement system 316 includes the current determination unit 206, the average current determination unit 302, and the warning circuit 312.

[0078] Fig. Figure 4A is a sketch of a particular embodiment of the LDO 202 implemented using the current measurement system 310 of Fig. 3C according to a fifth embodiment of the present disclosure. It will be appreciated that in a further embodiment, the current measurement system 310 is replaced by the current measurement system 316 of Fig. 3E or any other current measuring system can be provided according to technical understanding.

[0079] In the present embodiment, the LDO 202 includes a panic circuit 400, which may function as the panic circuit 120, as described with respect to Fig. 1A described.

[0080] In operation, panic circuit 400 detects when the feedback voltage Vfb exceeds a first threshold voltage value Vref1 or falls below a second threshold voltage value Vref2 and triggers a panic condition in response to the feedback voltage being outside the normal operating range. In the panic condition, panic circuit 400 controls DAC 212 to operate in a panic mode. This functionality can be provided by panic circuit 400 generating a panic signal 401, which is then provided to DAC 212 and switches DAC 212 into panic mode.

[0081] The LDO 202 further includes a clock circuit 402 that may function as the clock circuit 128, as described with respect to Fig. 1A. During operation, clock circuit 402 provides a clock signal 404 to comparison circuit 208. Clock circuit 402 operates in a fast mode during panic mode and in a slow mode otherwise. During fast mode, clock circuit 402 provides clock signal 404 at a higher frequency than the frequency provided in slow mode.

[0082] In a particular embodiment, the warning circuit 312 operates to indicate that the output current has passed outside an operating window enclosed by the thresholds during slow operation of the clock circuit 402.

[0083] In a particular embodiment, the warning circuit 312 may operate to indicate that the output current passes outside the operating window only during slow operation and not during fast operation.

[0084] The warning circuit 312 may receive a signal 403 from the clock circuit 402 indicating the current operating mode.

[0085] Fig. 4B is a diagram of a particular embodiment of the LDO 202 that may be used in accordance with a sixth embodiment of the present disclosure with a current measurement system of the present disclosure such as the current measurement system 310 of Fig. 3C can be used.

[0086] The panic circuit 400 includes a comparator 406 configured to compare the feedback voltage Vfb with the voltage threshold Vref1 and a comparator 408 configured to compare the feedback voltage Vfb with the voltage threshold Vref2.

[0087] The panic circuit 400 may include a logic circuit 410 configured to receive the outputs of the comparators 406, 408 and provide the panic signal 401 in response to the comparator outputs indicating that the feedback voltage Vfb has exceeded the voltage threshold Vref1 or fallen below the voltage threshold Vref2.

[0088] The LDO 202 may include a counter circuit 412 configured to receive the panic signal 401 and the error signal 210. The counter circuit 412 is also configured to increment the shift register 214 while the DAC 212 is operating in panic mode.

[0089] The clock circuit 402 may include a multiplexer 414 for receiving an input clock signal 416 and a frequency scaling unit 418. The clock circuit 402 is configured to provide the input clock signal 416 as the clock signal 404 during the fast mode, and the frequency scaling unit 418 is configured to reduce the frequency of the input clock signal 416 when generating the clock signal 404 during the slow mode.

[0090] Fig. Figure 5 is a sketch of a specific embodiment of the LDO 202 implemented using the current measurement system 200 of Fig. 2A according to a seventh embodiment of the present disclosure. It should be understood that in another embodiment, the current measurement system 200 may be provided by any other current measurement system as described herein according to the art.

[0091] In the present embodiment, the LDO 202 includes a DAC 500 that generates a DAC code signal 502. The operation of the DAC 500 will be clear to those skilled in the art based on the description of the DAC 212. Furthermore, in further embodiments, the DAC 500 may include any of the features described with respect to specific embodiments of the DAC 212, as understood by those skilled in the art. The DAC 212 may provide coarse regulation of the output voltage Vout, and the DAC 500 may provide fine regulation of the output voltage Vout.

[0092] The current determination unit 206 may be configured to generate the output current signal 207 using both DAC code signals 204, 502. The current determination unit 206 may generate the output current signal 207 by performing a calculation using the DAC code signals 204, 502 to calculate the output current, wherein the output current signal 207 is generated using the calculated output current.

[0093] For example, the output current can be calculated by multiplying each of the DAC code signals 204, 502 by a variable, which can be represented by the following equation: Iout=qq×v1+qqf×v2 where lout is the output current, qq is the DAC code signal 204, qqf is the DAC code signal 502, v1 is a first variable, and v2 is a second variable.

[0094] Fig. Figure 6 is a schematic diagram of a digital LDO 600 and a current measurement system 602 according to an eighth embodiment of the present disclosure. The digital LDO 600 includes the following components: • Clocked comparator (refers to the comparison circuit 208, as previously described). During operation, the clocked comparator 208 compares the target "vref" voltage (previously referred to as Vref) with the output "vout" voltage (previously referred to as Vout) and generates a "comp" signal (previously referred to as error signal 210) that is used by the coarse up-down counter (which includes a specific embodiment of the shift register 214) and the fine up-down counters (which refer to a specific embodiment of the DAC 500 that includes a shift register 604). • Panic comparators (refers to the specific implementation of the panic circuit 400). These form a window comparator and provide an output indicating whether the output voltage vout is too high (too high) or too low (too low). They are used to generate the panic. • Shift_counter_coarse (already described with respect to shift register 214). In the present embodiment, this is a 4-bit up-down counter that controls the large coarse-grained DAC 212. In the present embodiment, each bit 216, 218 of DAC 212 is a 10 mA current source, i.e., a 0 to 150 mA output. • Shift_counter_fine (described previously with respect to shift register 604). In the present embodiment, this is a 5-bit up-down counter that controls the small, fine-grained DAC 500. Each bit of DAC 500 is a 750µA current source, i.e., a 0 to 23.23mA output. The fine-grained DAC 500 is approximately 2.2 times larger than the coarse-grained DAC. When the up-down counter 604 reaches the limit (31 or 0), it indicates an increment ("inc") or decrement ("dec") of the coarse counter 212 to keep it within its controllable region. For example, when the upper limit of 31 is reached, one increment of the coarse DAC 212 adds 10 mA, so the fine DAC 500 subtracts the nearest value of 9.25 mA, or 12 codes, so the next output current increases by one increment of the fine DAC 500 of 0.75 mA. This allows the control loop to accommodate slowly changing loads without causing a "panic." • Clock_control (described previously with respect to clock circuit 402). In the present embodiment, panic circuit 402 controls the duration of the panic signals ("fast" and "fine") and divides the system clock for the slower fine control mode by "gating" the clock every 16 cycles, so that the "fine" mode runs at 1 / 16 of the clock speed. • Detection, which is the current measurement system 602, which can be provided by any of the current measurement systems described herein and as understood by those skilled in the art. In the present embodiment, the current measurement system 602 is a telemetry block that warns and indicates when the output current (labeled "Iload") reaches its maximum ("warn" and "limit") using the coarse and fine DAC codes ("qq" and "qqfine"). There is also a measurement of the output current using an IIR filter and the DAC codes. In the present example, two different indication signals are provided (labeled 606, 608), with indication signal 606 being provided when the output current Iload exceeds 125mA and indication signal 608 being provided when the output current Iload exceeds 152mA. • Overshoot detection. This is an RS latch-triggered pull-down resistor used when VOUT is above the "tooHi" threshold. When the load current drops (e.g., to zero), this is the active mechanism for discharging the output capacitor Co. In another embodiment, tt can also be used to discharge the output when the LDO is off.

[0095] The current measurement system 602 of the present embodiment provides the functionality of the average output current determination unit 302 by providing the average output current signal 304 and the warning circuit 312 by providing the current warning 606 and the limit flags 608.

[0096] Measuring the output current is a good indicator of the load's condition. It can provide an indication of a fault or (impending) system failure.

[0097] When the load exceeds the capacity of the LDO, the output voltage does not meet the required level, and the warning and limit flags allow the system to determine its operating state.

[0098] One advantage of the digital LDO 600 is that its operation can be easily measured digitally. Since the coarse and fine DAC outputs 204, 502 are scaled currents, this means the digital control values ​​are a reasonable representation of the output current. Regardless of the actual output current, the coarse and fine DAC codes 204, 502 have numerical limits that define the maximum output current.

[0099] The "Warning" and "Limit" flags are simple numeric thresholds with hysteresis that can warn the system when necessary. The average output current is a scaled and lightly filtered representation of the DAC output current.

[0100] In the present embodiment, the output current can be generated from the coarse and fine DAC codes using a scaled representation: / / calculate current, in multiples of 10uA current = qq*1000 + qqf*75;

[0101] This is easily achieved using integer math: / / calculate current, in multiples of 10uA / / current = qq*1000 + qqf*75; current = (qq<<10) - (qq<<4) - (qq<<3) + (qqf<<6) + (qqf<<3) + (qqf<<1) + qqf;

[0102] The "warning" and "limit" flags are hysteretic thresholds of this "current" value. This is only displayed when the circuit is not reacting to transients (i.e., when operating at the slow clock rate). Note: 5=logic 1 and 0=logic 0. / / only flag when not reacting to transients if(islow(fine)) { / / 125mA warn if(current>12500 && islow(iwarn)) iwarn=5; if(current<12000 && ishigh(iwarn)) iwarn=0; / / 152mA limit if(current>15200 && islow(ilim)) ilim=5; if(current<14700 && ishigh(ilim)) ilim=0;}

[0103] The current measurement system 602 may include a current mirror (not shown) as in Fig. 1B and as presented in Xiangyu Mao et al., A 1.2-A Calibration-Free Hybrid LDO With In-Loop Quantization and Auxiliary Constant Current Control Achieving High Accuracy and Fast DVS, IEEE Transactions on Circuits and Systems - I: Regular Papers, Vol. 69, No. 11, November 2022 . Knowing that each "coarse" and "fine" DAC current step is a fixed value (within the trimming tolerance), the average current calculation is accurate. Furthermore, using a current source (instead of an on / off MOS) improves the PSRR (as stated in the cited work).

[0104] Fig. 7A is a block diagram of an IIR filter 700 as may be implemented within the current measurement system 602 to provide the average output current signal, as previously described, for example, with respect to the average current determination unit 302 of Fig. 3B. IIR filtering of the fast and slow DAC current values ​​can be used to generate the average output current.

[0105] The IIR filter 700 comprises the multiplication units 702, 704 and the addition unit 706 as well as a delay unit block 708. Fig. Figure 7B is a schematic diagram of the IIR filter, including a comparator 710. The IIR filter 700 can be represented by the following transfer equation: H(z)=Y(Z)X(z)=a1−(1−a)Z−1 where in this example a=32.

[0106] The average current is provided using the IIR filter 700. In a specific embodiment, the following code may be used (which simplifies integer math). The calculated filter has a precision of 2 "decimal places" before an integer value is output. / / IIR filter of current value, with 2 DP's icalc = floor((32*icalc - icalc + 4*current) / 32); / / output iavg (1LSB=10uA), without DP's iavg = floor(icalc / 4);

[0107] Fig. Figure 8 is a graph showing the simulation results for a practical implementation of the IIR filter 700, where the data is clocked at 6.25 MHz (100 MHz / 16). The graph shows the frequency response, with the IIR filter 700 exhibiting a low-pass filter function with a -3 dB gain at 31.5 kHz (and -30 dB gain at 1 MHz). Gain (curve 800) and phase (curve 802) are shown.

[0108] Various improvements and modifications may be made without departing from the scope of the disclosure. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited non-patent literature

[0000] Jun Liu et. al., A Fully-Synthesizable 0.6V Digital LDO with Dual-Loop Control using standard digital cells, 2016 14th IEEE International New Circuits and Systems Conference (NEWCAS), Vancouver, BC, Canada, 2016, pp. 1-4

[0002] Xiangyu Mao et. al., A 1.2-A Calibration-Free Hybrid LDO With In-Loop Quantization and Auxiliary Constant Current Control Achieving High Accuracy and Fast DVS, IEEE Transactions on Circuits and Systems - I: Regular Papers, Vol. 69, No. 11, November 2022 [0010, 0103]

Claims

[1] A current measurement system for a digital low-dropout regulator (LDO) for receiving a reference voltage and generating an output voltage, wherein the output voltage of the digital LDO is dependent on a first DAC code signal, the current measurement system comprising: a current determination unit configured to: i) receiving the first DAC code signal; and ii) generating an output current signal using the first DAC code signal. [2] The current measurement system of claim 1, wherein the LDO comprises: a comparison circuit configured to: i) receiving the reference voltage; ii) receiving a feedback voltage, the feedback voltage being dependent on the output voltage; iii) comparing the reference voltage and the feedback voltage; and iv) generating an error signal which depends on the comparison between the reference voltage and the feedback voltage; and a first digital-to-analog converter configured to: i) receiving the error signal; ii) generating the first DAC code signal based on the error signal. [3] The current measurement system of claim 2, wherein the first digital-to-analog converter comprises a first shift register configured to generate the first DAC code signal. [4] The current measurement system of claim 3, wherein the first digital-to-analog converter comprises a plurality of first current sources, and each of the first current sources functions as a bit of the first DAC code signal. [5] The current measuring system of claim 4, wherein each of the first current sources comprises a first transistor. [6] The current measurement system of claim 5, wherein the first shift register comprises a plurality of outputs, each output associated with a single bit of the first DAC code signal and coupled to a gate of one of the plurality of first transistors. [7] Current measuring system according to one of the preceding claims, wherein the current determination unit is configured to generate the output current signal as follows: Calculating an output current using the first DAC code signal; and Providing the output current signal using the calculated output current. [8] The current measurement system of claim 7, wherein the current determination unit is configured to calculate the output current by multiplying the first DAC code signal by a first variable. [9] Current measuring system according to one of the preceding claims, comprising an average current determination unit configured to receive the output current signal and to provide an average output current signal. [10] A current measuring system according to any one of the preceding claims, comprising a warning circuit which indicates when the output current exceeds a first threshold current value or falls below a second threshold current value. [11] The current measurement system of claim 10, wherein the digital LDO comprises: a panic circuit configured to: i) detecting when the feedback voltage exceeds a first voltage threshold or falls below a second voltage threshold; and ii) controlling the first digital-to-analog converter to operate in a panic mode when the feedback voltage exceeds the first voltage threshold or falls below the second voltage threshold; and a clock circuit configured to: i) providing a clock signal for the comparison circuit; ii) operating in a fast mode during the panic mode by providing the clock signal at a first frequency; and iii) operating in a slow mode when not in panic mode by providing the clock signal at a second frequency, the second frequency being lower than the first frequency; wherein: the warning circuit is configured to: i) Indicate when the output current exceeds the first threshold current value or falls below the second threshold current value when the clock circuit is operating in slow mode. [12] A current measurement system according to any one of the preceding claims, wherein the digital LDO comprises a second digital-to-analog converter configured to: i) receiving the error signal; and ii) generating a second DAC code signal based on the error signal, wherein the output voltage is dependent on the second DAC code signal. [13] Voltage regulator system comprising: a digital low-dropout regulator (LDO) for receiving a reference voltage and generating an output voltage; and a current measuring system comprising: a current determination unit configured to: i) receiving a first DAC code signal, wherein an output voltage of the digital LDO is dependent on the first DAC code signal; and ii) generating an output current signal using the first DAC code signal. [14] A method for measuring a current from a digital low-dropout regulator (LDO) for receiving a reference voltage and generating an output voltage, the output voltage of the digital LDO being dependent on a first DAC code signal, the method comprising: Receiving the first DAC code signal at a current determination unit; and Generating an output current signal using the first DAC code signal, wherein the current determining unit is used.

Images