SAFETY OF RADAR Sequence Control Data for an Efficient Real-Time Programming Model

Abstract

A monolithic microwave semiconductor chip (MMIC semiconductor chip) comprising: a millimeter-wave signal generator configured to produce a signal having a plurality of signal sequences; a central sequence controller configured to control at least one decentralized sequence generator based on timestamp information and a configuration instance transmitted from the central sequence controller to the decentralized sequence generator to control at least one corresponding component in a cycle-accurate manner; a first fault detection mechanism corresponding to the transmission from the central sequence controller to the at least one decentralized sequence generator;and a second fault detection mechanism that is independent of the first fault detection mechanism, wherein the second fault detection mechanism corresponds to an execution by the decentralized sequence generator to control the at least one corresponding component based on the timestamp information and the configuration instance that are transmitted in the transmission.

Description

BACKGROUND

[0001] Radar sensors are used in a variety of applications to detect objects, with detection typically involving the measurement of distances, speeds, or angles of incidence associated with the detected targets. There is a growing need for radar sensors, particularly in the automotive sector, where they can be used in driver assistance systems (such as Advanced Driver Assistance Systems (ADAS)), like adaptive cruise control (ACC) or radar-based cruise control systems. These systems can automatically adjust a vehicle's speed to maintain a safe distance from other vehicles ahead (as well as other objects and pedestrians). Other examples of radar sensor applications in the automotive sector include blind spot monitoring, lane departure warning, and similar functions. SUMMARY

[0002] In some implementations, a radar semiconductor chip includes a ramp signal generator configured to produce a frequency-modulated ramp signal that has a plurality of frequency ramps of a ramp scenario; a memory configured to store a sequence control program that is associated with controlling one or more components of the radar semiconductor chip in a time-dependent manner;a main flow controller configured to: read the flow controller program from memory, derive from the flow controller program a plurality of instances of configuration data and a corresponding timestamp for each instance of configuration data, generate a plurality of telegrams, each telegram of the plurality of telegrams comprising at least one instance of configuration data, at least one timestamp associated with the at least one instance of configuration data, and an initial error detection code associated with the telegram, and transmit the plurality of telegrams;and at least one sequence generator configured to receive the majority of telegrams from the main sequence controller, to generate a second fault detection code for each telegram, to compare the first fault detection code and the second fault detection code associated with the same telegram, and to trigger a first alarm based on a mismatch between the first fault detection code and the second fault detection code.

[0003] In some implementations, a monolithic microwave semiconductor chip (MMIC semiconductor chip) comprises a millimeter-wave signal generator configured to produce a signal containing a plurality of signal sequences; a central control unit configured to control at least one decentralized sequence generator based on timestamp information and a configuration instance transmitted from the central control unit to the decentralized sequence generator to control at least one corresponding component in a cycle-accurate manner; and a first fault detection mechanism corresponding to the transmission from the central control unit to the at least one decentralized sequence generator.and a second fault detection mechanism that is independent of the first fault detection mechanism, wherein the second fault detection mechanism corresponds to an execution by the decentralized sequence generator to control the at least one corresponding component based on the timestamp information and the configuration instance that are transmitted in the transmission. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Implementations are described herein with reference to the attached drawings. Fig. Figure 1 is a diagram of an exemplary application of a frequency-modulated continuous wave (FMCW) radar sensor. Fig. Figure 2 illustrates an example of frequency modulation of a transmitted radar signal sent by the FMCW radar sensor. Fig. Figure 3 is a block diagram illustrating an example structure of the FMCW radar sensor. Fig. Figure 4 shows a schematic block diagram of a radar system according to one or more embodiments. Fig. Figure 5 illustrates an exemplary application cycle according to one or more implementations. Fig. Figure 6 illustrates an exemplary monolithic microwave semiconductor (MMIC) chip according to one or more implementations. Fig. Figure 7A illustrates an example sequence generator according to one or more implementations. Fig. Figure 7B illustrates an example sequence generator according to one or more implementations. Fig. Figure 8A illustrates an example sequence generator according to one or more implementations. Fig. Figure 8B illustrates an example time-lapse diagram of a timestamp validation check according to one or more implementations. Fig. Figure 9 illustrates an example sequence generator according to one or more implementations. Fig. Figure 10 illustrates a radar MMIC according to one or more implementations. DETAILED DESCRIPTION

[0005] Details are set forth below to provide a more thorough explanation of exemplary implementations. However, it is obvious to experts in the field that these implementations can be executed without these specific details. In other cases, well-known structures and devices are shown in block diagram form or in a schematic view rather than in detail to avoid obscuring the implementations. Additionally, features of the various implementations described below may be combined unless explicitly stated otherwise.

[0006] Furthermore, equivalent or identical elements, or elements with equivalent or identical functionality, are designated by equivalent or identical reference numerals in the following description. Since the identical or functionally equivalent elements in the figures are provided with the same reference numerals, a repeated description for elements with the same reference numerals can be omitted. Therefore, descriptions provided for elements with the same or identical reference numerals are mutually interchangeable.

[0007] Each of the illustrated x-axis, y-axis, and z-axis is essentially perpendicular to the other two axes. In other words, the x-axis is essentially perpendicular to the y-axis and the z-axis, the y-axis is essentially perpendicular to the x-axis and the z-axis, and the z-axis is essentially perpendicular to the x-axis and the y-axis. In some cases, a single reference symbol is shown to refer to a surface, or fewer than all instances of a part may be labeled with all surfaces of that part. All instances of the part may include associated surfaces of that part, although not every surface is labeled.

[0008] The orientations of the various elements in the figures are shown as examples, and the illustrated examples may be rotated relative to the depicted orientations. The descriptions provided herein and the following claims apply to any structures exhibiting the described relationships between various features, regardless of whether the structures are in the particular orientation shown in the drawings or rotated relative to such an orientation. Likewise, spatially relative terms such as "above," "below," "below," "underneath," "deeper," "over," "above," "middle," "left," and "right" are used herein for the convenience of description to express the relationship of one element to one or more other elements, as illustrated in the figures.The spatially relative terms are intended to encompass various orientations of the element, structure, and / or arrangement during use or operation, in addition to those depicted in the figures. A structure and / or arrangement may be oriented differently (rotated 90 degrees or in other orientations), and the spatially relative indexes used herein may be interpreted accordingly. Furthermore, the cross-sectional views in the figures show only features within the planes of the cross-sections and do not show materials behind the planes of the cross-sections unless otherwise indicated for the sake of simplicity.

[0009] It is understood that when an element is described as "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be intervening elements. In contrast, when an element is described as "directly connected" or "directly coupled" to another element, there are no intervening elements. Other words used to describe the relationship between elements should be interpreted in the same way (e.g., "between" versus "directly between," "adjacent" versus "directly adjacent," etc.).

[0010] In the implementations described herein or shown in the drawings, any direct electrical connection or coupling, e.g., any connection or coupling without any additional intervening elements, can also be implemented by an indirect connection or coupling, e.g., a connection or coupling with one or more additional intervening elements, or vice versa, as long as the general purpose of the connection or coupling, for example, to transmit a certain type of signal or to transmit a certain type of information, is substantially maintained. Features from different implementations can be combined to form other implementations. For example, variations or modifications described with respect to one of the implementations may also be applicable to other implementations unless otherwise stated.

[0011] For example, the terms "essentially" and "approximately" may be used herein to account for small manufacturing tolerances or other factors (e.g., within 5%) that are considered acceptable in the industry without deviating from the aspects of the implementations described herein. For example, a resistor with an approximate resistance value may practically have a resistance within 5% of the approximate resistance value. As another example, an approximate signal value may practically have a signal value within 5% of the approximate signal value.

[0012] In the present disclosure, expressions including ordinal numbers, such as "first," "second," and / or the like, may modify various elements. However, such elements are not restricted by the above expressions. For example, the above expressions do not restrict the order and / or importance of the elements. The above expressions are used merely for the purpose of distinguishing one element from the others. For example, a first box and a second box denote different boxes, although both are boxes. By another example, a first element could be called a second element, and likewise, a second element could also be called a first element, without deviating from the scope of the present disclosure.

[0013] A monolithic microwave semiconductor chip (MMIC), sometimes referred to as a single radar chip, can integrate all the core functions of a radar transceiver's high-frequency (RF) front end (e.g., local oscillator, power amplifier, low-noise amplifiers (LNAs), mixer, etc.), analog preprocessing of the intermediate frequency (IF) or baseband signals (e.g., filters, amplifiers, etc.), and analog-to-digital conversion into a single package. The RF front end typically includes multiple receive (RX) and transmit (TX) channels, particularly in applications employing beam steering techniques, phased antenna arrays, and other technologies. In radar applications, phased antenna arrays can be used to determine the angle of incidence of incoming RF radar signals (also known as the "direction of incidence" or DOA).

[0014] A microcontroller can act as a monitor for a radar MMIC by sending commands and receiving responses via one or more communication channels (e.g., a bus system such as a serial peripheral interface (SPI)). As a result, the radar MMIC can be controlled by the microcontroller.

[0015] Frequency-modulated continuous wave (FMCW) radar applications rely on transmitting multiple frequency sweeps in a timed manner. For example, the radar MMIC may include a ramp signal generator configured to produce a frequency-modulated ramp signal (e.g., an FMCW ramp signal) comprising multiple frequency ramps of a ramp scenario. In addition to generating the frequency-modulated ramp signal, the radar MMIC may be responsible for performing several on-chip functions, such as temperature monitoring, power or phase monitoring, receiver gain monitoring, decimation rate reconfiguration, and / or interference mitigation measures. These on-chip functions should be performed synchronously with a transmission of the frequency ramps or between different frequency ramp sequences of the ramp scenario.In some cases, the on-chip functions should be performed without disturbing the timing relationships between individual frequency ramps and / or between the different frequency ramp sequences of the ramp scenario.

[0016] FMCW radar systems are becoming increasingly common in vehicles to enable ADAS and autonomous driving features. Consequently, ensuring the proper functioning of an FMCW radar system is crucial for safer vehicle operation. Therefore, every parameter used in the FMCW radar system should be protected against random hardware failures to guarantee correct and safe operation.

[0017] Some implementations disclosed herein are directed to a radar MMIC that includes one or more protection mechanisms for safeguarding one or more aspects of the radar MMIC by detecting one or more faults. For example, a protection mechanism can safeguard the radar MMIC from random hardware failures by detecting and indicating the presence of a random hardware fault. For example, a protection mechanism can evaluate a data distribution between sequence control components of a sequence control circuit to detect one or more faults. Additionally or alternatively, a protection mechanism can evaluate a processing operation performed by one or more sequence control components of the sequence control circuit to detect one or more faults. Additionally or alternatively, a protection mechanism can evaluate the operation of a controlled component of the radar MMIC to detect one or more faults.Each protection mechanism can evaluate one or more aspects of the radar MMIC without disturbing the timing relationships between individual frequency ramps and / or between the different frequency ramp sequences of the ramp scenario.

[0018] Fig. Figure 1 is a diagram illustrating an exemplary application of an FMCW radar sensor in the form of a Radar Sensor 100 for measuring distances, velocities, or angles of incidence (AoAs) associated with objects also referred to as targets. As shown in Figure 1. Fig. As shown in Figure 1, the radar sensor 100 can have one or more TX antennas 102 and one or more RX antennas 104. In some implementations, a single antenna can be used that serves simultaneously as a TX antenna 102 and as an RX antenna 104.

[0019] During operation, the TX antenna 102 continuously emits an RF signal s RF(t) (also referred to as a transmitted radar signal) that is frequency-modulated, for example by a periodic linear frequency ramp signal (also referred to as a sweep or chirp signal). The transmitted radar signal s RF (t) is backscattered at a target T and a reflected signal y RF (t) (e.g. a backscattered signal, an echo signal, a received RF signal or a received radar signal) is received by the RX antenna 104. Fig. Figure 1 shows a simplified example - in practice, the radar sensor 100 can include a plurality of TX antennas 102 and RX antennas 104 in order to be able to determine an AoA of the received RF signal y RF (t) to determine and therefore to locate the target T with increased accuracy compared to a radar sensor that can use a single TX antenna and / or a signal RX antenna.

[0020] It is understood that “(t)” denotes an analog signal defined as a continuous-time signal that can change over a period t, and “[n]” denotes a digital signal defined as a discrete-time signal, where n is an integer and can represent an nth sample or a signal containing n samples. A signal can be represented with or without its continuous-time or discrete-time domain identifier (t) or [n], respectively. It is further understood that RF circuits, such as the Radar Sensor 100, can be used in fields other than radar. For example, RF circuits can be used in RF communication systems. Accordingly, the Radar Sensor 100 can be used in some implementations in RF applications other than radar, such as RF communication.

[0021] As stated above, Fig. 1 is provided as an example. Other examples may differ from what is provided in relation to Fig. 1 is described.

[0022] Fig. Figure 2 illustrates an example of frequency modulation of the RF signal s RF (t). As in the diagram above, 200 of Fig. Figure 2 illustrates that the RF signal s RF (t) a plurality of frequency ramps or a series of “chirps”; that is, the RF signal s RF (t) exhibits a sequence of sinusoidal signal profiles (e.g., waveforms) with an increasing frequency (referred to as an upward chirp) or a decreasing frequency (referred to as a downward chirp). In the in Fig. In example 2, the instantaneous frequency f increases. LO (t) of a chirp linearly from a starting frequency f START to a stopping frequency f STOP within a time interval T CHIRP , as shown in the lower diagram 210 of Fig. Figure 2 shows such chirps. These are also called linear frequency ramps. For a measurement, a sequence of frequency ramps is emitted and a resulting echo signal is evaluated in the baseband to detect one or more radar targets.

[0023] A frequency-modulated ramp signal, such as a local oscillator signal used to generate a radar signal, can comprise multiple radar frames, also known as radar operating cycles or chirp frames. A sequence of ramps can constitute a single radar frame. For example, a radar operating cycle can comprise several hundred radar ramps (passes), lasting a total of up to 10–30 milliseconds (ms). One frame length of the radar frame can correspond to one radar operating cycle. Successive ramps can have a short pause between them, and a longer pause can be used between successive radar frames. The longer pause between successive radar frames can be referred to as a configuration interval, during which one or more ramp parameters of the RF signal are adjusted. RF (t) can be set for subsequent radar frames. A ramp start time T STARTspecifies a start time for each chirp and can occur at a predetermined interval according to, for example, a number of clock cycles.

[0024] The starting frequency f START and the stopping frequency f STOP The ramps can lie within a frequency band with a minimum frequency Fmin and a maximum frequency Fmax. As a result, the minimum frequency Fmin and the maximum frequency Fmax define an operating frequency range or frequency band usable for the ramp signals, and thus the frequency range or frequency band of the radar application of a radar MMIC. In some implementations, the frequency range defined by a single ramp with the start and stop frequencies f START and f STOPThe defined threshold must be smaller than the usable radar frequency band. However, all ramps generated during operation can lie between the frequencies Fmin and Fmax of the radar frequency band (e.g., between 76 and 81 GHz) used to generate the ramp signals.

[0025] Fig. Figure 2 illustrates three identical linear frequency ramps or chirps. However, the parameters f START , f STOP , T CHIRP and / or the pause between the individual frequency ramps may vary depending on the actual implementation and / or use of the radar sensor 100. In practice, the frequency variation can be, for example, linear (linear ramp, frequency ramp), exponential (exponential ramp), or hyperbolic (hyperbolic ramp). In some implementations, the frequency may vary during the time interval T. CHIRPdecrease instead of increasing. Furthermore, in some implementations, a center frequency of each ramp (and therefore f) can be set. START and f STOP The frequency band can vary (e.g., from ramp to ramp or after detecting interference) to allow the use of all or part of the frequency band. In one example, the frequency band has a minimum frequency Fmin of 76 gigahertz (GHz) and a maximum frequency Fmax of 81 GHz.

[0026] While three identical linear frequency ramps or chirps with the same starting frequency f START and stopping frequency f STOP in Fig. 2 are illustrated, the starting frequency f START and the stopping frequency f STOP Thus, they can vary within a single radar frame or across multiple radar frames. A local oscillator signal S LO (t) can be used to generate the RF signal SRF(t). Thus, it can be said that the local oscillator signal S LO(t) and the RF signal SRF(t) are frequency-modulated ramp signals generated within an operating frequency range (e.g., a predefined radar frequency range). For example, the local oscillator signal S LO (t) be a frequency-modulated ramp signal comprising a plurality of frequency ramps, each starting at a respective ramp start frequency and ending at a respective ramp stop frequency, and the respective ramp start frequencies and ramp stop frequencies of the plurality of frequency ramps define a frequency range within the limits of the operating frequency range. The frequency range of the plurality of frequency ramps can be defined by the lowest start frequency f START and the highest stopping frequency f STOPThe frequency ramps can be defined within a given time interval (e.g., in an implementation where the frequency increases within each ramp). As mentioned above, the starting frequency f START and the stopping frequency f STOP This can be equivalent to a sequence control of frequency ramps, and thus the center frequency of each ramp can be constant. Alternatively, the center frequency of each ramp (and therefore f) can be START and f STOP The bandwidth (e.g., frequency range) of each ramp can vary from ramp to ramp or after interference is detected.

[0027] As stated above, Fig. 2 is provided as an example. Other examples may differ from what is provided in relation to Fig. 2 is described.

[0028] Fig. Figure 3 is a block diagram illustrating an exemplary structure of the radar sensor 100. As shown, the radar sensor 100 can include one or more TX antennas 102, one or more RX antennas 104, a radar MMIC 106 (which includes an RF front end 108, a baseband signal processing circuit 110, and an analog-to-digital converter (ADC) 112), a digital signal processor (DSP) 114, and a controller 116. In some implementations, the radar sensor 100 may include one or more TX antennas 102, one or more RX antennas 104, a radar MMIC 106 (which includes an RF front end 108, a baseband signal processing circuit 110, and an analog-to-digital converter (ADC) 112), a digital signal processor (DSP) 114, and a controller 116. In some implementations, the MMIC may include a digital front end (DFE) coupled downstream of the ADC 112.The digital front end can include circuit components dedicated to performing signal processing on a digital signal generated by the ADC 112 (e.g., digital filtering). In some cases, the DFE can include the DSP 114.

[0029] In the radar sensor 100, the one or more TX antennas 102 and the one or more RX antennas 104 are connected to the RF front end 108. The RF front end 108 can include circuit components associated with performing RF signal processing. These circuit components can include, for example, a local oscillator (LO), one or more RF power amplifiers, one or more LNAs, one or more directional couplers (e.g., rat-race couplers, circulators, or the like), or one or more mixers for downmixing (e.g., downconverting or demodulating) RF signals to a baseband or an IF band. The RF front end 108 can be integrated into the radar MMIC 106 with one or more other components, as shown in Fig. Figure 3 shows the IF band. The IF band is sometimes also referred to as the baseband. Accordingly, "baseband" and "IF band" can be used interchangeably here. Baseband signals are those signals on which radar targets are based.

[0030] Antenna arrays can be used instead of individual antennas. The example shown depicts a bistatic (or pseudo-monostatic) radar system, which has separate RX and TX antennas. In the case of a monostatic radar system, a single antenna or antenna array can be used to both receive and transmit electromagnetic (radar) signals. In this case, a directional coupler (e.g., a circulator) can be used to separate RF signals intended for transmission to the radar channel from RF signals intended for reception by the radar channel. In practice, radar systems often include multiple TX and RX channels, which allows for measurement of the direction (e.g., direction of incidence) from which the radar echoes are received.

[0031] In some implementations, the radar sensor 100 can include a plurality of TX antennas 102 and a plurality of RX antennas 104, enabling the radar sensor 100 to measure an AoA from which radar echoes are received. In such systems, individual TX channels and RX channels can be identical or similar in design and can be distributed across one or more radar MMICs 106.

[0032] In some implementations, a signal emitted by the TX antenna 102 can be in a range of approximately 20 GHz to approximately 100 GHz, such as in a range between approximately 76 GHz and approximately 81 GHz. As mentioned, a radar signal received by the RX antenna 104 includes radar echoes (e.g., chirp echo signals); that is, those signal components that are backscattered from one or more targets.

[0033] The received RF signal y RF(t) is, for example, downmixed to a baseband to create a baseband signal y BB (t), to generate, and the baseband signal y BB (t) is further processed in the baseband by analog signal processing performed by the baseband signal processing circuit 110. In some implementations, the baseband signal processing circuit 110 may be configured to process the baseband signal y. BB (t) to filter and / or amplify in order to generate an analog (baseband) output signal y(t) derived from the baseband signal y BB (t) is derived. The baseband signal y BB(t) can also be referred to as analog radar data. If the received RF signals are down-converted to the IF band, the baseband signal processing circuit 110 can be referred to as an IF signal processing circuit. Thus, the baseband signal processing circuit 110 can generally also be referred to as an analog signal processing circuit.

[0034] The ADC 112 can be configured to measure the baseband signal y BB (t) or to digitize the analog output signal y(t) to generate a digital baseband signal y[n], also referred to as a digital output signal. The digital baseband signal y[n] is representative of the radar data contained in the received RF signal y RF(t) can be received. The DSP 114 can be configured to further process the digital baseband signal y[n] in the digital domain. For example, the DSP 114 can be configured to receive the digital radar data in the digital baseband signal y[n] and process the digital radar data using the ramp parameters (e.g., the respective ramp start frequencies, the respective ramp stop frequencies, a bandwidth of a frequency range, a ramp start time, or a sampling start time) that are used to define the respective frequency ramps of the received RF signal y. RF (t) to generate an area Doppler map which can then be used by the DSP 114 for object detection, classification and so on.

[0035] In some implementations, the controller 116 is configured to control the operation of the radar sensor 100 (e.g., by controlling one or more other components of the radar sensor 100, as in Fig. 3 specified). The controller 116 can, for example, include a microcontroller unit (MCU).

[0036] In some implementations, the RF front end 108, the baseband signal processing circuit 110, the ADC 112, and / or the DSP 114 can be integrated into a single radar MMIC 106 (e.g., an RF semiconductor chip). Alternatively, two or more of these components can be distributed across multiple radar MMICs 106. In some implementations, the DSP 114 can be contained within the controller 116. In some implementations, the techniques associated with TX monitoring and / or RX monitoring can be performed by one or more components of the radar sensor 100, such as the DSP 114, the controller 116, or the like.

[0037] As stated above, Fig. 3 is provided as an example. Other examples may differ from what is provided in relation to Fig. 3 is described. The number and arrangement of devices and components that are described in Fig. Figure 3 is provided as an example. In practice, there may be additional devices or components, fewer devices or components, different devices or components, or devices or components arranged differently than those shown. Fig. 3 shown, give. Furthermore, two or more devices or components that are in Fig. 3 shown, are implemented within a single device or component, or a single device or component that is in Fig. Figure 3 shows that the device can be implemented as multiple, distributed devices or components. Additionally or alternatively, a set of devices or components (e.g., one or more devices or components) that are in Fig. 3 show, performing one or more functions that are not possible with another set of devices or components that are in Fig. 3 are shown, performed, and described.

[0038] Fig. Figure 4 shows a schematic block diagram of a radar system 400 according to one or more implementations. The radar system 400 comprises the radar MMIC 106 (e.g., a semiconductor chip) and an MCU 405. The MCU 405 can correspond to the controller 116, which, in conjunction with Fig. 3 is described. Thus, the MCU 405 can be an external controller. The radar MMIC 106 comprises a transmitter 410, which includes at least one transmit channel 411 for sending radar signals and / or at least one receive channel 420 for receiving and processing radar signals (e.g., radar echoes). The radar MMIC 106 can further include a sequence controller 430, a monitoring circuit 440, a ramp signal generator 450, a control / MMIC interface 460, and a power supply unit 470. The sequence controller 430 can be configured to receive and process the radar signals.

[0039] The transmit channel 411 can include one or more circuit components and is configured to generate radar transmit signals and output those signals to one or more antennas. As described in Fig. As specified in 4, the transmitter 410 can have one or more of the transmit channels 411. The receive channel 420 can include one or more circuit components and is configured to receive and process one or more radar receive signals from one or more antennas. As in Fig. As specified in 4, the receiving channel 420 can have one or more receivers 421, an analog frontend 422, an ADC 423, a digital frontend 424 and an interface 425.

[0040] The 422 analog front end can include all circuit components required for RF signal processing. Such circuit components can (but do not necessarily have to) include, for example, a local oscillator (LO), RF power amplifiers, line-level amplifiers (LNAs), directional couplers such as rat-race couplers, circulators, and mixers for downconverting RF signals to the baseband or an intermediate frequency (IF) band.

[0041] Antenna arrays can be used instead of individual antennas. The example shown depicts a bistatic (or pseudo-monostatic) radar system, which has separate RX and TX antennas. In the case of a monostatic radar system, a single antenna or antenna array can be used to both receive and transmit electromagnetic (radar) signals. In this case, a directional coupler (e.g., a circulator) can be used to separate RF signals intended for transmission to the radar channel from RF signals intended for reception by the radar channel. In practice, radar systems often include multiple TX channels and receive RX channels, which, among other things, allows for the measurement of the direction (e.g., DOA) from which the radar echoes are received.

[0042] In the case of an FMCW radar system, the transmitted RF signals radiated by the TX antenna can be in the range between approximately 20 GHz and 100 GHz (e.g., in the 21 to 26 GHz frequency band or the 76 to 81 GHz frequency band). As mentioned, the RF signal received by the RX antenna includes the radar echoes (for example, the signal backscattered from the radar targets).

[0043] The received RF signals are down-converted to the baseband (or IF band) and further processed in the baseband using analog signal processing at the 422 analog front end, which essentially involves filtering and amplifying the baseband signal. Since the received RF signals are down-converted to the IF band, the baseband signal processing chain of the 422 analog front end can be referred to as an IF signal processing chain. Thus, the processing chain of the 422 analog front end can generally be described as an analog signal processing chain.

[0044] The baseband signal is then digitized using the ADC 423 and further processed in the digital domain at the digital front end 424. The digital front end 424 comprises a digital signal processing chain, which is implemented, for example, in a DSP.

[0045] The sequence control 430 (e.g., a sequence control circuit) can be configured to determine a sequence control scheme for time-dependent functions of the transmitter 410 and / or the receive channel 420 and also to control circuit elements of the transmit channel 411 and / or the receive channel 420 according to the sequence control scheme. A time-dependent function of the transmitter 410 and / or the receive channel 420 can be a function that is or is intended to be executed in a manner that is temporally coordinated or synchronized with other time-dependent functions of the transmitter 410 and / or the receive channel 420 to ensure the correct operation of the radar sensor or radar system. Accordingly, the sequence control scheme represents a temporally coordinated or synchronized sequence of the behavior of individual time-dependent functions.

[0046] For example, the time-dependent functions may include a function of transmit channel 411 relating to the generation of a high-frequency radar transmit signal (e.g., a frequency-modulated ramp signal), a function of receive channel 420 relating to the processing of a high-frequency radar receive signal, a monitoring function for one or more circuit components of transmit channel 411 and / or receive channel 420, a monitoring function for a signal processed by transmit channel 411 and / or receive channel 420, or a calibration of transmit channel 411 and / or receive channel 420.For example, the time-dependent function can include a transmit calibration function for calibrating the transmit channel 411, a receive calibration function for calibrating the receive channel 420, a transmit monitoring function for monitoring the transmit channel 411, a receive monitoring function for monitoring the receive channel 420, a ramp function for generating ramp segments of a frequency-modulated ramp signal (e.g., a radar signal), an event monitoring function for monitoring for a trigger event, a read function for reading data from a read memory location of the radar MMIC 106, or a write function for writing data to a write memory location of the radar MMIC 106.

[0047] The sequence controller 430 can be implemented, for example, as a dedicated circuit or as a circuit for executing software (e.g., a sequence control program) and configured to determine the sequence control scheme and control circuit elements of the transmitter 410 and / or the receiver channel 420 according to the sequence control program. Thus, the sequence control program can be programmed with the sequence control scheme. In some implementations, the sequence controller 430 may be referred to as a digital timing machine, a timing control machine, or a timing controller.

[0048] In some implementations, the sequence controller 430 may include a decoder and a set of FIFO (First In, First Out) buffers. The decoder may be configured to read the sequence controller program (e.g., a specific instruction set comprising a set of opcodes associated with operating the radar device) from a sequence controller memory of the sequence controller 430 and to generate control values ​​and timestamps, at least partially, based on the sequence controller program. A control value may be a value to be provided as an input to a component of the radar MMIC 106 at a time specified by a corresponding timestamp. The component may be any on-chip component of the radar MMIC 106, including but not limited to the transmit channel 411, receive channel 420, monitoring circuit 440, and / or ramp signal generator 450.The control value (and optionally the timestamp) can be stored by a FIFO buffer assigned to the component, and the FIFO buffer can be configured to provide the control value as the input to the Radar MMIC 106 component at the time specified by the timestamp.

[0049] In some implementations, the Sequence Controller 430 may include a processing unit, such as a CPU, configured to read the Sequence Controller program from the Sequence Controller memory and execute the Sequence Controller program. Thus, the Sequence Controller 430 may include a memory (e.g., the Sequence Controller memory) that stores the Sequence Controller program for execution by the dedicated circuitry and / or by the processing unit.

[0050] Radar operations of at least one transmit channel 411 and / or at least one receive channel 420 are centrally controlled by the sequence control unit 430. Accordingly, the radar operations can be carried out essentially autonomously, including independently of external controls, due to the sequence control program executed by the sequence control unit 430.

[0051] Furthermore, a frequency-modulated ramp signal comprises a plurality of successive signal segments. Configuration ramp parameters for a ramp command can include frequency parameters for the respective signal segment, which specify a start frequency f. START , a stopping frequency f STOP , a time interval T CHIRPPhase parameters specify a phase setting for the transmitted signals, the slope of a frequency ramp, and / or the duration of a pause (e.g., the duration of a wait interval of a wait ramp segment) between adjacent signal segments. For example, a signal segment can correspond to a ramp segment of a frequency ramp in the radar signal. Some ramp segments can be frequency ramps with an increasing frequency (upward ramp) or a decreasing frequency (downward ramp). Whether a ramp segment is an upward or downward ramp can be implied by the start and stop frequencies or can be specified by a configuration parameter.

[0052] The radar MMIC 106 can, for example, be used for a (phase- or frequency-)modulated continuous-wave radar system. Accordingly, a transmit channel 411 and / or a receive channel 420 can be part of a modulated continuous-wave radar system, such as an FMCW radar in the automotive sector. The sequence control 430 can therefore be understood as a central sequence control unit that can coordinate essential time-critical functions of the automotive FMCW radar front end, so that radar operation is an autonomous process that, for example, does not require the participation of an external processor to perform the time-critical functions.

[0053] In addition to controlling a desired frequency profile of a radar transmission signal, the sequence control 430 can control various other aspects of a radar sensor or radar system in a synchronized manner.

[0054] For example, in transmitter 410 and specifically in a transmission channel 411, a power amplifier can be switched on and off in a synchronized manner, or a phase shift (implemented by a phase shifter) of radar transmission signals can be carried out in a synchronized manner.

[0055] Monitoring of a transmit channel 411 and / or a receive channel 420 can be performed by a monitoring circuit 440. This circuit can be controlled by the sequence controller 430 to trigger, activate, or deactivate a channel monitoring function in a synchronized manner according to the sequence controller scheme. For example, monitoring functions can be activated or deactivated in a synchronized manner during ramping, during calibration (e.g., amplification of a voltage-controlled oscillator), during cascaded operation, or during configuration of external components or slaves (e.g., via SPI or demultiplexing). The monitoring circuit 440 can monitor the receive channel 420. In some implementations, monitoring the receive channel 420 can include monitoring for and detecting interference (e.g.,This includes monitoring for interference signals (such as those from another radar device). In some implementations, monitoring the receive channel 420 may involve providing data to the MCU 405, which can then monitor for and detect interference based on that data. In some implementations, the control unit 430 may receive an indicator from the monitoring circuit 440 or the MCU 405 indicating that interference has been detected.

[0056] The ramp signal generator 450 can include a local oscillator, such as a phase-locked loop (PLL), configured to produce a signal with a plurality of signal sequences based on control values ​​received by the sequence controller 430. For example, the local oscillator can generate a frequency-modulated ramp signal based on control values ​​received by the sequence controller 430. Thus, the ramp signal generator 450 can be part of a millimeter-wave signal generator that includes the local oscillator and components of a transmit channel 411. The control values ​​can be used to set one or more ramp parameters, described herein and implemented by the ramp signal generator 450, to produce the frequency-modulated ramp signal. For example, the ramp parameters implemented by the ramp signal generator 450 can include at least one ramp start frequency f. STARTof the frequency-modulated ramp signal, a ramp stop frequency f STOP of the frequency-modulated ramp signal, a ramp frequency difference of the frequency-modulated ramp signal, a ramp time interval of the frequency-modulated ramp signal (e.g., time interval T) CHIRP ) and / or a ramp waiting time interval of the frequency-modulated ramp signal.

[0057] The Ramp Signal Generator 450 allows for synchronized adjustment of parameters such as the bandwidth of the PLL (e.g., charge pump current) or the activation or deactivation of more comprehensive modulation concepts (e.g., 2-point modulation, reset current). Similarly, loop filter reset circuits and monitoring functions can be activated or deactivated synchronously. Furthermore, voltages can be coarsely adjusted, calibration parameters (e.g., offset current, backlash, gain of a voltage-controlled oscillator) can be set, and a signal source (e.g., when using multiple PLLs) can be selected.

[0058] In the receiver 421, digital or analog filters (reset, configuration, bypass, etc.) and decimation rates can be set in a synchronized manner. Low-voltage differential signaling modes (LVDS modes) and calibrations can also be selected in a synchronized manner. Similarly, the receive channel 420 can be fully enabled or disabled, and a receive frame delay can be set, all in a synchronized manner. For example, the ADC 423 can also be configured, calibrated, enabled, or disabled in a synchronized manner.

[0059] Similarly, general-purpose inputs / outputs (GPIOs) can be configured in a synchronized manner, circuit components can be triggered to generate frequency ramps, or various circuit components (e.g., ADC 423) can be switched on or off. Furthermore, interrupts can be generated, or other chip functionality can be triggered.

[0060] To synchronize the time-dependent functions presented above as examples, the sequence control unit 430 can include an instruction processing unit (not shown) with a specific instruction set for determining the sequence control scheme. The instruction set can describe the configuration flow over time and may, for example, be similar to the instruction set of a general-purpose processor. For instance, the instruction set may include, firstly, specific instructions for configuring the circuit elements of a transmit channel 411 and / or a receive channel 420, and secondly, specific instructions for configuring frequency parameters of a high-frequency radar transmit signal generated by the transmit channel 411.

[0061] The sequence control 430 can thus be understood as a radar-specific sequence control unit with a command set that is assigned to a specific purpose in order to handle time-critical configurations in a highly integrated radar chip.

[0062] A 460 controller / MMIC interface, which is in Fig. As shown in Figure 4, it can also be used to send commands and responses between the MCU 405 and the sequence controller 430 via a communication channel or communication bus, such as an SPI, an LVDS or another type of communication interface.

[0063] A power supply unit 470 delivers power to the chip components and can be configured by the sequence control unit 430.

[0064] As stated above, Fig. 4 is provided as an example. Other examples may differ from what is provided in relation to Fig. 4 is described. The number and arrangement of devices and components that are in Fig. Figure 4 is provided as an example. In practice, there may be additional devices or components, fewer devices or components, different devices or components, or devices or components arranged differently than those shown. Fig. 4 shown, give. Furthermore, two or more devices or components that are in Fig. 4 are shown, are implemented within a single device or component, or a single device or component that is in Fig. As shown in Figure 4, the device can be implemented as multiple, distributed devices or components. Additionally or alternatively, a set of devices or components (e.g., one or more devices or components) that are in Fig. 4 shown, perform one or more functions that are not possible with another set of devices or components that are in Fig. 4 are shown, performed, and described.

[0065] Fig. Figure 5 illustrates an example Application Cycle 500 according to one or more implementations. The Application Cycle 500 can include a radar operating duty cycle that comprises an ON period and an OFF period. During the ON period, the Radar MMIC 106 can be configured to perform a warm-up calibration before executing a ramp scenario defined by a programming context. Additionally, during the ON period, the Radar MMIC 106 is configured to execute a ramp scenario in which multiple frequency ramp sequences (e.g., Frequency Ramp Sequence 1, Frequency Ramp Sequence 2, and Frequency Ramp Sequence 3) are transmitted according to ramp parameters defined in associated data of a programming context. In this example, the frequency ramp sequences are generated according to different sets of ramp parameters.Different ramp opcodes in the sequence control program can define the ramp parameters of the frequency ramp sequences. Successive frequency ramp sequences can be separated by a long wait ramp segment during which the frequency ramps are not generated (e.g., the frequency of the frequency-modulated ramp signal is held constant). The frequency ramps of each ramp scenario are typically preconfigured with one or more ramp parameters, such as start frequency, stop frequency, bandwidth, power amplifier setting, transmit phase, and duration. For example, each frequency ramp of a ramp scenario can have the same start frequency value, the same stop frequency value, and the same duration value. Different ramp scenarios can be configured with different ramp parameter values.

[0066] A setup operation (e.g., setup 1 and setup 2) can be performed by the Radar-MMIC 106 between frequency ramp sequences (e.g., during the long waiting ramp segment). A setup operation can be used to change one or more ramp parameters or to perform calibration between frequency ramp sequences.

[0067] Additionally, the Radar-MMIC 106 can be configured to monitor for reflected radar signals during the ON period. During the OFF period, the Radar-MMIC 106 can continue to monitor reflected radar signals but can no longer transmit radar signals. Consequently, the Radar-MMIC 106 can be configured in a reduced-power mode during the OFF period. During the OFF period, the MCU 405 can process the results of the monitoring provided by the Radar-MMIC 106 via signal processing.

[0068] The application cycles can differ in the following ways: by the type of calibration and monitoring performed, and by the ramp scenario used. Ramp scenarios include frequency ramp sequences, which further include a ramp set (e.g., shown as a triangular waveform). The ramp set can differ with respect to the starting frequency f. START , frequency ramp slope, stop frequency f STOP Ramp start time T START , time interval T CHIRP Transmit power and transmit phase are distinguished. Additionally, if there are multiple transmit channels, a ramp set can be defined according to which transmit channel is specified for transmitting the ramp set.

[0069] As stated above, Fig. 5 is provided as an example. Other examples may differ from what is provided in relation to Fig. 5 is described.

[0070] Fig. Figure 6 illustrates an exemplary radar MMIC 600 according to one or more implementations. The radar MMIC 600 can include a sequence controller 601 and a distributed sequence controller sublogic 602. The sequence controller 601 can be configured to control the sequence controller. The sequence controller 601 can control one or more components of the radar MMIC 600 that are provided in the distributed sequence controller sublogic 602. The sequence controller 601 can be similar to the sequence controller 430, which is used in conjunction with Fig. 4 is described. The one or more components can include one or more components of the ramp signal generator 450, such as the local oscillator, one or more components of the transmit channel 411, one or more components of the receive channel 420, and / or any other controllable component of the radar MMIC 106. For example, the radar MMIC 106 can include the decentralized sequence control sublogic 602, which is representative of one or more controllable components. Each controllable component can include digital logic for receiving and processing one or more control signals received by the sequence control 601.In some implementations, each decentralized sequence control sublogic can include 602 redundant logic circuits, which can be configured to produce the same outputs and can be checked in a lockstep manner to ensure that the redundant logic circuits are working correctly.

[0071] The 601 sequence controller can include a master sequence controller 604 (e.g., a central sequence controller) and a sequence generator 606 (e.g., a distributed sequence generator). In some implementations, the 601 sequence controller can include multiple sequence generators or multiple instances of the sequence generator 606. The master sequence controller 604 can control the sequence generator 606 (or any sequence generator) based on configuration data received from a controller, such as the MCU 405. For example, the MCU 405 can send a sequence controller program to the master sequence controller 604 via SPI.

[0072] The main flow controller 604 can include a memory 608, digital logic 610 (e.g., one or more logic circuits), one or more FIFO buffers 612, and a communication interface 614. In some implementations, the memory 608 can be located outside the main flow controller 604. In some implementations, the digital logic 610 can include redundant logic circuits that can be configured to produce the same outputs and can be checked in a lockstep manner to ensure that the redundant logic circuits are operating correctly.

[0073] Memory 608 can store the sequence control program, which is assigned to control one or more controllable components of the distributed sequence control sublogic 602 in a time-dependent manner (e.g., in a cycle-accurate manner). In some implementations, memory 608 can be random-access memory (RAM).

[0074] A logic circuit of the digital logic 610 can include a timestamp generator 616, a memory decoder 618, and an error detection code generator 620. The digital logic 610 can read the sequence control program from memory 608. The memory decoder 618 can derive multiple instances of configuration data from the sequence control program. Additionally, the timestamp generator 616 can derive a corresponding timestamp for each instance of configuration data from the sequence control program. The timestamp generator 616 can operate in conjunction with the memory decoder 618 to generate the timestamps. Each timestamp can specify a point in time at which a corresponding instance of configuration data associated with that timestamp is to be created by the sequence generator 606.The 618 memory decoder can derive the majority of instances of configuration data sequentially, so that a time corresponding to each subsequent timestamp is later than a time corresponding to a previous timestamp.

[0075] Each FIFO buffer 612 can sequentially store multiple instances of configuration data and a timestamp for each instance. Thus, the timestamp generator 616 and the memory decoder 618 can provide instances of configuration data and corresponding timestamps for a FIFO buffer 612.

[0076] The Fault Detection Code Generator 620 can sequentially read multiple instances of configuration data from the FIFO buffer 612 based on a FIFO sequence and sequentially generate multiple first fault detection codes based on the FIFO sequence. The Fault Detection Code Generator 620 can generate each first fault detection code based on at least one instance of configuration data and at least one corresponding timestamp associated with a given telegram. For example, in some implementations, a telegram might contain one instance of configuration data and one corresponding timestamp. Thus, the Fault Detection Code Generator 620 can generate a first fault detection code based on the instance of configuration data and the corresponding timestamp associated with that telegram.In some implementations, a telegram can contain a batch of configuration data instances (e.g., two or more configuration data instances) and corresponding timestamps. Thus, the Error Detection Code Generator 620 can generate an initial error detection code based on the batch of configuration data instances and their corresponding timestamps associated with that telegram. The initial error detection codes can be cyclic redundancy checks (CRCs), error correction codes (ECCs), or another type of error detection code.

[0077] In some implementations, each FIFO cache 612 can correspond to a controllable component or a specific set of controllable components. Thus, a FIFO cache 612 can store instances of configuration data for one or more corresponding controllable components.

[0078] The communication interface 614 can generate a plurality of telegrams and transmit the plurality of telegrams to the sequence generator 606. Each telegram in the plurality of telegrams can include at least one instance of configuration data, at least one timestamp associated with that at least one instance of configuration data, and the first error detection code associated with the telegram. For example, each telegram can include one instance of configuration data, the corresponding timestamp associated with that instance of configuration data, and the first error detection code associated with that instance of configuration data.Alternatively, each telegram can include multiple instances of configuration data, multiple timestamps associated with the multiple instances of configuration data, the first error detection code associated with the multiple instances of configuration data, and the multiple timestamps to be sent in the telegram.

[0079] The sequence generator 606 can receive multiple telegrams from the main sequence controller 604, generate a second fault detection code for each telegram, compare the first and second fault detection codes associated with the same telegram, and trigger a first alarm based on a mismatch between the first and second fault detection codes. Thus, the sequence generator 606 can incorporate a first fault detection mechanism corresponding to the transmission from the main sequence controller 604 to the sequence generator 606. Each sequence generator 606 can correspond to a controllable component or a specific set of controllable components.

[0080] A sequence generator 606 can include digital logic 622 (e.g., one or more logic circuits) and one or more FIFO buffers 624. A logic circuit of the digital logic 622 can include an error detection code generator 626 and an error detection code validator 628. In some implementations, the digital logic 622 can include redundant logic circuits that can be configured to produce the same outputs, which can be checked in a lockstep manner to ensure that the redundant logic circuits are operating correctly.

[0081] Since telegrams are received by the sequence generator 606, a FIFO buffer 624 can sequentially store the majority of configuration data instances and their timestamps. Thus, the majority of configuration data instances and timestamps received by the sequence generator 606 can be stored in the FIFO buffer 624 according to a FIFO sequence. In some implementations, the initial error detection codes can also be stored in the FIFO buffer 624 along with the majority of configuration data instances and their timestamps according to the FIFO sequence, as described in conjunction with... Fig. 7B is described.

[0082] The logic circuit of the 622 digital logic unit can store the first fault detection codes received in the telegrams and use these stored codes for comparison with the second fault detection codes generated by the 626 fault detection code generator. The 626 fault detection code generator can receive multiple instances of configuration data and timestamps extracted from the telegrams and generate multiple second fault detection codes based on these instances. In other words, when each telegram is received, the 622 digital logic unit stores the first fault detection code from the telegram and generates a second fault detection code based on the data received within the telegram (e.g., configuration data).(an instance of configuration data and the corresponding timestamp), and compares the first error detection code with the second error detection code.

[0083] If the data contained in the telegram has not been corrupted, the second fault detection code should match a corresponding first fault detection code previously generated by the fault detection code generator 620. The fault detection code validator 628 can compare the first and second fault detection codes associated with the same telegram and trigger the first alarm based on a mismatch between the first and second fault detection codes.

[0084] The digital logic 622 can generate a control signal for each instance of configuration data and apply each control signal to a corresponding component of the radar semiconductor chip at a time corresponding to a timestamp associated with the instance of configuration data. For example, a FIFO buffer 624 can sequentially store the plurality of instances of configuration data and the timestamps received from the main sequence controller 604. A logic circuit of the digital logic 622 can sequentially read the plurality of instances of configuration data from the FIFO buffer 624 based on a FIFO sequence and sequentially generate a plurality of control signals based on the plurality of instances of configuration data and a corresponding timestamp for each instance of configuration data.For example, the logic circuit of the digital logic 622 can generate a control signal with a control value to control a ramp parameter of the ramp signal generator 450.

[0085] In some implementations, the logic circuit of the 622 digital logic can generate a corresponding control signal associated with the instance of configuration data based on a match between the first and second fault detection codes. For example, if the first and second fault detection codes match, the logic circuit of the 622 digital logic can generate the corresponding control signal and transmit it to the distributed sequence control sublogic 602. Conversely, if the first and second fault detection codes do not match, the logic circuit of the 622 digital logic can prevent the generation of the corresponding control signal.In some implementations, the fault detection code validator 628 can transmit the first alarm to the MCU 405, and the MCU 405 can interrupt the digital logic 622 from generating the corresponding control signal.

[0086] As stated above, Fig. 6 is provided as an example. Other examples may differ from what is provided in relation to Fig. 6 is described.

[0087] Fig. Figure 7A illustrates an exemplary sequence generator 700A according to one or more implementations. The sequence generator 700A can include digital logic 701, which can comprise one or more logic circuits. Each logic circuit of the digital logic 701 can include a first fault detection code generator 702 for generating first fault detection codes based on instances of configuration data and timestamps extracted from telegrams received by the main sequence controller 604; a second fault detection code generator 703 for generating second fault detection codes based on instances of configuration data read from the FIFO buffer 624; and a timer 704 configured to detect a timer value (e.g.,to increment or count up a counter value, and include a fault detection code validator 705 to compare each first fault detection code with a corresponding second fault detection code. In some implementations, the digital logic 701 may include redundant logic circuits that can be configured to produce the same outputs, which can be checked in a lockstep manner to ensure that the redundant logic circuits are operating correctly.

[0088] Thus, the logic circuit of the digital logic 701 includes a second fault detection mechanism that is independent of the first fault detection mechanism. The second fault detection mechanism can be executed by the sequence generator 700A to control at least one corresponding component based on the timestamp information and the configuration instance transmitted in the transmission. For example, the second fault detection mechanism can be used to protect a processing stage of the FIFO buffer 624.

[0089] The first fault detection code generator 702 can generate a first fault detection code based on data received in a telegram (e.g., an instance of configuration data and the corresponding timestamp). Additionally, the second fault detection code generator 703 can generate a second fault detection code based on an instance of configuration data read from the FIFO buffer 624 and a current timer value from the timer 704. The second fault detection code generator 703 can sequentially read instances of configuration data from the FIFO buffer 624 based on a FIFO sequence and sequentially generate multiple second fault detection codes based on the FIFO sequence.The fault detection code validator 705 can be configured to compare the first and second fault detection codes corresponding to the same telegram to determine if they match. If the data moved through and output from the FIFO buffer 624 is not corrupted, the second fault detection code should match the first. The fault detection code validator 705 can compare the first and second fault detection codes associated with the same telegram and trigger a second alarm based on a mismatch between the first and second fault detection codes. Thus, the logic circuit of the digital logic 701 can detect data corruption in the FIFO buffers 624.

[0090] In general, the 700A sequence generator can be configured to receive a plurality of telegrams, each providing a plurality of instances of configuration data and corresponding timestamps, with each telegram comprising an instance of configuration data and a corresponding timestamp associated with that instance of configuration data; to generate a plurality of first corresponding error detection codes from the plurality of telegrams, comprising a first corresponding error detection code for each instance of configuration data; to store the plurality of instances of configuration data and their corresponding timestamps in a FIFO buffer according to a FIFO sequence; and to generate a plurality of second corresponding error detection codes, comprising a second corresponding error detection code for each instance of configuration data read from the FIFO buffer.based on the FIFO sequence, to compare the first corresponding fault detection code and the second corresponding fault detection code associated with the same instance of configuration data; and to trigger a second alarm based on a mismatch between the first corresponding fault detection code and the second corresponding fault detection code.

[0091] As stated above, Fig. 7A is provided as an example. Other examples may differ from what is provided in relation to Fig. 7A is described.

[0092] Fig. Figure 7B illustrates an exemplary sequence generator 700B according to one or more implementations. The sequence generator 700B can include digital logic 711, which can comprise one or more logic circuits. Each logic circuit of the digital logic 711 can include a first fault detection code generator 712 for generating first fault detection codes based on instances of configuration data and timestamps extracted from telegrams received by the main sequence controller 604; a second fault detection code generator 713 for generating second fault detection codes based on instances of configuration data read from the FIFO buffer 624; and a timer 714 configured to detect a timer value (e.g.,to increment or count up a counter value, and include an error detection code validator 715 to compare each first error detection code with a corresponding second error detection code. In some implementations, the digital logic 711 may include redundant logic circuits that can be configured to produce the same outputs, which can be checked in a lockstep manner to ensure that the redundant logic circuits are operating correctly.

[0093] Thus, the logic circuit of the digital logic 711 includes a second fault detection mechanism that is independent of the first fault detection mechanism. The second fault detection mechanism can be executed by the sequence generator 700B to control at least one corresponding component based on the timestamp information and the configuration instance transmitted in the transmission. For example, the second fault detection mechanism can be used to protect a processing step of the FIFO buffer 624.

[0094] The first fault detection code generator 712 can generate a first fault detection code based on data received in a telegram (e.g., an instance of configuration data and the corresponding timestamp) and store each first fault detection code in the FIFO buffer 624. Additionally, the second fault detection code generator 713 can generate a second fault detection code based on an instance of configuration data read from the FIFO buffer 624 and a current timer value from the timer 714. The second fault detection code generator 713 can sequentially read instances of configuration data from the FIFO buffer 624 based on a FIFO sequence and sequentially generate multiple second fault detection codes based on the FIFO sequence.The fault detection code validator 715 can be configured to compare the first fault detection code read from the FIFO buffer 624 with the second fault detection code corresponding to the same telegram to determine if they match. If the data processed by and output from the FIFO buffer 624 is not corrupted, the second fault detection code should match the first. The fault detection code validator 715 can compare the first and second fault detection codes associated with the same telegram and trigger a second alarm based on a mismatch between them.Thus, the logic circuit of the digital logic 711 can detect data corruption in the FIFO buffers 624.

[0095] In general, the Sequence Generator 700B can be configured to receive a plurality of telegrams, each providing a plurality of instances of configuration data and corresponding timestamps, with each telegram comprising an instance of configuration data and a corresponding timestamp associated with that instance of configuration data; to generate a plurality of first corresponding error detection codes from the plurality of telegrams, comprising a first corresponding error detection code for each instance of configuration data; to store the plurality of instances of configuration data and their corresponding timestamps in a FIFO buffer according to a FIFO sequence; and to generate a plurality of second corresponding error detection codes, comprising a second corresponding error detection code for each instance of configuration data read from the FIFO buffer.based on the FIFO sequence, to compare the first corresponding fault detection code and the second corresponding fault detection code associated with the same instance of configuration data; and to trigger a second alarm based on a mismatch between the first corresponding fault detection code and the second corresponding fault detection code.

[0096] As stated above, Fig. 7B is provided as an example. Other examples may differ from what is provided in relation to Fig. 7B is described.

[0097] Fig. Figure 8A illustrates an example sequence generator 800A according to one or more implementations. The sequence generator 800A may be similar to the sequence generator 606, 700A, or 700B, but may include additional digital logic to perform a timestamp underflow check. The main sequence controller (not illustrated) may be decoupled from a cycle-accurate timing request. For example, the buffer FIFOs of the main sequence controller may create a timing buffer to ensure early delivery of configuration data and timestamp instances.

[0098] The 800A sequence generator can include 801 digital logic, which comprises one or more logic circuits. Each logic circuit of the 801 digital logic can include a timestamp validation circuit 802 and a timer 803, which increments a timer value (e.g., a counter value). In some implementations, the 801 digital logic can include redundant logic circuits, which can be configured to produce the same outputs and can be checked in a lockstep manner to ensure that the redundant logic circuits are operating correctly.

[0099] When receiving telegrams, the sequence generator 800A's FIFO buffer 624 can sequentially store multiple instances of configuration data and a corresponding timestamp for each instance. The logic circuit of the digital logic 801 can sequentially read the multiple instances of configuration data from the FIFO buffer 624 based on a FIFO sequence, and the logic circuit can execute each instance of configuration data at an execution time corresponding to the corresponding timestamp associated with that instance. Additionally, the timestamp validation circuit 802 can be configured with a valid time window corresponding to a maximum delay time, extending from the execution time of the most recent instance of configuration data to a threshold time (e.g., the maximum delay time).The timestamp validation circuit 802 can use the timer value provided by the timer 803 to check the next corresponding timestamp read from the FIFO buffer 624 against the valid time window and trigger a third alarm if the next corresponding timestamp is outside the valid time window. In other words, the timestamp validation circuit 802 can check whether the next corresponding timestamp read from the FIFO buffer 624 exceeds the maximum delay time, which extends from the execution time of a most recent instance of configuration data, and trigger the third alarm if the next corresponding timestamp exceeds the maximum delay time.

[0100] As stated above, Fig. 8A is provided as an example. Other examples may differ from what is provided in relation to Fig. 8A is described.

[0101] Fig. Figure 8B illustrates an example timing diagram 800B of a timestamp validation check according to one or more implementations. The logic circuit of the digital logic 801 can read a first instance of configuration data and a corresponding first timestamp from the FIFO buffer 624 and execute the first instance of configuration data at a time corresponding to the first timestamp. At that time, the first instance of configuration data can be referred to as the most recent instance of configuration data.Next, the logic circuit of the digital logic 801 can read a second instance of configuration data and a corresponding second timestamp from the FIFO buffer 624. The timestamp validation circuit 802 can then perform the timestamp validation check by verifying whether the corresponding second timestamp lies within the valid time window, which is defined by the sum of the execution time of the first instance of configuration data (e.g., the time of the corresponding first timestamp) and the maximum delay time. If the corresponding second timestamp lies outside the valid time window due to exceeding the maximum delay time, the timestamp validation circuit 802 detects a timestamp underrun error and generates the third alarm.

[0102] As stated above, Fig. 8B is provided as an example. Other examples may differ from what is provided in relation to Fig. 8B is described.

[0103] Fig. Figure 9 illustrates an example Sequence Generator 900 according to one or more implementations. The Sequence Generator 900 may be similar to the Sequence Generator 606, 700A, or 700B, but may include additional digital logic to perform a FIFO empty check at one end of each ramp scenario.

[0104] Each logic circuit of Digital Logic 901 can include a Timer 902, which increments a timer value (e.g., a counter value) that can be used by the logic circuit to trigger a FIFO empty check. In some implementations, Digital Logic 901 can include redundant logic circuits that can be configured to produce the same outputs, which can be checked in a lockstep manner to ensure that the redundant logic circuits are operating correctly.

[0105] At the end of the ramp scenario, each instance of configuration data should have been read from the FIFO buffer 624 and processed by the logic circuit (e.g., converted into control signals to be applied to a corresponding component). The end of the ramp scenario can correspond to a specific timer value of the timer 902. Thus, the logic circuit can trigger the FIFO empty check when the timer value reaches the specific timer value associated with the end or ramp scenario. In some implementations, the digital logic 901, in response to receiving a command from the main sequence 604 at the end of the ramp scenario, can execute a dedicated firmware function to check if each FIFO buffer 624 is empty.The digital logic 901 can determine, based on the completion of the ramp scenario, whether a FIFO buffer 624 is empty, and trigger a fourth alarm based on the fact that the FIFO buffer 624 is not empty.

[0106] As stated above, Fig. 9 is provided as an example. Other examples may differ from what is provided in relation to Fig. 9 is described.

[0107] Fig. Figure 10 illustrates a Radar-MMIC 1000 according to one or more implementations. The Radar-MMIC 1000 may be similar to the Radar-MMIC 600, which is used in conjunction with Fig. The radar MMIC 1000 can comprise a sequence controller 1001 and a decentralized sequence controller sublogic 1002. The sequence controller can be configured to control the sequence controller. The sequence controller 1001 can comprise a main sequence controller 1004 (e.g., a central sequence controller) and at least one sequence generator 1006 (e.g., at least one decentralized sequence generator). The sequence generator 1006 can be similar to the FIF generator 606, 700A, 700B, 800A, 900, or any combination thereof.

[0108] The main sequence controller 1004 can include a first redundant logic circuit 1008, which includes a first logic circuit 1008a configured to generate a first plurality of outputs based on the sequence controller program, and a second logic circuit 1008b configured to operate in lockstep with the first logic circuit 1008a to generate a second plurality of outputs based on the sequence controller program. The first logic circuit 1008a and the second logic circuit 1008b can be similar to the logic circuit of the digital logic 610. Thus, the first plurality of outputs and the second plurality of outputs can be instances of configuration data, timestamps, and / or error detection codes. If the first logic circuit 1008a and the second logic circuit 1008b are operating correctly, their respective first and second outputs should be identical.

[0109] The main sequence control 1004 can also include a lockstep comparison circuit 1010 configured to compare the first plurality of outputs with the second plurality of outputs in a lockstep manner to generate a plurality of comparison results and to trigger a fifth alarm based on a mismatch between the first plurality of outputs and the second plurality of outputs.

[0110] The sequence generator 1006 can include a second redundant logic circuit 1012, comprising a first logic circuit 1012a configured to generate a first plurality of outputs based on the plurality of telegrams, and a second logic circuit 1012b configured to operate in a lockstep with the first logic circuit 1012a to generate a second plurality of outputs based on the plurality of telegrams. The first logic circuit 1012a and the second logic circuit 1012b can be similar to any of the logic circuits that are used in conjunction with Fig. 6, Fig. 7A, Fig. 7B, Fig. 8A, Fig. 9 or a combination thereof. Thus, the first and second multiple outputs can be error detection codes, timer values, control values, and / or comparison results. If the first logic circuit 1012a and the second logic circuit 1012b are operating correctly, their respective first and second outputs should match.

[0111] The sequence generator 1006 can also include a lockstep comparison circuit 1014 configured to compare the first plurality of outputs with the second plurality of outputs in a lockstep manner to generate a plurality of comparison results and to trigger a sixth alarm based on a mismatch between the first plurality of outputs and the second plurality of outputs.

[0112] The decentralized sequence control sublogic 1002 can include a third redundant logic circuit 1016, which includes a first logic circuit 1016a configured to generate a first plurality of outputs based on one or more control signals, and a second logic circuit 1016b configured to operate in a lockstep with the first logic circuit 1016a to generate a second plurality of outputs based on the one or more control signals.

[0113] The decentralized sequence control sublogic 1002 can also include a lockstep comparison circuit 1018 configured to compare the first plurality of outputs with the second plurality of outputs in a lockstep manner to generate a plurality of comparison results and to trigger a seventh alarm based on a mismatch between the first plurality of outputs and the second plurality of outputs.

[0114] As stated above, Fig. 10 is provided as an example. Other examples may differ from what is provided in relation to Fig. 10 is described.

[0115] The following provides an overview of some aspects of the present revelation:

[0116] Aspect 1: Radar semiconductor chip comprising: a ramp signal generator configured to produce a frequency-modulated ramp signal having a plurality of frequency ramps of a ramp scenario; a memory configured to store a sequence control program associated with controlling one or more components of the radar semiconductor chip in a time-dependent manner;a main flow controller configured to: read the flow controller program from memory, derive from the flow controller program a plurality of instances of configuration data and a corresponding timestamp for each instance of configuration data, generate a plurality of telegrams, each telegram of the plurality of telegrams comprising at least one instance of configuration data, at least one timestamp associated with the at least one instance of configuration data, and an initial error detection code associated with the telegram, and transmit the plurality of telegrams;and at least one sequence generator configured to receive the majority of telegrams from the main sequence controller, to generate a second fault detection code for each telegram, to compare the first fault detection code and the second fault detection code associated with the same telegram, and to trigger a first alarm based on a mismatch between the first fault detection code and the second fault detection code.

[0117] Aspect 2: Radar semiconductor chip according to Aspect 1, wherein the sequence generator is configured to generate a control signal for each instance of configuration data and to apply each control signal to a corresponding component of the radar semiconductor chip at a time corresponding to a timestamp associated with the instance of configuration data.

[0118] Aspect 3: Radar semiconductor chip according to Aspect 2, wherein the ramp signal generator is configured to generate the plurality of frequency ramps according to a plurality of ramp parameters, and wherein the sequence generator is configured to generate the control signal with a control value to control one ramp parameter of the plurality of ramp parameters.

[0119] Aspect 4: Radar semiconductor chip according to aspect 2 or 3, wherein the sequence generator is configured to produce a corresponding control signal associated with the instance of configuration data based on a match between the first fault detection code and the second fault detection code.

[0120] Aspect 5: Radar semiconductor chip according to one of aspects 1 to 4, wherein the main flow control is configured to generate each initial fault detection code based on at least one instance of configuration data and at least one corresponding timestamp associated with a respective telegram.

[0121] Aspect 6: Radar semiconductor chip according to one of aspects 1 to 5, where each timestamp indicates a time at which a respective instance of configuration data associated with the timestamp is to be created by the sequence generator.

[0122] Aspect 7: Radar semiconductor chip according to Aspect 6, wherein the main flow control is configured to derive the plurality of instances of configuration data sequentially such that a time corresponding to each subsequent timestamp is later than a time corresponding to a previous timestamp.

[0123] Aspect 8: Radar semiconductor chip according to any of aspects 1 to 7, wherein the main flow controller comprises: at least one FIFO buffer configured to sequentially store the plurality of instances of configuration data and a timestamp for each instance of configuration data; a fault detection code generator configured to sequentially read the plurality of instances of configuration data from the FIFO buffer based on a FIFO sequence and sequentially generate a plurality of first corresponding fault detection codes based on the FIFO sequence; and a communication interface configured to generate the plurality of telegrams based on the FIFO sequence.

[0124] Aspect 9: Radar semiconductor chip according to one of aspects 1 to 8, wherein the sequence generator comprises: at least one FIFO buffer configured to sequentially store the plurality of instances of configuration data and the at least one timestamp for each telegram; and a logic circuit configured to sequentially read the plurality of instances of configuration data from the FIFO buffer based on a FIFO sequence and to sequentially generate a plurality of control signals based on the plurality of instances of configuration data and a corresponding timestamp for each instance of configuration data.

[0125] Aspect 10: Radar semiconductor chip according to aspect 9, wherein the sequence generator is further configured to determine, based on a completion of the ramp scenario, whether the FIFO buffer is empty, and to trigger a second alarm based on the fact that the FIFO buffer is not empty.

[0126] Aspect 11: Radar semiconductor chip according to any of aspects 1 to 10, wherein the main flow control has: redundant logic circuits comprising: a first logic circuit configured to produce a first plurality of outputs based on the flow control program; and a second logic circuit configured to operate in a lockstep with the first logic circuit to produce a second plurality of outputs based on the flow control program; and a lockstep comparison circuit configured to compare the first plurality of outputs with the second plurality of outputs to produce a plurality of comparison results, and to raise a second alarm based on a mismatch between the first plurality of outputs and the second plurality of outputs.

[0127] Aspect 12: Radar semiconductor chip according to any of aspects 1 to 11, wherein the sequence generator has: redundant logic circuits comprising: a first logic circuit configured to generate a first plurality of outputs based on the plurality of telegrams; and a second logic circuit configured to operate in a lockstep with the first logic circuit to generate a second plurality of outputs based on the plurality of telegrams; and a lockstep comparison circuit configured to compare the first plurality of outputs with the second plurality of outputs to generate a plurality of comparison results, and to trigger a second alarm based on a mismatch between the first plurality of outputs and the second plurality of outputs.

[0128] Aspect 13: Radar semiconductor chip according to any of aspects 1 to 12, wherein the sequence generator comprises: a FIFO buffer configured to sequentially store the plurality of instances of configuration data and a corresponding timestamp for each instance of configuration data; a logic circuit configured to sequentially read the plurality of instances of configuration data from the FIFO buffer based on a FIFO sequence, wherein the logic circuit is configured to execute each instance of configuration data at an execution time corresponding to the corresponding timestamp associated with the instance of configuration data;and a timestamp validation circuit configured with a valid time window corresponding to a maximum delay time extending from the execution time of a most recent instance of configuration data, wherein the timestamp validation circuit is configured to check a next corresponding timestamp read from the FIFO buffer against the valid time window and to trigger a second alarm based on the fact that the next corresponding timestamp is outside the valid time window.

[0129] Aspect 14: Radar semiconductor chip comprising: a ramp signal generator configured to produce a frequency-modulated ramp signal having a plurality of frequency ramps of a ramp scenario; and a sequence generator configured to: receive a plurality of telegrams providing a plurality of instances of configuration data and corresponding timestamps, each telegram comprising an instance of configuration data and a corresponding timestamp associated with that instance of configuration data; generate a plurality of first corresponding fault detection codes from the plurality of telegrams, each comprising a first corresponding fault detection code for each instance of configuration data; and store the plurality of instances of configuration data and their corresponding timestamps in a FIFO buffer according to a FIFO sequence.to generate a plurality of second corresponding error detection codes, comprising a second corresponding error detection code for each instance of configuration data read from the FIFO buffer, to compare the first corresponding error detection code and the second corresponding error detection code associated with the same instance of configuration data based on the FIFO sequence, and to trigger a first alarm based on a mismatch between the first corresponding error detection code and the second corresponding error detection code.

[0130] Aspect 15: Radar semiconductor chip according to Aspect 14, further comprising: a memory configured to store a flow control program associated with controlling one or more components of the radar semiconductor chip in a time-dependent manner; and a main flow control configured to: read the flow control program from memory, derive from the flow control program the plurality of instances of configuration data and the corresponding timestamp for each instance of configuration data, generate the plurality of telegrams, and transmit the plurality of telegrams.

[0131] Aspect 16: Radar semiconductor chip according to Aspect 15, wherein the main flow control has: redundant logic circuits comprising: a first logic circuit configured to produce a first plurality of outputs based on the flow control program; and a second logic circuit configured to operate in a lockstep with the first logic circuit to produce a second plurality of outputs based on the flow control program; and a lockstep comparison circuit configured to compare the first plurality of outputs with the second plurality of outputs to produce a plurality of comparison results, and to raise a second alarm based on a mismatch between the first plurality of outputs and the second plurality of outputs.

[0132] Aspect 17: Radar semiconductor chip according to one of aspects 14 to 16, wherein the sequence generator is configured to generate a control signal for each instance of configuration data and to apply each control signal to a corresponding component of the radar semiconductor chip at a time corresponding to the relevant timestamp associated with the instance of configuration data.

[0133] Aspect 18: Radar semiconductor chip according to Aspect 17, wherein the sequence generator is configured to produce a corresponding control signal associated with the instance of configuration data based on a match between the first corresponding fault detection code and the second corresponding fault detection code.

[0134] Aspect 19: Radar semiconductor chip according to one of aspects 14 to 18, where the corresponding timestamp indicates a time at which the instance of configuration data associated with the corresponding timestamp is to be created by the sequence generator.

[0135] Aspect 20: Radar semiconductor chip according to any of aspects 14 to 19, wherein the sequence generator comprises: a timer configured to increment a counter value, wherein the sequence generator is configured to generate each first corresponding fault detection code based on a first respective data record received from a corresponding telegram, wherein the first respective data record includes a first respective instance of configuration data and a first corresponding timestamp associated with the first respective instance of configuration data, and wherein the sequence generator is configured to generate each second corresponding fault detection code based on a second respective data record received from a corresponding FIFO output of the FIFO buffer and the timer, wherein the second respective data record includes a second respective instance of configuration data and the counter value.where the counter value is assigned to a time at which the second respective instance of configuration data is output from the FIFO buffer.

[0136] Aspect 21: Radar semiconductor chip according to Aspect 20, wherein the sequence generator is further configured to: store each first corresponding fault detection code in the FIFO buffer according to the FIFO sequence, sequentially read each first corresponding fault detection code from the FIFO buffer based on the FIFO sequence, and compare each first corresponding fault detection code read from the FIFO buffer with the second corresponding fault detection code associated with the same instance of configuration data.

[0137] Aspect 22: Radar semiconductor chip according to one of aspects 14 to 21, wherein the sequence generator is further configured to determine, based on a completion of the ramp scenario, whether the FIFO buffer is empty, and to trigger a second alarm based on the fact that the FIFO buffer is not empty.

[0138] Aspect 23: Radar semiconductor chip according to any of aspects 14 to 22, wherein the sequence generator comprises: redundant logic circuits comprising: a first logic circuit configured to generate a first plurality of outputs based on the plurality of telegrams; and a second logic circuit configured to operate in a lockstep with the first logic circuit to generate a second plurality of outputs based on the plurality of telegrams; and a lockstep comparison circuit configured to compare the first plurality of outputs with the second plurality of outputs to generate a plurality of comparison results, and to trigger a second alarm based on a mismatch between the first plurality of outputs and the second plurality of outputs.

[0139] Aspect 24: Radar semiconductor chip according to any of aspects 14 to 23, wherein the sequence generator comprises: a logic circuit configured to sequentially read the plurality of instances of configuration data from the FIFO buffer based on the FIFO sequence, wherein the logic circuit is configured to execute each instance of configuration data at an execution time corresponding to the relevant timestamp associated with the instance of configuration data;and a timestamp validation circuit configured with a valid time window corresponding to a maximum delay time extending from the execution time of a most recent instance of configuration data, wherein the timestamp validation circuit is configured to check a next corresponding timestamp read from the FIFO buffer against the valid time window and to trigger a second alarm based on the fact that the next corresponding timestamp is outside the valid time window.

[0140] Aspect 25: Monolithic microwave semiconductor chip (MMIC semiconductor chip) comprising: a millimeter-wave signal generator configured to produce a signal having a plurality of signal sequences; a central sequence controller configured to control at least one decentralized sequence generator based on timestamp information and a configuration instance transmitted from the central sequence controller to the decentralized sequence generator to control at least one corresponding component in a cycle-accurate manner; a first fault detection mechanism corresponding to the transmission from the central sequence controller to the at least one decentralized sequence generator;and a second fault detection mechanism that is independent of the first fault detection mechanism, wherein the second fault detection mechanism corresponds to an execution by the decentralized sequence generator to control the at least one corresponding component based on the timestamp information and the configuration instance that are transmitted in the transmission.

[0141] Aspect 26: Radar semiconductor chip comprising: a ramp signal generator configured to produce a frequency-modulated ramp signal having a plurality of frequency ramps of a ramp scenario; a memory configured to store a sequence control program associated with controlling one or more components of the radar semiconductor chip in a time-dependent manner;a main flow controller configured to: read the flow controller program from memory, derive from the flow controller program a plurality of instances of configuration data and a corresponding timestamp for each instance of configuration data, generate a plurality of first corresponding error detection codes, comprising a first corresponding error detection code for each instance of configuration data, generate a plurality of telegrams, comprising a telegram for each instance of configuration data, each telegram comprising an instance of configuration data, the corresponding timestamp associated with the instance of configuration data, and the first corresponding error detection code associated with the instance of configuration data, and transmit the plurality of telegrams;and a sequence generator configured to receive the majority of telegrams from the main sequence control, to generate a second corresponding fault detection code for each telegram, to compare the first corresponding fault detection code and the second corresponding fault detection code associated with the same telegram, and to trigger a first alarm based on a mismatch between the first corresponding fault detection code and the second corresponding fault detection code.

[0142] Aspect 27: System configured to perform one or more operations listed in one or more of Aspects 1 to 26.

[0143] Aspect 28: Device comprising means for carrying out one or more operations listed in one or more of Aspects 1 to 26.

[0144] Aspect 29: Non-volatile, computer-readable medium storing a set of instructions, wherein the set of instructions comprises one or more instructions which, when executed by a device, cause the device to perform one or more operations listed in one or more of Aspects 1 to 26.

[0145] Aspect 30: Computer program product that includes commands or code for performing one or more operations listed in one or more of Aspects 1 to 26.

[0146] The foregoing disclosure provides illustration and description, but is not intended to be exhaustive or to limit implementations to the exact form disclosed. Modifications and variations are possible in light of the foregoing disclosure or may be derived from the execution of the implementations.

[0147] As used herein, the term component is to be understood broadly as hardware, firmware, or a combination of hardware and software. It is evident that systems and / or procedures described herein may be implemented in various forms of hardware, firmware, or a combination of hardware and software. The actual specialized control hardware or software code used to implement these systems and / or procedures does not limit the implementations. Thus, the operation and behavior of the systems and / or procedures have been described herein without reference to specific software code—it being understood that software and hardware may be designed to implement the systems and / or procedures based on the description herein.

[0148] Each of the processing components can be implemented as a central processing unit (CPU) or another type of processor that reads and executes a software program from a non-volatile, computer-readable recording medium, such as a hard disk or semiconductor storage device. For example, instructions can be executed by one or more processors, such as one or more CPUs, DSPs, general-purpose microprocessors, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), programmable logic controllers (PLCS), or other equivalent integrated or discrete logic circuits. Accordingly, the term "processor," as used herein, refers to any of the foregoing structures or any other structure suitable for implementing the techniques described herein.Software can be stored on a non-volatile, computer-readable medium such that the non-volatile, computer-readable medium includes a program code or program algorithm stored on it which, when executed, causes the processor, via a computer program, to perform the steps of a procedure.

[0149] A controller comprising hardware can also perform one or more of the techniques of this disclosure. A controller comprising one or more processors can use electrical signals and digital algorithms to perform its acquisition, analysis, and control functions, which may further include correction functions. Such hardware, software, and firmware can be implemented within the same device or within separate devices to support the various techniques described in this disclosure.

[0150] A signal processing circuit and / or a signal conditioning circuit can receive one or more signals (e.g., measurement signals) from one or more components in the form of raw measurement data and can derive further information from the measurement signal. Signal conditioning, as used here, refers to manipulating an analog signal in such a way that the signal meets the requirements of a subsequent processing stage. Signal conditioning can include analog-to-digital conversion (e.g., via an analog-to-digital converter), amplification, filtering, conversion, biasing, range matching, isolation, and any other processes necessary to make a signal suitable for post-conditioning processing.

[0151] Some implementations may be described herein in connection with thresholds. As used here, satisfying a threshold may refer to a value that is greater than the threshold, higher than the threshold, greater than or equal to the threshold, less than the threshold, less than the threshold, lower than the threshold, less than or equal to the threshold, equal to the threshold, or the like.

[0152] Even if certain combinations of features are listed in the claims and / or disclosed in the description, these combinations are not intended to limit the disclosure of implementations described herein. Many of these features can be combined in ways not expressly listed in the claims and / or disclosed in the description. For example, the disclosure includes each dependent claim in a set of claims in combination with each other individual claim in that set of claims and each combination of several claims in that set of claims. As used herein, an expression referring to "at least one of" a list of elements refers to any combination of those elements, including individual elements. As an example, "at least one of: a, b, or c" is intended to include a, b, c, a + b, a + c, b + c, and a + b + c, as well as any combination with multiples of the same element (e.g.,cover a + a, a + a + a, a + a + b, a + a + c, a + b + b, a + c + c, b + b, b + b + b, b + b + c, c + c and c + c + c or any other sequence of a, b and c).

[0153] Furthermore, it is understood that the disclosure of multiple actions or functions in the description or claims should not be interpreted as being in a specific sequence. Therefore, the disclosure of multiple actions or functions does not restrict them to a particular sequence unless such actions or functions are not interchangeable for technical reasons. Moreover, in some implementations, a single action may comprise or be broken down into multiple sub-actions. Such sub-actions may be included and form part of the disclosure of that single action unless expressly excluded.

[0154] No element, action, or command used herein should be construed as critical or essential unless expressly described as such. Furthermore, the article "the" as used herein should encompass one or more elements referred to in conjunction with the article "the" and may be used interchangeably with "the one or the several." Also, the terms "has," "have," "have," or the like, as used herein, should be open terms that do not restrict any element they modify (e.g., an element "has" A may also have B). Furthermore, the phrase "based on" should mean "at least partly based on" unless expressly stated otherwise. As used herein, the term "several" may be replaced by "a plurality of" and vice versa.Furthermore, the term “or”, as used herein, is to be inclusive when used in a series and may be used interchangeably with “and / or” unless expressly stated otherwise (e.g., when used in combination with “either” or “only one of”).

Claims

[1] Radar semiconductor chip which features: a ramp signal generator configured to produce a frequency-modulated ramp signal that has a plurality of frequency ramps of a ramp scenario; a memory configured to store a sequence control program assigned to control one or more components of the radar semiconductor chip in a time-dependent manner; a main control system configured to: to read the sequence control program from memory, to derive a plurality of configuration data instances and a corresponding timestamp for each configuration data instance from the flow control program, to generate a plurality of telegrams, wherein each telegram of the plurality of telegrams comprises at least one instance of configuration data, at least one timestamp associated with the at least one instance of configuration data, and an initial error detection code associated with the telegram, and to transmit the majority of telegrams; and at least one sequence generator configured to receive the majority of telegrams from the main sequence controller, generate a second fault detection code for each telegram, compare the first fault detection code and the second fault detection code associated with the same telegram, and trigger a first alarm based on a mismatch between the first fault detection code and the second fault detection code. [2] Radar semiconductor chip according to claim 1, wherein the sequence generator is configured to generate a control signal for each instance of configuration data and to apply each control signal to a corresponding component of the radar semiconductor chip at a time corresponding to a timestamp associated with the instance of configuration data. [3] Radar semiconductor chip according to claim 1 or 2, wherein the ramp signal generator is configured to generate the plurality of frequency ramps according to a plurality of ramp parameters, and wherein the sequence generator is configured to generate the control signal with a control value for controlling one ramp parameter of the plurality of ramp parameters. [4] Radar semiconductor chip according to claim 2 or 3, wherein the sequence generator is configured to generate a corresponding control signal associated with the instance of configuration data based on a match between the first fault detection code and the second fault detection code. [5] Radar semiconductor chip according to any of the preceding claims, wherein the main sequence control is configured to generate each first fault detection code based on the at least one instance of configuration data and at least one corresponding timestamp associated with a respective telegram. [6] Radar semiconductor chip according to one of the preceding claims, wherein each timestamp indicates a time at which a respective instance of configuration data associated with the timestamp is to be created by the sequence generator. [7] Radar semiconductor chip according to claim 6, wherein the main sequence control is configured to derive the plurality of instances of configuration data sequentially such that a time corresponding to each subsequent timestamp is later than a time corresponding to a previous timestamp. [8] Radar semiconductor chip according to any one of the preceding claims, wherein the main sequence control comprises: at least one FIFO (First In, First Out) buffer configured to sequentially store the plurality of configuration data instances and a timestamp for each configuration data instance; a fault detection code generator configured to sequentially read the plurality of instances of configuration data from the FIFO buffer based on a FIFO sequence and to sequentially generate a plurality of first corresponding fault detection codes based on the FIFO sequence; and a communication interface configured to generate the majority of telegrams based on the FIFO sequence. [9] Radar semiconductor chip according to any of the preceding claims, wherein the sequence generator comprises: at least one FIFO (First In, First Out) buffer configured to sequentially store the plurality of configuration data instances and the at least one timestamp for each telegram; and a logic circuit configured to sequentially read the plurality of instances of configuration data from the FIFO buffer based on a FIFO sequence and to sequentially generate a plurality of control signals based on the plurality of instances of configuration data and a corresponding timestamp for each instance of configuration data. [10] Radar semiconductor chip according to claim 9, wherein the sequence generator is further configured to determine, based on a completion of the ramp scenario, whether the FIFO buffer is empty, and to trigger a second alarm based on the fact that the FIFO buffer is not empty. [11] Radar semiconductor chip according to any one of the preceding claims, wherein the main sequence control comprises: redundant logic circuits, which include: a first logic circuit configured to generate an initial plurality of outputs based on the flow control program; and a second logic circuit configured to operate in a lockstep with the first logic circuit to generate a second plurality of outputs based on the flow control program; and a lockstep comparison circuit configured to compare the first plurality of outputs with the second plurality of outputs to generate a plurality of comparison results, and to trigger a second alarm based on a mismatch between the first plurality of outputs and the second plurality of outputs. [12] Radar semiconductor chip according to one of the preceding claims, wherein the sequence generator comprises: redundant logic circuits, which include: a first logic circuit configured to generate a first plurality of outputs based on the plurality of telegrams; and a second logic circuit configured to operate in a lockstep with the first logic circuit to generate a second plurality of outputs based on the plurality of telegrams; and a lockstep comparison circuit configured to compare the first plurality of outputs with the second plurality of outputs to generate a plurality of comparison results, and to trigger a second alarm based on a mismatch between the first plurality of outputs and the second plurality of outputs. [13] Radar semiconductor chip according to one of the preceding claims, wherein the sequence generator comprises: a FIFO (First In, First Out) buffer configured to sequentially store the plurality of instances of configuration data and a corresponding timestamp for each instance of configuration data; a logic circuit configured to sequentially read the plurality of instances of configuration data from the FIFO buffer based on a FIFO sequence, wherein the logic circuit is configured to execute each instance of configuration data at an execution time corresponding to the relevant timestamp associated with the instance of configuration data; and a timestamp validation circuit configured with a valid time window corresponding to a maximum delay time extending from the execution time of a most recent instance of configuration data, wherein the timestamp validation circuit is configured to check the next corresponding timestamp read from the FIFO buffer against the valid time window and trigger a second alarm based on the fact that the next corresponding timestamp is outside the valid time window. [14] Radar semiconductor chip which features: a ramp signal generator configured to produce a frequency-modulated ramp signal that features a plurality of frequency ramps of a ramp scenario; and a sequence generator configured to: to receive a plurality of telegrams, which provide a plurality of instances of configuration data and corresponding timestamps, wherein each telegram comprises an instance of configuration data and a corresponding timestamp associated with the instance of configuration data, to generate a plurality of first corresponding error detection codes from the plurality of telegrams, which include a first corresponding error detection code for each instance of configuration data, to store the majority of configuration data instances and their corresponding timestamps in a FIFO (First In, First Out) buffer according to a FIFO sequence, to generate a plurality of second corresponding error detection codes, which include a second corresponding error detection code for each instance of configuration data read from the FIFO buffer, based on the FIFO sequence, compare the first corresponding error detection code and the second corresponding error detection code that are associated with the same instance of configuration data, and to trigger an initial alarm based on a mismatch between the first corresponding fault detection code and the second corresponding fault detection code. [15] Radar semiconductor chip according to claim 14, further comprising: a memory configured to store a sequence control program assigned to control one or more components of the radar semiconductor chip in a time-dependent manner; and a main control system configured to: to read the sequence control program from memory, to derive the majority of configuration data instances and the corresponding timestamp for each configuration data instance from the flow control program, to generate the majority of telegrams, and to transmit the majority of telegrams. [16] Radar semiconductor chip according to claim 14 or 15, wherein the main sequence control comprises: redundant logic circuits, which include: a first logic circuit configured to generate an initial plurality of outputs based on the flow control program; and a second logic circuit configured to operate in a lockstep with the first logic circuit to generate a second plurality of outputs based on the flow control program; and a lockstep comparison circuit configured to compare the first plurality of outputs with the second plurality of outputs to generate a plurality of comparison results, and to trigger a second alarm based on a mismatch between the first plurality of outputs and the second plurality of outputs. [17] Radar semiconductor chip according to any one of claims 14 to 16, wherein the sequence generator is configured to generate a control signal for each instance of configuration data and to apply each control signal to a corresponding component of the radar semiconductor chip at a time corresponding to the corresponding timestamp associated with the instance of configuration data. [18] Radar semiconductor chip according to claim 17, wherein the sequence generator is configured to generate a corresponding control signal associated with the instance of configuration data based on a match between the first corresponding fault detection code and the second corresponding fault detection code. [19] Radar semiconductor chip according to any one of claims 14 to 18, wherein the corresponding timestamp indicates a time at which the instance of configuration data associated with the corresponding timestamp is to be created by the sequence generator. [20] Radar semiconductor chip according to one of claims 14 to 19, wherein the sequence generator comprises: a timer configured to increment a counter value, wherein the sequence generator is configured to generate each first corresponding error detection code based on a first respective data record received from a corresponding telegram, wherein the first respective data record comprises a first respective instance of configuration data and a first corresponding timestamp associated with the first respective instance of configuration data, and wherein the sequence generator is configured to generate every second corresponding fault detection code based on a second respective data record obtained from a corresponding FIFO output of the FIFO buffer and the timer, wherein the second respective data record comprises a second respective instance of configuration data and the counter value, the counter value being associated with a time at which the second respective instance of configuration data is output from the FIFO buffer. [21] Radar semiconductor chip according to claim 20, wherein the sequence generator is further configured to: to store each first corresponding fault detection code in the FIFO buffer according to the FIFO sequence, to sequentially read each first corresponding error detection code from the FIFO buffer based on the FIFO sequence, and to compare each first corresponding error detection code read from the FIFO buffer with the second corresponding error detection code associated with the same instance of configuration data. [22] Radar semiconductor chip according to one of claims 14 to 21, wherein the sequence generator is further configured to determine, based on a completion of the ramp scenario, whether the FIFO buffer is empty, and to trigger a second alarm based on the fact that the FIFO buffer is not empty. [23] Radar semiconductor chip according to one of claims 14 to 22, wherein the sequence generator comprises: redundant logic circuits, which include: a first logic circuit configured to generate a first plurality of outputs based on the plurality of telegrams; and a second logic circuit configured to operate in a lockstep with the first logic circuit to generate a second plurality of outputs based on the plurality of telegrams; and a lockstep comparison circuit configured to compare the first plurality of outputs with the second plurality of outputs to generate a plurality of comparison results, and to trigger a second alarm based on a mismatch between the first plurality of outputs and the second plurality of outputs. [24] Radar semiconductor chip according to one of claims 14 to 23, wherein the sequence generator comprises: a logic circuit configured to sequentially read the plurality of instances of configuration data from the FIFO buffer based on the FIFO sequence, wherein the logic circuit is configured to execute each instance of configuration data at an execution time corresponding to the relevant timestamp associated with the instance of configuration data; and a timestamp validation circuit configured with a valid time window corresponding to a maximum delay time extending from the execution time of a most recent instance of configuration data, wherein the timestamp validation circuit is configured to check the next corresponding timestamp read from the FIFO buffer against the valid time window and trigger a second alarm based on the fact that the next corresponding timestamp is outside the valid time window. [25] Monolithic microwave semiconductor chip (MMIC semiconductor chip) comprising: a millimeter wave signal generator configured to produce a signal that has a plurality of signal sequences; a central sequence controller configured to control at least one decentralized sequence generator based on timestamp information and a configuration instance transmitted from the central sequence controller to the decentralized sequence generator to control at least one corresponding component in a cycle-accurate manner; a first fault detection mechanism that corresponds to the transmission from the central sequence control to the at least one decentralized sequence generator; and a second fault detection mechanism that is independent of the first fault detection mechanism, wherein the second fault detection mechanism corresponds to an execution by the decentralized sequence generator to control the at least one corresponding component based on the timestamp information and the configuration instance that are transmitted in the transmission.

Images