LOW WIRE RESISTANCE STORAGE DEVICE AND METHOD FOR MAKING THIS

Abstract

A memory device comprises multiple memory cells, a word line, multiple bit lines, and multiple source lines. Each memory cell includes a once-programmable element (OTP element) and multiple selection transistors. The word line is connected to the gate terminals of the selection transistors of a memory cell. The bit lines are connected in parallel between a first node and a first OTP element terminal of the OTP element of the memory cell. The source lines are connected in parallel and connect second source / drain terminals of the selection transistors of the memory cell to a second node. A method for fabricating the memory device is also disclosed.

Description

CROSS-REFERENCE TO RELATED REGISTRATION

[0001] The present application claims priority over the preliminary US patent application No. 63 / 712,715, which was filed on October 28, 2024, and the contents of which are incorporated herein in their entirety by reference. BACKGROUND

[0002] Storage devices are responsible for storing and retrieving data. They exist in various forms and can be either programmable or non-programmable. Programmable storage devices, such as RAM (Random Access Memory), allow data to be written and overwritten multiple times, making them suitable for applications requiring frequent updates. In contrast, non-programmable storage devices, such as one-time programmable (OTP) devices, can only be written to once. Such devices can be used in various applications where data must be kept secure and protected from tampering.Regardless of their programmability, storage devices allow the reading of data stored within them, enabling electronic systems to access and use the information when needed. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Aspects of the present revelation are best understood from the detailed description below, when read together with the accompanying figures: Fig. Figure 1 is a schematic circuit diagram showing an example storage device according to various embodiments of the present disclosure; Fig. 2A is a schematic circuit diagram showing an example memory cell according to various embodiments of the present disclosure; Fig. Figure 2B is a schematic timing diagram showing an example relationship between a word line signal, a bit line signal, and a source line signal according to various embodiments of the present disclosure; Fig. Figure 3 is a schematic circuit diagram showing another example memory cell according to different embodiments of the present disclosure; Fig. Figure 4 is a schematic layout diagram showing an example of conductive lines of a memory cell according to various embodiments of the present disclosure; Fig. Figure 5 is a schematic layout diagram showing another example of conductive lines according to different embodiments of the present disclosure; Fig. 6A is a schematic circuit diagram showing another example storage device according to different embodiments of the present disclosure; Fig. Figure 6B is a schematic timing diagram showing an example relationship between a word line signal, a bit line signal, and a source line signal according to various embodiments of the present disclosure; Fig. Figure 7 is a schematic layout diagram showing another example of conductive lines according to different embodiments of the present disclosure; Fig. Figure 8 is a schematic layout diagram showing another example of conductive lines according to different embodiments of the present disclosure; Fig. Figure 9 is a schematic layout diagram showing another example of conductive lines according to various embodiments of the present disclosure; Fig. Figure 10 is a schematic layout diagram showing another example of conductive lines according to different embodiments of the present disclosure; Fig. Figure 11 is a schematic layout diagram showing another example of conductive lines according to different embodiments of the present disclosure; Fig. Figure 12 is a schematic layout diagram showing another example of conductive lines of a memory cell according to various embodiments of the present disclosure; Fig. Figure 13 is a schematic circuit diagram showing another example storage device according to different embodiments of the present disclosure; Fig. Figure 14 is a schematic circuit diagram showing another example storage device according to different embodiments of the present disclosure; Fig. Figure 15 is a schematic circuit diagram showing another example storage device according to different embodiments of the present disclosure; Fig. Figure 16 is a schematic circuit diagram showing another example storage device according to different embodiments of the present disclosure; Fig. Figure 17 is a schematic circuit diagram showing another example storage device according to different embodiments of the present disclosure; Fig. Figure 18 is a schematic circuit diagram showing another example storage device according to different embodiments of the present disclosure; Fig. Figure 19 is a schematic circuit diagram showing another example storage device according to different embodiments of the present disclosure; Fig. 20 is a flowchart of an example method for manufacturing a storage device according to various embodiments of the present disclosure; and Fig. Figure 21 is a schematic section diagram showing another example storage device according to different embodiments of the present disclosure. DETAILED DESCRIPTION

[0004] The following disclosure provides many different embodiments, or examples, for implementing various features of the present subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, forming a first element over or on top of a second element in the following description may include embodiments in which the first and second elements are in direct contact, and may also include embodiments in which additional elements may be formed between the first and second elements, so that the first and second elements may not be in direct contact. Furthermore, the present disclosure may repeat reference numbers and / or letters in the various examples.This repetition is done for the sake of simplicity and clarity and does not in itself prescribe any relationship between the various designs and / or configurations discussed.

[0005] Furthermore, terms relating to spatial relativity, such as "below," "under," "lower," "above," "on," "above," "below," and the like, may be used herein for the convenience of discussion to describe the relationship of one element or feature to another element or feature (or other elements or features), as illustrated in the figures. The terms relating to spatial relativity are intended to encompass various orientations of the structure used or operated in addition to the orientation illustrated in the figures. The device may be oriented in a different way (rotated by 90 degrees or otherwise oriented), and the terms relating to spatial relativity used herein may likewise be interpreted accordingly.

[0006] A storage device has multiple memory cells, arranged, for example, in an array of rows and columns, and allows data to be stored and retrieved. Storage devices can be either programmable or non-programmable. Programmable storage devices, such as RAM (Random Access Memory), allow data to be written and overwritten multiple times, making them suitable for applications that require frequent updates. Non-programmable storage devices, such as OTP (One-Time Programmable) storage devices, can only be written to once, ensuring that the data remains permanently and is protected from tampering.They are useful in various applications where data needs to be secure and protected from manipulation.

[0007] However, it can sometimes happen that OTP memory devices cannot be programmed. For example, during a programming operation, a programming voltage is applied to a memory cell of the OTP memory device via a bit line. The bit line may have a higher wire resistance than expected (e.g., due to a manufacturing anomaly), which limits the current flow required to program the memory cell, resulting in a programming error.

[0008] In certain examples described here, systems and methods feature a storage device that includes a memory cell connected to two or more bit lines. To reduce the overall wire resistance, the bit lines are connected in parallel. This parallel arrangement increases the probability that the memory cell will be successfully programmed.

[0009] Fig. Figure 1 is a schematic circuit diagram showing an example memory device according to various embodiments of the present disclosure. The example memory device 100, e.g., an OTP memory device, has several memory cells 110, several word lines (WLo-WLn), and several bit lines (BLo-BLn). An OTP memory device is a type of memory device that permanently stores data bits that cannot be modified after being written. For example, each memory cell 110 has an OTP element. In this embodiment, the OTP element has an antifuse (e.g., antifuse 210 in Figure 1). Fig. 2A) which is initially non-conductive, thus representing a logical '0' (or '1'). When programmed, the antifuse becomes conductive, for example by applying a high voltage or a high current, thus representing a programmed bit, for example a logical '1' (or '0').

[0010] The memory cells (110) can be arranged in an array of rows and columns. The memory cells (110) in each row are connected by their respective word lines (WLo-WLn). Likewise, the memory cells (110) in each column are connected by their respective bit lines (BLo-BLn). For example, each bit line (BLo-BLn) is connected between a voltage node (e.g., VDD node in Fig. 3) and the memory cells 110 in the respective column. In this embodiment, the storage device 100 further comprises several source lines (SLo-SLn), each of which connects the memory cells 110 in a column to a ground node (or VSS node).

[0011] Memory cell 110 stores one bit, either a logical '0' or '1', and undergoes a permanent and irreversible change when written or programmed. For example, this change occurs when a high voltage, i.e., a programming voltage, is applied to a corresponding bit line (BLo-BLn), ensuring that memory cell 110 cannot be reprogrammed (i.e., the bit stored in it cannot be overwritten). The word line (WLo-WLn) allows access to a corresponding memory cell 110 by activating it during read and write operations.

[0012] In certain embodiments, the memory cells 110 in each column are connected between two or more bit lines, e.g., two or more bit lines (BL[0]), connected in parallel, and two or more source lines, e.g., two or more source lines (SL[0]), connected in parallel. This parallel configuration reduces the total wire resistance of the bit lines (BL[0]) as well as the total wire resistance of the source lines (SL[0]), thereby minimizing the wire resistance opposing the current flow. The lower resistance in the wiring can help ensure that sufficient programming voltage or current can be reliably supplied to the memory cell 110, thereby increasing the probability that the antifuse will be successfully programmed into its conductive state.

[0013] To read memory cell 110, the word line, e.g., word line (WL[0]), corresponding to the desired row is activated by applying, for example, a high word line signal (WL signal) to it. The bit line, e.g., bit line BL[0], is then used to detect the state of memory cell 110. If the antifuse has been programmed, it exhibits a unique electrical characteristic, such as reduced resistance or increased current flow, indicating that a conductive path has been created. This characteristic corresponds to the programmed logical state, which represents a logical '1' (or '0'). The increase in current flow or the reduction in resistance is due to the creation of the conductive path across the antifuse, which is permanent and not reprogrammable. If, however, the antifuse is not programmed (i.e.,If the circuit remains intact, it maintains its high-resistance state, and memory cell 110 exhibits a different electrical signal corresponding to a logical '0' (or '1'). The absence of a conductive path results in higher resistance or lower current flow. The programmed data is read by sampling the voltage or current levels on the bit line (BL[0]), which reflect the state of memory cell 110. By further processing, e.g., amplifying, these voltage or current levels, the bit stored in memory cell 110 can be precisely retrieved, thus determining whether memory cell 110 holds a logical '1' or '0'.

[0014] In an alternative embodiment, the OTP element includes a fuse. Unlike an antifuse, which creates a conductive path during programming, a fuse is initially conductive and becomes non-conductive when it "burns out" or is programmed.

[0015] Fig. 2A is a schematic circuit diagram showing an example memory cell 200 according to various embodiments of the present disclosure. As in Fig. As shown in Figure 2A, the example memory cell 200, e.g., memory cell 110, has the form of a memory cell with four transistors and one resistor (4T1R memory cell) and features an OTP element 210 and four selection transistors 220 (for simplicity, only one of the selection transistors is shown in Figure 2A). Fig. (labeled 2A). The OTP element 210 has a first OTP element terminal that is connected to two or more bit lines (BLs). For example, each bit line (BL) is connected to a voltage node, e.g., a VDD node of Fig. 3. The memory cell 200 also has an interconnect line 230 that connects the bit lines (BLs) in parallel. The first OTP element terminal of the OTP element 210 is connected to the interconnect line 230.

[0016] In this embodiment, the OTP element 210 comprises an antifuse in the form of a magnetic tunnel junction (MTJ), a dielectric breakdown antifuse, a phase-change material-based antifuse, a resistive switching element, any other type of antifuse technology that transitions from a high-resistance state to a low-resistance state when programmed or written, or a combination thereof.

[0017] The selection transistor 220 in this embodiment is a field-effect transistor (FET) and has a gate terminal, a first source / drain terminal, and a second source / drain terminal. The gate terminals are connected to each other and to the word line (WL). The first source / drain terminals of the selection transistor 220 are connected to each other and to the second OTP element terminal of the OTP element 210. For example, the memory cell 200 also has an interconnect line 240 that connects the first source / drain terminals to each other. The second OTP element terminal of the OTP element 210 is connected to the interconnect line 240. The second source / drain terminals of the selection transistors 220 are connected to each other and to two or more source lines (SLs). For example, each source line (SL) is connected to a ground node (or VSS node).Memory cell 200 also has an interconnect line 250 that connects the source lines (SLs) in parallel. The second source / drain terminals of the selection transistors 220 are connected to each other and to the interconnect line 250.

[0018] In some embodiments, each selection transistor 220 is an n-type metal-oxide-semiconductor FET. In other embodiments, at least one of the selection transistors 220 is a p-type metal-oxide-semiconductor FET. In an alternative embodiment, the memory cell 200 comprises a planar transistor, a gate-all-around transistor (GAA transistor), a back-end metal-oxide-semiconductor, any suitable transistor, or a combination thereof.

[0019] From the preceding description, it is clear that memory cell 200 uses a combination of an OTP element 210 and a selection transistor 220 to permanently store a bit by changing the state of the OTP element 210. Before programming, for example, the OTP element 210 is intact, i.e., there is no conductive path through it, resulting in high resistance. In this state, the OTP element 210 behaves like an open circuit, preventing any significant current flow. The absence of a conductive path indicates that a logical '0' (or '1') is stored in memory cell 200. During a write or programming operation, the selection transistor 200 is activated by a high (or low) word line (WL) signal ('1') on the word line (WL), thus enabling access to memory cell 200. For example, Fig. Figure 2B shows a schematic timing diagram illustrating an example relationship between a word line signal (WL signal), a bit line signal (BL signal), and a source line signal (SL signal) according to various embodiments of the present disclosure. The memory cell 200 is then connected between the bit lines (BLs) and the source lines (SLs). A programming voltage, i.e., a higher voltage, is then applied across the bit lines (BLs), the memory cell 200, and the source lines (SLs), causing a current to flow through them. This current can permanently modify the structure of the OTP element 210, for example, by creating a conductive path and reducing its resistance to a low (or programmed) state. This programmed state represents a logical '1' (or '0') stored in the memory cell 200.Because the bit lines (BLs) are connected in parallel, the total wire resistance of the bit lines (BLs) is reduced. Since the source lines (SLs) are also connected in parallel, the total wire resistance of the source lines (SLs) is likewise reduced. This reduction in wire resistance improves current flow efficiency, thereby increasing the probability that memory cell 200 will be successfully programmed.

[0020] During a read operation, a high (or low) word line (WL) signal at the word line (WL) activates the select transistor 220 and connects the memory cell 200 between the bit lines (BLs) and the source lines (SLs). Instead of the higher programming voltage used for programming, a much lower read voltage is applied across the bit lines (BLs), memory cell 200, and the source lines (SLs). When the OTP element 210 is programmed (i.e., in a low-resistance state), current flows through it, and a sampling amplifier connected to memory cell 200 interprets the bit stored in memory cell 200 as a logical '1' (or '0'). Otherwise, i.e., when the OTP element 210 is non-conductive, essentially no current flows through it.In this state, the sampling amplifier interprets the bit stored in memory cell 200 as a logical '0' (or '1').

[0021] In an alternative embodiment, the source line (SL) is connected to the VDD node, while the bit line (BL) is connected to the ground node (or VSS node). In some embodiments, the memory cell 200 is connected between several bit lines (BL) connected in parallel and a single source line (SL). In other embodiments, the memory cell 200 is connected between a single bit line (BL) and several source lines (SLs) connected in parallel.

[0022] In certain embodiments, the memory cell 200 also has one or more potential-free OTP elements 260 to 280. Each OTP element 260 to 280 has a first OTP element terminal that is connected to the bit line (BL) and a second potential-free OTP element terminal (i.e., the second OTP element terminal has no electrical connection to the memory cell 200).

[0023] Although memory cell 200 is illustrated as a 4T1R memory cell, it is understood after reading this revelation that memory cell 200 can have any number of OTP elements and selection transistors, such as 1T1R, 2T2R, 1T1C (one transistor, one capacitor), 1T1MTJ (one transistor, one magnetic tunnel junction), and the like.

[0024] In an alternative embodiment, the OTP element 210 has a fuse. Unlike an antifuse, which creates a conductive path during programming, a fuse is initially conductive and becomes non-conductive when it "burns out" or is programmed.

[0025] Fig. Figure 3 is a schematic circuit diagram showing another example memory cell 300 according to various embodiments of the present disclosure. As in Fig. As shown in Figure 3, the example memory cell 300, e.g., memory cell 300, has an OTP element 310 and a selection transistor 320. The OTP element 310 has a first OTP element terminal that is connected to two or more bit lines (BLs). For example, each bit line (BL) is connected to a voltage node (VDD node). Memory cell 300 also has an interconnect line 330 that connects the bit lines (BLs) in parallel. The first OTP element terminal of the OTP element 310 is connected to the interconnect line 330. The selection transistor 320 has a gate terminal, a first source / drain terminal, and a second source / drain terminal. The gate terminal is connected to the word line (WL). The first source / drain terminal of the selection transistor 320 is connected to the second OTP element terminal of the OTP element 310.The second source / drain terminal of the select transistor 320 is connected to two or more source lines (SLs). For example, each source line (SL) is connected to a ground node (or VSS node). The memory cell 300 also has an interconnect line 350 that connects the source lines (SLs) in parallel. The second source / drain terminal of the select transistor 320 is connected to the interconnect line 350. In this embodiment, the OTP element 310 is an antifuse.

[0026] From the above description, with further reference to Fig. 2B The selection transistor 320 is activated during a write or programming operation by a high (or low) word line signal (WL signal) at the word line (WL), thus enabling access to memory cell 200. At this point, memory cell 300 is connected between the bit lines (BLs) and the source lines (SLs). A programming voltage is then applied across the bit lines (BLs), memory cell 200, and the source lines (SLs), causing a current to flow. This current can permanently modify the structure of the OTP element 310, for example, by creating a conductive path and reducing its resistance to a low (or programmed) state. This programmed state represents a logical '1' (or '0') stored in memory cell 300. Since the bit lines (BLs) are connected in parallel, the total wire resistance, e.g.,The equivalent wire resistances of 360 and 370 of the bit lines (BLs) are reduced. Since the source lines (SLs) are connected in parallel, the total wire resistance, e.g., the equivalent wire resistances of 380 and 390 of the source lines (SLs), is also reduced. This reduction in wire resistance improves current flow efficiency, thereby increasing the probability that memory cell 300 will be successfully programmed.

[0027] Fig. Figure 4 is a schematic layout diagram showing examples of conductive lines of a memory cell (e.g., memory cell 200) according to various embodiments of the present disclosure. As in Fig. As shown in Figure 4, the example layout 400 has two or more bit lines (BLs), one word line (WL), one interconnect line (IL), and two or more vias (VIAs). The bit lines (BLs) are spaced apart along a first direction (x), and each extends in a second direction (y) perpendicular to the first direction (x). In certain embodiments, the bit lines (BLs) are formed in the same metal layer, e.g., the metal layer (M6).

[0028] The word line (WL) and the interconnect line (IL) each extend in the first direction (x) and are spaced apart along the second direction (y). In certain embodiments, the word line (WL) and the interconnect line (IL) are formed in the same metal layer(s), e.g., the metal layer (M1 and / or M7).

[0029] Each via extends in a third direction (z), perpendicular to the first and second directions (x, y), and connects a corresponding bit line (BL) to the interconnect line (IL). Since the bit lines (BLs) are connected to the same interconnect line (IL), they are connected in parallel. This parallel connection reduces the overall wire resistance of the bit lines (BLs), thereby increasing the probability of successfully programming memory cell 200.

[0030] In certain embodiments, the Layout 400 also features two or more source lines (e.g., SLs from Fig. 2A), which are connected in parallel. The structure of the source lines (SLs) is similar to that described above in connection with the bit lines (BLs). Accordingly, a detailed description of the source lines (SLs) is omitted here for the sake of brevity.

[0031] In this embodiment, the bit lines (BLs), source lines (SLs), word line (WL), interconnect line (IL), and vias (VIAs) are formed from a conductive material, such as copper (Cu), aluminum (Al), other suitable metals, or their alloys, which are deposited over the memory cell 200 to establish an electrical connection.

[0032] In some embodiments, the bit line (BL) (and / or the source line SL) has substantially the same width (w) as the word line (WL). In some such embodiments, the interconnect line (IL) may have substantially the same width (w) as the word line (WL). In other embodiments, the bit line (BL) (and / or the source line SL) may have a different width than the word line (WL). For example, Fig. Figure 5 is a schematic layout diagram showing other examples of conductive lines of a memory cell (e.g., memory cell 200) according to various embodiments of the present disclosure. As in Fig. As shown in Figure 5, the bit line (BL) (and / or the source line SL) has a width (w1) that is greater than the width (w2) of the word line (WL). The design itself further reduces the total wire resistance of the bit lines (BLs) and / or the total wire resistance of the source lines (SLs).

[0033] Fig. 6A is a schematic circuit diagram showing another example storage device according to various embodiments of the present disclosure. As in Fig. As shown in Figure 6A, the example memory device 600, e.g., memory device 100, has several memory cells, e.g., memory cells 610 to 640, arranged in an array of rows and columns. The memory cells 610 to 640 in each row are connected to the respective word line (WL[0], WL[1]). Likewise, the memory cells 610 to 640 in each column are connected between the corresponding bit line (BL[0], BL[1]) and the corresponding source line (SL[0], SL[1]). Since the memory cells 610 to 640 are similar in structure and function, only memory cell 610 is described. Memory cell 610, e.g., memory cell 200, has the form of a 4T1R memory cell and includes one OTP element 650 and four selection transistors 660. For the sake of simplicity, only one of the selected transistors 660 is shown. Fig. The OTP element 650 is labeled 6A. It has a first OTP element terminal connected to two or more bit lines (BL[0]). For example, each bit line (BL[0]) is connected to a VDD node. The memory cell 610 also has an interconnect line 670 that connects the bit lines (BL[0]) in parallel. The first OTP element terminal of the OTP element 650 is connected to the interconnect line 670.

[0034] The selection transistor 660 has a gate terminal, a first source / drain terminal, and a second source / drain terminal. The gate terminals are connected to each other and to the word line (WL[0]). The first source / drain terminals of the selection transistor 660 are connected to each other and to the second OTP element terminal of the OTP element 650. For example, the memory cell 610 also has an interconnect line 680 that connects the first source / drain terminals of the selection transistors 660 to each other. The second OTP element terminal of the OTP element 650 is connected to the interconnect line 680. The second source / drain terminals of the selection transistors 660 are connected to each other and to two or more source lines (SL[0]). For example, each source line (SL[0]) is connected to a ground node (or VSS node).Memory cell 610 also has an interconnect line 690 that connects the source lines (SLs) in parallel. The second source / drain terminals of the selection transistors 660 are connected to each other and to the interconnect line 690.

[0035] The preceding description shows that the total wire resistance of the bit lines (BL[0]s) is reduced because the bit lines (BL[0]) are connected in parallel. Since the source lines (SL[0]s) are also connected in parallel, their total wire resistance is likewise reduced. This reduction in wire resistance improves current flow efficiency, thereby increasing the probability that memory cell 610 will be programmed successfully.

[0036] During a write or programming operation, the selection transistor 650 is activated by a high word line signal (WL[0] signal) (,1') on the word line (WL[0]), thereby enabling access to the memory cell 610. For example, Fig. Figure 6B shows a schematic timing diagram illustrating an example relationship between a word line signal (WL signal), a bit line signal (BL signal), and a source line signal (SL signal) according to various embodiments of the present disclosure. The memory cell 610 is then connected between the bit lines (BL[0]s) and the source lines (SL[0]s). A programming voltage (Vprog), i.e., a higher voltage, is then applied across the bit lines (BL[0]s), the memory cell 610, and the source lines (SL[0]s), causing a current to flow through them. This current can permanently modify the structure of the OTP element 650, for example, by creating a conductive path and reducing its resistance to a low (or programmed) state. This programmed state represents a logical '1' (or '0') stored in the memory cell 610.Since the bit lines (BL[0]s) are connected in parallel, the total wire resistance of the bit lines (BL[0]s) is reduced. Since the source lines (SL[0]s) are also connected in parallel, the total wire resistance of the source lines (SL[0]s) is likewise reduced. This reduction in wire resistance improves current flow efficiency, thereby increasing the probability that memory cell 610 will be programmed successfully.

[0037] During a read operation, a high word line signal (WL[0] signal) applied to the word line (WL[0]) activates the select transistor 660 and connects the memory cell 610 between the bit lines (BL[0]s) and the source lines (SL[0]s). Instead of the higher programming voltage used for programming, a much lower read voltage is applied across the bit lines (BL[0]s), the memory cell 610, and the source lines (SL[0]s). When the OTP element 610 is programmed (i.e., in a low-resistance state), current flows through it, and a sampling amplifier connected to the memory cell 610 interprets the bit stored in the memory cell 610 as a logical '1' (or '0'). Otherwise, the OTP element 650 is non-conductive, and essentially no current flows through it. In this state, the sampling amplifier interprets the bit stored in memory cell 610 as a logical '0' (or '1').

[0038] The read and write operations at the other memory cells are similar to those described above in connection with memory cell 610. For example, the next write operation at another memory cell 620-640 activates the word line (WL[1]) with a high word line signal (WL[1] signal), while the programming voltage (Vprog) is applied across the bit lines (BL[1]s) of memory cell 620-640 and the source lines (SL[1]s).

[0039] Fig. Figure 7 is a schematic layout diagram showing other examples of conductive lines of a storage device (e.g., storage device 600) according to various embodiments of the present disclosure. As in Fig. As shown in Figure 7, the example layout 700 has two or more bit lines (BL[0]), two or more bit lines (BL[1]), several word lines (e.g., WL[0] and WL[1]), several interconnect lines (e.g., IL[0] and IL[1]), two or more vias VIA[0], and two or more VIA[1]. The bit lines (BL[0], BL[1]) are arranged alternately along a first direction (x), and each extends in a second direction (y) that is perpendicular to the first direction (x).

[0040] The word lines (WL[0], WL[1]) and the interconnect lines (IL[0], IL[1]) each extend in the first direction (x) and are arranged alternately along the second direction (y). In certain embodiments, the word lines (WL[0], WL[1]) and the interconnect lines (IL[0], IL[1]) are formed in the same metal layer(s), e.g., the metal layer (M1 and / or M7).

[0041] Each via (VIA[0]) extends in a third direction (z), perpendicular to the first and second directions (x, y), and connects a corresponding bit line (BL[0]) to the interconnect line (IL[0]). Likewise, each via (VIA[1]) extends in the third direction (z) and connects a corresponding bit line (BL[1]) to the interconnect line (IL[1]). Since the bit lines (BL[0], BL[1]) are connected to the same interconnect line (IL[0], IL[1]), they are connected in parallel. This parallel connection reduces the overall wire resistance of the bit lines (BL[0], BL[1]), thereby increasing the probability of successfully programming memory cell 200.

[0042] Since the bit lines (BL[0], BL[1]) are arranged alternately along a first direction (x) and since the word lines (WL[0], WL[1]) and the interconnect lines (IL[0], IL[1]) are arranged alternately along the second direction (y), such a construction also increases the distances between vias (VIA[0], VIA[1]), thus preventing violations of via spacing requirements.

[0043] In certain embodiments, the Layout 700 also features two or more source lines (e.g. SL[0] of Fig. 6A), which are connected in parallel, and two or more source lines (e.g. SL[1]) from Fig. 6A), which are also connected in parallel. The structure of the source lines (SL[0], SL[1]) is similar to that described above in connection with the bit lines (BL[0], BL[1]). Accordingly, a detailed description of the source lines (SL[0], SL[1]) is omitted here for the sake of brevity.

[0044] Fig. Figure 8 is a schematic layout diagram showing another example of conductive lines of a storage device (e.g., storage device 600) according to various embodiments of the present disclosure. As in Fig. As shown in Figure 8, the example layout 800 has two or more bit lines BL[0], two or more bit lines BL[1], several word lines (e.g., WL[0] and WL[1]), several interconnect lines (e.g., IL[0] and IL[1]), two or more vias VIA[0], and two or more VIA[1]. The bit lines (BL[0], BL[1]) are arranged alternately along a first direction (x), and each extends in a second direction (y) that is perpendicular to the first direction (x).

[0045] The word lines (WL[0], WL[1]) and the interconnect lines (IL[0], IL[1]) each extend in the first direction (x) and are arranged alternately along the second direction (y). In certain embodiments, the word lines (WL[0], WL[1]) and the interconnect lines (IL[0], IL[1]) are formed in the same metal layer(s), e.g., the metal layer (M1 and / or M7).

[0046] Each via (VIA[0]) extends in a third direction (z), perpendicular to the first and second directions (x, y), and connects a corresponding bit line (BL[0]) to the interconnect line (IL[0]). Likewise, each via (VIA[1]) extends in the third direction (z) and connects a corresponding bit line (BL[1]) to the interconnect line (IL[1]). Since the bit lines (BL[0], BL[1]) are connected to the same interconnect line (IL[0], IL[1]), they are connected in parallel. This parallel connection reduces the overall wire resistance of the bit lines (BL[0], BL[1]), thereby increasing the probability of successfully programming memory cell 200.

[0047] Since the word lines (WL[0], WL[1]) and the interconnect lines (IL[0], IL[1]) are arranged alternately along the second direction (y), such a design also increases the spacing between the vias (VIA[0], VIA[1]). This increased spacing helps to prevent violations of via spacing requirements.

[0048] In certain embodiments, the Layout 800 also features two or more source lines (e.g. SL[0], SL[1] of Fig. 6A) which are connected in parallel. The structure of the source lines (e.g., SL[0] and SL[1]) is similar to that described above in connection with the bit lines (BL[0], BL[1]). Accordingly, a detailed description of the source lines (SL[0], SL[1]) is omitted here for the sake of brevity.

[0049] Fig. Figure 9 is a schematic layout diagram showing another example of conductive lines of a memory cell according to various embodiments of the present disclosure. As in Fig. As shown in Figure 9, the example layout 900 has two or more bit lines (BL[0] to BL[3]), several word lines (e.g., word lines WL[0] to WL[3]), several interconnect lines (e.g., IL[0] to IL[3]), and two or more vias (VIA[0] to VIA[3]). The bit lines (BL[0] to BL[3]) are arranged alternately along a first direction (x), and each extends in a second direction (y) that is perpendicular to the first direction (x).

[0050] The word lines (WL[0] to WL[3]) and the interconnect lines (IL[0] to IL[3]) each extend in the first direction (x) and are arranged alternately along the second direction (y). In certain embodiments, the word lines (WL[0] to WL[3]) and the interconnect lines (IL[0] to IL[3]) are formed in the same metal layer(s), e.g., the metal layer (M1 and / or M7).

[0051] Each via (VIA[0]) extends in a third direction (z), perpendicular to the first and second directions (x, y), and connects a corresponding bit line (BL[0]) to the interconnect line (IL[0]). Likewise, each via (VIA[1] to VIA[3]) extends in the third direction (z) and connects a corresponding bit line (BL[1] to BL[3]) to the interconnect line (IL[1]-IL[3]). Since the bit lines (BL[0] to BL[3]) are connected to the same interconnect line (IL[0] to IL[3]), they are connected in parallel. This parallel connection reduces the overall wire resistance of the bit lines (BL[0] to BL[3]), thereby increasing the probability of successful programming of the memory cell.

[0052] Since the bit lines (BL[0] to BL[3]) are arranged alternately along a first direction (x), and since the word lines (WL[0] to WL[3]) and the interconnect lines (IL[0] to IL[3]) are arranged alternately along the second direction (y), such a design also increases the spacing between vias (VIA[0], VIA[1]). This increased spacing helps to prevent violations of via spacing requirements.

[0053] In certain embodiments, the Layout 900 also features two or more source lines (e.g., SL[0] to SL[3]) connected in parallel. The structure of the source lines (SL[0] to SL[3]) is similar to that described above in connection with the bit lines (BL[0] to BL[3]). Therefore, a detailed description of the source lines (SL[0] to SL[3]) is omitted here for the sake of brevity.

[0054] Fig. Figure 10 is a schematic layout diagram showing another example of conductive lines of a memory cell according to various embodiments of the present disclosure. As in Fig. As shown in Figure 10, the example layout 1000 has two or more bit lines (BLs), several word lines (e.g., word lines WL[0] to WL[3]), several interconnect lines (e.g., interconnect lines IL[0] to IL[3]), and two or more vias. For simplicity, only one of the vias is shown in Fig. 10. The bit lines (BLs) are arranged along a first direction (x) and each extends in a second direction (y) that is perpendicular to the first direction (x).

[0055] The word lines (WL[0] to WL[3]) and the interconnect lines (IL[0] to IL[3]) each extend in the first direction (x) and are arranged alternately along the second direction (y). In certain embodiments, the word lines (WL[0] to WL[3]) and the interconnect lines (IL[0] to IL[3]) are formed in the same metal layer(s), e.g., the metal layer (M1 and / or M7).

[0056] Each via extends in a third direction (z), perpendicular to the first and second directions (x, y), and connects a corresponding bit line (BL) to the interconnect line (IL[0] to IL[3]). Since the bit lines (BLs) are connected to the same interconnect line (IL[0] - IL[3]), they are connected in parallel. This parallel connection reduces the overall wire resistance of the bit lines (BLs), thereby increasing the probability of successful memory cell programming.

[0057] Since the word lines (WL[0] to WL[3]) and the interconnect lines (IL[0] to IL[3]) are arranged alternately along the second direction (y), such a design also increases the spacing between vias along the second direction (y). This increased spacing helps prevent violations of via spacing requirements.

[0058] In certain embodiments, the Layout 1000 also features two or more source lines (e.g., SLs) connected in parallel. The structure of the source lines (SLs) is similar to that described above in connection with the bit lines (BLs). Therefore, a detailed description of the source lines (SLs) is omitted here for the sake of brevity.

[0059] Fig. Figure 11 is a schematic layout diagram showing another example of conductive lines of a storage device according to various embodiments of the present disclosure. As in Fig. As shown in Figure 11, the example layout 1100 has two or more bit lines (BLs), several word lines (e.g., word lines WL[0] to WL[3]), several interconnect lines (e.g., interconnect lines IL[0] to IL[3]), and two or more vias. For simplicity, only one of the vias is shown in Fig. 11. The bit lines (BLs) are arranged along a first direction (x) and each extends in a second direction (y) that is perpendicular to the first direction (x).

[0060] The word lines (WL[0] to WL[3]) and the interconnect lines (IL[0] to IL[3]) each extend in the first direction (x) and are arranged alternately along the second direction (y). In certain embodiments, the word lines (WL[0] to WL[3]) and the interconnect lines (IL[0] to IL[3]) are formed in the same metal layer(s), e.g., the metal layer (M1 and / or M7).

[0061] Each via extends in a third direction (z), perpendicular to the first and second directions (x, y), and connects an alternating pair of bit lines (BLs) to the interconnect line (IL[0] to IL[3]). Because the bit lines (BLs) are connected to the same interconnect line (IL[0] - IL[3]), they are connected in parallel. This parallel connection reduces the overall wire resistance of the bit lines (BLs), thereby increasing the probability of the memory cells being successfully programmed, as described above.

[0062] Since alternating bit lines are connected to the interconnect line (IL[0] - IL[3]) and since the word lines (WL[0] to WL[3]) and the interconnect lines (IL[0] to IL[3]) are arranged alternately along the second direction (y), such a design also increases the spacing between vias along the first and second directions (x, y). This increased spacing helps prevent violations of via spacing requirements.

[0063] In certain embodiments, the Layout 1100 also features two or more source lines (e.g., SLs) connected in parallel. The structure of the source lines (SLs) is similar to that described above in connection with the bit lines (BLs). Therefore, a detailed description of the source lines (SLs) is omitted here for the sake of brevity.

[0064] Fig. Figure 12 is a schematic layout diagram showing another example of conductive lines of a storage device according to various embodiments of the present disclosure. As in Fig. As shown in Figure 12, the example layout 1200 has two or more bit lines (BLs), several word lines (e.g., WL[0] to WL[3]), several interconnect lines (e.g., IL[0] to IL[3]), and two or more vias. For simplicity, only one of the vias is shown in Fig. 12 are labelled. The bit lines (BLs) are arranged along a first direction (x) and each extends in a second direction (y) that is perpendicular to the first direction (x).

[0065] The word lines (WL[0] to WL[3]) and the interconnect lines (IL[0] to IL[3]) each extend in the first direction (x) and are arranged alternately along the second direction (y). In certain embodiments, the word lines (WL[0] to WL[3]) and the interconnect lines (IL[0] to IL[3]) are formed in the same metal layer(s), e.g., the metal layer (M1 and / or M7).

[0066] Each via extends in a third direction (z), perpendicular to the first and second directions (x, y), and connects a corresponding set of bit lines (BLs) to the interconnect line (IL[0] to IL[3]). Since the bit lines (BLs) are connected to the same interconnect line (IL[0] - IL[3]), they are connected in parallel. This parallel connection reduces the overall wire resistance of the bit lines (BLs), thereby increasing the probability of successful programming of the memory cells, as described above.

[0067] Since a subset of bit lines is connected to the interconnect line (IL[0] - IL[3]) and since the word lines (WL[0] to WL[3]) and the interconnect lines (IL[0] to IL[3]) are arranged alternately along the second direction (y), such a design also increases the spacing between vias along the first and second directions (x, y). This increased spacing helps prevent violations of via spacing requirements.

[0068] In certain embodiments, the Layout 1200 also features two or more source lines (e.g., SLs) connected in parallel. The structure of the source lines (SLs) is similar to that described above in connection with the bit lines (BLs). Therefore, a detailed description of the source lines (SLs) is omitted here for the sake of brevity.

[0069] Fig. Figure 13 is a schematic circuit diagram showing another example storage device according to various embodiments of the present disclosure. As in Fig. As shown in Figure 13, the example storage device 1300 has several storage cells (e.g., storage cells 1310 to 1340), each comprising cell sections 1310a to 1310d, 1320a to 1320d, 1330a to 1330d, and 1340a to 1340d. In this embodiment, the cell sections 1310a-1310d, 1320a-1320d, 1330a-1330d, and 1340a-1340d of one storage cell 1310-1340 are separated by the cell sections 1310a-1310d, 1320a-1320d, 1330a-1330d, and 1340a-1340d of other storage cells 1310-1340. For example, cell segments 1310a-1310d, 1320a-1320d, 1330a-1330d, 1340a-1340d are arranged in an array of rows and columns. Cell segments 1310a, 1310b, 1320a, 1320b are arranged alternately along the first row and each is connected by a word line (WL[1]). Cell segments 1330a, 1330b, 1340a, 1340b are arranged alternately along the second row and each is connected by a word line (WL[0]).Cell sections 1310c, 1310d, 1320c, 1320d are arranged alternately along the third row and each is connected to the word line (WL[1]). Cell sections 1330c, 1330d, 1340c, 1340d are arranged alternately along the fourth row and each is connected to the word line (WL[0]).

[0070] Similarly, cell segments 1310a, 1310c, 1330a, 1330c are arranged alternately along the first column and are each connected between two or more bit lines (BL[1]) and two or more source lines (SL[1]). Cell segments 1320a, 1320c, 1340a, 1340c are arranged alternately along the second column and are each connected between two or more bit lines (BL[0]) and two or more source lines. Cell segments 1310b, 1310d, 1330b, 1330d are arranged alternately along the third column and are each connected between two or more bit lines (BL[1]) and two or more source lines (SL[1]). Cell sections 1320b, 1320d, 1340b, 1340d are arranged alternately along the fourth column and are each connected between two or more bit lines (BL[0]) and two or more source lines. Such an arrangement of the storage device 1330 simplifies the layout design of the conductive lines (e.g.Bit lines, source lines, and word lines) of the storage device 1330.

[0071] Fig. Figure 14 is a schematic circuit diagram showing another example storage device according to various embodiments of the present disclosure. As in Fig. As shown in Figure 14, the example storage device 1400 has several memory cells, e.g., memory cells 1410 to 1480, each of which forms several memory cells that are combined into a single memory cell. Since memory cells 1410 to 1480 are similar in structure, only one (e.g., memory cell 1410) is described. Memory cell 1410 has several memory cells 1490. For the sake of simplicity, only one of the memory cells 1490 is shown in Figure 14. Fig. 14. Each memory cell 1490 is connected to several word lines (WL) that are interconnected, and between two or more bit lines (BL[0]) that are connected in parallel, and two or more source lines (SL[0]) that are connected in parallel. Such an arrangement of the memory device 1400 simplifies the layout design of its conductive lines (e.g., bit lines, source lines, and word lines).

[0072] In some embodiments, the memory cell 1410 is connected between several bit lines (BL[0]) connected in parallel and a single source line. In other embodiments, the memory cell 1410 is connected between several source lines (SL[0]) connected in parallel and a single bit line (BL[0]).

[0073] Fig. Figure 15 is a schematic circuit diagram showing another example storage device according to various embodiments of the present disclosure. As in Fig. As shown in Figure 15, the example storage device 1500 has several memory cells, e.g., memory cells 1510 to 1580, each of which forms several memory cells that are combined into a single memory cell. Since memory cells 1510 to 1580 are similar in structure, only one (e.g., memory cell 1510) is described. Memory cell 1510 has several memory cells 1590. For the sake of simplicity, only one of the memory cells 1590 is shown in Figure 15. Fig. 15. Each memory cell 1590 is connected to the corresponding word line (WL[o]-WL[n]) and between two or more bit lines (BLs) connected in parallel and two or more source lines (SL) connected in parallel. Such an arrangement of the memory device 1500 simplifies the layout design of its conductive lines (e.g., bit lines, source lines, and word lines).

[0074] Fig. Figure 16 is a schematic circuit diagram showing another example storage device according to various embodiments of the present disclosure. As in Fig. As shown in Figure 16, the example storage device 1600 has several memory cells, e.g., memory cells 1610, 1620, each of which forms several memory cells that are combined into a single memory cell. Since memory cells 1610 and 1620 are similar in structure, only one (e.g., memory cell 1610) is described. Memory cell 1610 has several memory cells 1690. For the sake of simplicity, only one of the memory cells 1690 is shown in Figure 16. Fig. 16. Each memory cell 1690 is connected by several word lines (WLo) that are interconnected, and between two or more bit lines (BLs) that are connected in parallel, and two or more source lines (SL) that are connected in parallel. Such a configuration of the memory device 1600 simplifies the layout design of its conductive lines (e.g., bit lines, source lines, and word lines).

[0075] Fig. Figure 17 is a schematic diagram showing another example storage device according to various embodiments of the present disclosure. As in Fig. As shown in Figure 17, the example storage device 1700 has several memory cells, e.g., memory cells 1710, 1720, each of which forms several memory cells that are combined into a single memory cell. Since memory cells 1710 and 1720 are similar in structure, only one (e.g., memory cell 1710) is described. Memory cell 1710 contains several memory cells 1790. For the sake of simplicity, only one of the memory cells 1790 is shown in Figure 17. Fig. 17. Each memory cell 1790 is connected to several word lines (WL) that are interconnected, and between two or more bit lines (BL[0]) that are connected in parallel, and two or more source lines (SL[0]) that are connected in parallel. Such an arrangement of the memory device 1700 simplifies the layout design of its conductive lines (e.g., bit lines, source lines, and word lines).

[0076] In some embodiments, the memory cell 1710 is connected between several bit lines (BL[0]) connected in parallel and a single source line. In other embodiments, the memory cell 1710 is connected between several source lines (SL[0]) connected in parallel and a single bit line (BL[0]).

[0077] Fig. Figure 18 is a schematic circuit diagram showing another example storage device according to various embodiments of the present disclosure. As in Fig. As shown in Figure 18, the example storage device 1800 has several memory cells, e.g., memory cells 1810, 1820. Each memory cell 1810, 1820 is subdivided into several cell sections, e.g., cell sections 1810a, 1810b, 1820a, 1820b. Cell sections 1810a, 1810b are separated by cell section 1820a. Similarly, cell sections 1820a, 1820b are separated by cell section 1810b.

[0078] Furthermore, each memory cell 1810, 1820 forms several memory cells that are combined into a single memory cell. Since the memory cells 1810 and 1820 are similar in structure, only one (e.g., memory cell 1810) is described. Memory cell 1810 contains several memory cells 1890. For the sake of simplicity, only one of the memory cells 1890 is shown. Fig. 18. Each memory cell 1890 is connected to several word lines (WL) that are interconnected, and between two or more bit lines (BL[0]) that are connected in parallel, and two or more source lines (SL[0]) that are connected in parallel. Such an arrangement of the memory device 1800 simplifies the layout design of its conductive lines (e.g., bit lines, source lines, and word lines).

[0079] In some embodiments, the memory cell 1810, 1820 is connected between several bit lines (BL[0], BL[1]) connected in parallel and a single source line (SL[0], SL[1]). In other embodiments, the memory cell 1810 is connected between several source lines (SL[0], SL[1]) connected in parallel and a single bit line (BL[0], BL[1]). In some embodiments, the memory cell 1810 is connected between several bit lines (BL[0], BL[1]) connected in parallel and a single source line (SL[0], SL[1]). In other embodiments, the memory cell 1810 is connected between several source lines (SL[0], SL[1]) connected in parallel and a single bit line (BL[0], BL[1]).

[0080] Fig. Figure 19 is a schematic diagram showing another example storage device according to various embodiments of the present disclosure. As in Fig. As shown in Figure 19, the example storage device 1900 has several memory cells, e.g., memory cells 1910 and 1920. Each memory cell 1910 and 1920 is subdivided into several cell sections, e.g., cell sections 1910a, 1910b, 1920a, and 1920b. Cell sections 1910a and 1910b are separated by cell section 1920a. Similarly, cell sections 1920a and 1920b are separated by cell section 1910b.

[0081] Furthermore, each memory cell 1910, 1920 forms several memory cells that are combined into a single memory cell. Since the memory cells 1910, 1920 are similar in structure, only one (e.g., memory cell 1910) is described. Memory cell 1910 contains several memory cells 1990. For the sake of simplicity, only one of the memory cells 1990 is shown. Fig. 19. Each memory cell 1990 is connected to several word lines (WL0) that are interconnected, and between two or more bit lines (BLs) that are connected in parallel, and two or more source lines (SLs) that are connected in parallel. Such a configuration of the memory device 1900 simplifies the layout design of its conductive lines (e.g., bit lines, source lines, and word lines).

[0082] Fig. Figure 20 is a flowchart of an example process 2000 for manufacturing a storage device according to various embodiments of the present disclosure. For ease of understanding, the example process 2000 is now further explained with reference to Fig. 1 to 19 described. It is understood that the procedure 2000 applies to structures that differ from those of Fig. 1 to 19 are different, and can be applied. It is also understood that additional operations may be provided before, during, and after the 2000 process, and that some of the operations described below may be replaced or eliminated for an alternative embodiment of the 2000 process.

[0083] In process 2010, the fixture manufacturing tool produces a memory cell (e.g., memory cell 110, 200, 300, 610) over a substrate. For example, Fig. Figure 21 is a schematic sectional diagram showing another example storage device 2100 according to various embodiments of the present disclosure. As in Fig.As shown in Figure 21, the example storage device 2100 (e.g., storage device 100-1900) has a substrate 2110, several metal layers (M0-M7), and several vias (V0-V6). The substrate 2110 can be made of silicon, germanium, III-V semiconductors, other suitable substrate materials, and their alloys. At this stage, the device fabrication tool dopes the substrate 2110 to create source and drain regions (S, D) in active areas of the substrate 2110. The device fabrication tool then deposits a conductive material to form a metal deposition (MD) over the top surfaces of the source and drain regions (S, D) and a metal gate (MG) over the top surface of a gate region between the source and drain regions (S, D). The source and drain regions (S, D) and the metal gate (MG) form a selection transistor (e.g., the selection transistor 220, 320, 660).

[0084] Next, in process 2020, the fixture fabrication system deposits additional conductive material to form the stacked metal layers (e.g., metal layers M0-M7). For example, each metal layer (M0, M2) has at least one source line (SLs) connecting a selection transistor to a ground node (or VSS node). The metal layer (M1, M3, M5, M7) has multiple word lines (WLs), each connected to a corresponding metal gate (MG). The metal layer (M4, M6) has multiple bit lines (BLs) connecting between a VDD node and an OTP element 2120 (e.g., OTP element 260, 310, 650) of the memory cell. In this embodiment, the metal layer (M1, M3, M5, M7) further comprises an interconnect line (e.g., interconnect line 230, 330, 670) that connects the bit lines (BLs) in parallel. The via (Vo-V6) connects the metal layers (M0-M7).Examples of conductive materials include copper (Cu), aluminum (Al), other suitable metals, or their alloys.

[0085] In one embodiment, a memory device comprises multiple memory cells, a word line, multiple bit lines, and multiple source lines. Each memory cell includes a once-programmable element (OTP element) and multiple selection transistors. The word line is connected to the gate terminals of the selection transistors of a memory cell. The bit lines are connected in parallel between a first node and a first OTP element terminal of the OTP element of the memory cell. The source lines are connected in parallel and connect the second source / drain terminals of the selection transistors of the memory cell to a second node.

[0086] In another embodiment, a memory cell comprises a once-programmable element (OTP element) and several selection transistors. The OTP element has a first OTP element terminal connected to one or more bit lines. Each selection transistor has a gate terminal connected to a word line, a first source / drain terminal connected to a second OTP element terminal, and a second source / drain terminal connected to one or more source lines, with the bit lines or source lines connected in parallel.

[0087] In another embodiment, a method for fabricating a memory device comprises: fabricating a memory cell over a substrate; forming two or more bit lines connected in parallel between a first node and a first OTP element terminal (OTP: once programmable) of an OTP element of the memory cell by depositing a conductive material in a first metal layer over the memory cell; depositing a conductive material in at least one of a second metal layer below the first metal layer and a third metal layer above the first metal layer to form a word line connected to gate terminals of the selection transistors; and depositing a conductive material to form at least one source line. The at least one source line connects second source / drain terminals of the selection transistors to a second node.

[0088] The foregoing outlines features of several embodiments so that a person skilled in the art can better understand the aspects of the present disclosure. A person skilled in the art should recognize that they can readily use the present disclosure as a basis for designing or modifying other processes and structures to accomplish the same tasks and / or achieve the same advantages as the embodiments presented herein. A person skilled in the art should also understand that such equivalent embodiments do not deviate from the inventive concept and scope of the present disclosure, and that they can make various changes, substitutions, and modifications here without deviating from the inventive concept and scope of the present disclosure. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 712,715

[0001]

Claims

[1] Storage device comprising: multiple memory cells, each containing a once-programmable element (OTP element) and multiple selection transistors, a word line connected to the gate terminals of the selection transistors of one or more memory cells, several bit lines that are connected in parallel between a first node and a first OTP element terminal of the OTP element of the memory cell, and several source lines connected in parallel and connecting the second source / drain terminals of the selection transistors of the memory cell to a second node. [2] Storage device according to claim 1, wherein the parallel connection of the bit lines reduces the overall wire resistance to facilitate programming of the OTP element. [3] Storage device according to claim 1 or 2, wherein: the bit lines are arranged along a first direction and each extends in a second direction that is perpendicular to the first direction, and the word line extends in the first direction, the storage device further comprising: an interconnect line that is essentially parallel to the word line, and multiple vias that connect two or more bit lines to the interconnect line. [4] Storage device according to claim 3, wherein the two or more bit lines are adjacent to each other. [5] Storage device according to claim 3 or 4, wherein the distance between the vias is greater than the distance between the adjacent bit lines. [6] Storage device according to any one of the preceding claims, wherein: The OTP element has an antifuse that is initially in a non-conductive state and is configured to become permanently conductive when a programming voltage is applied to the memory cell via the bit lines and the source lines, and The antifuse is made of a material designed to break down when a programming voltage is applied to the memory cell via the bit lines and the sources form a conductive path. [7] Memory device according to any of the preceding claims, wherein the selection transistors are configured to provide access to the memory cell during programming and reading operations when a high or low selection signal is applied to the word line. [8] Storage device according to one of the preceding claims, further comprising a sampling amplifier connected to the bit line and configured to detect a state of the OTP element during a read operation. [9] Storage device according to any of the preceding claims, wherein the multiple storage cells comprise a first and a second storage cell, the storage device further comprising: a second word line connected to the gate terminals of the selection transistors of the first and second memory cells, several second bit lines connected in parallel, wherein the OTP element of the first memory cell and the OTP element of the second memory cell are connected between the second bit lines and first source / drain terminals of the selection transistors of the first and second memory cells, and several second source lines connected in parallel, coupling the second source / drain terminals of the selection transistors of the first and second memory cells to the ground node. [10] Memory cell, comprising: a once programmable element (OTP element) that has a first OTP element terminal connected to one or more bit lines, and multiple selection transistors, each having a gate terminal connected to a word line, a first source / drain terminal connected to a second OTP element terminal of the OTP element, and a second source / drain terminal connected to one or more source lines, with the bit lines or the source lines connected in parallel. [11] Memory cell according to claim 10, further comprising one or more dummy OTP elements, each comprising a first OTP element terminal connected to one or more bit lines and a second potential-free OTP element terminal. [12] Memory cell according to claim 10 or 11, further comprising: a first interconnect line that connects the bit lines, a second interconnect line that connects the source lines, and a third interconnect line that connects the first source / drain terminals of the selection transistors. [13] Memory cell according to claim 12, wherein: the bit lines are formed in the same metal layer, the word transmission is formed in one or more layers of metal, and the first interconnect line is formed in the same metal layer as the word line. [14] Memory cell according to claim 12 or 13, wherein: the source conductors are formed in the same metal layer, the word transmission is formed in one or more layers of metal, and the second interconnect line is formed in the same metal layer as the word line. [15] Memory cell according to one of claims 10 to 14, further comprising at least one dummy OTP element comprising a first OTP element terminal connected to one or more bit lines and a second floating OTP element terminal. [16] Method for manufacturing a storage device, the method comprising: Fabrication of a storage cell over a substrate, wherein the storage cell has: a once programmable element (OTP element), and one or more selection transistors, and Deposition of a conductive material to form multiple metal layers stacked on top of each other, wherein the multiple metal layers have: a first metal layer having at least one source line connecting the selection transistors to a first node, a second metal layer that has a word lead connected to the gate terminals of the selection transistors, and a third metal layer that has several bit lines connected in parallel between a second node and the OTP element. [17] The method of claim 16, further comprising: parallel connection of the bit lines by: Deposition of a conductive material in the same metal layer as the word conductor to form an interconnect conductor, and Forming multiple vias, each connecting a corresponding bit line to the interconnect line. [18] Method according to claim 16 or 17, further comprising: parallel connection of the source lines by: Deposition of a conductive material to form an interconnect line, and Forming multiple vias, each connecting a corresponding source line to the interconnect line. [19] Method according to any one of claims 16 to 18, further comprising forming one or more dummy OTP elements, each having a first OTP element connection connected to the bit lines and a second potential-free OTP element connection. [20] Method according to any one of claims 16 to 19, wherein the memory cell forms several memory cells, each of which is connected to the word line and between the two or more bit lines and the at least one source line.

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