SEMICONDUCTOR DEVICE

Abstract

A semiconductor device (100) comprising: a semiconductor chip (30) comprising a semiconductor substrate (29) with a cover surface, a cover surface electrode (31) applied to the cover surface of the semiconductor substrate (29), an insulating film (34) selectively covering edges of a cover surface of the cover surface electrode (31), and a plating layer (33) covering the cover surface of the cover surface electrode (31) exposed in an opening of the insulating film (34); a metal wiring plate (60) comprising a connecting part (61, 63, 65) located above the insulating film (34) and the plating layer (33), and which is provided with a groove (66) recessed upwards from a bottom surface of the connecting part (61, 63, 65); and a solder part (22-25) that fills the groove (66) to connect the plating layer (33) and the bottom surface of the connecting part (61, 63, 65), wherein in a top view a boundary between the insulating film (34) and the plating layer (33) is arranged within the groove (66), and wherein the solder part (22-25) has a greater thickness at the boundary than on the plating layer (33).

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention

[0001] The present invention relates to a semiconductor device for use as a power semiconductor module. 2. Description of the state of the art

[0002] Power semiconductor modules are known that include semiconductor chips containing main electrodes and insulating films dividing the main electrodes, and metal wiring boards connected to the semiconductor chips by soldering. For example, JP 2006-216736 A discloses a semiconductor device in which an electrode part of a semiconductor chip and a frame, which is a metal part, are connected by soldering. JP 2006-190728 A discloses a power semiconductor device in which parts corresponding to valleys of a line shaped into a waveform are connected to an electrode on a surface of a semiconductor substrate, and parts corresponding to crests of the line are located near a surface of a package.

[0003] JP 2000-349207 A discloses a semiconductor device in which a semiconductor chip is sandwiched between a connecting element connected to an electrode of the semiconductor chip via bumps and a radiation plate. JP 2012-191012 A discloses a semiconductor device in which a connecting element connected to an emitter electrode has slits at positions opposite a passivation film. JP 2011-66377 A discloses a semiconductor device including an insulating layer sandwiched between a gate electrode wire and solder, in addition to a passivation film for the gate electrode wire, to prevent a failure due to a short circuit between a gate and an emitter.

[0004] The respective semiconductor devices disclosed in these documents may cause cracks in the main electrode derived from the metal wiring board or the solder when subjected to a temperature cycle test. SUMMARY OF THE INVENTION

[0005] In view of the foregoing, the present invention provides a semiconductor device capable of preventing cracks in a main electrode to improve structural reliability.

[0006] To solve the above-described conventional problem, a semiconductor device according to one aspect includes (a) a semiconductor chip including a semiconductor substrate having a top surface, a top surface electrode deposited on the top surface of the semiconductor substrate, an insulating film selectively covering edges of a top surface of the top surface electrode, and a plating layer covering the top surface of the top surface electrode exposed in an opening of the insulating film, (b) a metal wiring board including a connecting part located above the insulating film and the plating layer and provided with a groove recessed upward from a bottom surface of the connecting part, and (c) a soldering part filling the groove to connect the plating layer and the bottom surface of the connecting part to each other.In a plan view, a boundary between the insulating film and the plating layer of the semiconductor device according to the aspect is arranged inside the groove, and the soldering part has a larger thickness at the boundary than on the plating layer.

[0007] The present invention can provide a semiconductor device capable of preventing cracks in a main electrode to improve structural reliability. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a perspective view illustrating an external appearance of a semiconductor device according to an embodiment of the present invention; Fig. 2 is a perspective view illustrating an internal structure of the semiconductor device according to the embodiment of the present invention, with a radiator, a case, and a sealing resin omitted; Fig. 3 is a plan view illustrating a stacked substrate, a semiconductor chip, and a metal wiring board of the semiconductor device according to the embodiment of the present invention; Fig. 4 is a cross-sectional view seen from direction IV-IV in Fig. 3; Fig. 5 is a perspective view illustrating the metal wiring board of the semiconductor device according to the embodiment of the present invention; Fig. 6 is a plan view illustrating an arrangement of the semiconductor chip and the metal wiring board of the semiconductor device according to the embodiment of the present invention; Fig. 7 is a cross-sectional view seen from direction VII-VII in Fig. 6; Fig. 8 is a contour view showing a plastic strain amplitude of a cover surface electrode connected to the metal wiring board without grooves; Fig. 9 is a contour view showing the plastic strain amplitude of the cover surface electrode connected to the metal wiring plate provided with grooves of 0.8 millimeters width; Fig. 10 is a contour view showing the plastic strain amplitude of the cover surface electrode connected to the metal wiring plate provided with grooves of 1.3 millimeters width; Fig. 11 is a contour view showing the plastic strain amplitude of the cover surface electrode connected to the metal wiring plate provided with grooves of 2.0 millimeters wide; and Fig. 12 is a view showing a relationship between a distance between an insulating film and a groove and a maximum value of the plastic strain amplitude of the cover surface electrode. DETAILED DESCRIPTION

[0008] An embodiment of the present invention will be described below with reference to the drawings. In the following description of the drawings, the same or similar components are denoted by the same or similar reference numerals, and overlapping explanations will not be given below. It should be understood that the drawings are schematically illustrated, and relationships between thicknesses and planar dimensions, as well as proportions of the thicknesses of the respective layers, are not drawn to scale. It should also be understood that the relationships or proportions of the dimensions may differ between the respective drawings.The embodiment described below illustrates an apparatus and a method for embodying the technical ideas of the present invention, and the technical ideas of the present invention should not be limited to the materials, shapes, structures, or arrangements of the elements as described herein.

[0009] In the following description, directional definitions such as "up" and "down" are used for illustrative purposes and are not intended to limit the technical concepts of the present invention. For example, if the direction of a target is changed by 90 degrees and then observed, the terms "up" and "down" become "left" and "right." If the observation direction of the target is changed by 180 degrees, the terms "up" and "down" are reversed. (semiconductor device)

[0010] As in Fig. As shown in Figure 1, a semiconductor device 100 according to the embodiment of the present invention includes a semiconductor chip 30 and a metal wiring board 60. The semiconductor device 100 may include a radiator 10, a stacked substrate 11, a package 20, and a sealing resin 21. The semiconductor chip 30 is an element having a function of controlling a flow of a main current through an active region including a pn junction formed in a semiconductor substrate 29 (see Fig. 7). The top surface of the radiator 10 is in direct or indirect contact with the bottom surface of the stacked substrate 11. The inner portion of the casing 20 is filled with the sealing resin 21 to seal the top surface of the stacked substrate 11, the semiconductor chip 30, the metal wiring board 60, and the like. The semiconductor device 100 according to the embodiment is a power semiconductor device (a power device) that uses the semiconductor chip 30, which serves, for example, as a power semiconductor, to convert input electric power into a predetermined electric power. The embodiment is shown below, and the semiconductor device 100 includes the single stacked substrate 11, the single semiconductor chip 30, and the single metal wiring board 60 for illustrative purposes.The semiconductor device 100 may include a plurality of stacked substrates, a plurality of semiconductor chips, and a plurality of metal wiring boards. The illustration in the drawings or the explanations below are not provided with respect to, for example, terminals, wires, and signal processing circuits used for connection to external components.

[0011] The radiator 10 radiates heat generated by the semiconductor chip 30 and the like when the main current flows to the active region to the outside via the stacked substrate 11. The radiator 10 is a substantially cuboid-shaped heat sink made of a material with high thermal conductivity, such as aluminum (Al). The radiator 10 may include a plurality of fins to increase the surface area and thus improve the radiation performance. The spaces between the respective fins may serve as flow channels of a coolant. The coolant may be either a liquid, such as an aqueous ethylene glycol solution or water, or a gas, such as air. A coolant capable of a phase transition, such as chlorofluorocarbon, may also be used.

[0012] The casing 20 has, for example, a rectangular frame-like shape and is arranged to surround the components such as the stacked substrate 11, the semiconductor chip 30, and the metal wiring board 60 on the top surface of the radiator 10 via the sealing resin 21. The casing 20 can be formed of either a conductive material such as metal or an insulating material such as resin. The sealing resin 21 used can be a resin with high insulating ability and moldability, such as epoxy resin or maleimide resin. A linear expansion coefficient and a Young's modulus of the sealing resin 21 can be adjusted depending on the amount of a filler mixed with the resin.

[0013] As in Fig. 2 to Fig. As shown in Figure 4, the stacked substrate 11 includes an insulating substrate 13, a metal plate 12 bonded to the bottom surface of the insulating substrate 13, and circuit pattern layers (14, 15, 16) bonded to the top surface of the insulating substrate 13. The stacked substrate 11 may be, for example, a DCB substrate in which copper is directly bonded to a surface of a ceramic substrate, or an AMB substrate in which metal is provided by active metal brazing on a surface of a ceramic substrate. The stacked substrate 11 is bonded and thermally connected to the top surface of the radiator 10 by a brazing part 22. The brazing part 22 may be a tin (Sn)-antimony (Sb)-based or Sn-Sb-silver (Ag)-based brazing material. The stacked substrate 11 may be arranged so that its main surface is parallel to the XY plane.

[0014] As in Fig. 2 to Fig. As shown in Figure 4, the circuit pattern layers (14, 15, 16) include a first circuit pattern layer 14, a second circuit pattern layer 15, and a plurality of third circuit pattern layers 16. The first circuit pattern layer 14 is provided with the semiconductor chip 30 mounted on its top surface, and the second circuit pattern layer 15 is provided with the metal wiring board 60 connected to its top surface. The circuit pattern layers (14, 15, 16) are electrically connected to the semiconductor element implementing the semiconductor chip 30 and communicate with the semiconductor element implementing the semiconductor chip 30 to transmit and receive electricity and electrical signals. The circuit pattern layers (14, 15, 16) may include metal wires, pads, and the like provided on the top surface of the insulating substrate 13, and may include signal processing circuits and the like.

[0015] As in Fig. As shown in Figure 7, the semiconductor chip 30 includes the semiconductor substrate 29, a top surface electrode 31-1 and the like deposited on the top surface of the semiconductor substrate 29, an insulating film 34 and the like selectively covering end portions of the top surface electrode 31-1 and the like, and a plating layer 33-1 and the like covering the top surface electrode 31-1 and the like exposed in the opening of the insulating film 34 and the like. A first main electrode formed by the top surface electrode 31-1 and the like and the plating layer 33-1 and the like is divided by the insulating film 34 and the like, which are arranged in a lattice-like pattern.

[0016] The semiconductor substrate 29 has a top surface and a bottom surface opposite the top surface. The semiconductor substrate 29 is a semiconductor die formed from a semiconductor material such as silicon (Si), silicon carbide (SiC), or gallium nitride (GaN). The semiconductor chip 30 has a thickness of approximately 50 to 450 micrometers and a rectangular shape with a length of approximately 5 to 15 millimeters on each side. The semiconductor element formed in the semiconductor substrate 29 to realize the semiconductor chip 30 includes a vertical semiconductor element, such as an insulated gate bipolar transistor (IGBT) or a power MOSFET. The semiconductor element can include, for example, a bipolar junction bipolar transistor (BJT), a field effect transistor (FET), a static induction transistor (SIT), a gate turn-off thyristor (GTO), and a static induction thyristor (SI).In addition to the semiconductor switching elements listed above, the semiconductor element may include a diode, such as a Schottky barrier diode. The semiconductor element implementing semiconductor chip 30 may also include a reverse-blocking IGBT (RB-IGBT) or a reverse-conducting IGBT (RC-IGBT), in which an IGBT and a freewheeling diode are integrated into a single chip.

[0017] The semiconductor chip 30 is illustrated here as a vertical element in which a plurality of first main electrodes are provided on the top surface of the semiconductor substrate 29 and a second main electrode is provided on the bottom surface of the semiconductor substrate 29. When the semiconductor element implementing the semiconductor chip 30 is an IGBT or a BJT, the respective first main electrodes refer to one of an emitter electrode and a collector electrode, and the second main electrode refers to the other electrode. When the semiconductor element is the IGBT, the control electrode refers to a gate electrode. When the semiconductor element is the BJT, the control electrode refers to a base electrode.In a case of an FET or a SIT, the respective first main electrodes refer to one of a source electrode and a drain electrode, the second electrode refers to the other electrode, and the control electrode refers to a gate electrode. In a case of a thyristor, such as a GTO thyristor, the respective first main electrodes refer to one of an anode electrode and a cathode electrode, the second electrode refers to the other electrode, and the control electrode refers to a gate electrode.

[0018] As in Fig. 4, the semiconductor chip 30 is connected to the top surface of the first circuit pattern layer 14 via a soldering part 23. The semiconductor chip 30 can be arranged so that its main surface is parallel to the XY plane. The second main electrode of the semiconductor chip 30 is electrically connected to the first circuit pattern layer 14, while the semiconductor chip 30 is thermally connected to the radiator 10 via the stacked substrate 11. The semiconductor chip 30 is connected to the metal wiring board 60 via a soldering part 25. The soldering part 23 has a thickness set in a range of 0.05 to 0.4 millimeters, and preferably in a range of 0.1 to 0.2 millimeters. The soldering part 25, which is located on the top surface of the respective plating layers 33-1 to 33-6 (see Fig. 3) contained in the semiconductor chip 30 has a thickness that is set in a range of 0.05 to 0.4 millimeters, preferably in a range of 0.05 to 0.3 millimeters, and more preferably in a range of 0.1 to 0.2 millimeters. The solder parts 23 and 25 used can be, for example, an Sn-Sb-based or an Sn-copper (Cu)-based solder.

[0019] As in Fig. As shown in FIG. 3, the semiconductor chip 30 is provided with the plurality of plating layers 33-1 to 33-6 implementing the first main electrodes and a plurality of electrode pads 39. A plurality of gate runners 36-1 to 36-3 are arranged between the respective patterns of the plating layers 33-1 to 33-6. The respective plating layers 33-1 to 33-6 may have a rectangular shape in a plan view. The gate runners 36-1 to 36-3 serve as wires for the control electrode for controlling the main current of the semiconductor element implementing the semiconductor chip 30. A pattern of a guard ring 35 is arranged to surround the pattern of the respective plating layers 33-1 to 33-6. Fig. Fig. 4 omits the illustration of the respective plating layers 33-1 to 33-6, the guard ring 35, the respective gate sliders 36-1 to 36-3, and the respective electrode pads 39 for the sake of brevity. As used herein, the term "in a plan view" refers to a state as viewed in the direction perpendicular to the top surface of the semiconductor substrate 29 (see Fig. 7) (in the positive direction of the Z-axis).

[0020] As in Fig. 3, the two gate runners 36-1 and 36-2 extend in the direction parallel to each other (in the Y-axis direction) on the top surface of the semiconductor chip 30. The other gate runner 36-3 extends in the direction perpendicular to the gate runners 36-1 and 36-2 (in the X-axis direction). The six cladding layers 33-1 to 33-6 are arranged in a 2 × 3 matrix shape so as to be separated from each other by the three gate runners 36-1 to 36-3. The guard ring 35 is arranged along the four sides of the semiconductor chip 30 to surround the cladding layers 33-1 to 33-6. The electrode pads 39 are arranged so as to be separated from each other within the guard ring 35 in the planar pattern.

[0021] As in Fig. 2 to Fig. 4, the metal wiring board 60 is a lead frame including, for example, Cu, a Cu alloy, Al, or an Al alloy. The metal wiring board 60 has, for example, a thickness of about 0.5 to 1.5 millimeters. The metal wiring board 60 includes a first connecting part 61, a first upright part 62 connected to the first connecting part 61, and a connecting part 63 connected to the first upright part 62 to have a first crank shape. The bottom surface of the first connecting part 61 is connected to the top surface of the semiconductor chip 30 via the soldering part 25. The metal wiring board 60 further includes the connecting part 63, a second upright part 64 connected to the connecting part 63, and a second connecting part 65 connected to the second upright part 64 to have a second crank shape.The bottom surface of the second connecting part 65 is connected to the top surface of the second circuit pattern layer 15 via a solder part 24. The first connecting part 61 opposite the respective top surfaces of the plating layers 33-1 to 33-6 includes a surface that is substantially parallel to the top surface of the semiconductor chip 30. The bottom surface of the second connecting part 65 is substantially parallel to the top surface of the second circuit pattern layer 15. The solder part 24 used can be, for example, an Sn-Cu-based or Sn-Sb-based solder.

[0022] The first upright part 62 extends at an end portion of the first connecting part 61 toward the connecting part 63 in the upward direction, for example, a perpendicular direction, from the planar surface that is the top surface of the semiconductor chip 30 to form a substantially L-shape together with the first connecting part 61. The second upright part 64 extends at an end portion of the second connecting part 65 toward the connecting part 63 in the upward direction, for example, a perpendicular direction, from the planar surface that is the top surface of the second circuit pattern layer 15 to form a substantially L-shape together with the second connecting part 65.According to the embodiment, the first upright part 62 and the second upright part 64 extend in the vertical direction (Z-axis direction) perpendicular to the top surface of the semiconductor chip 30 and the top surface of the second circuit pattern layer 15. The metal wiring board 60 is processed by bending it by 90 degrees at appropriate locations with a press, for example, to have the first connecting part 61, the first upright part 62, the connecting part 63, the second upright part 64, and the second connecting part 65.

[0023] The angle between the first connecting part 61 and the first upright part 62 and the angle between the second upright part 64 and the second connecting part 65 can be set in a range of 45 degrees or more to 135 degrees or less, preferably set in a range of 80 degrees or more to 100 degrees or less, and can be set substantially to 90 degrees. The main surface of the connecting part 63 can be substantially parallel to the main surface of each of the first connecting part 61 and the second connecting part 65. The main surface of each of the first connecting part 61, the connecting part 63, and the second connecting part 65 can be slightly inclined to the main surface of each of the semiconductor chip 30, the first circuit pattern layer 14, and the second circuit pattern layer 15.

[0024] The first main electrodes of the semiconductor chip 30 are electrically connected to the second circuit pattern layer 15 via the metal wiring board 60. Specifically, the first connection part 61 is connected to the first main electrodes of the semiconductor chip 30, and the second connection part 65 is connected to the second circuit pattern layer 15.

[0025] As in Fig. 5, the first connecting part 61 has three grooves 66-1 to 66-3 on the connecting surface (the bottom surface) connected to the first main electrodes of the semiconductor chip 30. The three grooves 66-1 to 66-3 are arranged to correspond respectively to the three gate sliders 36-1 to 36-3 shown in Fig. 3. As shown in Fig. 6, the patterns of the grooves 66-1 to 66-3 are arranged to enclose the patterns of the gate sliders 36-1 to 36-3 in plan view. Namely, the gate sliders 36-1 to 36-3 are located in the center of the corresponding grooves 66-1 to 66-3 to be placed in the corresponding grooves 66-1 to 66-3. As shown in Fig. As shown in Figure 5, the grooves 66-1 to 66-3 are recessed from the connecting surface of the first connecting part 61 toward the rear surface on the opposite side of the connecting surface. Therefore, the first connecting part 61 has a thinner thickness at the grooves 66-1 to 66-3 than at the other areas.

[0026] As in Fig. As shown in Figure 6, the two grooves 66-1 and 66-2 extend in the direction parallel to each other (Y-axis direction) on the connecting surface of the first connecting part 61. The other groove 66-3 extends in the direction perpendicular to the grooves 66-1 and 66-2 (X-axis direction). Therefore, the connecting surface of the first connecting part 61 is provided with flat land parts 67-1 to 67-6, which separately protrude into a mesa state to be arranged in a 2 × 3 matrix shape, as shown in Figure 6. Fig. 5. The six regions on the connecting surface of the first connecting part 61 defined by the grooves 66-1 to 66-3 correspond to the six flat land parts 67-1 to 67-6 with the flat top surfaces. Therefore, the first connecting part 61 has a greater thickness at the flat land parts 67-1 to 67-6 than at the other regions.

[0027] As in Fig. 6, the width D of the grooves 66-1 to 66-3 is greater than the width d of the gate sliders 36-1 to 36-3. For example, as shown in Fig. 7, the side surfaces of the groove 66-1 are inclined such that the width D decreases toward the rear surface of the first connecting part 61, and they are connected to the surface of the ceiling of the groove 66-1, which is parallel to the rear surface of the first connecting part 61. Similarly, the side surfaces of the respective grooves 66-2 and 66-3 (not shown) are inclined such that the width D decreases toward the rear surface of the first connecting part 61, and they are connected to the surface of the ceiling of the respective grooves 66-2 and 66-3, which is parallel to the rear surface of the first connecting part 61. As shown in Fig. 6, the flat land parts 67-1 to 67-6 are arranged to correspond to the center of the plating layers 33-1 to 33-6 so as to be enclosed within the plating layers 33-1 to 33-6 in the planar pattern.

[0028] As in Fig. As shown in Figure 7, the semiconductor chip 30 has a region corresponding to one of the first main electrodes, including the top surface electrode 31-1 on the top surface and the plating layer 33-1 further deposited on the top surface of the top surface electrode 31-1. The semiconductor chip 30 also has a region corresponding to another of the first main electrodes, including the top surface electrode 31-2 on the top surface and the plating layer 33-2 further deposited on the top surface of the top surface electrode 31-2. The top surface electrodes 31-1 and 31-2 are formed of metal or an alloy such as Al or Al-Si. The plating layers 33-1 and 33-2 are formed of, for example, metal or an alloy including nickel (Ni). Fig. 7, only the first two main electrodes are shown, which correspond to the plating layer 33-1 and the plating layer 33-2. The other four in Fig. 6 also have the same configuration as in the plating layers 33-3 to 33-6 shown in Fig. 7 to define the other first main electrodes, including the top surface electrodes. The top surface electrodes will be collectively referred to as "top surface electrodes 31" hereinafter, where appropriate. The semiconductor chip 30 further includes a bottom surface electrode 28 provided on the bottom surface of the semiconductor substrate 29.

[0029] The gate slider 36-1 element in the semiconductor device according to the embodiment is manufactured to have a structure including a wiring layer 32 deposited on the top surface of the semiconductor chip 30 and the insulating film 34 covering the wiring layer 32. The wiring layer 32 is formed of a conductive material such as metal or polysilicon. The wiring layer 32 is a wire pattern that electrically connects, for example, the control electrode of the semiconductor element implementing the semiconductor chip 30 and the electrode pads 39. The insulating film 34 insulates the wiring layer 32 from the plating layers 33-1 to 33-6, the top surface electrodes 31-1 and 31-2, and the solder part 25. Although in Fig. 7, the other gate runners 36-2 and 36-3 are also fabricated to include the wiring layers arranged on the top surface of the semiconductor chip 30 and the insulating film covering the respective wiring layers. The insulating film implementing the surface of the respective gate runners 36-1 to 36-3 and the guard ring 35 may be formed of, for example, a continuous insulating film made of polyimide. The electrode pads 39 may be used for an electrode for temperature detection. The gate runners 36-1 to 36-3 may be arranged in a lattice state in plan view.

[0030] As in Fig. As shown in Figure 7, the insulating film 34 selectively covers the end portions on the top surface of the respective top surface electrodes 31-1 and 31-2. The plating layers 33-1 and 33-2 cover the top surfaces of the top surface electrodes 31-1 and 31-2, which are exposed in the openings (windows) of the insulating film 34 to be in contact with the insulating film 34. Three types of material are thus coexisting along regions on the top surface of the respective top surface electrodes 31-1 and 31-2 to serve as boundaries. A pair of right-side boundaries A R and a left-hand boundary A L is present on the top surface of the respective top surface electrodes 31-1 and 31-2. At the right-hand boundary A RThree types of material with different properties contained in the top surface of the top surface electrode 31-1, the edge of the plating layer 33-1, and the edge of the insulating film 34 are present together in a line. At the left-side boundary A L Three types of material with different properties are present in the top surface of the top surface electrode 31-2, the edge of the plating layer 33-2, and the edge of the insulating film 34 together in a line. The right-side boundary A R and the left-hand boundary A L are each defined by a point in the cross section of Fig. 7, but are actually defined by the lines extending in the direction perpendicular to the sheet of the cross-sectional view of Fig. 7. The outline of the right-hand boundary A R and the left-hand boundary A Lextending in the direction perpendicular to the sheet of the cross-sectional view are indicated by the dashed lines in the planar patterns of Fig. 8 to Fig. 11. The limits A R and A L can each have a width, can vary in line width in the direction of extension, or can twist in the direction of extension.

[0031] In the area around the right-hand border of the A R a gap tends to be caused on the top surface electrode 31-1 between the edge of the insulating film 34 and the plating layer 33-1, and the soldering part 25 may enter the gap at the right-side boundary A R to be brought into contact with the exposed part on the top surface of the top surface electrode 31-1. Similarly, in the area around the left-side boundary A Ltends to cause a gap between the edge of the insulating film 34 and the edge of the plating layer 33-2, and the soldering part 25 may enter the gap at the left-side boundary A L to be brought into contact with the exposed part on the top surface of the top surface electrode 31-2. As described above, the stacked substrate 11, the semiconductor chip 30, and the metal wiring board 60 are sealed by the sealing resin 21. When the semiconductor chip 30 is subjected to a temperature cycle test, the first upright part 62, which is in Fig. 2 to Fig. 6, the solder portion 25, the plating layers 33-1 and 33-2, and the top surface electrodes 31-1 and 31-2 due to expansion or contraction due to a temperature change. At the same time, the top surface electrodes 31-1 and 31-2 increase a plastic strain amplitude at the boundaries A. R and A Lcompared to the other regions, which may lead to cracks in the top surface electrodes 31-1 and 31-2. The plastic strain amplitude tends to increase, particularly in the gate slider 36-2 toward the first upright portion 62. The cracks caused in the top surface electrodes 31-1 and 31-2 may further lead to cracks in the semiconductor chip 30.

[0032] According to the semiconductor device 100 of the embodiment as shown in Fig. 7, the boundaries between the insulating film 34 and the respective plating layers 33-1 and 33-2, which correspond to the paired boundaries A R and A L correspond, within the groove 66-1. As shown in Fig. 6, the limits A R and A L between the insulating film 34 (see Fig. 7) and the respective plating layers 33-1 and 33-2 (see Fig. 7) enclosed in the gate runner 36-1 substantially correspond to the positions of the edges of the gate runner 36-1, and they are located in plan view within the groove 66-1. As shown in Fig. 7, since the soldering part 25 is provided for filling the groove 66-1, the thickness T1 of the soldering part 25 immediately above the insulating film 34 in the area between the right-hand boundary A R and the left-hand boundary A Lgreater than the thickness T2 of the solder part 25 immediately above the respective plating layers 33-1 and 33-2. A stress exerted on the top surface electrodes 31-1 and 31-2 caused by a force received by the metal wiring board 60 is therefore canceled by the solder part 25 within the groove 66-1, so that the plastic strain amplitude is reduced and the reliability of the semiconductor device 100 is accordingly improved. The same effects are also applied to the other four plating layers 33-3 to 33-6 that are not in Fig. 7. The depth D1 of the groove 66-1 from the main surfaces of the flat land parts 67-1 and 67-2 in the Z-axis direction is set in a range of 0.2 to 0.8 millimeters, and preferably in a range of 0.4 to 0.6 millimeters.

[0033] Fig. 8 to Fig. 11 are contour views showing simulation results of a maximum plastic shear strain amplitude (here also simply referred to as plastic strain amplitude) in the top surface electrodes 31 in the semiconductor device according to the embodiment while only changing the width D of the respective grooves 66-1 to 66-3. The simulation was performed using finite element analysis software ADINA (registered trademark; product name). Fig. 8 to Fig. 11 each show the plastic strain amplitude in a range from 0% to 1.8% in eleven-tone gradations, with the deeper color indicating a larger plastic strain amplitude. The dashed lines shown in the drawings indicate the edges of the gate sliders 36-1 to 36-3, which correspond to the positions of the respective paired boundaries A. R and A L are equivalent to. Fig. 8 to Fig. 11 omit the illustration of the cover surface electrodes 31, which are present in the areas within the rectangles surrounded by the dashed lines on the two or three sides.

[0034] In the simulation, the cover surface electrodes 31, made of Al-Si and having a thickness of 5 micrometers, and the plating layers 33-1 to 33-6, made of Ni and having a thickness of 4.5 micrometers, were used. Furthermore, the solder part 25, made of Sn-0.7 Cu and having a thickness of 100 micrometers, was used to have a low 0.2% yield strength. The metal wiring plate 60, made of Cu (specifically, C1020-1 / 2H; linear expansion coefficient: 16.7 × 10 -6 / °C) and a thickness of 1.0 millimeter, and grooves 66-1 to 66-3 with a depth D1 of 0.5 millimeters were used. The width d of the insulating film 34 was set to 260 micrometers. The plastic strain amplitude was calculated under the conditions described above as a strain difference when the semiconductor chip 30 was heated for one second to raise the temperature from 40°C to 175°C and then cooled to 40°C for nine seconds.

[0035] Fig. Figure 8 shows the simulation result of the plastic strain amplitude in the cover surface electrodes 31 when the width D of the grooves 66-1 to 66-3 is zero, that is, the connecting surface (the bottom surface) of the first connecting part 61 is not provided with the grooves 66-1 to 66-3. The simulation revealed that the plastic strain amplitude in the cover surface electrodes 31 along the outline of the connecting surface of the first connecting part 61, shown in the center of Fig. 8 having a rectangular shape (a semi-cylindrical shape) rounded at the two corners on the upper side. The plastic strain amplitude was relatively increased between the first upright part 62 and a region across the gate slider 36-2 in the plan view. The plastic strain amplitude was particularly increased in the region between the gate slider 36-2, which is indicated by the circle with a dashed line on the lower right side in the outline of the semi-cylindrical shape in Fig. 8, and the maximum value was approximately 1.55%. The plastic strain amplitude, which continuously changes between the gate slider 36-2 and the first upright portion 62, had the second peak value toward the first upright portion 62, and the value was approximately 1.29%.

[0036] Fig. Figure 9 shows the simulation result of the plastic strain amplitude in the cover surface electrodes 31 when the width D of the grooves 66-1 to 66-3 is set to 0.8 millimeters. The plastic strain amplitude in the cover surface electrodes 31 was increased along the contour of the connecting surface of the first connecting part 61, as shown in the Fig. 8. The plastic strain amplitude was most increased in the area defined by the circle with dashed line on the lower right side in the outline of the semi-cylindrical shape in Fig. 9, and the maximum value was approximately 1.74%. The plastic strain amplitude in this case, which also changes continuously between the gate slider 36-2 and the first upright part 62, had the second peak value toward the first upright part 62, and the value was approximately 1.23%.

[0037] Fig. Figure 10 shows the simulation result of the plastic strain amplitude in the cover surface electrodes 31 when the width D of the grooves 66-1 to 66-3 is set to 1.3 millimeters. The plastic strain amplitude in the cover surface electrodes 31 was increased along the contour of the connecting surface of the first connecting part 61, as shown in the figures shown in Fig. 8 and Fig. 9 cases. The plastic strain amplitude was most increased in the area defined by the circle with dashed line on the lower right side in the outline of the semi-cylindrical shape in Fig. 10, and the maximum value was approximately 1.54%. The plastic strain amplitude in this case, which also changes continuously between the gate slider 36-2 and the first upright part 62, had the second peak value toward the first upright part 62, and the value was approximately 1.16%.

[0038] Fig. Figure 11 shows the simulation result of the plastic strain amplitude in the cover surface electrodes 31 when the width D of the grooves 66-1 to 66-3 is set to 2.0 millimeters. The plastic strain amplitude in the cover surface electrodes 31 was increased along the contour of the connecting surface of the first connecting part 61, as shown in the figures in Fig. 8, Fig. 9 and Fig. 10 cases shown. The plastic strain amplitude was most increased in the area defined by the circle with dashed line on the lower right side in the outline of the semi-cylindrical shape in Fig. 11, and the maximum value was approximately 1.29%. The plastic strain amplitude in this case, which also changes continuously between the gate slider 36-2 and the first upright part 62, had the second peak value toward the first upright part 62, and the value was approximately 1.07%.

[0039] Fig. 12 is a graph showing the plastic strain amplitude in the respective cases described in Fig. 8 to Fig. 11. The abscissa axis indicates a distance between the respective edges of the insulating film 34 in the width direction and the respective edges of the corresponding grooves 66-1 to 66-3 in the width direction, and the ordinate axis indicates the plastic strain amplitude. The mark "circle" in Fig. 12 refers to the amplitude at the maximum (the first peak) in the area across the gate slider 36-2, and the mark “square” refers to the amplitude at the second peak in the direction of the first upright part 62. The data of the distance (on the abscissa axis) in the area shown in Fig. The case shown in Figure 8 without grooves 66-1 to 66-3 is plotted at zero (mm). The plastic strain amplitude has the maximum value in the region across the gate slider 36-2, particularly in the region including the boundaries between the insulating film 34 and the respective plating layers 33-2 and 33-3.

[0040] It was found that the maximum value of the plastic strain amplitude in the top surface electrodes 31 decreases as the width D of the groove 66-1 to 66-3 is increased and as the distance between the insulating film 34 and the respective grooves 66-1 to 66-3 is increased. It was also found that the plastic strain amplitude toward the first upright part 62 decreases as the width D of the grooves 66-1 to 66-3 provided in the first connecting part 61 is increased.

[0041] In the cross-sectional view of Fig. 7, the respective edges of the insulating film 34 in the width direction, which are the edges along the extending direction of the insulating film 34, substantially correspond to the positions of the paired boundaries A R and A L . The positions of the respective edges of the insulating film 34 can also be indicated below by the reference symbols A R and A L The respective edges of the grooves 66-1 to 66-3 are the edges along the extending direction of the grooves 66-1 to 66-3, which correspond to the edges B R and B L in the Fig. 7 shown structure of the groove 66-1. The term “distance” on the abscissa axis in Fig. 12 refers to a distance C R in the direction parallel to the main surface of the semiconductor chip 30 between the edge on the right side of the insulating film 34 and the edge B R on the right side of the groove 66-1, defined in the Fig. 7 shown structure of the groove 66-1. The term “distance” also refers to a distance C L between the edge on the left side of the insulating film 34 and the edge B L on the left side of the groove 66-1 in the direction parallel to the main surface of the semiconductor chip 30. Hereinafter, the edges of the grooves 66-1 to 66-3 are collectively referred to as the “edges B”. The distance on the abscissa axis in Fig. 12 refers to the shortest distance C = C R or C L between the edge of the insulating film 34 and the edge B of the corresponding grooves 66-1 to 66-3 in the Fig. 6 planar patterns shown.

[0042] The Fig. 12, which corresponds to the point “al” shown in Fig. 9, gives the distance C = C R or C L (0.27 millimeters; see Fig. 7) and the maximum value of the plastic strain amplitude of the cover surface electrodes 31 when the metal wiring plate 60 includes the grooves 66-1 to 66-3 with a width of 0.8 millimeters. The point "a2" in Fig. 12, which corresponds to Fig. 10, indicates the distance C (0.52 millimeters) and the maximum value of the plastic strain amplitude of the cover surface electrodes 31 when the metal wiring plate 60 includes the grooves 66-1 to 66-3 with a width of 1.3 millimeters. The point "a3" in Fig. 12, which corresponds to Fig. 11, indicates the distance C (0.87 millimeters) and the maximum value of the plastic strain amplitude of the cover surface electrodes 31 when the metal wiring plate 60 includes the grooves 66-1 to 66-3 with a width of 2.0 millimeters. The line "e" in Fig. 12, which in Fig. 8, indicates the maximum value of the plastic strain amplitude of the cover surface electrodes 31 when the metal wiring plate 60 does not include the grooves 66-1 to 66-3.

[0043] The plastic strain amplitude Δεp typically follows the Manson-Coffin law according to the following formula (1): ΔεP×Nfb=c where N f is a fatigue life, and b and c are material-derived constants. According to formula (1), the plastic strain amplitude must be reduced to extend the fatigue life.

[0044] As in Fig. As shown in Figure 12, it is assumed that the maximum value of the plastic strain amplitude increases when the distance C is about 0.5 millimeters or less, compared to the case where the metal wiring plate 60 does not include the grooves 66-1 to 66-3. This is assumed to be based on the mechanism described below. It can be seen, as shown in Fig. 8 to Fig. 11 shows that the plastic strain amplitude is increased in the area along the contour of the connecting surface of the first connecting part 61. Since the edges B L and B R the respective grooves 66-1 to 66-3, if provided, may also be part of the outline of the connecting surface of the first connecting part 61, the plastic strain amplitude immediately below the edges B L and B R increased. The plastic strain amplitude at the boundaries A L and A R is therefore increased when the distance between the boundary AL and edge B L and the distance between the boundary A R and edge B R are small, compared to the case where no grooves 66-1 to 66-3 are provided. It is believed that this is the mechanism by which Fig. 12, the plastic strain amplitude at the point a1 is larger than at the point where the distance C is zero (mm). It is also known that the plastic strain amplitude changes inversely proportional to the thickness of the soldering part 25. By providing the metal wiring plate 60 such that the distance C is set to 0.5 millimeters or larger, the thickness of the soldering part 25 at the position around the paired boundaries A L and A R be sufficiently ensured. This also leads to a lesser influence of the edges B L and B Rdue to the sufficiently ensured distance C. The plastic strain amplitude in the cover surface electrodes 31 can therefore be reduced accordingly. The upper limit of the distance C can be set to a value sufficient to ensure a suitable area of ​​the respective flat land parts 67-1 and 67-2, which is necessary for connection with the plating layers 33-1 to 33-6.

[0045] The Fig. 12 may vary depending on the composition of the solder part 25. However, as described above, the plastic strain amplitude of the cover surface electrodes 31 changes inversely proportional to the thickness of the solder part 25. The thickness of the solder part 25 may be the distance C between the respective edges of the insulating film 34 and the respective edges B of the corresponding grooves 66-1 to 66-3. It is assumed that the characteristics of the plastic strain amplitude with respect to the distance shown in Fig. 12, be substantially displaced in the vertical direction, regardless of whether the composition of the solder part 25 is changed. Therefore, it is believed that providing the grooves 66-1 to 66-3 such that the distance C between the respective edges B and the insulating film 34 is set to 0.5 millimeters or greater results in reducing the plastic strain amplitude of the top surface electrodes 31.

[0046] The semiconductor device according to the embodiment of the present invention defines the extending positions of the pair of boundaries A R and A L so that they are enclosed within the areas of the grooves 66-1 to 66-3 in the planar pattern, as seen from the top surface of the top surface electrodes 31. As described above, the boundaries A R and A L each a triple boundary at which the respective edges of the insulating film 34 and the respective edges of the corresponding plating layers 33-1 to 33-6 are present together on the top surface of the top surface electrodes 31. The thickness T1 of the solder part 25 immediately above the area formed between the pair of boundaries A R and A L is greater than the thickness T2 of the soldering part 25 immediately above the middle portion of the respective plating layers 33-1 to 33-6, as shown in Fig.7. Thus, a stress applied to the top surface electrodes 31-1 and 31-2 caused by a force received by the metal wiring plate 60 is absorbed by the solder portion 25 within the groove 66-1. This allows the plastic strain amplitude of the top surface electrode 31-1 to be reduced, thus correspondingly extending the lifetime of the semiconductor device.

[0047] Furthermore, three types of material with different properties are also present together in a line on the guard ring 35 at the boundaries between the respective edges of the insulating film and the respective edges of the corresponding plating layers 33-1 to 33-6 on the top surfaces of the top surface electrodes 31. When the first connecting part 61 is located at the boundaries between the respective edges of the insulating film and the respective edges of the plating layers 33-1 to 33-6 on the guard ring 35, the bottom surface of the first connecting part 61 may be provided with grooves to ensure a sufficient thickness of the soldering part 25 along the boundaries. (Other embodiments)

[0048] While the present invention has been illustrated by reference to the above embodiment, it should be understood that the present invention is not intended to be limited to the descriptions and drawings that form a part of this disclosure. It will be apparent to those skilled in the art that the present invention encompasses various alternative embodiments, examples, and technical applications in accordance with the above disclosure.

[0049] For example, in addition to the grooves 66-1 to 66-3 corresponding to the gate sliders 36-1 to 36-3, other grooves may be provided. It is only necessary that the grooves 66-1 to 66-3 be provided to respectively correspond to at least the extending positions of the pair of boundaries A. R and A L and the dimensions and arrangement positions may vary depending on the planar pattern of the pair of boundaries A R and A Lbe determined appropriately. LIST OF REFERENCE SYMBOLS 10 RADIATOR 11 Stacked substrate 13 INSULATING SUBSTRATE 14 FIRST CIRCUIT PATTERN LAYER 15 SECOND CIRCUIT PATTERN LAYER 16 THIRD CIRCUIT PATTERN LAYER 20 HOUSINGS 21 SEALING RESIN 22 to 25 SOLDERING PARTS 28 GROUND SURFACE ELECTRODE 29 SEMICONDUCTOR SUBSTRATE 30 semiconductor chips 31, 31-1, 31-2 COVER SURFACE ELECTRODE 32 WIRING LAYER 33-1 to 33-6 PLATING LAYER 34 INSULATION FILM 35 PROTECTIVE RING 36-1 to 36-3 GATE RUNNERS 39 ELECTRODE PAD 60 METAL WIRING PLATE 61 FIRST CONNECTING PART 62 FIRST UPRIGHT PART 63 CONNECTING PART 64 SECOND UPRIGHT PART 65 SECOND CONNECTING PART 66-1 to 66-3 NUT 67-1 to 67-6 FLATLAND PART 100 SEMICONDUCTOR DEVICES

Claims

[1] A semiconductor device (100) comprising: a semiconductor chip (30) comprising a semiconductor substrate (29) having a cover surface, a cover surface electrode (31) deposited on the cover surface of the semiconductor substrate (29), an insulating film (34) selectively covering edges of a cover surface of the cover surface electrode (31), and a plating layer (33) covering the cover surface of the cover surface electrode (31) exposed in an opening of the insulating film (34); a metal wiring board (60) including a connecting part (61, 63, 65) located above the insulating film (34) and the plating layer (33), and provided with a groove (66) recessed upward from a bottom surface of the connecting part (61, 63, 65); and a soldering part (22-25) filling the groove (66) to connect the plating layer (33) and the bottom surface of the connecting part (61, 63, 65) to each other, wherein in a plan view a boundary between the insulating film (34) and the plating layer (33) is arranged within the groove (66), and wherein the solder part (22-25) has a greater thickness at the boundary than on the plating layer (33). [2] The semiconductor device (100) according to claim 1, wherein the metal wiring plate (60) is arranged so that a distance between an edge of the groove (66) and the insulating film (34) is set to 0.5 millimeters or larger. [3] The semiconductor device (100) according to claim 1 or 2, further comprising a wiring layer (32) deposited on a top surface of the semiconductor chip (30) separately from the top surface electrode (31), wherein the insulating film (34) covers the wiring layer (32), and wherein the groove (66) is provided so as to enclose a position of the wiring layer (32) in plan view. [4] The semiconductor device (100) according to claim 3, wherein the wiring layer (32) is used for a control electrode for controlling a main current of a semiconductor element implementing the semiconductor chip (30). [5] The semiconductor device (100) according to any one of claims 1 to 4, further comprising: an insulating substrate (13) on which the semiconductor chip (30) is mounted; and a sealing resin (21) provided to seal at least the semiconductor chip (30), the metal wiring board (60), the soldering part (22-25) and the insulating substrate (13).

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