SEMICONDUCTOR DEVICE

Abstract

Semiconductor device comprising: at least one semiconductor element (40) comprising a first main electrode (41C) arranged on a surface side and a second main electrode (41E) arranged on a back surface side which is opposite in a thickness direction to the one surface side; a substrate (50) arranged to accommodate the semiconductor element, and comprising a first substrate (50C) arranged on one surface side and electrically connected to the first main electrode, and a second substrate (50E) arranged on the back surface side and electrically connected to the second main electrode; a main terminal (71) comprising at least one first main terminal (71C) electrically connected to the first main electrode via the first substrate, and at least one second main terminal (71E) electrically connected to the second main electrode via the second substrate; and a bonding element (80), wherein the bonding element is arranged between the first main electrode and the first substrate, as well as between the second main electrode and the second substrate; at least one connection from the first main connection and the second main connection in which the main connection contains several connections; the first main terminal and the second main terminal are arranged alternately and a side surface of the first main terminal and a side surface of the second main terminal are facing each other in a direction orthogonal to the thickness direction of the semiconductor element; the first main connection is directly connected to the second substrate without the bonding element, and the second main connection is directly connected to the second substrate without the bonding element, characterized by the fact that the substrate includes an opposing section (51C, 51E) in which the first substrate and the second substrate face each other in the thickness direction, and a non-opposing section (52E) which is connected to the opposing section of the second substrate and does not face the first substrate; the first main connection is directly connected to a surface (500C) of the first substrate on the side of the second substrate without the bonding element; and the second main connection is directly connected to a surface (500E) of the non-opposite section of the second substrate on the side of the first substrate without the bonding element.

Description

Technical field

[0001] The present invention relates to a semiconductor device. State of the art

[0002] JP 2015-82614A discloses a semiconductor device. The semiconductor device comprises a semiconductor element having a first main electrode and a second main electrode, a heat sink arranged such that the semiconductor element is received or arranged between it, and a main terminal.

[0003] The heat sink comprises a first heat sink, which is electrically connected to the first main electrode, and a second heat sink, which is electrically connected to the second main electrode. The main terminal comprises a first main terminal, which is electrically connected to the first heat sink, and a second main terminal, which is electrically connected to the second heat sink.

[0004] The semiconductor device described in JP 2015-82614A has a first main terminal and a second main terminal as main terminals. It is necessary to further reduce the inductance.

[0005] The main connection is linked to the heat sink, for example, via a bonding element or connecting element. There is also a need to improve the reliability of the main connections.

[0006] WO 2019 / 021 731 A1 (forming the preamble) discloses a semiconductor module in which several switching elements are connected in parallel. First current paths are formed between a first main terminal and each first main electrode, and second current paths are formed between a second main terminal and each second main electrode. If the self-inductance of any current path that is the second current path in any switching element is denoted by Lsn, the mutual inductance between the arbitrary current path and any other current path besides the arbitrary current path is denoted by Mn, and the sum of Lsn and Mn is denoted by Ln, then the switching elements and the current paths are arranged such that Ln is the same for all switching elements.

[0007] WO 2020 / 021 843 A1 discloses a semiconductor device comprising: at least one semiconductor element having a first main electrode and a second main electrode between which a main current flows; and a main terminal having a first main terminal connected to the first main electrode and a second main terminal connected to the second main electrode, wherein at least one of the first main terminals and the second main terminal is present multiple times, and the first main terminal and the second main terminal are arranged side by side such that their side faces are directed towards each other in a direction perpendicular to the thickness direction of the semiconductor element. A main terminal group is formed with three or more main terminals arranged continuously in one direction.At least part of each of the main terminals that form the main terminal group is arranged in one direction in a region between extension lines radiating from both end surfaces of the semiconductor element. Summary of the invention

[0008] It is an object of the present invention to provide a semiconductor device in which the connection reliability of main terminals is improved and the inductance is reduced. This object is achieved by a semiconductor device with the features of claim 1. The dependent claims are directed to advantageous embodiments of the invention.

[0009] According to one aspect of the present invention, the semiconductor device comprises: at least one semiconductor element having a first main electrode arranged on one side and a second main electrode arranged on the back side, opposite in thickness direction to the first side; a substrate arranged to accommodate the semiconductor element between or within itself, and comprising a first substrate arranged on one side and electrically connected to the first main electrode, and a second substrate arranged on the back side and electrically connected to the second main electrode; a main terminal comprising a first main terminal electrically connected to the first main electrode via the first substrate and a second main terminal electrically connected to the second main electrode; and a bonding element or connecting element.The bonding element is positioned between the first main electrode and the first substrate, and between the second main electrode and the second substrate. At least one connection between the first and second main electrodes contains multiple main terminals. The first and second main electrodes are arranged alternately, such that their faces are orthogonal to the thickness direction of the semiconductor element. The first main electrode is directly connected to the first substrate without using the bonding element. The second main electrode is directly connected to the second substrate without using the bonding element.

[0010] According to the semiconductor device of the present invention, the first main terminal and the second main terminal are arranged alternately, such that their side faces are facing each other. The semiconductor device has several pairs of facing side faces of the first main terminal and the second main terminal. This makes it possible to reduce the inductance.

[0011] For example, if the terminal area remains constant, the gap between the terminals increases as the number of main terminals increases, thus reducing the inductance. As a result, the current-carrying area of ​​the main terminal becomes small, and heat generation at the main terminal leads to problems. According to the semiconductor device of the present invention, the main terminal is directly connected to the corresponding substrate. Since no bonding element is used, it is possible to improve the connection reliability of the main terminals while reducing the inductance. Brief description of the drawings

[0012] The above and further problems, features and advantages of the present invention will become clear with reference to the following detailed description and the accompanying drawings. These show: Fig. 1 a diagram showing a schematic configuration of an electrical power conversion device for which a semiconductor device according to a first embodiment is used; Fig. 2 a perspective view showing the semiconductor device; Fig. 3 a view, if the drawing of the Fig. 2 is viewed in the direction A; Fig. 4 a view, if the drawing of the Fig. 2 is viewed in the direction B; Fig. 5 a cross-sectional view along line VV of the Fig. 4; Fig. 6 a cross-sectional view along line VI-VI of the Fig. 4; Fig. 7 a cross-sectional view to illustrate a manufacturing process; Fig. 8 a cross-sectional view to illustrate a manufacturing process; and Fig. 9 a diagram showing the relationship between the number of main terminals, the inductance and the terminal temperature. Embodiments for carrying out the invention

[0013] Several embodiments are described below with reference to the drawings. In these embodiments, functionally and / or structurally corresponding parts are designated by the same reference numerals. In the following description, a thickness direction of the semiconductor element is designated as a Z-direction, and a direction orthogonal to the Z-direction is designated as an X-direction. A direction orthogonal to both the Z-direction and the X-direction is designated as a Y-direction. Unless otherwise specified, a shape along or in an XY plane defined by the X-direction and the Y-direction is designated as a surface shape or plane shape, respectively. First embodiment

[0014] First, an electrical power conversion device containing a semiconductor device is described with reference to Fig. 1 described. Outline configuration of a power converter

[0015] The in Fig. The electrical power conversion device 1 shown is, for example, mounted on an electric vehicle or a hybrid vehicle. The electrical power conversion device 1 performs an electrical power conversion between the DC power source or DC power supply 2 and the motor-generator 3.

[0016] The DC power source 2 is a secondary battery or accumulator capable of being charged and discharged, for example, a lithium-ion battery or a nickel-hydrogen battery. The motor-generator 3 is a three-phase AC rotary machine. The motor-generator 3 serves as a vehicle propulsion power source, i.e., as an electric motor. The motor-generator 3 also serves as a generator during regeneration.

[0017] The electrical power conversion device 1 includes a smoothing capacitor 4 and an inverter 5 as a power converter. A positive electrode terminal of the smoothing capacitor 4 is connected to a positive electrode of the DC power source 2, which is a high-potential electrode of the DC power source 2. A negative electrode terminal of the smoothing capacitor 4 is connected to a negative electrode of the DC power source 2, which is a low-potential electrode of the DC power source 2. The inverter 5 converts the input DC power into three-phase AC power having a predetermined frequency and outputs the three-phase AC power to the motor-generator 3. The inverter 5 converts the AC power generated by the motor-generator 3 into DC power. The inverter 5 is a DC-AC converter.

[0018] The inverter 5 contains upper-lower arm circuits 6 for three phases. In the upper-lower arm circuit 6 of each phase, two arms are connected in series between a high-potential power source line 7 and a low-potential power source line 8. The high-potential power source line 7 is a power source line or current line on a positive electrode side, and the low-potential power source line 8 is a power source line or current line on a negative electrode side. In the upper-lower arm circuit 6 of each phase, a connection point between the upper arm and the lower arm is connected to an output line 9 to the motor-generator 3.

[0019] In this embodiment, an insulated-gate bipolar transistor of n-channel type 6i (hereinafter referred to as IGBT 6i) is used as a switching element forming each arm. Freewheeling diodes 6d (hereinafter referred to as FWD) are connected in reverse parallel to the respective IGBTs 6i. The upper-lower-arm circuit 6 for one phase comprises two IGBTs 6i. In the upper arms, the collector electrodes of the IGBTs 6i are electrically connected to the high-potential power source line 7. In the lower arms, the emitter electrodes of the IGBTs 6i are electrically connected to the low-potential power source line 8. The emitter electrodes of the IGBTs 6i in the upper arms and the collector electrodes of the IGBTs 6i in the lower arms are connected to each other.

[0020] In addition to the smoothing capacitor 4 and the inverter 5 described above, the power conversion device 1 may include a converter (which is a different type of power converter than the inverter 5), a control circuit for the switching element that forms the inverter 5, and the converter or similar components. The converter is a DC-DC converter that converts one DC voltage into another DC voltage with a different value. Semiconductor device

[0021] As it is in the Fig. As shown in Figures 2 to 6, the semiconductor device 20 comprises a sealing resin body 30, a semiconductor element 40, a substrate 50, a terminal 60, a terminal frame 70 which includes a main terminal 71 and a signal terminal 73, and a bonding element or connecting element 80. Fig. 3 is a view from the perspective in direction A. Fig. 2. Fig. 4 is a view from the perspective in direction B. Fig. 2, and for the sake of simplicity, the sealing resin body is 30 in Fig. 4 shown by an alternating long and short dashed line.

[0022] The sealing resin body 30 seals a portion of other elements that form the semiconductor device 20. The remaining elements are exposed to the outside of the sealing resin body 30. For example, the sealing resin body 30 seals the semiconductor element 40. The sealing resin body 30 seals a connection section formed between other elements that form the semiconductor device 20. For example, the sealing resin body 30 seals the connection section between the semiconductor element 40 and the substrate 50. The sealing resin body 30 seals the connection section between the semiconductor element 40 and the terminal 60. The sealing resin body 30 seals the connection section between the terminal 60 and the substrate 50. The sealing resin body 30 seals the connection section between the substrate 50 and the main terminal 71. The sealing resin body 30 can also be referred to as a molding resin.

[0023] The sealing resin body 30 consists, for example, of epoxy resin. The sealing resin body 30 is formed, for example, by an injection molding process. As described in the Fig. 2 and Fig. As shown in Figure 3, the sealing resin body 30 has a surface 300 and a rear surface 301, which is opposite one surface 300 in the Z-direction. The one surface 300 and the rear surface 301 are, for example, flat surfaces. The sealing resin body 30 has a side surface that connects the one surface 300 and the rear surface 301. As shown in Figure 3, the sealing resin body 30 has a side surface that connects the one surface 300 and the rear surface 301. Fig. 2 and Fig. As shown in Figure 4, the sealing resin body 30 of the present embodiment has a substantially rectangular shape in the plane. The sealing resin body 30 has a side surface 302, on which the main connection 71 projects to the outside, and has a side surface 303, on which the signal connection 73 projects to the outside. The side surface 303 is a surface that is opposite the side surface 302 in the Y-direction.

[0024] In the semiconductor element 40, an element is formed on a semiconductor substrate such as Si, SiC, or GaN. The semiconductor device 20 contains at least one semiconductor element 40. In the present embodiment, the IGBTs 6i and FWDs 6d mentioned above are formed on the semiconductor substrate that forms the semiconductor element 40. As described above, an inverting IGBT (RC-IGBT) is used as the semiconductor element 40. The semiconductor element 40 forms one of the arms mentioned above. The semiconductor element 40 is sometimes also referred to as a semiconductor chip.

[0025] Semiconductor element 40 has a vertical structure, so that the main current flows in the Z direction. Although not shown, semiconductor element 40 has a gate electrode. The gate electrode has, for example, a trench structure. As shown in Fig. 5 and Fig. As shown in Figure 6, the semiconductor element 40 has main electrodes on both sides in the thickness direction, i.e., in the Z-direction. Specifically, the collector electrode 41C is arranged as a main electrode on one side, and the emitter electrode 41E is arranged as a main electrode on the rear side, which is the side opposite the first side. In the present embodiment, the collector electrode 41C also serves as the cathode electrode of the FWD 6d. The emitter electrode 41E also serves as an anode electrode of the FWD 6d. The collector electrode 41C extends over almost the entire surface of one side. The emitter electrode 41E extends over a portion of the rear side. The collector electrode 41C corresponds to a first main electrode, and the emitter electrode 41E corresponds to a second main electrode.

[0026] As it is in Fig. As shown in Figures 4 to 6, the semiconductor element 40 has a terminal area 42, which serves as an electrode for signals, on the formation area of ​​the emitter electrode 41E. The terminal area 42 is located at a different position than the emitter electrode 41E. The terminal area 42 is electrically insulated from the emitter electrode 41E. The semiconductor element 40 has a substantially rectangular shape in the plane. The terminal area 42 is positioned at one end in the Y-direction opposite to the formation area of ​​the emitter electrode 42E.

[0027] The semiconductor element 40, for example, has five terminal pads 42. These terminal pads 42 include, in particular, a gate electrode terminal pad, a potential sensing terminal pad for the emitter electrode 41E, a current sensing terminal pad, and a temperature sensing terminal pad for the semiconductor element 40. The temperature sensing terminal pad 42 contains an anode potential terminal pad for a temperature sensing diode, which is a temperature sensing element, and a cathode potential terminal pad. The five terminal pads 42 are arranged side by side in the X direction.

[0028] In the semiconductor element 40, for example, an aluminum-based material can be used as the forming material for the electrodes, such as the collector electrode 41C, the emitter electrode 41E, and the terminal pad 42. If bonding or joining is carried out using solder or a similar material, this preferably includes copper. For example, AlCuSi can be used.

[0029] The substrate 50 is arranged such that the semiconductor element 40 is positioned between it and / or embedded within it in the Z-direction. The substrate 50 serves as a wiring interface, electrically connecting the semiconductor element 40 and the main terminal 71. The board 50 forms the main circuit of the inverter 5. Therefore, the substrate 50 can also be referred to as a printed circuit board or wiring board. The substrate 50 contains at least one metallic material and serves to dissipate heat generated by the semiconductor element 40. Therefore, the substrate 50 can also be referred to as a heat sink or heat dissipation substrate.

[0030] Substrates 50 are arranged in pairs, with the semiconductor element 40 positioned between these pairs. The semiconductor device 20 comprises a substrate 50C located on the collector electrode 41C side and a substrate 50E located on the emitter electrode 41E side, forming a pair of substrates 50 and a substrate pair, respectively. Substrate 50C corresponds to a first substrate, and substrate 50E corresponds to a second substrate.

[0031] Substrates 50C and 50E are arranged such that they accommodate the semiconductor element 40 between them when viewed from the Z-direction. Substrate 50C has a mounting surface 500C on the side of the semiconductor element 40 and a heat dissipation surface 501C opposite mounting surface 500C in the Z-direction. Substrate 50E has a mounting surface 500E on the side of the semiconductor element 40 and a heat dissipation surface 501D opposite mounting surface 500E in the Z-direction. Mounting surfaces 500C and 500E face each other in the Z-direction. Mounting surfaces 500C and 500E are substantially parallel to each other. Mounting surface 500C corresponds to the surface on the side of the second substrate. Mounting surface 500E corresponds to the surface on the side of the first substrate.

[0032] In the present embodiment, the substrate 50 has opposing sections 51C and 51E, in which the substrates 50C and 50E face each other in the Z-direction, and non-opposing sections 52C and 52E, in which the substrates 50C and 50E do not face each other. The substrate 50C has an opposing section 51C that faces the substrate 50E in the Z-direction and a non-opposing section 52C that is connected to the opposing section 51C and does not face the substrate 50E in the Z-direction. The substrate 50E has an opposing section 51E that faces the substrate 50C in the Z-direction and a non-opposing section 52E that is connected to the opposing section 51E and does not face the substrate 50C in the Z-direction. Fig. 5 and Fig. 6 The boundaries between the opposing sections 51C and 51E and the non-opposing sections 52C and 52E are indicated by a dashed line.

[0033] Substrates 50C and 50E are essentially rectangular in shape in the plane. Substrates 50C and 50E are essentially the same shape and size. As shown in Fig. As shown in Figure 4, substrates 50C and 50E essentially coincide in the X-direction. Substrates 50C and 50E are arranged such that they are offset from each other in the Y-direction. In the Y-direction, the opposing sections 51C and 51E are arranged between the non-opposite sections 52C and 52E. In the Y-direction, the non-opposite section 52C is located on the side of the signal terminal 73, and the non-opposite section 52E is located on the side of the main terminal 71, so that the central, opposing sections 51C and 51E are arranged between them.

[0034] A collector electrode 41C is connected to the mounting surface 500C of the substrate 50C via a bonding element 80. The collector electrode 41C is connected at least to the opposite section 51C. A terminal 60 is connected to the mounting surface 500E of the substrate 50E via a bonding element 80. An emitter electrode 41E is connected to a surface of the terminal 60 opposite the mounting surface 500E via a bonding element 80. Corresponding main terminals 71 are also connected to the mounting surfaces 500C and 500E, as described later.

[0035] Terminal 60 serves as a wiring connection for electrically linking the emitter electrode 41E and the substrate 50E. Terminal 60 serves to dissipate the heat generated by the semiconductor element 40. Terminal 60 is made of a material exhibiting excellent electrical and thermal conductivity, for example, copper. Terminal 60 is positioned such that, viewed along the Z-axis, it essentially coincides with the emitter electrode 41E. Terminal 60 has a substantially rectangular parallelepiped shape. Terminal 60 is connected to the opposite section 51E of the substrate 50E.

[0036] At least a portion of each of the substrates 50C and 50E is sealed by the sealing resin body 30. In this embodiment, the heat dissipation surface 501C of substrate 50C is exposed by the sealing resin body 30. The heat dissipation surface 501C is arranged substantially on the same plane as the surface 300. The portion of the surface of substrate 50C that is not the connection section with the collector electrode 41C, the heat dissipation surface 501C, and the connection section with the corresponding main terminal 71C is covered by the sealing resin body 30. Similarly, the heat dissipation surface 501E of substrate 50E is exposed by the sealing resin body 30. The heat dissipation surface 501E is arranged substantially on the same plane as the rear surface 301.The section of the surface of the substrate 50E that is not the connecting section with the connection 60, the heat dissipation surface 501E and the connecting section with the corresponding main connection 71E is covered by the sealing resin body 30.

[0037] Substrate 50 can be, for example, a metal plate or a composite material consisting of an electrical insulator, such as resin or ceramic, and a metal body. One example of a composite material is a DBC substrate (DBC: direct bonded copper). The same materials can be used for substrate 50C and substrate 50E, or different materials can be used. As described in Fig. As shown in Figures 4 to 6, DBC substrates are used as substrates 50C and 50E in this embodiment.

[0038] The substrate 50 comprises an insulator 50x and metal bodies 50y and 50z, arranged such that the insulator 50x is positioned between them. The insulator 50x is a ceramic substrate. The metal bodies 50y and 50z are formed from a material containing, for example, copper. The metal bodies 50y and 50z are directly bonded to the insulator 50x. The substrate 50 is layered or stacked in the order metal body 50y, insulator 50x, and metal body 50z, starting from the side of the semiconductor element 40. The substrate 50 has a three-layer structure.

[0039] The plane shapes and sizes of the metal bodies 50y and 50z are essentially the same. The surface shape of the insulator 50x, which forms the intermediate layer, is similar to that of the metal bodies 50y and 50z. The size of the insulator 50x is larger than that of the metal bodies 50y and 50z. The insulator 50x extends further to the outside of the metal bodies 50y and 50z. In the substrates 50C and 50E, a surface of the metal body 50y forms a mounting surface 500C and 500E. In the substrates 50C and 50E, a surface of the metal body 50z forms a heat dissipation surface 501C and 501E. When a composite material is used as the substrate 50, the opposing sections 51C and 51E and the non-opposing sections 52C and 52E of the substrate 50 are strictly defined by the metal bodies that form the mounting surfaces 500C and 500E.

[0040] In the present embodiment, the metal body 50y of the substrate 50C has a main section 50y1 and a terminal surface 50y2. The main section 50y1 occupies most of the metal body 50y. The collector electrode 41C is connected to the main section 50y1. The terminal surface 50y2 is arranged in accordance with the suspension line 75 described later. The main section 50y1 and the terminal surface 50y2 are electrically isolated from each other. The terminal surfaces 50y2 are located at two of the four corners of the metal body 50y on the side of the signal terminal 73 and are substantially rectangular in shape. Most of the main body 50y1 is located on the opposite section 51C, and a portion of it is located on the non-opposite section 52C. The terminal surface 50y2 is located on the non-opposite section 52C.

[0041] The connection frame 70 has a main connection 71 and a signal connection 73 as external connection points. The connection frame 70 is designed as an element separate from the substrate 50. The connection frame 70 is formed by processing a metal plate made of copper or similar material by pressing or similar means.

[0042] The main terminal 71 is an external connection terminal through which the main current flows. The terminal frame 70 has several main terminals 71. The main terminal 71 is electrically connected to the corresponding main electrode of the semiconductor device 40. The semiconductor device 20 has, as main terminals 71, a main terminal 71C, which is electrically connected to the collector electrode 41, and a main terminal 71E, which is electrically connected to the emitter electrode 41. The main terminal 71C corresponds to a first main terminal, and the main terminal 71E corresponds to a second main terminal. The main terminal 71C can also be referred to as the collector terminal. The main terminal 71E can also be referred to as the emitter terminal.

[0043] The main terminal 71 is connected to the corresponding substrate 50. In the main terminal 71, the connection section with the substrate 50 is sealed by the sealing resin body 30. Each of the main terminals 71 extends from the connection section with the substrate 50 in the Y-direction towards the semiconductor element 40. All main terminals 71 project outwards from the side face 302 of the sealing resin body 30. The main terminal 71C has a substantially constant width and extends in the Y-direction in a Z-direction view. The main terminal 71E also has a substantially constant width and extends in the Y-direction in a Z-direction view. The widths of the main terminals 71C and 71E are substantially equal. The main terminal 71C extends substantially parallel to the current paths of the main terminal 71E and the substrate 50E.

[0044] As it is in Fig. 4 and Fig. As shown in Figure 5, the main terminal 71C has a connecting section 710C and an extension section 711C. The connecting section 710C is a connecting section of the main terminal 71C to the substrate 50C. The connecting section 710C is directly connected to the substrate 50C by ultrasonic bonding, friction stir welding, laser welding, or similar methods. The connecting section 710C is directly connected to the substrate 50C without the use of the bonding element 80. The extension section 711C is a section that extends from the connecting section 710C. The extension section 711C is integrally connected to the connecting section 710C.

[0045] In this embodiment, the main terminal 71C is directly connected to the metal body 50y of the substrate 50C by means of an ultrasonic connection. The connecting section 710C of the main terminal 71C is connected to the opposite section 51C of the substrate 50C. The extension section 711C faces the mounting surface 500E of the substrate 50E at a position closer to the substrate 50E than the connecting section 710C. The main terminal 71C bridges the non-opposite section 52E in the Y-direction. The extension section 711C approaches the substrate 50E in the Z-direction and extends away from the semiconductor element 40 in the Y-direction.

[0046] The extension section 711C has a curved section. The extension section 711C projects from the sealing resin body 30 at a position that is closer to the mounting surface 500E in the Z direction than the connecting section 710C. The main connection 71C has a crank or lever shape in the YZ plane and includes a section that extends substantially parallel to the mounting surface 500E on the non-opposite section 52E. As shown in Fig. As shown in Figure 5, the facing distance D1 between the parallel section of the extension section 711C and the non-opposite section 52E is smaller than the facing distance D2 between the mounting surfaces 500C and 500E of the substrates 50C and 50E.

[0047] As it is in Fig. 4 and Fig. As shown in Figure 6, the main terminal 71E has a connecting section 710E and an extension section 711E. The connecting section 710E connects the main terminal 71E to the substrate 50E. The connecting section 710E is also directly connected to the substrate 50E without the use of the bonding element 80. The extension section 711E extends from the connecting section 710E. The extension section 711E is integrally connected to the connecting section 710E.

[0048] In this embodiment, the main terminal 71E is directly connected to the metal body 50y of the substrate 50E by means of an ultrasonic connection. The connecting section 710E of the main terminal 71E is connected to the non-opposite section 52E of the substrate 50E. The extension section 711E extends in the Y direction away from the semiconductor element 40. The extension section 711E also has a curved section. The extension section 711E projects from the sealing resin body 30 at a position that is closer to the mounting surface 500E in the Z direction than the connecting section 710E. The main terminal 71E has a cranked shape in the YZ plane.

[0049] The main connections 71C and 71E are arranged side by side in one direction orthogonal to the Z-direction. The main connections 71C and 71E are arranged such that the side surfaces 712C and 712E face each other. The extension sections 711C and 711E of the main connections 71C and 71E face each other. The connection frame 70 has several of the main connections 71C and 71E.

[0050] The main connections 71C and 71E are arranged alternately in the direction of assembly. Alternating means that the main connections 71C and 71E are adjacent to each other in the direction of assembly. The main connections 71C and 71E do not face each other on the plate surfaces; instead, the side surfaces 712C and 712E face each other. Due to the alternating arrangement, the connection frame 70 has several sets of side surfaces 712C and 712E facing each other. At least a portion of the side surfaces 712C and 712E can face each other in the plate thickness direction of the main connection 71. The side surfaces can, for example, be arranged such that they are offset from each other in the plate thickness direction. Preferably, one of the facing side surfaces 712C and 712E is arranged such that it faces the other over its entire area in the thickness direction.

[0051] The minimum alternating configuration is one that contains a total of three main terminals 71. In the case of two main terminals 71C and one main terminal 71E, for example, the main terminal 71C, the main terminal 71E, and the main terminal 71C are arranged sequentially in the arrangement direction. Two sets of mutually facing side surfaces 712C and 712E are formed. In this embodiment, the terminal frame 70 has four main terminals 71C and five main terminals 71E. The main terminals 71C have essentially the same structure. The main terminals 71E have essentially the same structure.

[0052] The main terminals 71C and 71E are arranged alternately in the X direction. The main terminals 71E are arranged at both ends in the direction of arrangement. The main terminals 71C and 71E are arranged in substantially the same positions in the Z direction on the side of the projecting end of the main terminal 71E from the bent section. The side surfaces 71C and 71E face each other. As shown in Fig. As shown in Figure 3, the connection frame 70 has eight sets of mutually facing side surfaces 712C and 712E. The facing distance between the side surfaces 712C and 712E, in other words the offset or distance of the main connections 71C and 71E, is almost constant.

[0053] As it is in Fig. As shown in Figure 4, the main terminals 71C and 71E are arranged symmetrically with respect to the center line CL, which passes through the element center in the X-direction of the semiconductor element 40. The element center is the center of the semiconductor element 40 when there is a single semiconductor element 40, as in the present embodiment. If there are two semiconductor elements 40, it is, for example, the central position between their centers in the orientation direction of the two semiconductor elements 40. The center line CL is a virtual line orthogonal to the X-direction that passes through the element center.

[0054] The signal terminal 73 is electrically connected to the connection surface 42 of the corresponding semiconductor element 40. The connection frame 70 has several signal terminals 73. The signal terminal 73 is connected to the connection surface 42 within the sealing resin body 30. The five signal terminals 73 connected to the connection surfaces 42 extend in the Y direction and each extends away from the semiconductor element 40. The signal terminals 73 are arranged in a row in the X direction. All signal terminals 73 project outwards from the side surface 302 of the sealing resin body 30.

[0055] As it is in Fig. 5 and Fig. As shown in Figure 6, the signal terminal 73 in this embodiment is connected to the terminal surface 42 via the bonding element 80. A conductive paste containing solder, silver, or a similar material can be used as the bonding element 80. In this embodiment, solder is used as the bonding element 80.

[0056] The connection frame 70 has a suspension line 75. The signal connections 73 are supported by the suspension lines 75 via webs (not shown) in a state before the webs are removed in a process. After the sealing resin body 30 has been molded, unnecessary parts of the connection frame 70, including the webs, are removed. Two suspension lines 75 are arranged such that the signal connection 73 is located between them in the X-direction. The suspension line 75 extends in the Y-direction. One end of the suspension line 75 is connected to the connection surface 50y2 described above, and a portion containing the other end projects from the side surface 303 of the sealing resin body 30. In the present embodiment, the suspension line 75 is directly connected to the connection surface 50y2 without the bonding element 80 being interposed.The suspension line 75 is directly connected to the substrate 50C via an ultrasonic connection.

[0057] In the semiconductor device 20 configured as described above, the sealing resin body 30 seals a portion of each of the semiconductor element 40 and the substrate 50, a portion of each of the terminal 60 and the main terminal 71, and a portion of the signal terminal 73 in one piece. That is, the elements forming an arm are sealed. Such a semiconductor device 20 can also be referred to as a one-in-one package.

[0058] Furthermore, the heat dissipation surface 501C of the substrate 50C is arranged essentially on the same plane as a surface 300 of the sealing resin body 30. The heat dissipation surface 501E of the substrate 50E is arranged essentially on the same plane as the rear surface 301 of the sealing resin body 30. The semiconductor device 20 has a double-sided heat dissipation structure in which the heat dissipation surfaces 501C and 501E are both exposed by the sealing resin body 30. The semiconductor device 20 can be formed, for example, by separating the substrate 50 together with the sealing resin body 30. Alternatively, the sealing resin body 30, with the heat dissipation surfaces 501C and 501E in contact with the cavity wall surface of the mold, can be cast or molded to form the sealing resin body 30. Manufacturing process of the semiconductor device

[0059] An example of the manufacturing process of the semiconductor device 20 described above is given with reference to the Fig. 7 and Fig. 8 described.

[0060] First, the in Fig. The stacked bodies shown in section 7 are formed. This is the state before the substrate 50E is connected to the stacked body. As shown in Fig. As shown in Figure 7, the semiconductor element 40 is positioned on the mounting surface 500C of the substrate 50C via the bonding element 80. The terminal 60 is also positioned on the emitter electrode 41E of the semiconductor element 40 by means of the bonding element 80. The bonding element 80 is positioned on the surface of the terminal 60 on the substrate 50E side. The terminal 60 can, for example, be positioned on the emitter electrode 41E with the bonding elements 80 pre-positioned on both sides of the terminal 60. Furthermore, a connection section of the signal terminal 73 with the connection surface 42 is positioned via the bonding element 80. In this configuration, a connection section is formed via the bonding element 80 by heating or similar means. If solder is used as the bonding element 80, a solder joint is formed by a solder reflow process.

[0061] After the connection section is formed, the main terminal 71C and the suspension line 75 are connected to the substrate 50C. In this embodiment, the connection section 710C of the main terminal 71C is directly connected to the mounting surface 500C on the opposite section 51C of the substrate 50C by means of an ultrasonic connection. Furthermore, one end of the suspension line 75 is directly connected to the connection surface 50y2 of the substrate 50C by means of an ultrasonic connection. As a result, a stacked body is formed.

[0062] As it is in Fig. As shown in Figure 8, the substrate 50E is then positioned on the terminal 60. In this configuration, the substrate 50E and the terminal 60 are connected via the bonding element 80. If solder is used, the substrate 50E and the terminal 60 are joined by a reflow soldering process. After the substrate 50E is connected, the main terminal 71E is connected to the substrate 50E. In this embodiment, the connecting section 710E of the main terminal 71E is directly connected to the mounting surface 500E on the non-opposite section 52E of the substrate 50C by means of an ultrasonic connection. Since the substrates 50C and 50E are positioned offset from each other in the Y-direction, the main terminal 71E can be directly connected to the mounting surface 500E of the substrate 50E.The substrate 50E can be arranged so that it comes into contact with the heat dissipation surface 501E on a base (not shown), and the main terminal 71E can be connected in this arrangement. For example, the substrate 50E can be arranged vertically below the substrate 50C, and the main terminal 71E can be connected.

[0063] Although not shown, the sealing resin body 30 is subsequently formed. The semiconductor device 20 can then be obtained by cutting away an unnecessary part of the connection frame 70, such as a web. Summary of the first embodiment

[0064] According to the semiconductor device 20 of the present embodiment, the main terminals 71C and 71E are arranged alternately. The side faces 712C and 712E of adjacent main terminals 71C and 71E face each other. At the main terminals 71C and 71E, the directions of the main currents are substantially opposite. As a result, magnetic fluxes generated when the main current flows cancel each other out, and the inductance can be reduced. However, the side face is smaller than the plate surface area when viewed in the plate thickness direction. On the other hand, the terminal frame 70 has three or more main terminals 71. Consequently, the main terminals 71 have multiple sets of mutually facing side faces 712C and 712E. Accordingly, it is possible to effectively reduce the inductance. Furthermore, multiple main terminals 71C and 71E of the same type are arranged in parallel.This also makes it possible to reduce the inductance.

[0065] Fig. Figure 9 is a diagram showing the relationship between the total number of main connections, the inductance, and the connection temperature or temperature of the connections. Fig. Figure 9 shows simulation results, such as a magnetic field analysis. Here, the width of the entire main connection (as width W1 in Fig. 4 defined) kept constant. From Fig. As can be seen in Figure 9, the inductance can be reduced by increasing the number of main terminals 71, that is, by increasing the number of pairs of facing side surfaces 712C and 712E. In this embodiment, there are four main terminals 71C and five main terminals 71E. Accordingly, it is possible to effectively reduce the inductance.

[0066] This can, for example, reduce the surge voltage generated by switching the IGBT 6i.

[0067] In the configuration where, for example, all main connections 71 are extended from the side surface 302 of the sealing resin body 30, as in the present embodiment, the connection width W1 is limited by the width of the side surface 302, more precisely, the width of the substrate 50. If the width W1 of the entire main connection remains constant, increasing the number of main connections 71 increases the ratio of the gaps between the main connections 71 to the width W1. The cross-sectional area of ​​each of the main connections 71 becomes smaller, and the current-carrying area of ​​the main connections 71 at the same potential becomes smaller. Therefore, it is difficult, for example, for a DC current to flow. As shown in Fig.As shown in Figure 6, the temperature of the main terminals 71 therefore increases when the number of main terminals 71 is increased. The DC current is a current (i.e., direct current) that flows in a stable state when the semiconductor element (i.e., the switching element) is switched on. On the other hand, in the present embodiment, the main terminals 71C and 71E are directly connected to the corresponding substrates 50C and 50E without the use of a bonding element 80 such as solder. Since metals are joined together and the bonding element 80, such as solder, is not used, the connection reliability of the main terminal 71 to the substrate 50 can be improved. For example, the occurrence of electromigration can be suppressed.

[0068] According to the above description, it is possible to create a semiconductor device 20 that is able to improve the connection reliability of the main terminal 71 while simultaneously reducing the inductance.

[0069] Furthermore, in the present embodiment, substrates 50C and 50E are arranged offset from one another. As a result, substrate 50E has the non-opposite section 52E. Therefore, the main terminal 71E of the connection frame 70 can be directly connected to the mounting surface 500E of the non-opposite section 52E. When the connection frame structure is used, both main terminals 71C and 71E can be directly connected to the mounting surfaces 500C and 500E of the corresponding substrates 50C and 50E.

[0070] The reduction in inductance is also achieved by the facing arrangement of substrates 50C and 50E. However, the semiconductor element 40 and the terminal 60 are arranged between substrates 50C and 50E. Furthermore, in the present embodiment, the extension section 711C of the main terminal 71C is arranged facing substrate 50E at a position that is closer to substrate 50E (i.e., the mounting surface 500E) than the connecting section 710C. As a result, the extension section 711C of the main terminal 71C is the section closest to having the same potential as the collector electrode 41C facing substrate 50E. Therefore, the inductance reduction effect can be increased. Since several such main terminals 71C are provided, the inductance reduction effect can be further enhanced.

[0071] In particular, the main terminal 71C of the present embodiment extends over the non-opposite section 52E of the substrate 50E in the Z-direction view. The main terminal 71C crosses the non-opposite section 52E in the Y-direction. The extension section 711C of the main terminal 71C is arranged facing the non-opposite section 52C. Accordingly, it is possible to effectively reduce the inductance.

[0072] In the present embodiment, the main terminals 71C and 71E are arranged symmetrically with respect to the center line CL of the semiconductor element 40 in the X-direction. As a result, the main current flows in such a way that it is symmetrically with respect to the center line CL. The main current flows almost equally on the left and right sides with respect to the center line CL. This makes it possible to reduce the inductance. Furthermore, it makes it possible to prevent local heat generation.

[0073] An example configuration of the main terminal 71 has been shown that has four main terminals 71C and five main terminals 71E, but the present embodiment is not limited to this feature. The number of main terminals 71C can be greater than the number of main terminals 71E. For example, the number of main terminals 71C can be five, and the number of main terminals 71E can be four. In this case, the main terminals 71C are arranged at both ends in the orientation direction or arrangement direction. The total number of main terminals 71 is not limited to an odd number. It can be an even number.

[0074] Although not shown, the signal terminal 73 can be electrically connected to the contact surface 42 of the semiconductor element 40 via a connecting wire or bonding wire. The thickness of the terminal 60 increases the height of the connecting wire.

[0075] An example is shown in which the semiconductor device 20 includes a terminal 60, but the present invention is not limited to this. If the signal terminal 73 is connected to the terminal 42 via the bonding element 80 as in the present embodiment, the terminal 60 does not need to be provided. Since the distance D2 between the substrates 50C and 50E becomes smaller, the inductance can be further reduced accordingly. On the other hand, in a configuration in which the signal terminal 73 is connected to the terminal 42 via the bonding element 80, the distance D2 between the substrates 50C and 50E can be set to a predetermined value using the terminal 60.

[0076] The connection position of the main terminal 71 with the substrate 50 is not limited to the example above. The main terminal 71 can, for example, be connected to the side surface of the corresponding substrate 50. Other embodiments

[0077] The invention described herein is not limited to the exemplary embodiment shown. The invention covers the illustrated embodiment as well as modifications based on the illustrated embodiment that are obvious to a person skilled in the art. For example, the invention is not limited to the combinations of parts and / or elements shown in the embodiment. The invention can be implemented in various combinations. The invention may include additional parts that are added to the embodiment. The invention also covers the omission of parts and / or elements of the embodiment. The invention includes the substitution of components and elements between one embodiment and another embodiment, as well as a combination thereof. The disclosed technical scope is not limited to the description of the embodiments.

[0078] Although an example has been described in which the semiconductor device 20 is used for the inverter 5, the invention is not limited to the above example. The present invention can, for example, be used for a converter. The present invention can also be used for both the inverter 5 and the converter.

[0079] An example has been described in which the IGBT 6i and the FWD 6d are formed on the semiconductor element 40, but the present invention is not limited to this feature. The IGBT 6i and the FWD 6d, which form the same arm, can be arranged on separate chips.

[0080] Although the IGBT 6i is shown as an example of the switching element, the present invention is not limited to the above example. For instance, a MOSFET can be used.

[0081] An example is shown in which the heat-dissipating surfaces 501C and 501E are exposed by the sealing resin body 30, but the present invention is not limited to this feature. At least one of the heat-dissipating surfaces 501C and 501E can be covered by the sealing resin body 30. The heat-dissipating surfaces 501C and 501E can be covered with an insulating element (not shown) that is not the resin sealing body 30.

[0082] An example in which the semiconductor device 20 contains the sealing resin body 30 is shown, but the present invention is not limited to this example.

Claims

[1] Semiconductor device comprising: at least one semiconductor element (40) having a first main electrode (41C) arranged on one surface side and a second main electrode (41E) arranged on a back surface side opposite to the one surface side in a thickness direction; a substrate (50) arranged to receive the semiconductor element therein, and comprising a first substrate (50C) arranged on the one surface side and electrically connected to the first main electrode, and a second substrate (50E) arranged on the back surface side and electrically connected to the second main electrode; a main terminal (71) including at least one first main terminal (71C) electrically connected to the first main electrode via the first substrate and at least one second main terminal (71E) electrically connected to the second main electrode via the second substrate; and a bonding element (80), wherein the bonding element is arranged between the first main electrode and the first substrate and between the second main electrode and the second substrate; at least one of the first main port and the second main port in the main port contains a plurality of ports; the first main terminal and the second main terminal are arranged alternately, and a side surface of the first main terminal and a side surface of the second main terminal face each other in a direction orthogonal to the thickness direction of the semiconductor element; the first main terminal is directly connected to the second substrate without the bonding element, and the second main terminal is directly connected to the second substrate without the bonding element, characterized by , that the substrate includes an opposing portion (51C, 51E) in which the first substrate and the second substrate face each other in the thickness direction, and a non-opposing portion (52E) connected to the opposing portion of the second substrate and not facing the first substrate; the first main terminal is directly connected to a surface (500C) of the first substrate on the side of the second substrate without the bonding element; and the second main terminal is directly connected to a surface (500E) of the non-opposing portion of the second substrate on the side of the first substrate without the bonding element. [2] A semiconductor device according to claim 1, wherein the first main terminal is directly connected to the opposite portion of the first substrate; and the first main terminal includes a connecting portion (710C) to the first substrate and an extending portion (711C) extending from the connecting portion and disposed facing the second substrate at a position closer to the second substrate than the connecting portion. [3] A semiconductor device according to claim 2, wherein the first main connection bridges the non-opposing section in a view in the thickness direction; and the extension section is arranged facing at least the non-opposite section of the second substrate. [4] A semiconductor device according to any one of claims 1 to 3, further comprising: a sealing resin body (30) which integrally seals at least a part of the semiconductor element, at least a part of the substrate and a part of the main terminal, wherein all main connections protrude from one surface of the sealing resin body to an outer side of the sealing resin body.

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