INTEGRATED COOLING STRUCTURE FOR QUANTUM DEVICE WITH SEMICONDUCTOR QUBITS

Abstract

Structure (150) for cooling a component (C1) of a quantum device by circulating a given current between a first element (51) for contact with the component and a second element (52) for contact with the component, the first contact element (51) comprising at least one given superconducting metallic material, in particular at a given temperature below 2K, and being in contact by a first end with a first semiconductor portion of said component (C1) so as to form with the first semiconductor portion at least one cooling tunnel junction. Figure for abstract: 1

Description

Title of the invention: INTEGRATED COOLING STRUCTURE FOR QUANTUM DEVICE WITH SEMICONDUCTOR QUBITS

[0001] TECHNICAL FIELD AND PRIOR ART

[0002] The present application relates to the field of electronic devices quantum devices, particularly those with qubits formed in a semiconductor region, and relates to an improved integrated structure for cooling such a type of device as well as a manufacturing method.

[0003] Quantum devices rely on qubits (sometimes also noted as "Qbits") or quantum bits as information vectors, that is, bits of information based on a given quantum state among at least two measurable levels.

[0004] Qubits can be formed in a semiconductor material within nanometric-sized, electrostatically controlled confinement structures. These confinement structures are typically called "quantum dots". A quantum dot behaves like a potential well confining one or more elementary charges (electrons or holes) in a semiconductor region.

[0005] A special type of semiconductor qubit is the spin qubit when the degree of freedom of the spin of electrons or holes is used to encode quantum information.

[0006] To measure the state of a spin qubit, it is known in particular to carry out a spin / charge conversion which makes it possible to convert the spin state of the charged particles into a charge state of the quantum dots containing said particles. It is then necessary to measure this charge state in order to deduce the spin state of the charged particles before conversion. For this, a means for measuring the charge state is generally arranged near each quantum dot.

[0007] Reading a qubit can be carried out in particular by using another quantum box called a “reading island” or “detection island” coupled to that of the qubit intended to be read. These two elements form two potential wells separated by a potential barrier.

[0008] Such devices generally operate at a very low temperature, i.e. typically of the order of Kelvin or a few hundred milli-Kelvins, to prevent thermal noise from destroying quantum coherence. Compared to the field of superconducting qubits where the temperature range is limited to a few tens of milli-Kelvins, the operation of spin qubits has already been demonstrated at 1.5 K, offering other perspectives for their cooling. The qubits are cooled by placing the device in a refrigerant system or cryostat that can reach temperatures of the order of tens of milli-Kelvins.

[0009] However, it is also sought to improve thermal management within the device itself, for example between components intended to store quantum information, for which the operating temperature is critical, but typically exhibiting low heat dissipation, and associated control components in the form, for example, of a reading circuit produced in CMOS technology, for which the operating temperature is less critical, but typically exhibiting high heat dissipation.

[0010] For co-integration of these elements, an operating temperature of 1 K may be preferred in order to increase the available cooling power of the cryostat for thermalization of the system.

[0011] Document FR3°114°443 presents a solution consisting of providing in an area conductive routing tracks ensuring a thermal and electrical conductor function, and superconducting routing tracks ensuring an electrical conductor and thermal insulator function. This makes it possible to improve thermalization at the system level while ensuring good thermal insulation between the quantum or qubit components and the control components.

[0012] In another field, that of superconducting qubits (which encode quantum information on anharmonic resonators made from Josephson junctions), documents US2022 / 0138609, WO2023 / 156701A1 and US11302857B2 propose a cooling method at the scale of superconducting qubits by means of a remote cooling tunnel junction at a distance from the qubits.

[0013] The problem arises of improving the thermal management of a quantum device with semiconductor qubits, in particular at the qubit scale, while limiting the size required for this management. Statement of the invention

[0014] It is therefore an aim of the present invention to provide a cooling structure for a quantum device with semiconductor qubits and which is integrated within or as close as possible to the quantum or control components to be cooled.

[0015] To do this, according to one embodiment, the present invention provides a quantum electronic device, in particular with spin qubits, comprising a substrate and a component arranged on the substrate, the component comprising at least one so-called “channel” zone formed in at least one semiconductor layer and comprising one or more islands, each island being controlled by means of an electrostatic control gate and forming a quantum box or a detection island for reading the state quantum dot of a quantum dot, the device further comprising: a structure provided for cooling the component by circulating a given current between a first contact element with the component and a second contact element with the component, the first contact element comprising at least one given superconducting metallic material, and being in contact by a first end with a first semiconductor portion of the component so as to form with the first semiconductor portion at least one tunnel junction.

[0016] This tunnel junction, also called a “cooling” junction, is in particular of the NS (for “Normal” “Superconductor”) or NIS (for “Normal” “Insulating” “Superconductor”) type.

[0017] This achieves cooling of the component as close as possible to the semiconductor layer(s) in which the qubits are provided, while not impacting the size, which is essential for scaling up quantum devices. This integrated local cooling solution makes it possible in particular to improve the stability of quantum operations, by protecting against the heat dissipated by the control components integrated nearby in a monolithic manner or by 3D integration techniques.

[0018] In addition to the compact aspect of such a cooling structure and the possibility of cooling as close as possible to the qubits, such a structure has the advantage of being able to be integrated without requiring a number of additional steps and / or significant adaptations of the manufacturing process. The choice of materials used makes it possible to obtain such a tunnel junction in the quantum component and / or the control component.

[0019] According to an advantageous embodiment, the given superconducting metallic material may be a material having a critical temperature Te greater than 2 K, advantageously greater than 4 K, such as TiN.

[0020] Advantageously, the first contact element may be, from the first end to a second end, formed from the given superconducting metallic material.

[0021] Alternatively, the first contact element comprises at the first end a stack of a dielectric zone in contact with the first semiconductor portion and a section based on the given superconducting metallic material.

[0022] Advantageously, this dielectric zone may be an oxidized zone of the semiconductor material of the first semiconductor portion.

[0023] According to a particular configuration, the first contact element may comprise at the first end a stack of the given superconducting material in contact with the first semiconductor portion and of a second superconducting material having a gap higher than the given superconducting material.

[0024] According to an embodiment in which the channel zone extends in a first direction parallel or substantially parallel to a main plane of the substrate and in which the first element extends in a direction orthogonal or substantially orthogonal to the first direction, the first contact element can be connected by a second end to a metal track of superconducting metallic material parallel or substantially parallel to the main plane of the substrate.

[0025] Advantageously, the first contact element can be formed from a set of contact pads connected in parallel to the metal track.

[0026] According to an advantageous implementation, the second contact element may comprise at least one superconducting metallic material and be in contact with a second semiconductor portion of the component so as to form with the second semiconductor portion at least one second NS or NIS tunnel junction.

[0027] According to one possible implementation, the second contact element is in contact with a second semiconductor portion of the component and the channel zone extends between a semiconductor region called the “source” region and a second semiconductor region called the “drain” region, the first semiconductor portion and the second semiconductor portion each being portions of the source region or the drain region.

[0028] Advantageously, the structure for cooling the component further comprises a third contact element in contact with a third semiconductor portion of the component and a fourth contact element with a fourth semiconductor portion of the component, the third contact element forming a tunnel junction, in particular of the NIS or NS type with the third semiconductor portion of the component, the third semiconductor portion and the fourth semiconductor portion each being portions of an electrostatic control grid of the component.

[0029] The second contact element may be in contact with a second semiconductor portion of the component while the first semiconductor portion and the second semiconductor portion are each portions of an electrostatic control grid.

[0030] According to a possible implementation, the second contact element being in contact with a second semiconductor portion of the component in which the “channel” zone comprises one or more detection islands for reading the quantum state of one or more quantum dots of another part of the component or of another component and in which the channel zone extends between a first semiconductor region called “source” and a second semiconductor region called “drain”, the first portion and the second portion being: respectively a portion of the source region and a portion of the drain region.

[0031] According to one possible embodiment, in order to facilitate cooling, at least one cavity arranged opposite the component can be provided in the substrate.

[0032] Advantageously, each island of the component can form a quantum dot, the device further comprising: another component for reading the quantum state of the component, the device further comprising a structure provided for cooling the other component by circulating a given current between a contact element with this other component and another contact element with this other component, the contact elements forming at least one tunnel junction, in particular of the NIS or NS type, with a semiconductor portion of the other component.

[0033] The component and the other component may advantageously be connected by a metal interconnection line of a metal level of interconnections arranged in at least one insulating layer. According to a particular configuration, the metal interconnection line may be surrounded by a cavity forming an empty space around the metal interconnection line and surrounded by the insulating layer. This also contributes to better cooling.

[0034] According to another aspect, the present application relates to a method of manufacturing a device as defined above.

[0035] One embodiment provides in particular a method of manufacturing a device as defined previously and comprising steps consisting of:

[0036] - providing the substrate and the component formed on the substrate,

[0037] - in at least one insulating layer covering the component, produce at least a first hole and at least one second hole respectively revealing the first semiconductor portion and the second semiconductor portion of the component,

[0038] - forming the first contact element in the first hole and the second element contact in the second hole, by depositing at least the given superconducting metallic material in the first hole and in the second hole. Brief description of the drawings

[0039] The present invention will be better understood on the basis of the following description and the attached drawings in which:

[0040] [Fig. 1] illustrates an example of a structure for cooling a component of a quantum device, the component comprising one or more quantum dots formed in a semiconductor zone, the structure being provided with contact elements between which a current is made to flow.

[0041] [Fig.2] illustrates a first particular example of realization of the tunnel junction cooling, here of the NS type and using a Schottky barrier, formed between the contact element and the portion of the component to be cooled.

[0042] [Fig.3] illustrates a second particular example of embodiment of the junction of cooling, here of the NIS type, the insulator being formed of a native oxide between the contact element and the portion of the component to be cooled.

[0043] [Fig.4] illustrates a third particular example of embodiment of the junction of cooling, here of the NIS type, the insulator being formed by a deposit of dielectric material between the contact element and the portion of the component to be cooled.

[0044] [Fig.5] illustrates a fourth particular embodiment example the junction of cooling, here of the NS type, the superconducting contact being formed of two superconducting materials deposited one after the other.

[0045] [Fig.6] illustrates an example of an embodiment for which the structure dedicated to the cooling is provided with contact elements on both the source region and the drain region of the component.

[0046] [Fig.7] illustrates an example of an embodiment for which the structure dedicated to the cooling is provided with contact elements on at least one electrostatic control grid of the component.

[0047] [Fig.8] illustrates an example of an embodiment for which the structure dedicated to the cooling is provided with contact elements both on at least one electrostatic control grid as well as on the source and drain regions of the component.

[0048] [Fig.9] illustrates an exemplary embodiment in which the structure for cooling is configured to cool a channel area with detection islands dedicated to quantum state detection of quantum dots.

[0049] [Fig. 10] illustrates another example in which the cooling structure is configured both to cool the channel zone provided with one or more detection islands and one or more control grids of this or these islands.

[0050] [Fig. 11] illustrates an exemplary embodiment where several contact elements of the cooling structure are connected to the same superconducting track.

[0051] [Fig.l2A]

[0052] [Fig.l2B]

[0053] [Fig.l2C]

[0054] [Fig. 12D] illustrate an exemplary embodiment of a quantum device component provided with at least one semiconductor layer intended to accommodate one or more quantum dots.

[0055] [Fig.l2E]

[0056] [Fig. 12F]

[0057] [Fig. 12G] illustrate an example of the embodiment of contact elements for a structure intended to cool the component.

[0058] [Fig. 13] illustrates an exemplary embodiment in which contact elements of the structure for cooling are further arranged on electrostatic control grids of the quantum dots.

[0059] [Fig. 14] illustrates an example of the production of metal tracks to enable the contact elements of the structure to be polarized.

[0060] [Fig. 15] illustrates an exemplary embodiment in which the cooling structure is arranged both on a first component intended to accommodate one or more quantum dots and on a second component intended to detect the quantum state of the first component.

[0061] [Fig.16A]

[0062] [Fig.16B] illustrate different possibilities of arrangements of a matrix of quantum components or qubits in relation to the associated control components.

[0063] [Fig. 17] illustrates an alternative embodiment in which one or more cavities are formed in the dielectric and / or in the substrate in order to limit heat transfer via these media and thus limit heating of a quantum device comprising quantum and control components.

[0064] [Fig. 18] illustrates a fifth particular embodiment of the cooling junction, here of the NIS type, with a superconducting contact formed of two stacked superconducting materials, the superconducting contact being surrounded by an envelope of dielectric material.

[0065] [Fig. 19] illustrates a sixth particular embodiment of the cooling junction, here of the NIS type, with a superconducting contact formed of two stacked superconducting materials and arranged on the oxide.

[0066] Identical, similar or equivalent parts of the different figures described below bear the same numerical references so as to facilitate the transition from one figure to another.

[0067] Furthermore, in the following description, terms which depend on the orientation of the structure such as "above", "below", "rear", "front", "upper", "lower", apply considering that the structure is oriented in the manner illustrated in the figures.

[0068] The different parts represented in the figures are not necessarily on a uniform scale, in order to make the figures more readable.

[0069] DETAILED DESCRIPTION OF PARTICULAR EMBODIMENTS

[0070] We first refer to [Fig.l] which gives a particular example of embodiment of a device provided with at least one quantum component Ci, in particular with spin qubits, according to a first embodiment and represented in a top view.

[0071] The component Ci comprising several quantum boxes BQ1, BQ2, BQ3 each formed in an island of a zone 12a called “channel” of the component which extends in at least one semiconductor layer 12. This semiconductor layer 12 may be the surface layer of a substrate or a layer transferred or deposited on a substrate and formed from a semiconductor material or several stacked semiconductor materials.

[0072] For example, the semiconductor layer 12 may be made of silicon or Germanium. According to a particular embodiment, the semiconductor layer 12 is the surface layer of a semiconductor-on-insulator type substrate, in particular a silicon layer of an SOI substrate (SOI for “Silicon On Insulator” or silicon on insulator).

[0073] The quantum boxes BQ1, BQ2, BQ3 each ensure the confinement of at least one elementary charge (electron or hole). The spin of this charge, in particular of an electron, is here provided to encode the quantum information. The qubits associated respectively with the quantum boxes BQ1, BQ2, BQ3 are spin qubits.

[0074] Electrostatic control grids 22b 222, 223 are provided opposite each of the islands respectively forming the quantum dots BQ1, BQ2, BQ3 and are, in this particular embodiment, arranged above the semiconductor layer 12. The electrostatic control grids 22b 222, 223 may be formed from a metallic material such as for example TiN, or a semiconductor such as for example polysilicon or a stack of metallic material and semiconductor.

[0075] On either side of the zone 12a, the component comprises a semiconductor region 13s also called a “source” region forming a first reservoir of charges or dopants of the component Cl and a semiconductor region 13d also called a “drain” region forming a second reservoir of charges or dopants of the component CL. The semiconductor regions 13s, 13d, can be formed for example based on silicon and / or SiGe and / or Ge and are typically doped in volume.

[0076] The device here has the particularity of being provided with an integrated cooling structure 150 for cooling the component Ci. This structure 150 comprises a first contact element 51 and a second contact element 52, each in contact with a semiconductor region of the component Ci.

[0077] Cooling of the component Ci is implemented by passing a current from the first element 51 to the second element 52. For this, it is provided that the first contact element 51, at least partially made of superconducting material, forms, with a semiconductor portion of the component with which this element is in contact, at least one NIS (for “Normal Insulating Superconductor”) type cooling tunnel junction or at least one cooling tunnel junction NS type (for "Normal Superconductor") with a Schottky barrier. In the second configuration with Schottky barrier, it is actually a special case of NIS junction where the Insulator is replaced by a metal-superconductor contact to advantageously form the barrier of the junction.

[0078] Several cooling tunnel junctions (NIS or NS) can be connected in series and / or in parallel. In order to increase the cooling power, several junctions can be connected in series. Thus, for example, two NIS (or NS) cooling tunnel junctions can be connected in series (in symmetry with the element to be cooled) to create a “SINIS” (or “SNS”) junction and thus double the cooling power.

[0079] The superconducting material(s) of element 51 is preferably a material having a critical superconductivity temperature Te which is greater than 2 K, advantageously greater than 4 K, such as for example Niobium (Nb), Niobium nitride (NbN), Titanium nitride (TiN), Tantalum nitride (TaN), Niobium-Titanium nitride (NbTiN).

[0080] A principle of NIS junction cooling is given in the document “Micrometer-scale refrigerators”, by Juha T Muhonen et al, 2012 Rep. Prog. Phys. 75 046501.

[0081] The cooling structure according to the present invention has the advantage of being directly carried out in or on the component to be cooled, which allows a gain in terms of compactness and cooling efficiency.

[0082] To adequately bias the junction and cause a current to flow which may to cool the component, it is preferably applied between the element of contact and the semiconductor portion a voltage Vr_opt equal to (A-0.66Aj»T), with N--ë-2- N typically equal to 1 or 2 and corresponding to the number of cooling tunnel junctions electrically coupled in series, A the gap in the density of states of the superconductor, e is the elementary charge, kB the Boltzmann constant and T the temperature.

[0083] The bias voltage range depends on the material used and the temperature. For example, for TiN between 0.1 K and 4 K, the optimal bias is typically in the range 0.5 mV to 4 mV, typically in the order of 0.7 mV at 1 K.

[0084] At a temperature T <TC avec Te la température critique du matériau supraconducteur, la tension optimale Vr_opt de polarisation pour obtenir une puissance de refroidissement optimale est par exemple de l’ordre de 700 pV, pour une jonction tunnel de refroidissement de type NIS dans laquelle S est du TiN et fonctionnant à une température de 1 K. A 1 K, le TiN est particulièrement adapté pour permettre d’avoir le maximum de refroidissement. L’utilisation du TiN, couramment utilisé dans microelectronics is also advantageous because it allows the manufacturing of these cooling junctions integrated with industrial processes.

[0085] For a volume to be cooled of the order of 1.3*103 pm3 (corresponding for example to a semiconductor region of length 1 pm, width of 60 nm and thickness of 20 nm, encompassing the channel, the source and the drain, with a SINIS junction in which S is TiN, with an assumption of resistance of the insulating barrier RT of 1 kQ, a cooling power is estimated at 1 K and at the voltage Vr_opt which can be for example of the order of 35 pW and in any case higher than that of heating of the electrons by phonons and the Joule effect, the Joule effect being in this particular example of the order of 8 pW. Such conditions can be implemented in order for example to cool a component as described in the document “A new FDSOI spin qubit platform with 40nm effective control pitch”, by T. Bédécarrats and al. 2021 IEEE International Electron Devices Meeting (IEDM).

[0086] A cooling current typically between 50 nA and 500 nA can be implemented. For example, when the cooling junction is of NIS type, with the superconducting material S of TiN at 1K, a current of 120nA can be implemented.

[0087] The first contact element 51 and the second contact element 52 extend here in a direction making a non-zero angle with a main plane of the substrate or of the semiconductor layer 12, in particular a direction orthogonal to this main plane. By "main plane" of the substrate or of the semiconductor layer 12 is meant a plane passing through the substrate or the semiconductor layer 12 and which is parallel to the plane [O;x;y] of the orthogonal reference frame [O;x;y;z].

[0088] To enable signals and / or polarization potentials to be applied to them, the first contact element 51 and the second contact element 52 are here connected respectively to a first track 101, typically metallic and preferably superconducting, and a second track 102, typically metallic and preferably superconducting. For example, the tracks 101, 102 may be formed using one or more of the following superconducting materials: TiN, Nb, NbN, NbTiN, TaN. The metal tracks 101 and 102 may belong to a metal interconnection level, for example the first metal interconnection level Mi, i.e. the one provided just above the semiconductor layer and the contacts.

[0089] To enable the establishment of the current between the contact elements 51 and 52, the metal tracks 101, 102 are here set to different potentials and in particular to the voltage Vr_opt.

[0090] Different examples of configurations of the contact element 51 are given in Figures 2 to 5, and 18-19.

[0091] According to a first particular embodiment illustrated in [Fig.2], the first contact element 51 is entirely made of superconducting metallic material 47, for example TiN, or TaN or a Ti / TiN stack which can be deposited by a conformal deposition process such as CVD (“Chemical Vapor Deposition”, i.e. chemical vapor deposition), and is arranged directly in contact on a semiconductor portion 15 which can be doped, for example N-doped. This semiconductor portion 15 is here for example a portion of the source region 13s of the component.

[0092] A Schottky barrier is thus created between the element 51 and the semiconductor portion of the component with which this element 51 is in contact, thus forming a cooling tunnel junction of the NS type for “Normal Superconductor”. The superconducting metallic material 47 is then directly in contact with a doped semiconductor portion 15 which is preferably not silicided or does not include a metal and semiconductor alloy zone as in a conventional transistor contact. The semiconductor portion 15 with which this element 51 is in contact is here preferably heavily doped, i.e. of the order of 1020 cm3 or greater.

[0093] A second example of embodiment of the contact element 51 is given in the [Fig. 3]. The element 51 is this time formed of a main section 48 of superconducting metallic material 47 connected to the track 101 and of a dielectric zone 38, of thickness which can be for example between 2 and 10 nm and which is arranged between one end of the section of superconducting metallic material 47 and the semiconducting portion, preferably doped, of the component with which the element 51 is in contact. The semiconducting portion 15 doped for example of a source region 13s, the dielectric zone 38, and the section of superconducting metallic material 47 here form a cooling tunnel junction of the NIS type (for “Normal Insulating Superconductor”).

[0094] Advantageously, the dielectric zone 38 may be a semiconductor oxide zone, in particular formed by oxidation, native or assisted, of the semiconductor material of the doped semiconductor portion 15, for example a SiO2 zone when the doped semiconductor portion is made of silicon.

[0095] According to an alternative embodiment illustrated in [Fig. 4], the contact element 51 is this time formed of a central part 40 made of superconducting metallic material 47, for example in the form of a rod, one end 40a of which is in contact with the track 101. This central part 40 is surrounded by an envelope 39 made of dielectric material, which extends against the lateral flanks of the central part 40 and here covers another end 40b opposite the end 40a. The dielectric envelope 39 is itself in contact with the doped semiconductor portion (here the source region 13s). Thus, the doped semiconductor portion, the dielectric envelope 39, and the central part 40 of superconducting metallic material 47 form a NIS type cooling tunnel junction. The dielectric envelope 39 may for example be based on SiO2 deposited for example by PECVD (for “Plasma Enhanced CVD”, i.e. “CVD assisted by plasma”) or by PEALD (for “Plasma Enhanced Atomic Layer Deposition”, i.e. Plasma-assisted atomic layer deposition) or a high-k dielectric such as for example Al2O3 or HfO2 deposited by PEALD.

[0096] According to another embodiment, the contact element 51 can be formed from a superposition of several different superconducting metallic materials with, preferably, the superconducting metallic material having the largest superconducting gap being placed in contact with the doped semiconductor portion.

[0097] Thus, in the particular embodiment illustrated in [Fig.5], the element 51 is this time formed of a central part 40, made of superconducting metallic material 47 surrounded by an envelope 48, made of a superconducting metallic material 49 different from the superconducting metallic material 47 and having in particular a larger gap than the superconducting metallic material 47. The envelope 48 is in contact with the doped semiconductor portion (here the source region 13s). The doped semiconductor portion, the envelope 48 and the central part 40 here form an NS type cooling junction. For example, the envelope 48 can be made of TiN, and the central part 40 of Aluminum.

[0098] This embodiment can be combined with one or other of those previously described, in particular in connection with [Fig.3] or with [Fig.4].

[0099] Thus, an element 51 formed from a superposition of two superconducting materials 47, 49 can itself be surrounded by a dielectric envelope 39 as in [Fig. 18] and / or be arranged on a dielectric zone 38 formed from a semiconducting oxide as in [Fig. 19].

[0100] The second contact element 52 through which the current I exits, can advantageously be provided with a structure which can be identical to that of the first element 51 and / or incorporating one or other of the arrangements described previously in connection with FIGS. 2 to 5. Thus, it is possible to provide a SINIS (for Superconductor Normal Insulating Superconductor) type arrangement with two NIS junctions in series. Such an arrangement and a symmetrization of the junctions can make it possible to further increase the cooling power.

[0101] A particular example of the dimensioning of elements of the component Cl of [Fig.l] is given in the table below, in the particular case where the elements 51, 52 have a configuration such as for example in [Fig.2], 3 or 4 and form a junction: Level Dimensioning: Thickness (dimension measured parallel to the z axis) Width (dimension measured parallel to the y axis) Length (dimension measured parallel to the x axis) Track 101 10 to 500 nm 50 nm to 50 pm > 100 nm Element 51, 52 or part 40 of this element 51, 52 50 to 200 nm 30 to 100 nm 30 to 100 nm Dielectric 38 or 39 2 to 10 nm 30 to 100 nm 30 to 100 nm Source / drain region 13s, 13d 10 to 30 nm 40 to 300 nm > 50 nm Channel 12a 10 to 20 nm 30 to 60 nm > 100 nm Grid 22 x 20 to 50 nm > 100 nm 20 to 50 nm

[0102] In the embodiment described previously in connection with [Fig. 1], provision is made to arrange the structure 150 to cool the component Ci on its source region 13s.

[0103] Alternatively, such a structure 150 can be arranged on the second reservoir of charges or dopants, in other words on the drain region 13d of the component Cl.

[0104] It is also possible to arrange such a structure 150 both on the drain region 13d and on the source region 13s.

[0105] Thus, in [Fig.6], the structure 150 for cooling the component Ci, provided with the elements 51, 52 in contact on the source region 13s, is also provided with other contact elements 53, 54 on the drain region 13d. The cooling structure 150 thus comprises a third contact element 53 and a fourth contact element 54, each in contact with the semiconductor drain region 13d. The third contact element 53 and the fourth contact element 54 are here connected respectively to a third metal track 103 and a fourth metal track 104, to allow appropriate bias potentials and / or signals to be applied to them. The third metal track 103 and the fourth metal track 104 may be formed in the same interconnection level as the tracks 101, 102 and are preferably made of superconducting metal material, for example based on the same superconducting metal material as the tracks 101, 102. The third element 53 and the fourth element 54 may have a structure similar to that of the first element 51 and / or taking one or other of the configurations described previously in connection with figures 2 to 5, 18, 19.

[0106] As a variant of one or other of the examples described previously, the cooling structure 150 can be provided this time at the level of one or more control grids of the quantum box(es).

[0107] Thus, in the embodiment illustrated in [Fig.7], a contact element 151 and another contact element 152 are arranged, each in contact with an electrostatic control grid, the contact element(s) 151 each forming with a grid portion 22b, in particular a preferably doped semiconductor portion with which it is (are) in contact, a cooling tunnel junction, in particular of the NIS or NS type.

[0108] The contact elements 151, 152 may have a structure similar to that of the element 51 described previously and / or a configuration according to one or other of the possibilities described previously in connection with FIGS. 2 to 5, 18, 19. The contact elements 151, 152 are here also connected respectively to a metal track 201 and a metal track 202 based on a superconducting material, typically formed in a metal level of interconnections, for example the first level M1 commonly called “metal 1”. In the particular embodiment of [Fig.7], each of the control grids may be cooled. Thus, on a second control grid 222, contact elements 153, 154 are also provided for circulating a current, while on a third control grid 223, contact elements 155, 156 are also arranged for circulating a current for cooling this grid 223.

[0109] Another embodiment provides a cooling structure partially formed on at least one of the source and / or drain regions and partially formed on one or more control gates.

[0110] Thus, in another embodiment illustrated in [Fig.8], the first element 51 and the second element 52 are provided in contact with the source region 13s, the third element 53 and the fourth element 54 in contact with the drain region 13d, and the elements 151, 152, 153, 154, 155, 156 each in contact with a control grid 22b 222, 223.

[0111] In one or other of the examples described above, a cooling structure is provided making it possible to circulate a current in a source region and / or in a drain region and / or in one or more electrostatic control grids of a component Ci intended to accommodate one or more quantum boxes BQ1, BQ2, BQ3.

[0112] Such a cooling structure can also be applied to another part of the component Ci or to another component, this time dedicated to a detection of quantum state(s), for example of the respective state or states of the quantum boxes BQ1, BQ2, BQ3 of the component Ci.

[0113] In the embodiment illustrated in [Fig.9], a cooling structure 950 is provided on another component C2 comprising a so-called “channel” zone 92a, a semiconductor zone arranged between a source semiconductor region 92s and a drain semiconductor region 92d.

[0114] Electrostatic control gates 922b 9222, 9223 are provided opposite semiconductor islands ID1, ID2, ID3 of the channel area 92a, here called detection islands and each provided to detect the quantum state of an associated quantum dot (not shown). The device is here provided with a structure 950 for cooling the component C2 by circulating a current in the channel area 92a, for example from the source semiconductor region 92s to the drain semiconductor region 92d. The structure 950 thus comprises a contact element 951 and a contact element 952, respectively in contact with the source semiconductor region 92s and the drain semiconductor region 92d, the contact elements 951, 952 each forming with semiconductor portions of the source and drain regions at least one cooling tunnel junction, in particular of the NIS or NS type.Since the detection islands ID1, ID2, ID3 of the component C2 are adapted here to read a quantum state rather than to store a quantum state, a current flow through the channel area 92a in order to cool the component C2, does not risk altering or losing the quantum information.

[0115] According to a particular aspect of the cooling structure 950 illustrated here, the elements 951, 952 are here formed of several pads 960 placed in parallel and each in contact with a semiconductor portion of source region 92s or drain region 92d. Each contact pad 960 may have a structure similar to that of a contact element 51 as described previously and / or as illustrated in one of FIGS. 2 to 5, 18, 19.

[0116] The contact pads 960 of the contact element 951 are here connected in parallel to the same metal track 1001, preferably made of metallic superconducting material. Similarly, the contact pads 960 of the contact element 952 may be connected in parallel to the same metal track 1002, preferably made of metallic superconducting material. Such parallelization of the cooling tunnel junctions may improve cooling by reducing the total resistance of the RT junction. The metal tracks 1001, 1002 may be, here again, tracks of the same metallic interconnection level, for example of the first metallic interconnection level noted “metal 1”.

[0117] Such parallelization of the contacts can also be adapted on the source region 13s and / or on the drain region 13d or even on the control grid(s) of the first component Cp

[0118] Another embodiment illustrated in [Fig. 10], differs from that previously described in that the structure 950 for cooling the component C2 further provides a contact element 1051 and another contact element 1052, each in contact with an electrostatic control grid 922b, the contact element(s) 1051, 1052 each forming with a grid portion, in particular a preferably doped semiconductor portion with which it(they) is(are) in contact a cooling tunnel junction, in particular of the NIS or NS type.

[0119] The contact elements 1051, 1052 may have a structure similar to that of the element 51 described previously and / or a composition according to one or other of the possibilities described previously in connection with FIGS. 2 to 5, 18, 19.

[0120] The contact elements 1051, 1052 are also typically connected respectively to metal tracks 1101, 1102 of superconducting metallic material and produced at the same interconnection level as the tracks 1001, 1002.

[0121] A device having a similar arrangement and this time seen in section is illustrated in [Fig. 11], with contact elements 1051, 1053 of distinct grids.

[0122] In this particular embodiment, the source regions 92s, the channel zone 92a and the drain region 92d of the component C2 are here formed in the same semiconductor layer 12.

[0123] An example of a method for producing a quantum device of a type as described previously will now be given in connection with FIGS. 12A-12F.

[0124] A possible starting structure for producing the device is here in the form of a substrate 5 of the semiconductor-on-insulator type, the surface layer 12 of which, with a thickness which may be, for example, between 5 nm and 25 nm, for example of the order of 12 nm, is here intended to accommodate quantum dots. The substrate 5 of the semiconductor-on-insulator type may in particular be a substrate of the SOI type (for “Silicon On Insulator”) with a surface layer 12 of silicon, for example 28Si, in particular when this layer is to accommodate electron spin qubits. The insulating layer 11 and the support layer 10 of the substrate 5 are typically, respectively, a silicon oxide layer commonly called “BOX” (for “Burried Oxide” or “buried oxide”) and a semiconductor layer, for example based on silicon. The thickness of the layer insulating 11 may for example be between 20 nm and 200 nm, for example of the order of 145 nm.

[0125] One or more patterns are then defined in the semiconductor layer 12, including, as in [Fig. 12B], a pattern comprising a channel zone 12a arranged between a semiconductor zone 12s intended to form a source region and another semiconductor zone 12d intended to form a drain region.

[0126] A gate stack covering the surface semiconductor layer 12 is also produced. This gate stack comprises a gate dielectric layer 17, such as for example silicon oxide or a high-k dielectric such as for example Al2O3 or HfO2. The gate dielectric layer may for example be produced with a thickness for example between 2 nm and 20 nm.

[0127] The gate dielectric layer 17 is surmounted by at least one layer 18 of gate material which can be formed for example by CVD (Chemical Vapor Deposition) and with a thickness for example between 20 nm and 50 nm. The gate material layer 18 can be formed from at least one semiconductor material such as for example polysilicon or a stack of metal and semiconductor for example TiN followed by polySi.

[0128] One or more gate electrodes are then defined ([Fig.l2C]) in the gate stack typically by forming a mask in which patterns are produced which are then reproduced in the gate stack, for example by anisotropic etching.

[0129] Such a step may optionally be followed by the production of insulating spacers (not shown), on either side of the grid electrodes, for example by deposition of SiN then etching.

[0130] Then, again optionally, growth of semiconductor material by epitaxy in order to increase the thickness of source and drain regions and form so-called “raised” source and drain regions can be implemented.

[0131] Such a step may be accompanied or followed by a step of doping the source and drain regions. Such doping may be carried out, for example, by implantation and / or in situ during epitaxial growth.

[0132] Other insulating spacers can then be produced. In the case where the junctions of the device are silicided, these additional spacers make it possible to control the position of the siliciding front relative to the doped regions.

[0133] The whole thing can then be covered with an insulating thickness 25 ([Fig. 12D]). This insulating thickness 25 can be formed from an insulating layer of the CESL type (“contact etch stop layer”) for example made of silicon nitride and a layer of the PMD type (“pre-metal dielectric”).

[0134] We can then proceed to produce the cooling structure.

[0135] To form the contact element(s) of the cooling structure, one or more holes are then made in the insulating thickness 25. Such an embodiment typically comprises photolithography and etching steps. In the particular embodiment illustrated in [Fig. 12E], a hole 27a is made opposite an area intended to electrically contact a source region and a hole 27b is made opposite an area intended to electrically contact a drain region.

[0136] In a particular case as described previously in connection with FIGS. 3 and 4, where it is desired to produce contact elements forming a cooling junction of the NIS type, a dielectric zone 38 is formed at the bottom of the holes 27a, 27b, for example by oxidation of the semiconductor material located at the bottom of the holes 27a, 27b and / or by deposition of dielectric material. Deposition by PECVD (“Plasma Enhanced Chemical Vapor Deposition”) or PEALD (“Plasma Enhanced Atomic Layer Deposition”) may in particular be implemented.

[0137] In the particular example illustrated in [Fig. 12F], the zone of dielectric material 38 extends only to the bottom of the holes. However, this dielectric zone may, as a variant, in particular in the case of production by deposition, be arranged in a conformal layer covering the bottom as well as the vertical walls of the holes 27a, 27b.

[0138] These holes 27a, 27b are then filled using a superconducting metallic material 47 ([Fig.l2G]), for example TiN or TaN or a stack of Ti / TiN or TaN / Ta. Such filling can be carried out by CVD and typically followed by a planarization step by CMP (Chemical mechanical polishing) in order to remove metallic material protruding from the mouth of the holes 27a, 27b.

[0139] [Fig. 13] illustrates an advantageous case where additional contact elements are provided on the gates 22. The production of these elements can then be similar to that which has just been given for forming contact elements on the source and drain regions. Thus, one or more other holes are made in the insulating thickness 25 facing the gate electrode(s) respectively. A dielectric zone 38 is formed at the bottom of these other holes. Then, these other holes are filled with a superconducting metallic material 47. Such filling can be followed by a CMP planarization step in order to remove the metallic material protruding from the mouth of the holes.

[0140] It is then possible to form, as in [Fig. 14], one or more metal tracks 101, 103, 202, on the contact element(s) 51, 53, 151 produced, for example by deposition and etching of a superconducting metal material which can be chosen from one or more of the following materials: TiN, Nb, NbN, NbTiN, TaN.

[0141] A structure 1500 for cooling both components Cio of a co-integrated semiconductor qubit circuit and components C2o of an electronic circuit dedicated to controlling and / or reading the qubits, for example in the form of transistors, in particular cryoCMOS type transistors, is illustrated in [Fig. 15] with contact elements 951, 952 forming at least one cooling tunnel junction, in particular of the NIS or NS type and arranged respectively on semiconductor portions of the components Ci0, C20.

[0142] Such a structure 1500 adapts to different types of arrangements of the components Cio, C2o and the circuits to which they belong, in particular both to an arrangement, for example, as in [Fig. 16A] where the control components C20 of a circuit 1620 dedicated to reading and / or controlling the qubits are distributed on the periphery of a quantum component arranged in a matrix circuit 1610 with qubits, and to a distribution, for example in [Fig. 16B] with several matrix circuits 1610A, 1610B, 1610C with qubits between which circuits 1620A, 1620B, 1620C dedicated to reading and / or controlling the qubits are arranged.

[0143] A structure as described above for cooling a quantum device can be co-integrated with several other means or elements making it possible to promote this cooling or to limit heating.

[0144] Thus, for example, one or more structured cavities in a substrate on which the quantum device is produced may be provided. The implementation of such cavities is provided for in the patent application filed with the INPI by the applicant and having the filing number: FR2310911

[0145] Similarly, at least one cavity around interconnecting metal levels can be implemented in order to better dissipate heat.

[0146] In the embodiment illustrated in [Fig. 17], a cavity 172 is provided in particular in the support layer 10 of a substrate opposite components Cio of the qubit circuit. Similarly, in the support layer 10 of this substrate, another cavity 174 is provided opposite the control components based on cryoCMOS C20 type transistors of the electronic circuit dedicated to the control and / or reading of the qubits. Such cavities 172, 174, typically produced by localized etching of the substrate, make it possible to limit thermal leaks through the latter.

[0147] In this exemplary embodiment, another type of cavity 171 is made this time in at least one insulating layer 127 encapsulating one or more metal lines. interconnection. Such a cavity 171 may in particular be produced around at least one metal line 130 for connection between components CiO of the qubit circuit and components C2o of the electronic circuit dedicated to controlling and / or reading the qubits. The cavity 171 forms an empty or air-filled space ("airgap" according to English terminology) around the metal interconnection line and surrounded by said insulating layer 127. This type of cavity makes it possible to limit thermal leaks through the dielectric present between the interconnection levels. Combined with the use of superconducting material for the metal interconnection line 130, it makes it possible to ensure optimized thermal insulation between the components Cio and C20. It can be implemented in particular by producing openings 129 or trenches 129 through the insulating layer 127 and by etching insulating material exposed by the bottom of these openings or trenches 129.

[0148] A cooling structure as described above can also be integrated into a device as described in applications EP3971983 A1, and EP3971982A1 from the applicant and in which mixed routing is provided with both routing and / or interconnection lines or tracks made of conductive material and lines or tracks made of superconductive material on different metal levels of interconnections of level(s) known as BEOL (for "back end of line").

[0149] For example, such mixed routing comprises horizontal metal connection lines between qubits and cryoCMOS transistors provided in superconducting metal material, while vertical connection elements or vias are in conventional metal material. Such mixed routing may also comprise, for example, connection lines between qubit or cryoCMOS components in superconducting metal material on the one hand and connection lines to an external reading circuit on the other hand in conventional metal material such as, for example, Cu or W.

Claims

Claims

1. Quantum electronic device, in particular with spin qubits, comprising a substrate and a component (Ci, C2, Cio) arranged on the substrate, the component comprising at least one so-called “channel” zone (12a, 92a) formed in at least one semiconductor layer (12) and comprising one or more islands, each island being controlled by means of an electrostatic control gate and forming a quantum dot or a detection island for reading the quantum state of a quantum dot, the device further comprising: a structure (150, 950) provided for cooling said component (Cb C2, Ci 0) by circulating a given current between a first element (51, 151, 951) for contact with the component and a second element (52, 152, 952) for contact with the component, the first contact element (51, 151, 951) comprising at least one superconducting metallic material (47) given,and being in contact by a first end with a first semiconductor portion (15, 13s, 221 92s, 12s) of said component (Ci, C2, Ci0C20) so as to form with the first semiconductor portion at least one tunnel junction, in particular of the NS (for “Normal” “Superconductor”) or NIS (for “Normal” “Insulator” “Superconductor”) type.,

2. Device according to claim 1, the first contact element (51, 151, 951) being, from the first end to a second end, formed of said given superconducting metallic material (47).

3. Device according to claim 1, the first contact element (51, 151, 951) comprising at the first end a stack of a dielectric zone (38, 39) in contact with the first semiconductor portion and a section (40, 48) based on said given superconducting metallic material (47).

4. A device according to claim 3, wherein the dielectric region (38) is an oxidized region of the semiconductor material of the first semiconductor portion.

5. Device according to any one of the preceding claims, the first contact element (51, 151, 951) comprising at the first end a stack of the given superconducting material in contact with the first semiconductor portion and a second superconducting material (48) having a higher band gap than the given superconducting material (47).

6. Device according to one of the preceding claims, the given superconducting metallic material (47) having a critical temperature Te greater than 2K, advantageously greater than 4K, such as TiN.

7. Device according to one of the preceding claims, in which the channel zone (12a, 92a) extends in a first direction parallel or substantially parallel to a main plane of the substrate and in which the first element extends in a direction orthogonal or substantially orthogonal to the first direction, the first contact element (51, 151, 951) being connected by a second end to a metal track (101, 201, 1001) of superconducting metallic material parallel or substantially parallel to the main plane of the substrate.

8. Device according to claim 7, in which the first contact element (951) is formed from a set of contact pads (960) connected in parallel to the metal track (1001).

9. Device according to one of the preceding claims, the second contact element (52, 152, 952) comprising at least one superconducting metallic material and being in contact with a second semiconductor portion of said component (Ci, C2, CiO, C2o) so as to form with the second semiconductor portion at least one second NS or NIS tunnel junction.

10. Device according to one of the preceding claims, the second contact element (52, 152, 952) being in contact with a second semiconductor portion of said component (Ci, C2, Cio) and in which the channel zone extends between a semiconductor region called "source" and a second semiconductor region called "drain", the first semiconductor portion and the second semiconductor portion each being portions of said source region (13s) or of said drain region (13d).

11. Device according to claim 10, wherein the structure (150) for cooling the component further comprises a third contact element (151) in contact with a third semiconductor portion of the component and a fourth contact element (152) with a fourth semiconductor portion of said component, the third contact element forming a junction tunnel, in particular of the NIS or NS type with the third semiconductor portion of the component, the third semiconductor portion and the fourth semiconductor portion each being portions of an electrostatic control grid (220 of said component.

12. Device according to one of claims 1 to 8, the second contact element (52, 152, 952) being in contact with a second semiconductor portion of said component (Ci, C2, Cio, C2o) in which the first semiconductor portion and the second semiconductor portion are each portions of an electrostatic control grid (22J).

13. Device according to one of claims 1 to 8, wherein the second contact element (952) is in contact with a second semiconductor portion of said component (C2) in which the “channel” zone (92a) comprises one or more detection islands for reading the quantum state of one or more quantum dots of another part of the component or of another component (Ci) and in which the channel zone extends between a first semiconductor region called the source region and a second semiconductor region called the “drain” region, the first portion and the second portion being: respectively a portion of the source region and a portion of the drain region.

14. Device according to one of claims 1 to 13, in which the substrate comprises a cavity (172) arranged opposite said component.

15. Quantum electronic device according to one of the preceding claims, wherein each island being of the component (Cb C2, Cio ) forms a quantum dot, the device further comprising: another component (C2 0) for reading the quantum state of said component (Ci, C2, Cio), the device further comprising a structure (1500) provided for cooling said other component (C20) by circulating a given current between a contact element (1052) with said other component (C20) and another contact element with said other component (C20), said contact elements (1052, 1500) forming at least one tunnel junction, in particular of the NIS or NS type, with a semiconductor portion of said other component (C20).

16. Device according to claim 15, wherein said component (Cio) and said other component (C20) are connected by a line

17. metallic interconnection line (130) of a metallic level of interconnections arranged in at least one insulating layer (127), the metallic interconnection line being surrounded by a cavity (171) forming an empty space around the metallic interconnection line and surrounded by said insulating layer (127). Method of manufacturing a device according to one of the claims 1 to 16, comprising steps consisting of: - providing the substrate (5) and said component formed on the substrate (5), - in at least one insulating layer (25) covering the component, making at least one first hole (27a) and at least one second hole respectively revealing the first semiconductor portion and the second semiconductor portion of said component, - forming the first contact element (51) in the first hole and the second contact element in the second hole, by depositing at least said given superconducting metallic material (47) in the first hole and in the second hole.

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