WORD LINE DRIVER STAGE ARRANGEMENT FOR SEMICONDUCTOR MEMORY DEVICES

Abstract

An arrangement of a word line driver stage for a semiconductor memory device is illustrated. The present invention is characterized in that the word line driver stages are divided into a plurality of substages WD11-WD51 within an array of memory cells, a word line extending from either of the substages is uncoupled to the substage adjacent thereto, and the other word line proximate to the first word line is coupled to the other substage. Consequently, this arrangement is capable of reducing signal transmission delay and eliminating detrimental factors in current critical design standards and geometries.