Analogue to digital converter for image sensor readout

Abstract

To provide an analog to digital converter that reduces a noise without significantly decreasing a speed or accuracy of an image sensor.SOLUTION: An analog to digital converter 800 comprises: an analog storage 806 that stores a reset pixel value output with a first gain by a dual conversion gain pixel; a circuitry 804 that outputs a reset pixel value output with a second gain and a signal pixel value output with the second gain by the dual conversion gain pixel as a first input and a second input to a converter stage 808, and also outputs the reset pixel value with the first gain stored in the analog storage 806 and a signal pixel value output with the first gain as a first input and a second input; and the converter stage 808 that outputs digital values indicating a difference between the reset pixel value with the second gain and the signal pixel value with the second gain and a difference between the reset pixel value with the first gain and the signal pixel value with the first gain that are input as the first inputs and the second inputs.SELECTED DRAWING: Figure 8

Description

[Technical Field]

[0001] This disclosure relates in general to analog-to-digital converters. In particular, this disclosure relates to analog-to-digital converters for converting the analog output of pixels of an image sensor. [Background technology]

[0002] Analog-to-digital converters (ADCs) form a fundamental part of the electronic circuitry in many electronic devices. In particular, image sensors rely on ADCs to convert analog signals output by the image sensor's pixels into digital signals, generating a digitized version of the perceived image. Several applications, such as microscopy, astronomy, and spectroscopy, require low-noise, high-dynamic-range image sensors; therefore, the ADC within the image sensor must also be low-noise and have a high dynamic range.

[0003] An image sensor typically comprises a pixel matrix and a readout element. Figure 1 provides a schematic diagram of an image sensor 100 comprising a controller 102, a pixel matrix 108, and a readout element 110. As shown in Figure 1, the pixel matrix 108 is an array of pixels 104 arranged in rows and columns. The controller 102 can sequentially enable each row or column of pixels 104, and the enabled pixels 104 are read out. In the image sensor 100 of Figure 1, the controller 102 is connected to each row of pixels 104, so that each row of pixels 104 can be sequentially enabled. In the image sensor 100 of Figure 1, each column of pixels 104 is connected to a readout element 110 equipped with an ADC 106. When the controller 102 enables a specific row of pixels 104, each pixel 104 in each column transmits an analog measurement signal based on the photons incident on the pixel to the ADC 106, which receives the analog signal from each pixel 104 and converts it into a digital signal. In one example, the output of each pixel 104 may be stored by the readout element 110 and sequentially input to the ADC 106. The controller 102 sequentially enables each row to effectively scan the pixel matrix 108, so that the readout element 110 acquires a digital signal for each pixel 104 and provides a signal representing the photons incident on the pixel matrix 108, i.e., a signal representing the perceived image.

[0004] To increase the sensitivity of the readout element 110 and reduce noise contribution from the pixel, two samples can be acquired from the pixel. The first sample is acquired when the pixel is in a reset state and is therefore not based on photons incident on the pixel's photodiode. The second sample is acquired when the charge collected by the pixel's photodiode from the incident photons has been transferred to the readout node. The first sample is a reference sample and is subtracted from the second sample as a measurement sample to remove noise generated by the pixel. This is known as correlated double sampling (CDS). One way to subtract the first sample from the second sample is to use the first and second samples as difference signals.

[0005] Figure 2 shows an example of a pixel architecture supporting CDS. Pixel 200 includes a photodiode 204 that detects photons incident on the pixel. Pixel 200 further includes four transistors with control signals labeled as a transfer gate (TX) 208, a reset (RST) 206, and a row selector (SEL) 210, and a transistor labeled as a source follower (SF) 202. The transfer gate 208 controls the photodiode readout to enable CDS readout. When the transfer gate 208 is off, the photodiode does not contribute to the output signal, allowing noise from the rest of the circuit to be output from the pixel. This output is referred to throughout the specification as the signal pixel value and provides a pixel measurement. The reset pixel value can be removed from the signal pixel value to reduce the noise contribution from the pixel. The noise contribution from the pixel includes thermal noise and low-frequency noise, which vary from pixel to pixel, and these variations, along with other noise sources within the pixel, need to be detected and isolated from the signal to reduce distortion of the photodiode signal.

[0006] To read the reset pixel value and signal pixel value from the pixels, the readout element 110 may also include, in front of the ADC 106, a correlated double sampling (CDS) amplifier that calculates the difference pixel signal and amplifies it to the required level, and an output buffer that takes the analog signal from the pixel matrix 108, which is then adjusted and digitized.

[0007] Figure 1 shows a single readout element 110, but the time required for the ADC 106 and optionally the CDS amplifier to convert each pixel output will result in a large delay between detection and output, and an extremely slow device. Thus, as the speed requirements of the image sensor increase, the number of readout elements 110 can be increased accordingly. Theoretically, the achievable frame rate of the image sensor increases linearly with the number of readout elements 110 operating in parallel.

[0008] As a result of increased speed requirements, the image sensor is equipped with a readout element 110 for each column of pixels (known as column-level readout parallel processing), so that each readout element 110 processes the signals arriving from a single column of pixels. Column-level readout parallel processing can improve speed or accuracy. In high-speed applications, speed can be increased by increasing the overall bandwidth. Alternatively, the increased parallel processing, accompanied by the relaxation of the individual ADC bandwidth, can improve the accuracy of each unit element for high-resolution applications.

[0009] The ability to trade precision for speed is inherent in all ADC topologies, including single-ramp ADCs and integrated ADC topologies, which are often used in image sensors with column-level readout parallel processing, due to the small amount of circuitry per column, and thus compatible with extremely low pixel pitches. In these ADCs, the number of clock cycles required to digitize with B-bit resolution is proportional to 2^B. For example, with 10-bit resolution, 1024 clock cycles are required to acquire a single digitized data, but 4096 clock cycles are required to encode 12 bits, demonstrating a theoretical precision-speed trade-off, where eliminating one or more bits doubles the conversion time. Thus, achieving high-speed and high-precision analog-to-digital conversion is difficult.

[0010] To achieve high-speed and high-precision ADCs, it is sometimes desirable to reduce noise generated by pixels or readout elements. If the ADC incorporates a switched-capacitor (SC) circuit, sampling noise can be reduced by increasing the value of the sampling capacitor. However, since the root mean square (RMS) value of sampling noise is measured by the square root of the capacitance, larger capacitors are required to accommodate scaling up the ADC resolution. This results in inefficient column implementations, particularly for very low pixel pitches, in terms of both power consumption and area occupancy.

[0011] To address this problem, oversampling ADCs can be used. In this case, oversampling is used to reduce the equivalent sampling noise for a given capacitance. Furthermore, noise feedback techniques can be applied to reduce the quantization noise of low-resolution quantizers. An example of an oversampling ADC using noise feedback techniques is the first-order sigma-delta ADC, shown in the schematic diagram of Figure 3, which uses a comparator as a single-bit quantizer. The Sigma-Delta ADC300 is described in more detail below. The Sigma-Delta ADC300 requires few components and is extremely efficient in terms of analog content. This is because it requires only one additional integrator compared to a single-ramp ADC that includes a comparator. Furthermore, due to sigma-delta modulation, its operation is robust even in the presence of circuit non-idealisms and interference, and its effects are attenuated by the number of times the input signal is sampled to obtain one transformation, which is known as the oversampling ratio (OSR). In the case of oversampling, the sampling noise is equal to KT / (OSR·Cs), where Cs is the value of the sampling capacitor, K is Boltzmann's constant, and T is the temperature. This shows that OSR and capacitance are interchangeable in terms of noise reduction.

[0012] While the ADC300 reduces sampling noise through the use of high OSR, for such noise reduction to improve the speed and / or accuracy of the readout element 110, noise sources before the ADC must also be minimized, which is not always achieved. For example, as mentioned above, the noise contribution from the CDS amplifier can mask the advantages of the ADC300's sigma-delta topology.

[0013] Thus, to further reduce noise before the ADC, the CDS amplifier within the readout element 110 can be removed, and instead, the CDS can be performed internally by the ADC by performing two transformations for each pixel: one transformation for the reset pixel value and one transformation for the signal pixel value. The output of the ADC can then be digitally subtracted to obtain the difference between signals. Combined with the sigma-delta method of oversampling, this type of digital CDS offers two distinct advantages. First, the sampling noise is determined not by the sampling capacitance itself, but by the product of OSR·Cs. Second, the noise source before the ADC is also oversampled, with subsequent attenuation due to OSR.

[0014] The drawbacks of CDS operation are that the conversion noise is doubled in power, the ADC needs to perform the conversion twice for each pixel, doubling the conversion time, increasing power consumption, and requiring digital data storage and subtraction.

[0015] An object of the embodiments of the present invention is to mitigate at least one or more of the problems of the prior art. [Overview of the Initiative] [Means for solving the problem]

[0016] The inventors have achieved a remarkable feat: to reduce noise without significantly reducing the speed or accuracy of the image sensor, the CDS amplifier can be removed from the readout circuit. The inventors have devised an ADC with an embedded analog CDS that does not require a prior CDS amplifier. The ADC also reduces the space required for each readout element 110.

[0017] However, as will be explained in more detail below, in order to cover a high dynamic range, pixels capable of operating in two different modes, namely low-gain mode and high-gain mode, have been developed. These pixels are known as dual conversion gain (DCG) pixels and output signals in a specific sequence. Therefore, we have devised an analog-to-digital converter with a built-in analog CDS that can sequentially sample signals at low and high gain, thereby providing a high dynamic range, by operating with dual conversion gain pixels.

[0018] Thus, according to one aspect of the present invention, an analog-to-digital converter is provided for converting the analog output of a doubly transforming gain pixel of an image sensor. The doubly transforming gain pixel is operable to sequentially output a reset pixel value and a signal pixel value with both a first gain and a second gain different from the first gain. The analog-to-digital converter includes analog storage for storing the reset pixel value output with the first gain. The analog-to-digital converter further includes a converter stage configured to sequentially sample a first analog input indicating the reset pixel value of the doubly transforming gain pixel and a second analog input indicating the signal pixel value of the doubly transforming gain pixel. The converter stage is configured to sequentially sample the first and second inputs and output a digital value indicating the difference between the first and second inputs. The analog-to-digital converter further provides a reset pixel value output at a second gain as a first input to the converter stage, and a signal pixel value output at a second gain as a second input to the converter stage. The converter stage includes a circuit configured to sequentially sample the first and second inputs and output a first digital value indicating the difference between the reset pixel value output at a second gain and the signal pixel value output at a second gain. This circuit is further configured to provide a reset pixel value output at a first gain and stored in analog storage as a first input to the converter stage, and to provide a signal pixel value output at a first gain as a second input to the converter stage. The converter stage is configured to sample the first and second inputs and output a difference signal indicating the difference between the reset pixel value output at a first gain and the signal pixel value output at a first gain.

[0019] The ADC described above incorporates CDS operation by a converter stage configured to sequentially sample reset pixel values ​​and signal pixel values ​​and output a digital value indicating the difference between the reset pixel value and the signal pixel value, and by a circuit that provides these inputs to the converter. As will be described in more detail below, the ADC operates with DCG pixels. This is because it allows the first gain reset pixel value to be stored in analog storage, and CDS can be performed separately for low-gain and high-gain signals. Thus, the ADC described above can perform oversampling (for at least the second gain), operate with DCG pixels, and incorporate CDS operation and direct conversion without requiring a CDS amplifier or sample-and-hold block. The combination of functions in the ADC provides a low-noise, high-dynamic-range, and high-precision ADC without compromising speed.

[0020] In high-gain operation, the converter stage can sequentially sample the reset pixel value and the signal pixel value and output a digital value indicating the difference between the reset pixel value and the signal pixel value. This sampling may be performed over a number of clock cycles, and these values may be oversampled. However, in low-gain operation, the converter stage may simultaneously sample the reset pixel value and the signal pixel value from storage and output a differential signal, for example, to a second converter stage. Thus, in low-gain operation, the converter stage can operate in a manner similar to a CDS amplifier. Oversampling is advantageous for high-gain signals due to their high noise contribution, but the noise contribution of low-gain signals is generally lower than shot noise and lower than the noise contribution of high-gain signals, so the benefit of oversampling low-gain signals is reduced. Further, due to the storage of the first gain reset pixel value, this value can only be sampled once. Therefore, to speed up the operation of the ADC and to effectively utilize storage, low-gain signals may not need to be oversampled, but can be sampled only once and output a differential signal instead of a digital signal. The combined use of converter stages for high-gain conversion and low-gain conversion reduces the size of the ADC and the power consumption of the ADC.

[0021] The ADC does not require a sample-and-hold block and incorporates a correlated double sampling (CDS) operation, enabling multiple samplings of pixels in the analog domain without the need to store samples in either the analog or digital domain. Furthermore, the removal of another CDS amplifier and the sample-and-hold block not only reduces the area and speed of the image sensor but also reduces the noise generated before the ADC. The CDS amplifier does not allow oversampling to be applied to the pixels, but the integrated CDS allows analog multi-sampling of the pixel signals, which also reduces pixel noise. The ADC is based on a sigma-delta topology and allows oversampling that reduces the noise power by a factor of the oversampling ratio (OSR). Furthermore, by combining direct conversion and the sigma-delta approach, the ADC can average the noise arriving from the pixels.

[0022] The ADC can operate using DCG pixels, perform the conversion of pixel signals with both a first gain and a second gain, optimize the trade-off between noise and resolution and power consumption and area, and provide a high dynamic range. In particular, the dual conversion gain function enables the present invention to extend the dynamic range.

[0023] An analog-to-digital converter for converting the analog output of the dual conversion gain pixels of an image sensor can convert the difference between a received first analog input and a second analog input into a digital value.

[0024] A dual-converter gain pixel can be operated to sequentially output the reset pixel value and the signal pixel value in both the first gain and a second gain distinct from the first gain. This can be understood as meaning that the dual-converter gain pixel can operate to sequentially output the reset pixel value in both the first and second gains, and then sequentially output the signal pixel value in both the second and first gains. The converter stage can be configured to sequentially receive the reset pixel value and the signal pixel value, perform an internal CDS, and find the difference between the signal pixel value and the reset pixel value. However, as mentioned above, the dual-converter gain pixel does not have to sequentially output the reset pixel value and the signal pixel value in the first gain; these values ​​can be separated by the second gain value (i.e., the reset and signal values ​​output in the second gain). Therefore, the circuit can be configured to store the reset pixel value output in the first gain in analog storage, and as a result, the converter stage can be configured to sequentially receive the reset pixel value and the signal pixel value in the second gain, and to receive the reset pixel value in the first gain from storage before or during the reception of the signal pixel value in the first gain from the pixel. Therefore, the converter stage can sequentially receive the reset pixel value and signal pixel value for each gain, which allows the internal CDS to run for both the first and second gains using the same ADC.

[0025] This circuit can further be configured to operate a dual-conversion gain pixel to sequentially output the reset pixel value and the signal pixel value using both the first gain and a second gain distinct from the first gain.

[0026] Analog storage can also be capacitors.

[0027] The ADC can also be a column-specific ADC.

[0028] This circuit may include switches that are controlled to be open or closed in order to sequentially provide the values ​​output from the pixels as inputs to the converter stage, and / or to control the operation of the converter stage. This circuit may further include a controller that controls whether the switches are open or closed.

[0029] The second gain may be greater than the first gain. The first gain can be understood as a low gain, and the second gain as a high gain, as will be explained below. The terms first gain and low gain may be used interchangeably throughout this specification. The terms second gain and high gain may be used interchangeably throughout this specification.

[0030] When the second gain is high gain and the first gain is low gain, as will be further explained below, if there are fewer electrons in the photodiode, the digital value converted from the high-gain signal is a more useful signal, and if there are more electrons in the photodiode, the digital value converted from the low-gain signal is the most useful signal. The converter enables the output of both digital values ​​and operates the pixel with the first and second gains to sense a wide range of electrons in the photodiode, providing the image sensor with a high dynamic range.

[0031] The converter stage may include an integrator for integrating the voltage difference between the analog input sampled by the converter stage and the feedback signal. The converter stage may further include a comparator for comparing the integrated voltage difference with a reference voltage. The feedback signal may depend on the output of the comparator.

[0032] The integrator can also be a switched-capacitor integrator.

[0033] The converter stage may further include a digital-to-analog converter that converts the comparator output into an analog signal. The feedback signal may also be an analog signal.

[0034] The converter stage may be based on or incorporate a sigma-delta ADC. The use of a sigma-delta ADC or a sigma-delta architecture ADC reduces the noise contribution of the ADC and averages out the noise originating from the pixels. The sigma-delta ADC may also be an incremental sigma-delta ADC. The sigma-delta ADC may be a first-order or second-order ADC. A first-order incremental ADC is advantageous for minimizing circuit configuration.

[0035] The digital value may be based on the output of the comparator.

[0036] The polarity of the feedback signal may depend on whether the analog input received by the converter stage is the first or second input, and the digital value output by the converter stage may represent the difference between the first and second inputs.

[0037] If the analog input is the first input, the feedback signal can be positive; if the analog input is the second input, the feedback signal can be negative. The size of the feedback signal may also depend on whether the analog input received by the converter stage is the first or second input. If the analog input is the first input and the comparator output is high (logic 1), the feedback signal can be set to the second reference voltage. If the analog input is the first input and the comparator output is low (logic 0), the feedback signal may be grounded. If the analog input is the second input and the comparator output is high (logic 1), the feedback signal may be grounded. If the analog input is the second input and the comparator output is low (logic 0), the feedback signal can be set to a negative second reference voltage.

[0038] This circuit can be configured to output a feedback signal configured as described above, for example, to control the digital-to-analog converter based on the analog input. Additionally or alternatively, the converter stage may include circuitry to control the digital-to-analog converter based on the analog input.

[0039] This circuit can be configured to provide a reset pixel value output with a second gain as a first input to the converter stage over multiple clock cycles of the converter stage, so that the converter stage samples the first input multiple times and provides multiple outputs to the comparator for the first input. This circuit can further be configured to provide a signal pixel value output with a second gain as a second input to the converter stage over multiple clock cycles of the converter stage, so that the converter stage samples the second input multiple times and provides multiple outputs to the comparator for the second input.

[0040] Each clock cycle may involve repetitions. During repetitions, the components of the converter stage may perform their intended operation. The conversion may involve any number of repetitions and can be performed using any number of clock cycles. By providing the first and second inputs to the converter stage over multiple clock cycles, the inputs are effectively oversampled. Oversampling reduces the noise contribution of the ADC. Furthermore, the more clock cycles used to obtain the conversion, the more accurate the analog-to-digital conversion becomes.

[0041] This circuit can be configured to output a reset pixel value with a first gain, which is stored in analog storage as the first input to the converter stage, and to output a signal pixel value with the first gain, which is provided as the second input to the converter stage over one clock cycle of the converter stage. As a result, the converter stage samples the first and second inputs once to provide the difference signal to the integrator.

[0042] The analog-to-digital converter is optimized to match DCG pixels and performs conversion of pixel signals at both low and high gain. In particular, the dual-gain conversion feature allows the present invention to extend the dynamic range. However, the need to convert at both low and high gain increases the time required for each conversion, reducing the speed of the ADC. Therefore, when the first gain is low gain, the ADC uses only one clock cycle to reduce the time it takes to process the input for the low gain, meaning that the components of the converter stage operate, propagating the input signal once through the converter stage without feedback of the signal. Thus, the signal pixel value and reset pixel value propagate through the integrator in one clock cycle, and the resulting difference signal is output from the integrator. This low-gain conversion is inaccurate, and since the input is not oversampled, noise is not reduced by oversampling. However, due to the high intrinsic noise associated with the photon signal, known as shot noise, high-precision conversion may not be required at low gain. Thus, by converting the first gain component in only one clock cycle, the conversion time is reduced, increasing the ADC speed without compromising the accuracy of these conversions.

[0043] Each output in the comparator may include a digital signal, and the digital value is based on the digital signal.

[0044] Digital signals may be stored in digital storage such as a counter. Digital values ​​may also be the accumulation of digital signals. Alternatively, digital values ​​may be based on the number of ones in the accumulation of digital signals. Alternatively, digital values ​​may be based on the percentage of ones in the accumulation of digital signals.

[0045] The converter may further include a second converter stage. This circuit can be further configured to provide a difference signal to the second converter stage. The second converter stage can sample the difference signal and output a first-gain digital value indicating the difference between a reset pixel value output with the first gain and a signal pixel value output with the first gain. The difference signal may be output by an integrator in the converter stage.

[0046] The second converter stage can be configured to output a first gain digital value based on a comparison between the difference signal and a variable reference voltage.

[0047] The use of a second converter stage allows for the conversion of differential signals into digital signals, thereby eliminating the dependence on the first converter stage for converting first-gain signals into digital signals, and enabling increased speed and efficient use of storage in the first converter stage. As will be explained in more detail below, the second converter stage can operate in parallel with the first converter stage, so that while the first converter stage is converting the next pixel, the second converter stage can finish converting the previous pixel. Thus, the combination of the first and second converter stages provides a low-noise, high-dynamic-range, and high-precision ADC without compromising speed.

[0048] This circuit can be further configured to sequentially provide the reset pixel value output with a second gain as the first input to the converter stage, and the signal pixel value output with a second gain as the second input to the converter stage, and then provide the analog residue to the second converter stage. The second converter stage can be configured to sample the analog residue and output a second digital value representing the analog residue.

[0049] The analog residue may also be the signal accumulated by the integrator of the converter stage when the converter stage has finished converting the reset pixel value and the signal pixel value to the first digital value of the second gain. The analog residue may also be output by the integrator of the converter stage.

[0050] The use of a second converter stage allows the remainder to be converted without requiring further iterations of the converter stage, thereby increasing the accuracy of the ADC without reducing speed.

[0051] The two converter stages provide a pipelined architecture, so that after the analog residual or difference signal is sampled by the second converter stage, while the second converter stage is converting the analog residual or difference signal, the first converter stage can simultaneously sample the next input from the double-converted gain pixel. This reduces the time required to convert all pixel outputs without reducing accuracy. This overcomes the speed limitations of a pure integral sigma-delta ADC, and the conversion time increases with the number of integrations. Furthermore, sample-and-hold is not required to continue the conversion, and the first-stage ADC can perform pixel noise reduction when oversampling is performed. Thus, the use of a pipelined architecture allows the first and second converter stages to operate in parallel, so that the ADC can maintain its high speed despite being optimized for low noise and high dynamic range.

[0052] The second converter stage can be configured to output a second digital value based on a comparison between the sampled analog residue and a variable reference voltage.

[0053] The second converter stage may include a single-ramp ADC. Using such an ADC as the second stage is advantageous because it involves a small amount of circuitry. This makes it possible to use multiple ADCs within the image sensor without a significant increase in sensor size or circuitry.

[0054] The variable reference voltage may increase over time. The second converter stage may further include a comparator that compares the sampled analog residual or difference signal with the variable reference voltage and a counter, the digital value being based on the counter value as the comparator output changes.

[0055] The converter stage and the second converter stage can form a pipeline architecture for each gain, so that the first gain output is converted by the converter stage while the second gain output is converted by the second converter stage. More specifically, after the converter stage converts the reset pixel value and signal pixel value of the second gain, the converter stage converts the reset pixel value and signal pixel value of the first gain, and the remainder of this conversion may be converted by the second converter stage. Then, after the converter stage converts the reset pixel value and signal pixel value of the first gain, the converter stage converts the next pixel input of the second gain, and the difference signal from this conversion may be converted by the second converter stage.

[0056] The analog-to-digital converter can be configured to determine a second gain digital value that represents the difference between the reset pixel value output with the second gain and the signal pixel value output with the second gain. The second gain digital value may depend on the first and second digital values.

[0057] A second gain digital value can be formed by combining a first digital value and a second digital value. For example, a second gain digital value can be formed by concatenating the first digital value and the second digital value. The first digital value can provide the most significant bit of the second gain digital value, and the second digital value can provide the least significant bit of the second gain digital value. The second gain digital value may include outputs from both the converter stage and the second converter stage, but the first gain digital value may include only the output from the second converter stage. Thus, the second gain digital value may contain more bits than the first gain digital value. In this way, the second gain digital value can have a wider range or higher sensitivity than the first gain digital value.

[0058] This circuit can be further configured to select one of the first and second gain digital values ​​and output it from the converter. If the second gain is greater than the first gain, the second gain digital value is a more useful signal if there are few electrons in the photodiode, and the first gain digital value is the most useful signal if there are many electrons in the photodiode. Therefore, this circuit can be configured to select the most useful digital value of the first and second gain digital values ​​based on the above.

[0059] According to another aspect of the present invention, an image sensor is provided comprising an array of double-conversion gain pixels and at least one analog-to-digital converter as described herein.

[0060] An image sensor may be equipped with an analog-to-digital converter for each column of the pixel array. This allows for simultaneous conversion of each pixel within a row, providing an image sensor with increased speed.

[0061] The image sensor may also be a complementary metal-oxide-semiconductor (CMOS) image sensor.

[0062] According to another aspect of the present invention, a system for sensing an image is provided. This system comprises the image sensor described above and a controller. The controller is configured to select one or more pixels of the image sensor to be sensed. The controller is further configured to control the operation of one or more pixels to sequentially output a reset pixel value and a signal pixel value with both a first gain and a second gain different from the first gain. The controller is further configured to control the circuitry of at least one transducer of the image sensor based on the operation of one or more pixels to convert the analog output of each of the one or more pixels into a digital value.

[0063] According to another aspect of the present invention, a method for an analog-to-digital converter is provided for converting the analog output of a dual-conversion gain pixel of an image sensor, wherein the dual-conversion gain pixel is operable to sequentially output a reset pixel value and a signal pixel value with both a first gain and a second gain different from the first gain. The method includes the step of storing the reset pixel value output with the first gain in analog storage. The method further includes the step of sequentially sampling the reset pixel value output with the second gain as a first analog input and the signal pixel value output with the second gain as a second analog input in a converter stage. The method further includes the step of sequentially sampling the first and second inputs in a converter stage and outputting a first digital value indicating the difference between the reset pixel value output with the second gain and the signal pixel value output with the second gain. The method further includes the step of sampling the reset pixel value output with the first gain and stored in analog storage as a first input and the signal pixel value output with the first gain as a second input in a converter stage. This method further includes the step of sampling the first and second inputs in the converter stage and outputting a difference signal that shows the difference between the reset pixel value output with the first gain and the signal pixel value output with the first gain.

[0064] Many modifications and other embodiments of the invention described herein will be obvious to those skilled in the art in relation to these inventions from the perspective of the teachings presented herein. Therefore, it will be understood that the disclosure herein is not limited to the specific embodiments disclosed herein. Furthermore, while the description provided herein provides illustrative embodiments in the context of specific combinations of elements, steps and / or functions can be provided by alternative embodiments without departing from the scope of the invention. [Brief explanation of the drawing]

[0065] Herein, exemplary embodiments of the present invention will be described merely as examples with reference to the accompanying drawings. [Figure 1] A schematic diagram of the image sensor is provided. [Figure 2] Pixel circuit diagram provided. [Figure 3] A schematic diagram of the ADC is provided. [Figure 4] A circuit diagram of an ADC is provided as an example. [Figure 5] Figure 4 provides an example timing diagram for the ADC. [Figure 6] A circuit diagram of a dual-conversion gain pixel is provided. [Figure 7] Figure 6 provides an example timing diagram of pixels. [Figure 8] A schematic diagram of an ADC (Automated DC) as an example is provided. [Figure 9] A circuit diagram of an ADC is provided as an example. [Figure 10] A flowchart illustrating an example of the method is provided. [Figure 11] A schematic diagram of an image sensor, as an example, is provided. [Figure 12] A schematic diagram of an image sensor, as an example, is provided. [Figure 13] A schematic diagram of a system for detecting an image related to an example is provided. [Figure 14] A schematic diagram of an image sensor, as an example, is provided. [Figure 15]Figure 14 provides an example timing diagram of an image sensor. [Figure 16] A schematic diagram of the ADC is provided.

[0066] Throughout the description and drawings, the same reference number refers to the same part. [Modes for carrying out the invention]

[0067] This disclosure provides many examples of analog-to-digital converters and image sensors including analog-to-digital converters. Various embodiments of the present invention are described below, but the present invention is not limited to these embodiments, and modifications can be made to the examples provided herein without departing from the scope of the invention.

[0068] As described above, Figure 3 provides a schematic diagram of a sigma-delta ADC for converting an analog input signal to a digital value. The sigma-delta ADC 300 in Figure 3 is an example of a first-order incremental ADC. The sigma-delta ADC 300 comprises an adder 302, an integrator 304, a comparator 306, a counter 308, and a digital-to-analog converter (DAC) 310. The clock and its connections are not shown in Figure 3, but they can form part of the ADC 300. The conversion of the analog input signal to a digital value by the ADC can be performed over any number of clock cycles, also known as iteration. Each clock cycle the components of the ADC can perform their functions, which are described below. The analog input may be an analog input signal from a pixel. The input signal from the pixel can be sampled during each clock cycle, so the number of times the input signal is sampled for one conversion depends on the number of clock cycles in which the conversion is performed.

[0069] In each clock cycle, the adder 302 subtracts the feedback signal from the analog input signal received from the pixel and provides the voltage difference to the integrator 304. The adder 302 shown in Figure 3 represents any circuit that can provide a difference, for example, the potential difference between the input signal and the feedback signal to the integrator 304. The integrator 304 has a gain g and is for integrating the voltage difference provided by the adder 302. In each clock cycle, the integrator 304 accumulates the difference between the input signal and the feedback signal. For example, the integrator 304 can effectively add the voltage difference to a signal already present in the integrator. A comparator 306 is connected to the integrator and, in each clock cycle, compares the integrated signal with a reference voltage Vr / 2. The comparator 306 outputs a digital signal in response to the comparison. For example, if the voltage of the signal output by the integrator is higher than Vr / 2, the comparator output can be high (logic 1), and if the voltage of the signal output by the integrator is lower than Vr / 2, the comparator output can be low (logic 0). During each conversion, the comparator output (logic 0 or logic 1) is digitally accumulated in counter 308. The output accumulated in counter 308 forms the digital value output from ADC 300.

[0070] The output from comparator 308 is also fed back to adder 302 via DAC310, which converts the digital output from comparator 308 into a feedback signal having an analog voltage based on the comparator output. During the next clock cycle, adder 302 subtracts this feedback signal from the analog input signal received from the pixel in the next clock cycle. The analog voltage of the feedback signal output from DAC310 depends on the reference voltage input to the DAC, which is Vr in ADC300. For example, if the comparator output is high (logic 1), the DAC can feed back a signal with voltage Vr to the adder, and if the comparator output is low (logic 0), the DAC can feed back a signal with ground voltage to the adder. The reference voltage Vr / 2 input to comparator 306 is shown as half of the reference voltage Vr input to DAC310, but these reference voltages do not have to be linked, and other reference voltages are assumed.

[0071] At the start of each transformation, both the integrator and the digital accumulator can be reset by the reset control line shown in Figure 3, addressing the high-frequency components associated with pixel-to-pixel transitions.

[0072] As described above, the digital signal output from the comparator is accumulated in counter 308, mapped to a digital value, and then output from ADC300. For example, the digital value may be the sum of a series of digital signals. The more digital signals there are, the more precise the digital value becomes. Since the comparator outputs a digital signal in each clock cycle, the accuracy of the digital value output by ADC300 improves with each clock cycle. For example, in a conversion using four consecutive clock cycles, the possible digital signals can be mapped to digital values ​​as follows: • The continuous digital signal 0000 can be mapped to the digital value "0". • Continuous digital signals 1000, 0100, 0010, or 0001 can be mapped to the digital value "1". • Continuous digital signals 1100, 0110, or 0011 can be mapped to the digital value "2". • The continuous digital signal 1110 or 0111 can be mapped to the digital value "3". The consecutive digital signals 1111 can be mapped to the digital value "4".

[0073] Thus, the number of digital signals with logic 1 output by the comparator can determine the digital value. In the example above, four repetitions result in five different digital values, meaning that five digital levels can be resolved. Number of consecutive comparisons n C The number of digital levels obtained is n C It is +1. Therefore, the equivalent ADC resolution per bit is log2(n C It is equal to (+1). Digital signals can also be mapped to digital values ​​in other ways.

[0074] To eliminate the need for an external CDS amplifier, the sigma-delta ADC300 in Figure 3 can be configured to allow CDS integration. To do this, the ADC300 can be configured to employ signal inversion using a feedback signal, and the final code in the counter represents the difference between the signal pixel value and the reset pixel value. For example, the reset pixel value can be accumulated any number of times, and the signal pixel value can be accumulated the same number of times, but with inverted polarity. In such a case, the n of the reset pixel value C After the comparison, the output of the integrator will be as follows.

[0075]

number

[0076] Then, the signal pixel value V applied to the input sig n with the cancellation voltage CAfter the back special comparison, the output of the integrator becomes as follows.

[0077]

Number

[0078]

Number

[0079]

Number

[0080]

Number

[0081] The ADC400 in Figure 4 can be controlled using control signals ph0 412, ph1 408, ph2 414, pha 402, phb 428, and phc 430. These control signals can operate as shown in Figure 5, providing the illustrative timing for the ADC400 in Figure 4, except for the clock waveform. When ph0 412, ph1 408, ph2 414, and pha 402 are high (also called active), the corresponding switches are closed.

[0082] The ADC400 includes a switched-capacitor (SC) integrator comprising an operational transconductance amplifier (OTA) 410 and a capacitor C2 406. The OTA 410 is a voltage-controlled current source, i.e., it receives an input voltage and provides an output current, for example, to charge capacitor C2 406. The corresponding switches are alternately controlled by control signals ph1 408 and ph2 414, respectively, as shown in Figure 5. When ph1 408 is active, i.e., when ph2 414 is inactive, the switch corresponding to ph1 408 is closed and the switch corresponding to ph2 414 is opened. Capacitor C1 404 is charged, but capacitor C2 406 is not. When ph2 414 is active, i.e., when ph1 408 is inactive, the switch corresponding to ph2 414 is closed and the switch corresponding to ph1 408 is opened. The OTA 410 provides an output current based on the input voltage provided by capacitor C1 404, charging capacitor C2 406 and effectively adding the voltage across capacitor C1 404 to the voltage already present across capacitor C2 406. Thus, as ph1 408 and ph2 414 are alternately activated during the clock cycle, the SC integrator integrates the signal with each clock cycle and operates effectively as integrator 304 in Figure 3.

[0083] During a clock cycle, the clock transitions between high and low. The duration of a clock cycle is the time between two low-to-high clock transitions, or two high-to-low clock transitions. Triggers may be activated by specific clock transitions occurring in each clock cycle, and such triggers can cause switch flips or phase transitions. For example, a low-to-high clock transition can activate a trigger, activating ph1 408 or starting phase 1, deactivating ph2 414, or ending phase 2. A low-to-high clock transition can activate a trigger, activating ph2 414 or starting phase 2. It may also deactivate ph1 408 or end phase 1.

[0084] The inverting input to the OTA410 is connected to capacitor C1 404. Capacitor C1 404 is connected to the input that receives the signal from the pixel via a switch corresponding to the control signal pha 402, connected to ground via switch 426, and connected to a reference voltage Vr via switch 424. The signal received by capacitor C1 404 depends on which switch is closed. Switches 424 and 426 operate to provide capacitor C1 404 with either a Vr or ground feedback signal. When the control signal phb 428 is active, it closes one of switches 424 or 426, causing capacitor C1 404 to sample the Vr or ground feedback signal. When the control signal pha 402 is active, it closes the corresponding switch, causing capacitor C1 404 to sample the analog input signal from the pixel. The control signals pha 402 and phb 428 are activated alternately, as shown in Figure 5, and as will be explained in more detail below, this results in the alternating accumulation of the analog input signal and the subtraction of the Vr or ground feedback signal, causing the overall accumulation of the voltage difference across the SC integrator's capacitor C2 406. Thus, switches 424, 426, the switch corresponding to pha 402, and capacitor C1 404 are configured to operate similarly to the adder 302 in Figure 3.

[0085] The SC integrator then outputs an integrated signal to a latch comparator 416, which operates similarly to comparator 306 in Figure 3. Comparator 416 can be connected to a counter (not shown) which operates similarly to counter 308 in Figure 3. The XOR gate 418 and AND gates 420, 422 control switches 424, 426, connected to Vr and ground respectively, to provide a Vr or ground feedback signal to capacitor C1 404 based on the digital output from comparator 416. Thus, these components operate similarly to DAC310 in Figure 3. ADC400 may further include a clock and a clock connection (not shown).

[0086] CDS is implemented in the sigma-delta modulator of the ADC400 by integrating the signal pixel value and the reset pixel value in opposite directions. When using CDS, the ADC is configured to first receive a sample of the reset pixel value, and then receive a sample of the signal pixel value. Thus, each column of the pixel array is selected twice within the line spacing. During the first selection, the reset pixel value is sampled and integrated by the ADC400 during the iteration, without the need for sample and hold. During the second selection, the photodiode charge in the pixel is transferred to the sense node, and the signal pixel value is integrated by the ADC stage.

[0087] The ADC400 is controlled to perform CDS operation by employing signal inversion during sigma-delta processing. First, the reset pixel value is accumulated multiple times (by an integrator), and then the signal pixel value is accumulated the same number of times, but with inverted polarity so that the actual multiple subtraction takes place. Along this process, the accumulated comparator determination comes to form a digital representation of the difference. Thus, the final code in the counter represents the subtraction between the two pixel values.

[0088] In CDS, the polarity of the signal depends not only on the input signal, but also on the input signal itself, in order to maintain proper feedback so that the integrator output is bound by Vr, whether the voltage magnitude is Vr or ground. For example, in ADC400, during the processing of reset pixel values, the DAC output is Vr when the comparator is high (logic 1), and ground otherwise. However, while the cancel signal pixel value is being converted, the DAC output is ground when the comparator output is high (logic 1), and -Vr when the output is low (logic 0).

[0089] The combination of XOR gate 418 and AND gates 420 and 422 provides various feedback signals as described below. XOR gate 418 outputs a signal to AND gate 420 and an inverted signal to AND gate 422. As shown in Figure 5, when a reset pixel value is received by ADC 400, control signal phc 430 is set to low, and when a signal pixel value is received by ADC 400, control signal phc 430 is set to high. Control signal phc 430 effectively controls XOR gate 418, propagating a logic signal when control signal phc 430 is low (logic 0), and inverting a logic signal when control signal phc 430 is high (logic 1). Control signal phb 428 controls whether or not a feedback signal is selected. When phb 428 is low, no feedback signal is selected. This is because when phb 428 is low, the output to AND gates 420 and 422 is low (logic 0), and neither switch 424 nor 426 is closed.

[0090] When a reset pixel value is received, the control signal phc430 is low, and as a result, the XOR gate 418 propagates the output from comparator 416. When the output from comparator 416 is high (logic 1), the XOR gate output is high (logic 1) and the inverted output is low (logic 0). When the control signal phb428 is high (logic 1), the output of the AND gate 420 is high (logic 1), which turns on switch 424 and provides the voltage Vr to capacitor C1 404. When the output of AND gate 422 is low, switch 426 is open, meaning the ground terminal is disconnected from the circuit.

[0091] When a reset pixel value is received and the output from comparator 416 is low (logic 0), the XOR gate output is low (logic 0) and the inverted output is high (logic 1). When the control signal phb428 is high (logic 1), the output of AND gate 422 is high (logic 1), which turns on switch 426 and supplies ground voltage to capacitor C1 404. When the output of AND gate 420 is low, it means that switch 424 is open and terminal Vr is disconnected from the circuit.

[0092] If a signal pixel value is received, the control signal phc430 is high, and as a result, the XOR gate 418 inverts the output from comparator 416. If the output from comparator 416 is high (logic 1), the XOR gate output is low (logic 0), and the inverted output is high (logic 1). If phb428 is high (logic 1), the output of AND gate 422 is high (logic 1), which turns on switch 426 and supplies ground voltage to capacitor C1 404. If the output of AND gate 420 is low, switch 424 is open, meaning that terminal Vr is disconnected from the circuit.

[0093] When a signal pixel value is received and the output from comparator 416 is low (logic 0), the XOR gate output is high (logic 1) and the inverted output is low (logic 0). When phb428 is high (logic 1), the output of AND gate 420 is high (logic 1), which turns on switch 424 and provides the voltage Vr to capacitor C1 404. When the output of AND gate 422 is low, switch 426 is open, meaning the ground terminal is disconnected from the circuit.

[0094] In the ADC400, for the signal pixel value to be effectively subtracted from the reset pixel value, the voltage difference during integration of the signal pixel value must have the opposite polarity to the voltage difference during integration of the reset pixel value. This is achieved by the timing of the control signal, as described below.

[0095] As shown in Figure 5, the conversion time slot is divided into two sub-slots marked by the change in signal plc430. When plc430 is low, the reset pixel value is sampled at the input, and when plc430 is high, the signal pixel value is sampled.

[0096] When ph0 412 and ph1 408 are simultaneously activated at the start of the first conversion subslot, the integrator is reset. The OTA410 is held in a single (unity) gain feedback configuration, and capacitors C1 404 and C2 406 are precharged with an intermediate voltage called Vcm. Simultaneously, the reset pixel value is stored in capacitor C1 404. All capacitors also store the OTA offset. This auto-zero technique enables the elimination of the OTA offset effect. It also attenuates the low-frequency 1 / f noise of the OTA.

[0097] Next, ph2 414 and ph1 408 are activated alternately in a non-overlapping sequence for a predetermined number of clock cycles. Control signals pha402 and phb428 are also activated alternately in a non-overlapping sequence. The number of clock cycles may be the same for both sub-slots. A switch comprising OTA410, capacitors C1 404, C2 406, switches 426, 424, and corresponding control signals ph1 408, ph2 414, pha 402, phb 428 performs the operation of a switched-capacitor integrator.

[0098] In each cycle, in phase 1, if ph1 408 is high, pha 402 is high, ph2 414 is low, and phb 428 is low, the reset pixel value is sampled so that the charge from the pixel is sampled into capacitor C1 404, and as a result, the voltage across capacitor C1 404 becomes approximately equal to the reset pixel value. In phase 2, if ph2 414 is high, phb 428 is high, ph1 408 is low, and pha 402 is low, the charge accumulated in capacitor C1 404 is transferred to capacitor C2 406 and added to the charge already present in capacitor C2 406. Thus, the voltage across C1 404, the voltage of the reset pixel value, is added to capacitor C2 406. For the pixel reset value, phase 1 is the acquisition phase, and phase 2 is the charge transfer phase, also known as non-inverting operation, which results in the addition of the reset pixel value voltage to capacitor C2 406.

[0099] Simultaneously, in Phase 2, the feedback signal is sampled so that the charge from the feedback signal is stored in capacitor C1 404, resulting in the voltage across capacitor C1 404 being approximately equal to the feedback signal. At the same time, the charge stored in capacitor C1 404 is transferred to capacitor C2 406 and added to the charge already stored in capacitor C2 406, which is the negative of the feedback signal voltage stored in C2 406. With respect to the feedback signal, Phase 2 is the charge transfer phase and acquisition phase, known as the inversion operation, which results in the subtraction of the feedback signal voltage from capacitor C2 406.

[0100] In both inverting and non-inverting operation, if the capacitance of capacitor C1 404 is not equal to the capacitance of capacitor C2 406, the gain of C1 / C2 is applied to the cumulative signal.

[0101] At the end of each clock cycle, the comparator is latched by the cancellation phase of ph2 414 (when ph2 414 is low) and makes a decision Y about the sign of the output voltage reference Vr / 2 from the switched-capacitor integrator output. This decision is accumulated and forms the output of ADC400, for example, in a counter (not shown). As described above, this decision is fed back to capacitor C1 404 to sample either ground or Vr.

[0102] Thus, as described above, in each clock cycle, the difference between the feedback signal and the reset pixel value is accumulated in capacitor C2 with a gain equal to C1 / C2. Therefore, after the nth clock cycle, the output of the integrator will be as follows.

[0103]

number

[0104]

number

[0105] As described above, the XOR operation of the comparator output with phc 430 active generates an inversion of the feedback signal, and as a result, during phase phb428, if the comparator output is low, a voltage Vr is applied to the left of capacitor C1, otherwise the ground voltage is applied. To achieve the change in polarity, the timing of the control signals in the second subslot differs from the first subslot, in that for the subtraction of the signal pixel value, the activation of ph1 408 coincides with phb428, and the activation of ph2 414 coincides with pha402. This means that the inverting and non-inverting operation of the SC integrator is switched, and for the pixel reset value, the switched capacitor integrator is in inverting operation, resulting in the subtraction of the pixel reset voltage, and for the feedback signal, the switched capacitor integrator is non-inverting operation, resulting in the addition of the feedback signal voltage. Thus, the difference between the feedback signal and the signal pixel value is effectively subtracted from C2 406 with a gain equal to C1 / C2, which is the opposite of the first subslot. n in the second sub-slot C After several iterations, the output of the integrator will be as follows.

[0106]

number

[0107]

number

[0108] Because the ADC400 uses oversampling, the contribution of pixel noise is reduced. Furthermore, thermal noise originating from the pixels is reduced by the integrated CDS, and flicker noise is attenuated.

[0109] Low-noise devices require high conversion gain. Conversion gain is the relationship between the voltage at a floating diffusion node (node ​​A) and the collected electrons. The conversion gain is inversely proportional to the capacitance CA at the floating diffusion node (CG = q / CA, where q represents the electron charge value q = 1.6e-19). All noise preceding the pixel, such as ADC noise, is divided by the conversion gain when acquiring electrons. Thus, the higher the conversion gain, the less noise is supplied from the image sensor. However, increasing the conversion gain has the drawback of reducing the maximum number of electrons that can be collected within a pixel, known as full-well capacity (FWC), because the maximum voltage swing is limited by either the pixel voltage or the ADC input range. Higher conversion gain results in a lower FWC from the image sensor. This is a trade-off when using a typical pixel architecture, such as the one shown in Figure 2.

[0110] To overcome this limitation, a pixel architecture with a dual conversion gain can be used, as shown in Figure 6. The dual conversion gain extends the maximum number of electrons that the image sensor can collect and digitize while maintaining low noise performance.

[0111] Figure 6 provides a circuit diagram of a dual-conversion gain pixel 600. A specific architecture for the dual-conversion gain pixel is shown in Figure 6, but others are also conceivable. The dual-conversion gain pixel 600 is an adapted version of the pixel 200 in Figure 2, described in detail above. Thus, the pixel 600 also comprises four transistors having control signals labeled as transfer gate (TX) 208, reset (RST) 206, and row selection (SEL) 210, as described in Figure 2, and a transistor labeled as source follower (SF) 202. The pixel 600 further comprises a transistor having a control signal labeled as high dynamic range (HDR) 602.

[0112] In this architecture, two transformations are performed. The first transformation, which occurs when HDR is low, is performed by integrating the charge only at node A, known as high-gain operation (HG). The second transformation, which occurs when HDR is high, is performed by integrating the signals at nodes A and B with a considerably lower transformation gain, known as low-gain operation (LG).

[0113] Figure 7 provides an illustrative timing diagram for pixel 600 in Figure 6, showing the waveforms used in the dual-conversion-gain operation. First, with HDR remaining up and RST down, the reset pixel value is sampled for low gain (RST_LG). Next, as HDR goes down, the reset pixel value is sampled for high gain (RST_HG). Before the signal pixel value can be acquired, the charge from the photodiode must be transferred in the first transfer to a floating spread node with high conversion gain, as shown on the lower line in Figure 7. Once this is complete, the high-gain signal pixel value is sampled (SIG_HG). Next, the signal HDR rises, and the voltage at the floating spread node also rises, allowing the second transfer to extract any remaining electrons in the photodiode (if any). Finally, the low-gain signal pixel value is sampled (SIG_LG).

[0114] When CDS is performed, two values ​​are obtained: a high-gain value and a low-gain value. One of these values ​​can then be selected as the final value. If the amount of electrons is small, the photodiode is empty after the first transfer, and the SIG_LG value remains close to RST_LG, which is not useful. In this case, the effective conversion value is the high-gain value, which can be selected as the final value. If the amount of electrons is large, after the first transfer, the voltage of the floating diffusion saturates, and there is still charge in the FD that should be transferred to the FD overall. In the second transfer, all the charge is moved to the floating diffusion node in a low conversion-gain configuration. In this case, the high-gain value is not useful, and the useful value is the low-gain value, which can be selected as the final value.

[0115] As mentioned above, the lower the conversion gain, the higher the noise. Thus, for low-gain signals, the noise associated with the photon signal, or shot noise, is considerably larger than that of high-gain signals, and therefore low-noise conversion is not required. Shot noise is equal to the square root of the photon signal. The noise inherent in low-gain signals is equal to the square root of the signal value at the inflection point from high-gain to low-gain.

[0116] To provide a high dynamic range, it is advantageous for the ADC to be able to operate with the dual-conversion gain pixel 600. For an ADC incorporating a CDS, such as the ADC400 in Figure 4, to be able to operate with the dual-conversion gain pixel, the ADC needs to be able to operate to sequentially receive the reset pixel value when the pixel is low-gain, the reset pixel value when the pixel is high-gain, the signal pixel value when the pixel is high-gain, and the signal pixel value when the pixel is low-gain, as shown in the timing diagram 700 in Figure 7. Figure 8 provides a schematic diagram of an example ADC810. The ADC800 is able to operate with the dual-conversion gain pixel 600.

[0117] The ADC800 is for converting the analog output of the dual-conversion gain pixel 802 of the image sensor. The dual-conversion gain pixel 802 is operable to sequentially output a reset pixel value and a signal pixel value with both a first gain and a second gain different from the first gain. The first gain may be a low gain, and the second gain may be a high gain. The ADC800 includes an analog storage 806 for storing the reset pixel value output with the first gain. The ADC800 further includes a converter stage 808 configured to sequentially receive a first analog input indicating the reset pixel value of the dual-conversion gain pixel 802 and a second analog input indicating the signal pixel value of the dual-conversion gain pixel 802. The converter stage 808 is configured to sequentially sample the first and second inputs and output a digital value indicating the difference between the first and second inputs. The ADC800 further includes a circuit 804 configured to sequentially provide a reset pixel value output at a second gain as a first input to the converter stage 808, and a signal pixel value output at a second gain as a second input to the converter stage 808, so that the converter stage 808 sequentially samples the first and second inputs and outputs a first digital value indicating the difference between the reset pixel value output at a second gain and the signal pixel value output at a second gain. The circuit 804 is further configured to provide a reset pixel value output at a first gain and stored in the analog storage 806 as a first input to the converter stage 808, and a signal pixel value output at a first gain as a second input to the converter stage 808. The converter stage 808 is configured to sample the first and second inputs and output a difference signal indicating the difference between the reset pixel value output at a first gain and the signal pixel value output at a first gain.

[0118] The ADC800 can perform CDS using a converter stage 808 configured to sequentially sample the first and second inputs and output a digital value indicating the difference between the first and second inputs. Furthermore, the ADC800 can perform DCG by receiving inputs from pixels in a predetermined sequence, finding the difference between the high-gain signal and the reset pixel value, and then storing the low-gain reset pixel value in analog storage 806 for use with the low-gain signal pixel value. Combined with the operability with the DCG pixels, the ADC800 with integrated CDS provides a readout element 110 with reduced noise and increased dynamic range while maintaining high speed. Thus, the present invention achieves an optimal balance between speed, noise, and full-well capacity.

[0119] Figure 9 provides a circuit diagram of an example ADC900. The ADC900 is an example of the ADC800 described above with reference to Figure 8, and provides an integrated CDS that can operate with a dual-conversion gain pixel. The ADC900 has many of the same components as the ADC400 in Figure 4. Therefore, a detailed description of the same components will not be provided with reference to Figure 8. During high-gain operation, while sequentially receiving high-gain reset pixel values ​​and high-gain signal pixel values, the ADC900 can perform conversions as described above with reference to Figures 4 and 5.

[0120] The ADC900 further includes an additional branch between the pixel input and the inverting input of the OTA410, which includes a switch connected to the control signal pha_LG902 and a capacitor C1_LG904. Capacitor C1_LG904 is also connected to ground via switch 906. When pha402 is active and the corresponding switch is closed, the pixel input can be connected to the inverting input of the OTA via C1, but even when pha_LG is active and the corresponding switch is closed, the pixel input can be connected to the inverting input of the OTA via C1_LG. The functions of capacitor C1_LG904 and the additional switch are as follows:

[0121] As explained in relation to Figures 6 and 7, during dual conversion gain operation, the pixel sequentially outputs a reset pixel value when the pixel is low gain, a reset pixel value when the pixel is high gain, a signal pixel value when the pixel is high gain, and a signal pixel value when the pixel is low gain. When the pixel outputs a reset pixel value at low gain, the control signal pha_LG902 is high and the corresponding switch is closed, and the control signal pha402 is high and the corresponding switch is open, and switch 906 is also open, and the reset pixel value at low gain is sampled by the capacitor C1_LG904 of the ADC900.

[0122] Next, when the control signal pha_LG902 transitions to low and the corresponding switch opens, the subsequent pixel output does not affect the storage of the low-gain reset pixel value in capacitor C1_LG904. High-gain conversion begins, and the ADC900 performs an internal CDS as described in relation to Figures 4 and 5. During high-gain conversion, the ADC900 samples the reset pixel value, followed by the signal pixel value over multiple clock cycles. At the end of high-gain conversion, capacitor C2 406 is reinitialized before performing any other operations. Then, the previously sampled low-gain reset pixel value is first transferred from capacitor C1_LG904 to capacitor C2 406 using the SC integrator as described above, while the low-gain signal pixel value is sampled simultaneously. During low-gain conversion, the ADC900 can sample the reset pixel value and the signal pixel value over one clock cycle.

[0123] In detail, in phase 2, as explained with respect to Figures 4 and 5, ph2 414 is high, phb 428 is high, ph1 408 is low, and pha 402 is low. Switch 906 is also closed. The charge stored in capacitor C1_LG904, which represents the low-gain reset pixel value, is transferred to capacitor C2 406, resulting in the addition of the reset pixel value voltage to capacitor C2 406. Simultaneously in phase 2, the low-gain signal pixel value is sampled so that the charge from the low-gain signal pixel value is stored in capacitor C1_LG904, and as a result, the voltage across capacitor C1_LG904 becomes approximately equal to the low-gain signal pixel value. At the same time, the charge stored in capacitor C1_LG904 is transferred to capacitor C2 406 and added to the charge already stored in capacitor C2 406, but it is the negative of the voltage of the low-gain signal pixel value stored in capacitor C2 406. The reason is that when the low-gain reset pixel value is transferred to capacitor C2 406, the low-gain reset pixel value is sampled such that what is actually transferred to capacitor C2 406 is the difference between the low-gain reset pixel value and the low-gain signal pixel value. As mentioned above, if the capacitance of capacitor C1_LG904 is not equal to the capacitance of capacitor C2 406, the gain of C1_LG / C2 is applied to the accumulated signal. Since the low-gain conversion is performed in one clock cycle, the converter stage can output only the accumulated signal and the difference signal in the integrator. At low gain, there may be no output from the comparator. Thus, at first gain, at the output of the first-stage ADC, the result of CDS operation at low gain values ​​is the difference signal V LG That is the case.

[0124]

number

[0125] As mentioned above, unlike during high-gain conversion, during low-gain conversion, the signal pixel value and reset pixel value are sampled only once, which can provide an OSR of 1. This is because low-gain ADC conversion optimizes timing at the expense of higher noise. However, since the noise is typically always considerably smaller than shot noise, there may be little to no disadvantage to the noise of the final signal using an OSR of 1 for low-gain conversion.

[0126] Alternatively, the ADC900 may sample low-gain reset and signal pixel values ​​for more than one clock cycle, and the comparator may output a digital signal based on the low-gain reset and signal pixel values. For example, the comparator may output 1 bit for the low gain.

[0127] Figure 10 provides an illustrative flowchart of Method 1000, an analog-to-digital converter for converting the analog output of a dual-conversion gain pixel of an image sensor. Method 1000 can be performed by ADC 800 in Figure 8 or ADC 900 in Figure 9. As described above, the dual-conversion gain pixel 600 is operable to sequentially output a reset pixel value and a signal pixel value with both a first gain and a second gain distinct from the first gain. Method 1000 includes step 1002 of storing the reset pixel value output with the first gain in analog storage 806. Method 1000 further includes step 1004 of sequentially receiving the reset pixel value output with the second gain as a first analog input and the signal pixel value output with the second gain as a second analog input in a converter stage 808. Method 1000 further includes step 1006 in the converter stage 808, sequentially sampling the first and second inputs and outputting a first digital value indicating the difference between the reset pixel value output at the second gain and the signal pixel value output at the second gain. Method 1000 further includes step 1008 in the converter stage 808, receiving the reset pixel value output at the first gain and stored in the analog storage 806 as the first input, and receiving the signal pixel value output at the first gain as the second input. Method 1000 further includes step 1010 in the converter stage 808, sampling the first and second inputs and outputting a difference signal indicating the difference between the reset pixel value output at the first gain and the signal pixel value output at the first gain. This method may further include any of the steps described above in relation to the ADC400 in Figure 4, the ADC800 in Figure 8, or the ADC900 in Figure 9. In particular, the method may further include a step in the second converter stage of receiving a difference signal and outputting a first gain digital value that indicates the difference between a reset pixel value output with a first gain and a signal pixel value output with a first gain, based on the difference signal.

[0128] Figure 11 provides a schematic diagram of an example image sensor 1100. The image sensor 1100 comprises a pixel array 1102 including an array of double-conversion gain pixels 600, and an ADC 1110. The ADC 1110 may have any of the features described above in relation to the ADC 800 in Figure 8 and / or the ADC 900 in Figure 9. Figure 12 provides a schematic diagram of an example image sensor 1200. The image sensor 1200 is an example of the image sensor 1100 in Figure 11. The image sensor 1200 also comprises an array of double-conversion gain pixels 600. Furthermore, the image sensor 1200 includes an ADC 1210 for each row of the array of pixels 600.

[0129] Figure 13 provides a schematic diagram of a system 1300 for sensing an image according to one example. The system 1300 comprises an image sensor 1304 which may have any of the features of the image sensor 1100 in Figure 11 and / or the image sensor 1200 in Figure 12, and a controller 1302. The controller 1302 is configured to select one or more pixels 600 of the image sensor 1304 to be sensed. The controller 1302 is further configured to control the operation of one or more pixels 600 to sequentially output a reset pixel value and a signal pixel value with both a first gain and a second gain distinct from the first gain. The controller 1302 is further configured to control the circuitry of at least one transducer of the image sensor based on the operation of one or more pixels 600 to convert the analog output of each of the one or more pixels 600 to a digital value.

[0130] In some embodiments, an ADC based on a sigma-delta topology, such as ADC400 in Figure 4, ADC800 in Figure 8, or ADC900 in Figure 9, may also be the first stage of a two-stage ADC. For example, to reduce the time required to reach an accurate digital value, considering the need to perform CDS and DCG, and to overcome the speed limitations of a pure integral sigma-delta ADC, the ADC may include a second transducer stage, so that the first and second stages of the ADC operation can operate in a pipelined manner. Thus, ADC800 in Figure 8 may further include a second transducer stage (not shown). ADC900 may be connected to the second transducer stage by the output of OTA410. An example of a two-stage ADC is shown in Figure 14.

[0131] Figure 14 provides a schematic diagram of an example image sensor 1400. The image sensor 1400 includes an ADC 1404, which can be used in any other image sensor. The image sensor 1400 further includes a pixel array, and as described in relation to Figure 1, a pixel 1406 is selected and outputs a signal via a data column line. The signal is then supplied to the ADC 1404 via an analog buffer 1408. The analog buffer 1408 is used to isolate the ADC load from the column load, ensuring that the pixels drive only the pixel column load. The image sensor 1400 does not require a sample-and-hold block. The image sensor 1400 may also include other components connected to the pixel array and / or the ADC 1404, such as a programmable current source and a programmable offset.

[0132] The ADC1404 is a two-stage ADC with direct conversion, integrated CDS, and dual conversion gain. The ADC1404 includes a first-stage ADC1410, which is based on a first-order sigma-delta topology, performs integrated CDS, and can operate with a dual conversion gain pixel. The first-stage ADC1410 may include any of the features described above in relation to the ADC400 in Figure 4, the ADC800 in Figure 8, and / or the ADC900 in Figure 9. The operation of the first-stage ADC is described in relation to these figures and will not be described again in detail with reference to Figure 14. The output from the comparator or any counter of the first-stage ADC1410 provides a plurality of bits N.

[0133] The ADC1404 further includes a second-stage ADC1412. The second-stage ADC1412 is connected to the pixels via the first-stage ADC1410. At high gain, the final analog voltage value after sigma-delta operation in the first-stage ADC1410 is known as the residue. The residue is sampled and transformed by the second-stage ADC1412. At the end of the high-gain transformation, after the first-stage ADC1410 has performed high-gain reset pixel value and signal pixel value transformations over multiple clock cycles and generated digital values, the residue remaining in the integrator is sampled and transformed by the second-stage ADC1412, which generates its own digital value.

[0134] The digital output word, also known as the second gain digital value, is a combination of two digital values ​​coming from the two ADC stages: the first digital value from the first stage ADC outputs the most significant bit, and the second digital value from the second stage ADC outputs the least significant bit. The output of the first stage ADC 1410 is scaled by the number of bits of the second stage, N2, which is a power of 2, and D is shown by the following equation. out D1 is a digital output word, where D1 is a digital value output by the first stage ADC1410, and D2 is a digital value output by the second stage ADC1412.

[0135]

number

[0136] Figure 15 provides an illustrative timing diagram of the image sensor 1400 shown in Figure 14.

[0137] As shown in Figure 15, the presented architecture optimizes conversion time because it can operate in overlap mode. The first-stage ADC 1410 performs CDS conversion (integration of signal pixel value and reset pixel value) while the pixel outputs a reset pixel value and a signal pixel value. After conversion by the first-stage ADC 1410, the analog residue from the first-stage ADC 1410 is sampled by the second-stage ADC 1412 and finally converted to the digital domain. The conversion of the residual data in the second-stage ADC 1412 is performed while the first-stage ADC 1410 is performing CDS conversion of the next pixel value. This parallel operation reduces conversion time. Furthermore, noise in the second-stage ADC 1412 is also reduced by the OSR of the first-stage ADC 1410 because the input signal to the second-stage ADC 1412 is amplified by the OSR coefficient of the first-stage ADC 1410.

[0138] In the pixel array, each pixel in a row can be read simultaneously by the corresponding ADC 1404, and the ADC 1404 can be connected to each column of the pixel array. Thus, the illustrated row time is the time required for each pixel in the row to be sampled twice by the first-stage ADC 1410. The row time also indicates the total conversion delay caused by the pixel row, and the second-stage ADC converts the remainder after the row time, but this conversion is performed in parallel with the conversion of the pixels in the next pixel row by the first-stage ADC.

[0139] If rows are read simultaneously, the selection line SEL becomes active, enabling the pixel or pixel row. The reset line RST resets the pixel and / or the first stage ADC1410 and / or the second stage ADC1412. The TRF line transfers the charge collected by the pixel's photodiode to a readout node to obtain the signal pixel value.

[0140] The second-stage ADC1412 may also be a single-slope ADC, an example of which is shown in Figure 16. Thus, the ADC1404 in Figure 14 can be equipped with a first-order sigma-delta modulator that generates the most significant bit, followed by a single-slope ADC (also known as a ramp converter) that generates the least significant bit.

[0141] Figure 16 provides a schematic diagram of a single-slope ADC 1600. The second-stage ADC 1412 in Figure 14 may comprise or be based on the ADC 1600. The ADC 1600 comprises an analog ramp 1602 that generates an analog ramp reference. The analog ramp reference is a voltage reference that increases linearly with time. The ADC 1600 further comprises a comparator 1606 for comparing an analog signal sampled by the ADC 1600, e.g., the residue of the previous converter stage, with the analog ramp reference. The ADC 1600 further includes a digital counter 1604 (also known as a digital ramp), which increases with time in discrete time intervals. The ADC1600 further includes a digital register 1608 for storing the digital value provided by the digital counter 1604.

[0142] During conversion, the analog signal is sampled, and comparator 1606 compares this signal to an analog ramp reference generated by analog ramp 1602. Digital counter 1604 also starts. When the analog ramp reference 1602 crosses the analog input level, comparator 1606 switches on and off, and the digital count of counter 1604 is sampled into digital register 1608, where the digital count corresponds to the period during which the analog ramp reference crosses the input signal. When comparator 1606 switches on and off, it can provide an "enable" signal to register 1608, which retrieves the digital count of counter 1604. The higher the analog signal, the longer it takes for the analog ramp reference to cross the input signal, and the higher the digital count. Thus, the digital count represents the analog input signal and is output as a digital value by ADC 1600.

[0143] Ramp ADCs are advantageous for image sensors that have an ADC for each row. This is because they require less circuitry, resulting in more compact image sensors that can accommodate extremely low pixel pitches. Furthermore, since a single analog ramp signal and a single digital ramp signal can be applied to all ramp ADCs in the image sensor, the only circuitry required for each row is a comparator and a register.

[0144] While ramp ADCs are typically slow, their inclusion as second-stage ADCs within a pipeline architecture allows the speed of two-stage ADCs to be maintained.

[0145] The circuit described above may contain more components than those shown, and the feedback loop within the circuit may also contain more components than those shown. For example, the clock circuit and power circuit connected to the ADC and image sensor components are not shown but may be included.

[0146] The circuits or systems described above can be implemented on chips, computers, tablets, mobile phones, or any other such devices. Furthermore, the descriptions of the circuits or systems described above may be provided in computer-readable media, and such computer-readable media can be used, for example, to instruct a machine to generate the circuits or systems.

[0147] It will be understood that embodiments of the present invention can be implemented in the form of hardware, software, or a combination of hardware and software. Such any software can be stored in the form of volatile or non-volatile storage, such as in a storage device such as ROM, whether erasable or rewritable, or in the form of memory, such as RAM, memory chips, devices, or integrated circuits, or on optically or magnetically readable media, such as CDs, DVDs, magnetic disks, or magnetic tapes. It will be understood that the storage device and storage medium are embodiments of machine-readable storage suitable for storing one or more programs that implement embodiments of the present invention at runtime. Accordingly, embodiments provide programs containing code for implementing any system or method described in any prior claim, and machine-readable storage for storing such programs. Furthermore, embodiments of the present invention can be electronically transported over any medium, such as communication signals carried over wired or wireless connections, and embodiments appropriately encompass this.

[0148] All of the features and / or steps of the methods or processes disclosed herein (including the attached claims, abstract, and drawings) may be combined in any combination except in which at least some of the features and / or steps are mutually exclusive.

[0149] Each feature disclosed herein (including the attached claims, abstract, and drawings) may be replaced by an alternative feature serving the same, equivalent, or similar purpose unless otherwise explicitly stated. Therefore, unless otherwise explicitly stated, each disclosed feature is merely an example of a comprehensive set of equivalent or similar features.

[0150] The present invention is not limited to the details of the embodiments described above. The present invention extends to any novel features or combinations of features disclosed herein (including the appended claims, abstract, and drawings), or to any novel methods or steps of processes so disclosed herein. The claims should be construed to cover not only the embodiments described above, but also any embodiments that fall within the scope of the claims.

Claims

1. 1. An analog-to-digital converter for converting analog outputs of dual conversion gain pixels of an image sensor, comprising: the dual conversion gain pixel is operable to sequentially output the reset pixel value and the signal pixel value at both a first gain and a second gain different from the first gain; the analog-to-digital converter includes an analog storage for storing a reset pixel value output at a first gain; a converter stage configured to sequentially sample a first analog input indicative of a reset pixel value of the dual conversion gain pixel and a second analog input indicative of a signal pixel value of the dual conversion gain pixel, the converter stage configured to sequentially sample the first and second inputs and output a digital value indicative of a difference between the first and second inputs; circuitry configured to sequentially provide as a first input to the converter stage the reset pixel value output at the second gain and as a second input to the converter stage the signal pixel value output at the second gain, the converter stage sequentially sampling the first and second inputs and outputting a first digital value indicative of the difference between the reset pixel value output at the second gain and the signal pixel value output at the second gain; the circuit is further configured to provide a reset pixel value output at the first gain and stored in analog storage as a first input to the converter stage, and to provide a signal pixel value output at the first gain as a second input to the converter stage; an analog-to-digital converter configured such that the converter stage samples the first input and the second input and outputs a difference signal indicative of the difference between the reset pixel value output at the first gain and the signal pixel value output at the first gain;

2. The analog-to-digital converter of claim 1 , wherein the second gain is greater than the first gain.

3. 2. The analog-to-digital converter of claim 1, wherein the circuit is configured such that the converter stages sequentially sample both the first and second inputs over multiple clock cycles of a first converter stage.

4. 2. The analog-to-digital converter of claim 1, wherein the circuit and the converter stage are configured such that the converter stage performs built-in analog correlated double sampling (CDS) on reset pixel values ​​and signal pixel values ​​output at a second gain.

5. The converter stage includes an integrator for integrating a voltage difference between the analog input sampled by the converter stage and a feedback signal; 2. An analog-to-digital converter as claimed in claim 1, comprising: a comparator for comparing the integrated voltage difference with a reference voltage, the feedback signal being dependent on the output of the comparator.

6. 6. An analog-to-digital converter as claimed in claim 5, wherein the polarity of the feedback signal depends on whether the analog input sampled by the converter stage is the first input or the second input, and the digital value output by the converter stage represents the difference between the first input and the second input.

7. the circuit is configured to provide as a first input to a converter stage the reset pixel value output at the second gain over multiple clock cycles of the converter stage, such that the converter stage samples the first input multiple times to provide multiple outputs to the comparator for the first input; 6. An analog-to-digital converter as claimed in claim 5, wherein the circuit is configured to provide as a second input to the converter stage the signal pixel value output at the second gain over multiple clock cycles of the converter stage, such that the converter stage samples the second input multiple times to provide multiple outputs to the comparator for the second input.

8. 6. An analog to digital converter as claimed in claim 5, wherein the circuit can be configured to provide a reset pixel value output at a first gain and stored in analog storage as a first input to the converter stage, and to provide a signal pixel value output at the first gain as a second input to the converter stage over one clock cycle of the converter stage, such that the converter stage samples the first and second inputs once and provides a difference signal to the integrator.

9. further comprising a second converter stage; the circuitry is further configured to provide a differential signal to a second converter stage; 2. The analog-to-digital converter of claim 1, wherein the second converter stage is configured to sample the difference signal and output a first-gain digital value indicative of the difference between the reset pixel value output at the first gain and the signal pixel value output at the first gain.

10. 10. The analog-to-digital converter of claim 9, wherein the second converter stage is configured to output a first gain digital value based on a comparison of the difference signal with a variable reference voltage.

11. the circuitry is further configured to sequentially provide the reset pixel value output at the second gain as a first input to the converter stage and the signal pixel value output at the second gain as a second input to the converter stage, and then provide the analog residue to a second converter stage; 10. The analog-to-digital converter of claim 9, wherein the second converter stage is configured to sample the analog residue and output a second digital value indicative of the analog residue.

12. 12. The analog-to-digital converter of claim 11, wherein the second converter stage is configured to output a second digital value based on a comparison of the sampled analog residue and a variable reference voltage.

13. the analog-to-digital converter is configured to determine a second gain digital value indicative of a difference between a reset pixel value output at a second gain and a signal pixel value output at a second gain; 12. The analog-to-digital converter of claim 11, wherein the second gain digital value is dependent on the first digital value and the second digital value.

14. 14. The analog to digital converter of claim 13, wherein the circuitry is further configured to select one of a first gain digital value and a second gain digital value to output from the converter.

15. An image sensor comprising an array of dual conversion gain pixels and at least one analog-to-digital converter according to any one of claims 1 to 14.

16. 1. A system for sensing an image, comprising: An image sensor according to claim 15 and a controller, The controller Selecting one or more pixels of the image sensor to be sensed; controlling the operation of one or more pixels to sequentially output reset pixel values ​​and signal pixel values ​​at both a first gain and a second gain different from the first gain; Controlling at least one converter circuit of the image sensor based on the activity of one or more pixels to convert the analog output of each of the one or more pixels into a digital value. The system is configured as follows.

17. 1. An analog-to-digital converter method for converting an analog output of a dual conversion gain pixel of an image sensor, comprising: the dual conversion gain pixel is operable to sequentially output the reset pixel value and the signal pixel value at both a first gain and a second gain different from the first gain; The method comprises: storing the reset pixel value output at the first gain in analog storage; - receiving, in a converter stage, as a first analog input, a reset pixel value output at a second gain, and as a second analog input, a signal pixel value output at a second gain; - sequentially sampling the first and second inputs in a converter stage and outputting a first digital value indicative of the difference between a reset pixel value output at the second gain and a signal pixel value output at the second gain; - receiving at a converter stage as a first input the reset pixel value output at the first gain and stored in analog storage, and as a second input the signal pixel value output at the first gain; - sampling the first input and the second input at the converter stage and outputting a difference signal indicative of the difference between the reset pixel value output at the first gain and the signal pixel value output at the first gain.

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