Test method for device under test and testing device

Abstract

To provide a test method for a device under test which is a switching element.SOLUTION: A test method for a device under test includes the steps of: applying a gate voltage of a predetermined first pulse to the device under test; measuring a turn-off loss of the device under test on the basis of a collector current during a rise time thereof, the collector current flowing through the device under test according to the first pulse; and measuring a reverse bias safe operation area of the device under test on the basis of the collector current during a fall time of the collector current according to the first pulse.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to a method and apparatus for testing a device under test. [Background technology]

[0002] Patent Document 1 describes "a semiconductor testing device that can reduce the number of testing steps by integrating thermal resistance testing, surge testing, and switching characteristic testing of power semiconductor elements." [Prior art document] [Patent documents] [Patent Document 1] Patent No. 5267053 Summary of the Invention [Problem to be solved by the invention]

[0003] It is desirable to improve tester cycle time and thus increase chip testing throughput. [Means for solving the problem]

[0004] In a first aspect of the present invention, there is provided a method for testing a device under test which is a switching element, comprising the steps of: applying a gate voltage of a predetermined first pulse to the device under test; measuring a turn-on loss of the device under test based on a collector current during a rise period of a collector current flowing in the device under test in response to the first pulse; and measuring a reverse bias safe operating area of ​​the device under test based on the collector current during a fall period of the collector current in response to the first pulse.

[0005] The above-mentioned method for testing a device under test may include a step of applying a predetermined second pulse gate voltage to the device under test before the step of applying the first pulse gate voltage to the device under test, and a step of measuring a turn-off loss of the device under test based on the collector current during a falling period of the collector current flowing in the device under test in response to the second pulse.

[0006] In any of the above-described methods for testing a device under test, the step of applying the first pulse of gate voltage may include a step of applying the first pulse of gate voltage for a time until the collector current increases to a first reference current required for measuring the reverse bias safe operating area.

[0007] In any of the above-mentioned methods for testing a device under test, the step of applying the second pulse gate voltage may include a step of applying the second pulse gate voltage until the collector current increases to a second reference current smaller than the first reference current, and may include a step of storing energy corresponding to a current flowing in an inductive load circuit after turning off the second pulse gate voltage, and in the step of applying the first pulse gate voltage, the collector current may increase at a first rate of change based on the energy stored in the inductive load circuit, and then the collector current may increase to the first reference current at a second rate of change that is gentler than the first rate of change.

[0008] In any of the above methods for testing a device under test, a time period during which the first pulse of gate voltage is applied may be shorter than a time period during which the second pulse of gate voltage is applied.

[0009] In any of the above methods for testing a device under test, a time between the step of applying the second pulse of gate voltage and the step of applying the first pulse of gate voltage may be not less than 1 μs and not more than 100 μs.

[0010] In a second aspect of the present invention, there is provided a test apparatus for a device under test which is a switching element, comprising: a power supply section; a load section connected in series with the device under test and the power supply section; a voltage application section which applies a gate voltage to the device under test; and a measurement section which measures characteristics of the device under test based on a collector current flowing through the device under test, wherein the voltage application section applies a gate voltage of a predetermined first pulse to the device under test, and the measurement section is configured to measure the turn-on loss of the device under test based on the collector current during a rise period of the collector current flowing through the device under test in response to the first pulse, and to measure a reverse bias safe operating area of ​​the device under test based on the collector current during a fall period of the collector current in response to the first pulse.

[0011] In the above-mentioned test apparatus for the device under test, the voltage application section may be configured to apply a gate voltage of a predetermined second pulse to the device under test, and the measurement section may be configured to measure the turn-off loss of the device under test based on the collector current during a falling period of the collector current in response to the second pulse.

[0012] In any of the above test apparatus for a device under test, the voltage application section may be configured to apply the first pulse gate voltage for a period of time until the collector current increases to a first reference current required for measuring the reverse bias safe operating area.

[0013] In any of the above-mentioned test apparatus for a device under test, the voltage application section may apply the second pulse gate voltage until the collector current increases to a second reference current smaller than the first reference current, and the load section may have an inductive load circuit that stores energy corresponding to a current flowing through the load section after the second pulse gate voltage is turned off, and when the first pulse gate voltage is applied, the collector current may increase at a first rate of change based on the energy stored in the inductive load circuit, and then the collector current may increase to the first reference current at a second rate of change that is gentler than the first rate of change.

[0014] In any of the above-described device under test testing apparatuses, the load section may be provided between the positive terminal of the power supply section and the device under test.

[0015] In any of the above-described device under test test apparatuses, the load section may include a diode connected in series with the device under test and arranged in parallel with the inductive load circuit.

[0016] In any of the above-described device under test test apparatuses, the load section may include a power semiconductor element connected in series with the device under test and provided in parallel with the diode.

[0017] In any of the above-described device under test test apparatuses, a rated current and a rated voltage of the power semiconductor element may be higher than a rated current and a rated voltage of the device under test.

[0018] In any of the above-described test apparatuses for a device under test, the load section does not need to include a power semiconductor element.

[0019] In any of the above-described test apparatuses for a device under test, the device under test may be any of an IGBT, a MOSFET, and a bipolar transistor.

[0020] The above summary of the invention does not list all of the features of the present invention. Also, subcombinations of these features may also be inventions. [Brief description of the drawings]

[0021] [Figure 1] 1 is a circuit diagram showing an overview of a test apparatus for a device under test according to an embodiment of the present invention; [Figure 2A] 1 is a circuit diagram showing the flow of a collector current when an on-voltage is applied to a device under test. [Figure 2B] 1 is a circuit diagram showing the flow of a collector current when an off-voltage is applied to a device under test. [Diagram 3] 1 is a graph showing an outline of a test method for a device under test according to the present embodiment; [Figure 4A] 11 is a graph showing an outline of a test method for a device under test of a comparative example. [Figure 4B] 11 is a graph showing an outline of a test method for a device under test of a comparative example. [Figure 5A] 4 is a flowchart showing an outline of a testing method for a device under test according to the present embodiment; [Figure 5B] 13 is a flowchart showing an outline of a testing method for a device under test of a comparative example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0022] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0023] 1 is a circuit diagram showing an overview of a test apparatus 100 for a device under test (DUT) 3 of this example. The test apparatus 100 of this example includes a power supply section 1, a load section 2, a DUT 3, a voltage application section 4, and a measurement section 5.

[0024] The load section 2 is connected in series with the DUT 3. The load section 2 is provided between the positive terminal of the power supply section 1 and the DUT 3. By providing the load section 2, it is possible to adjust the change over time of the collector current Ic flowing through the DUT 3.

[0025] The load section 2 includes an inductive load circuit 21 that stores energy according to the collector current Ic flowing through the DUT 3. The inductive load circuit 21 may be a coil. By storing energy based on the collector current Ic in the inductive load circuit 21, when the gate voltage Vge is applied to the DUT 3, the collector current Ic can be increased at a steeper slope than when no energy is stored, thereby improving the cycle time of the test device and the throughput of the chip test.

[0026] The load section 2 includes a diode 22 connected in series with the DUT 3 and arranged in parallel with the inductive load circuit 21. By providing the diode 22, energy based on the collector current Ic can be stored in the inductive load circuit 21 even when the gate voltage is applied to the DUT 3 and then the application of the gate voltage is released.

[0027] The load section 2 may include a power semiconductor element 23 connected in series with the DUT 3 and arranged in anti-parallel with the diode 22, and a fixed power supply 24 that applies a gate voltage to the power semiconductor element 23. In this specification, "the power semiconductor element 23 is arranged in anti-parallel with the diode 22" means that the direction of the collector-emitter current of the power semiconductor element 23 is opposite to the rectification direction of the diode 22. The rated current and rated voltage of the power semiconductor element 23 may be higher than or approximately equal to the rated current and rated voltage of the DUT3.

[0028] When the DUT 3 is destroyed, the current that continues to flow due to the energy stored in the inductive load circuit 21 is consumed by the power semiconductor element 23 through a closed circuit formed by the inductive load circuit 21 and the power semiconductor element 23. This makes it possible to prevent the measuring device from being damaged by a current that continues to flow from the inductive load circuit 21 to the destroyed DUT 3. The load section 2 does not have to include the power semiconductor element 23.

[0029] The DUT3 includes a switching element such as a semiconductor device. The DUT3 in this example is a reverse conducting IGBT in which an IGBT and a diode provided in anti-parallel with the IGBT are configured on the same semiconductor chip. The DUT3 may also be configured with an IGBT and a diode configured on separate chips and connected in anti-parallel, may be a metal-oxide-semiconductor field-effect transistor (MOSFET), or may be a bipolar transistor. When a gate voltage is applied to the DUT3, a collector current Ic flows based on the power supply voltage Vcc of the power supply unit 1. In one example, the power supply voltage Vcc is 600V. The test device 100 may include a capacitance C.

[0030] The voltage application unit 4 applies a gate voltage to the DUT 3. The voltage application unit 4 includes a variable power supply 40 and a gate resistor 45. The voltage application unit 4 may apply a pulse-shaped gate voltage to the DUT 3. The voltage application unit 4 may apply a predetermined first pulse gate voltage and a predetermined second pulse gate voltage as the pulse-shaped gate voltage. The first pulse and the second pulse will be described later.

[0031] The variable power supply 40 switches between two different voltage values ​​and outputs the voltage. The two different voltage values ​​may be set to a predetermined on-voltage Von and an off-voltage Voff that is lower than the on-voltage Von and is equal to or less than 0 V. In one example, the on-voltage Von is 15 V and the off-voltage Voff is −15 V. The off-voltage Voff may be 0 V. The variable power supply 40 switches between the on-voltage Von and the off-voltage Voff, thereby applying a pulsed gate voltage to the DUT 3.

[0032] When the on-voltage Von is applied to the DUT 3 by the voltage application unit 4, a collector current Ic flows through the DUT 3 according to the power supply voltage Vcc supplied from the power supply unit 1 and the self-inductance L of the inductive load circuit 21. The collector current Ic increases linearly during the period in which the on-voltage Von is applied to the DUT 3.

[0033] When the off-voltage Voff is applied to the DUT 3 by the voltage application unit 4, the collector current Ic stops flowing through the DUT 3. At this time, the off-current Ioff flows through a closed circuit including the inductive load circuit 21 and the diode 22 according to the collector current Ic immediately before the off-voltage Voff is applied. The inductive load circuit 21 stores energy according to the off-current Ioff.

[0034] The measurement unit 5 measures the characteristics of the DUT 3 based on the collector current Ic flowing through the DUT 3. The measurement unit 5 includes a voltmeter 51 that measures the collector-emitter voltage Vce, and an ammeter 52 that measures the collector current Ic flowing through the DUT 3. The characteristics of the DUT 3 may be a reverse bias safe operating area (RBSOA), a turn-on loss Eon, or a turn-off loss Eoff.

[0035] The measuring unit 5 measures the turn-on loss Eon of the DUT 3 based on the collector current Ic during the rising period of the collector current Ic that flows through the DUT 3 when the voltage applying unit 4 applies a first pulse gate voltage to the DUT 3. In this specification, the rising period of the collector current Ic may be the time from when the collector current Ic starts to flow until it reaches a predetermined current value when the DUT 3 is turned on. The predetermined current value may be the maximum value of the collector current Ic excluding the peak current during reverse recovery. The rising period of the collector current Ic may be the time from when the collector current Ic reaches 10% of its maximum value until it reaches 90% of its maximum value.

[0036] The measuring unit 5 measures the reverse bias safe operating area RBSOA of the DUT 3 based on the collector current Ic during the fall period of the collector current Ic that flows through the DUT 3 when the voltage applying unit 4 applies a first pulse gate voltage to the DUT 3. In this specification, the fall period of the collector current Ic may be the time from when the off-voltage Voff is applied until the collector current Ic is turned off. The fall period of the collector current Ic may be the time from when the off-voltage Voff is applied until the collector current Ic becomes zero, or may be the time until the collector current Ic reaches 10% of its maximum value on the tangent line of the descending collector current Ic.

[0037] The measuring unit 5 measures the turn-off loss Eoff of the DUT 3 based on the collector current Ic during the falling period of the collector current Ic flowing through the DUT 3 when the voltage applying unit 4 applies the second pulse of gate voltage to the DUT 3 before applying the first pulse of gate voltage to the DUT 3. This makes it possible to measure the turn-off loss Eoff, turn-on loss Eon, and reverse bias safe operating area RBSOA of the DUT 3 in a single measurement.

[0038] Fig. 2A is a diagram showing the flow of the collector current Ic in a state in which an on-voltage Von is applied to the DUT 3 by the voltage application unit 4. In the closed circuit shown by the bold line in Fig. 2A, the collector current Ic flows in the direction of the arrow. When a power semiconductor element 23 is provided, the collector current Ic may flow between the collector and emitter of the power semiconductor element 23.

[0039] 2B is a diagram showing the flow of the off-current Ioff in a state in which the off-voltage Voff is applied after the on-voltage Von is applied to the DUT 3. In the closed circuit shown by the bold line in FIG. 2B, the off-current Ioff flows in the direction of the arrow. In the case where the power semiconductor element 23 is provided, the off-current Ioff may flow between the collector and emitter of the power semiconductor element 23.

[0040] 2B, when an off-voltage Voff is applied after an on-voltage Von is applied to DUT 3, the off-current Ioff flows circulating through a closed circuit including inductive load circuit 21 and diode 22, and energy according to the off-current Ioff is stored in inductive load circuit 21. When an on-voltage Von is further applied to DUT 3 in a situation where energy based on the off-current Ioff is stored in inductive load circuit 21, the collector current Ic can be increased at a steeper slope based on the energy stored in inductive load circuit 21 than when no energy is stored.

[0041] 3 is a graph showing an outline of the method for testing the device under test of this example, which shows the changes over time in the gate voltage Vge, the collector current Ic, and the collector-emitter voltage Vce in the method for testing the device under test of this example.

[0042] First, in a period Tw1, the voltage application unit 4 applies a second pulse of gate voltage to the DUT 3. That is, the voltage application unit 4 applies an off-voltage Voff to the DUT 3 at a point in time before the period Tw1, and applies an on-voltage Von to the DUT 3 in the period Tw1. In the period Tw1, the collector current Ic increases linearly based on the power supply voltage Vcc and the self-inductance L of the inductive load circuit 21.

[0043] The on-voltage Von is applied until the collector current Ic increases to the second reference current value I2. In other words, the period Tw1 during which the second pulse gate voltage is applied is determined according to the period until the collector current Ic increases to the second reference current value I2.

[0044] After the second pulse gate voltage is applied for a predetermined period Tw1, the off-voltage Voff is applied to the DUT 3. At this time, the off-current Ioff corresponding to the second reference current I2 that flowed when the second pulse gate voltage was turned off flows through the load unit 2, and energy corresponding to the off-current Ioff is stored in the inductive load circuit 21. The measurement unit 5 measures the turn-off loss Eoff of the DUT 3 based on the collector current Ic during the falling period of the collector current Ic corresponding to the falling edge of the second pulse gate voltage.

[0045] Thereafter, the off-voltage Voff is applied for a predetermined period Tw2. The predetermined period Tw2 is determined based on the period until the noise detected by the measurement unit 5 due to the sudden change in the gate voltage Vge becomes equal to or less than a predetermined value. The period Tw2 may be shorter than the period Tw1. The period Tw2 may be 1 μs or more and 100 μs or less.

[0046] After a predetermined period Tw2 has elapsed, the on-voltage Von is applied to the DUT 3 again. In the predetermined period Tw3, the voltage application unit 4 applies a first pulse of gate voltage to the DUT 3. When the first pulse of gate voltage is applied, unlike the period Tw1, the collector current Ic increases at a first rate of change that is steeper than when the second pulse of gate voltage is applied, based on the energy stored in the inductive load circuit 21. Thereafter, the collector current Ic increases at a second rate of change that is gentler than the first rate of change, based on the power supply voltage Vcc and the self-inductance L of the inductive load circuit 21.

[0047] The measuring section 5 measures the turn-on loss Eon of the DUT 3 based on the collector current Ic during the rising period of the collector current Ic that corresponds to the rising edge of the gate voltage of the first pulse.

[0048] Thereafter, the on-voltage Von is applied at the second rate of change until the collector current Ic increases to the first reference current value I1. That is, the period Tw3 during which the first pulse of gate voltage is applied is determined according to the period until the collector current Ic increases to the first reference current value I1. The period Tw3 during which the first pulse of gate voltage is applied may be shorter than the period Tw1 during which the second pulse of gate voltage is applied.

[0049] The first reference current I1 is a current value required to measure the reverse bias safe operating area RBSOA of the DUT3. The first reference current I1 is greater than the second reference current I2. In one example, the first reference current I1 is 800 A, and the second reference current I2 is 550 A. The magnitudes of the first reference current I1 and the second reference current I2 may be changed according to the characteristics of the DUT3.

[0050] After the first pulse gate voltage is applied for a predetermined period Tw3, an off voltage Voff is applied to the DUT 3. The measurement unit 5 measures the reverse bias safe operating area RBSOA of the DUT 3 based on the collector current Ic during the falling period of the collector current Ic corresponding to the falling edge of the first pulse gate voltage. As a result, in this example, three items, the turn-off loss Eoff, the turn-on loss Eon, and the reverse bias safe operating area RBSOA, can be measured by a single measurement using two pulse gate voltages, thereby improving the cycle time of the test device and the throughput of chip testing.

[0051] 4A and 4B are graphs showing an outline of a method for testing a device under test in a comparative example: Fig. 4A is a graph relating to a method for testing turn-off loss Eoff and turn-on loss Eon of a device under test in a comparative example;

[0052] As shown in Fig. 4A, the gate voltage of the second pulse is applied during the period Tw1'. The comparative example differs from the embodiment shown in Fig. 3 in that the off-voltage Voff is 0V. Thereafter, the turn-off loss Eoff of the DUT3 is measured based on the collector current Ic during the falling period of the collector current Ic corresponding to the falling edge of the gate voltage of the second pulse, the off-voltage Voff is applied during the period Tw2' until the noise detected with the sudden change in the gate voltage Vge becomes equal to or lower than a predetermined value, and the turn-on loss Eon of the DUT3 is measured after the period Tw2' has elapsed, which are the same as those in the present application, and therefore will not be described here.

[0053] In the comparative example shown in FIG. 4A, Voff is 0V, and the difference between Von and Voff is smaller than in this example. Therefore, in the comparative example, even if the first pulse gate voltage is applied after the period Tw2' has elapsed, the value of dV / dt does not become large enough, and the reverse bias safe operation area RBSOA cannot be measured. Therefore, in the comparative example, a third pulse gate voltage is required to measure the reverse bias safe operation area RBSOA.

[0054] 4B is a graph showing a test method for the reverse bias safe operating area (RBSOA) of a device under test in a comparative example. In the comparative example shown in FIG. 4B, the off-voltage (Voff) is set to 0 V or less, similar to the embodiment shown in FIG.

[0055] 4B, a third pulse of gate voltage is applied during a period Tw4. ​​The period Tw4 is determined based on the period until the collector current Ic flowing through the DUT3 increases to the first reference current I1 required for measuring the reverse bias safe operating area RBSOA.

[0056] 4B, there is no period during which the on-voltage Von is applied before the period Tw4, and therefore, unlike the embodiment shown in FIG 3, the collector current Ic increases at a constant rate up to the first reference current I1.

[0057] In this example, the collector current Ic increases at a steep first rate of change, and then increases to the first reference current I1 at a second rate of change that is gentler than the first rate of change, so that the collector current Ic can be increased to the first reference current I1 in a shorter period than in the comparative example of FIG. 4B. That is, the period Tw3 in this example is shorter than the period Tw4 in the comparative example. As a result, in this example, the reverse bias safe operating area RBSOA can be measured in a shorter measurement time than when it is measured alone.

[0058] 5A is a flowchart showing an outline of a method for testing a device under test according to the present embodiment. The method includes step S100 of applying a second pulse of gate voltage, step S110 of waiting until noise falls below a threshold, step S120 of applying a first pulse of gate voltage, and step S130 of analyzing the obtained data.

[0059] In step S100, a second pulse of gate voltage is applied to the DUT 3. As a result, a collector current Ic starts to flow through the DUT 3 according to the power supply voltage Vcc and the self-inductance L of the inductive load circuit 21. When the collector current Ic reaches a predetermined second reference current I2, the application of the gate voltage is released, and the turn-off loss Eoff of the DUT 3 is measured based on the collector current Ic during the falling period of the collector current Ic.

[0060] In step S110, after the second pulse gate voltage is turned off, energy corresponding to the off current Ioff flowing through the inductive load circuit 21 is stored. This makes it possible to increase the collector current Ic at a first rate of change in step S130 where a first pulse gate voltage is applied, which will be described later.

[0061] In step S120, a waiting period of a predetermined period Tw2 is generated. The period Tw2 is determined according to the period until the noise caused by the sudden change in the gate voltage Vge becomes equal to or lower than a predetermined value. During this waiting period, data analysis and transfer may be performed.

[0062] In step S130, a first pulse of gate voltage is applied to the DUT 3. At this time, based on the energy stored in the inductive load circuit 21, the collector current Ic increases at a first rate of change, and the turn-on loss Eon of the DUT 3 is measured based on the collector current Ic during the rising period of the collector current Ic. After that, the first pulse of gate voltage is applied until the collector current Ic increases to a predetermined first reference current I1, and then the application of the gate voltage is released, and the reverse bias safe operating area RBSOA of the DUT 3 is measured based on the collector current Ic during the falling period of the collector current Ic.

[0063] In step S140, various data measured in steps S100 to S130 are analyzed. This provides data on the turn-off loss Eoff, turn-on loss Eon, and reverse bias safe operating area RBSOA of the DUT 3. The data may be analyzed by the measurement device, or may be transferred from the measurement device to a separate analysis device and analyzed by the separate analysis device.

[0064] 5B is a flow chart showing an outline of a test method for a device under test of a comparative example. The comparative example differs from this example in that it includes step S540 for switching the gate voltage value, step S550 for applying a third pulse gate voltage, and step S560 for performing data analysis. In the following, steps S500 and S510 are similar to steps S100 and S120 of this example, so that a description thereof will be omitted.

[0065] In step S520, a first pulse gate voltage is applied to the DUT 3. As described above, in step S520 of the comparative example, the reverse bias safe operating area RBSOA cannot be measured using the first pulse gate voltage, and therefore, this step differs from step S120 in Fig. 5A in that only the turn-on loss Eon is measured.

[0066] In step S530, data analysis is performed on the turn-off loss Eoff and the turn-on loss Eon measured based on the gate voltage of the second pulse and the gate voltage of the first pulse. Step S530 of the comparative example differs from step S130 in FIG. 5A in that the measurement result of the reverse bias safe operating area RBSOA is not analyzed.

[0067] In step S540, the gate voltage value is switched. Specifically, the off voltage Voff, which has been set to 0 V in order to measure the turn-off loss Eoff and the turn-on loss Eon, is set to 0 V or less in order to measure the reverse bias safe operating area RBSOA.

[0068] In step S550, a third pulse of gate voltage is applied to the DUT 3. As is clear from Fig. 5B, although there is a step of applying a gate voltage before step S550, there is no step corresponding to step S110 of storing energy in this example. Therefore, in step S550, the collector current Ic increases linearly according to the power supply voltage Vcc and the self-inductance L of the inductive load circuit 21.

[0069] In step S550, a third pulse of gate voltage is applied until the collector current Ic increases to a predetermined first reference current I1, and then the application of the gate voltage is released, and the reverse bias safe operating area RBSOA of DUT3 is measured based on the collector current Ic during the falling period of the collector current Ic.

[0070] In step S560, various data measured in steps S500 to S550 are analyzed. This provides data on the turn-off loss Eoff, turn-on loss Eon, and reverse bias safe operating area RBSOA of the DUT 3. The data may be analyzed by the measurement device, or may be transferred from the measurement device to a separate analysis device and analyzed by the separate analysis device.

[0071] Here, in the comparative example shown in Fig. 5B, data including the measurement results of the turn-off loss Eoff and the turn-on loss Eon measured based on the gate voltage of the second pulse and the gate voltage of the first pulse, and data including the measurement result of the reverse bias safe operating area RBSOA measured based on the gate voltage of the third pulse are obtained. On the other hand, in the present example shown in Fig. 5A, all three measurement results are obtained based on the gate voltage of the second pulse and the gate voltage of the first pulse, so the number of measurement data is reduced.

[0072] Generally, tests related to these switching characteristics require resolution on the microsecond scale, so the volume of each measurement data is often large. In this example, the amount of measurement data per DUT3 can be reduced, so the data volume can be reduced and the time required for data transfer, etc. can be reduced, improving the throughput of chip tests.

[0073] Although the present invention has been described above using the embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It is clear to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the description of the claims that such modifications and improvements can also be included in the technical scope of the present invention.

[0074] It should be noted that the order of execution of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before," "prior to," etc., and may be realized in any order unless the output of a previous process is used in a later process. Even if the operational flow in the claims, specifications, and drawings is explained using "first," "next," etc. for convenience, it does not mean that it is essential to perform the process in this order. [Explanation of symbols]

[0075] 1 power supply section, 2 load section, 3 DUT, 4 voltage application section, 5 measurement section, 21 inductive load circuit, 22 diode, 23 power semiconductor element, 24 fixed power supply, 40 variable power supply, 45 gate resistor, 51 voltmeter, 52 ammeter, 100 test equipment

Claims

1. 1. A method for testing a device under test that is a switching element, comprising the steps of: applying a predetermined first pulse of gate voltage to the device under test; measuring a turn-on loss of the device under test based on a collector current during a rising period of a collector current flowing through the device under test in response to the first pulse; measuring a reverse bias safe operating area of ​​the device under test based on the collector current during a falling edge of the collector current in response to the first pulse; Equipped with Test method for device under test.

2. prior to the step of applying the first pulse of gate voltage to the device under test, applying a second pulse of a gate voltage to the device under test; measuring a turn-off loss of the device under test based on the collector current during a falling edge period of the collector current flowing through the device under test in response to the second pulse; Equipped with 2. The method for testing a device under test according to claim 1.

3. The step of applying the first pulse of gate voltage includes applying the first pulse of gate voltage for a time until the collector current increases to a first reference current required for measuring the reverse bias safe operating area.

3. The method for testing a device under test according to claim 2.

4. The step of applying the second pulse of gate voltage includes the step of applying the second pulse of gate voltage until the collector current increases to a second reference current smaller than the first reference current, storing energy according to a current flowing through an inductive load circuit after turning off the gate voltage of the second pulse; In the step of applying the first pulse gate voltage, the collector current increases at a first rate of change based on the energy stored in the inductive load circuit, and then the collector current increases to the first reference current at a second rate of change that is slower than the first rate of change.

4. The method for testing a device under test according to claim 3.

5. A time for applying the gate voltage of the first pulse is shorter than a time for applying the gate voltage of the second pulse.

4. The method for testing a device under test according to claim 3.

6. The time between the step of applying the second pulse of gate voltage and the step of applying the first pulse of gate voltage is 1 μs or more and 100 μs or less.

6. The method for testing a device under test according to claim 5.

7. A test apparatus for a device under test that is a switching element, comprising: A power supply unit; A load section connected in series with the device under test; a voltage application section that applies a gate voltage to the device under test; a measurement section for measuring a characteristic of the device under test based on a collector current flowing through the device under test; Equipped with the voltage application section applies a gate voltage of a first pulse to the device under test; The measurement section is configured to measure a turn-on loss of the device under test based on the collector current during a rising period of the collector current flowing through the device under test in response to the first pulse, and to measure a reverse bias safe operating area of ​​the device under test based on the collector current during a falling period of the collector current in response to the first pulse. Test equipment for the device under test.

8. the voltage application section is configured to apply a gate voltage of a second pulse determined in advance to the device under test; The measurement section is configured to measure a turn-off loss of the device under test based on the collector current during a falling period of the collector current in response to the second pulse.

8. The device under test testing apparatus according to claim 7.

9. the voltage application unit is configured to apply the first pulse of gate voltage for a time until the collector current increases to a first reference current required for measuring the reverse bias safe operating area; 9. The device under test testing apparatus according to claim 8.

10. the voltage application unit applies the second pulse of gate voltage until the collector current increases to a second reference current smaller than the first reference current; the load section has an inductive load circuit that stores energy according to a current flowing through the load section after the gate voltage of the second pulse is turned off, when the first pulse gate voltage is applied, the collector current increases at a first rate of change based on the energy stored in the inductive load circuit, and then the collector current increases to the first reference current at a second rate of change that is slower than the first rate of change.

10. The device under test testing apparatus according to claim 9.

11. The load section is provided between the positive terminal of the power supply section and the device under test.

8. The device under test testing apparatus according to claim 7.

12. The load section includes a diode connected in series with the device under test and in parallel with the inductive load circuit. The device under test testing apparatus according to claim 10.

13. The load section includes a power semiconductor element connected in series with the device under test and provided in anti-parallel with the diode. The device under test testing apparatus according to claim 12.

14. The rated current and rated voltage of the power semiconductor element are higher than the rated current and rated voltage of the device under test. The device under test testing apparatus according to claim 13.

15. The load section does not include a power semiconductor element. The device under test testing apparatus according to claim 12.

16. The device under test is any one of an IGBT, a MOSFET, and a bipolar transistor.

8. The device under test testing apparatus according to claim 7.

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