Semiconductor device and semiconductor chip

Abstract

To suppress increases in design and manufacturing costs while suppressing signal collisions by devising a circuit to enable stacking of identical semiconductor chips.SOLUTION: Each of a plurality of semiconductor chips connected to each other and stacked by through electrodes includes: a gate circuit that outputs a first selection signal to an internal circuit when a control input terminal shows an effective level; a decoder circuit that sets either of output terminals to an effective level according to a logical value of a second selection signal; and a plurality of first program elements disposed between the plurality of output terminals and the control input terminal. Each of the semiconductor chips is set to have one of the first program elements in a conductive state, and the internal circuit operates by receiving the first selection signal output from the gate circuit when the first program element connected to the output terminal set to the effective level according to the logical value of the second selection signal is in a conductive state. The first program elements in a conductive state are different among the plurality of semiconductor chips.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] A method is known for manufacturing a semiconductor device by stacking semiconductor substrates on which a plurality of semiconductor chips are formed, connecting the semiconductor chips constituting the semiconductor substrates in different layers so that signals can be transmitted, and then dicing the semiconductor chip portions into individual pieces. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2010 / 032729 [Patent Document 2] JP 2015-164160 A Summary of the Invention [Problem to be solved by the invention]

[0004] For example, when signal terminals of multiple stacked memory chips are connected by through electrodes to form a semiconductor device with a large memory capacity, some of the signals are transmitted to each memory chip using different through electrodes to avoid collision of control signals or data signals. In this case, since the positions of some of the signal terminals are different for each memory chip, there is a problem that memory chips with the same circuits using the same design data cannot be stacked. If the memory chips to be stacked are not the same, photomasks such as reticles cannot be shared, which increases the design cost and manufacturing cost.

[0005] In addition, even when semiconductor substrates on which multiple memory chips are formed are stacked and connected with through electrodes, and then the memory chip portions are separated, the positions of some of the signal terminals in the memory chip portions differ for each semiconductor substrate, which makes it impossible to standardize photomasks such as reticles, resulting in problems such as increased design costs and manufacturing costs.

[0006] Therefore, an object of the present invention is to prevent signal collisions while suppressing increases in design costs and manufacturing costs by enabling identical semiconductor chips to be stacked through circuit innovation. [Means for solving the problem]

[0007] A semiconductor device according to one aspect of the present invention includes a plurality of semiconductor chips stacked on one another, each of the semiconductor chips having a first selection terminal for receiving a first selection signal and one or more second selection terminals for receiving a second selection signal, and a plurality of through electrodes penetrating the plurality of semiconductor chips and connected to the first selection terminal and the second selection terminal of the plurality of semiconductor chips, respectively, each of the plurality of semiconductor chips having an internal circuit that operates upon receiving the first selection signal, a gate circuit having a control input terminal and outputting the first selection signal to the internal circuit when the control input terminal indicates an active level, and a plurality of output terminals, and switching the logic level of the first selection signal to a logic level corresponding to the logic level of the second selection signal. The semiconductor chip has a decoder circuit that sets one of the output terminals to an active level, and a plurality of first program elements that are respectively arranged between the plurality of output terminals and the control input terminal, wherein each of the plurality of semiconductor chips has one of the plurality of first program elements set to a conductive state, and the internal circuit of each of the plurality of semiconductor chips operates in response to the first selection signal output from the gate circuit when the first program element connected to the output terminal that is set to the active level in accordance with the logical value of the second selection signal is in a conductive state, and the first program elements in a conductive state are different from one another in the plurality of semiconductor chips. Effect of the Invention

[0008] According to the present invention, by enabling identical semiconductor chips to be stacked by devising a circuit, it is possible to prevent signal collisions while suppressing increases in design costs and manufacturing costs. [Brief description of the drawings]

[0009] [Figure 1]FIG. 1 is a partial perspective view illustrating a problem with a semiconductor device including a plurality of stacked semiconductor chips. [Diagram 2] 1 is an exploded perspective view showing an example of a semiconductor device according to a first embodiment of the present invention. [Diagram 3] 3 is a diagram illustrating an example of a chip selection decoder circuit of FIG. 2 and its operation. [Figure 4] 3 is a cross-sectional view showing an outline of a laminated structure of the semiconductor device of FIG. 2. [Diagram 5] 3 is a diagram showing an example of a command for operating the semiconductor device of FIG. 2. [Figure 6] 3 is a timing chart showing an example of a read operation of the semiconductor device of FIG. 2. [Figure 7] FIG. 11 is an exploded perspective view showing an example of a semiconductor device according to a second embodiment of the present invention. [Figure 8] 8 is a diagram illustrating an example of a chip selection decoder circuit of FIG. 7 and its operation. [Figure 9] 8 is a cross-sectional view showing an outline of a laminated structure of the semiconductor device of FIG. 7. [Figure 10] FIG. 11 is an exploded perspective view showing an example of a semiconductor device according to a third embodiment of the present invention. [Figure 11] 11 is a diagram showing an example of a connection between an internal data bus and pads of the semiconductor chip of FIG. 10. [Figure 12] 12 is a circuit diagram showing an example of a data input / output circuit of FIG. 11. [Figure 13] 13 is a diagram illustrating a setting example of the data input / output circuit of FIG. 12. [Figure 14] FIG. 13 is a circuit diagram showing an example of a data input / output circuit of each semiconductor chip mounted on a semiconductor device according to a fourth embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, the embodiments will be described with reference to the drawings. In each drawing, the same components are given the same reference numerals, and duplicated explanations may be omitted. Reference numerals indicating signal names are also used to indicate signal line names or terminal names. A single signal line may be composed of multiple lines. For example, one data line for one bit may be a complementary data line.

[0011] Fig. 1 is a partial perspective view for explaining a problem of a semiconductor device including a plurality of stacked semiconductor chips. The semiconductor device 100 shown in Fig. 1 has four stacked semiconductor chips CP1-CP4. The semiconductor chips CP1-CP4 may be stacked in this order on a substrate such as an interposer (not shown). In the following, when the semiconductor chips CP1-CP4 are described without distinction, they are also referred to as semiconductor chips CP.

[0012] For example, each of the semiconductor chips CP1-CP4 is a Synchronous Dynamic Random Access Memory (SDRAM) chip having a memory core MCR and 1024-bit data terminals DQ (DQ0-DQ1023). The memory core MCR is an example of an internal circuit, a memory circuit, or a data retention circuit. In the semiconductor chips CP1-CP4, data terminals (pads PAD) with the same number are formed at the same position in a planar view and are connected to each other via a common Through Silicon Via (TSV). The pads PAD connected to the TSV are indicated by black squares. The TSV is an example of a through electrode.

[0013] The semiconductor chips CP1-CP4 each receive a chip select signal / CS1- / CS4, which is different for each semiconductor chip, via a dedicated TSV. For this reason, in the semiconductor chips CP1-CP4, chip select terminals / CS1- / CS4 (pads PAD) that receive the chip select signals / CS1- / CS4 are formed at different positions in a plan view. In the following, when the chip select signals / CS1- / CS4 are described without distinction, they are also referred to as the chip select signal / CS. Note that control signals and clock signals other than the chip select signal / CS are also used to access the semiconductor chips CP1-CP4, but are not described here.

[0014] In each semiconductor chip CP, a through hole called a through via TVIA is formed at a position corresponding to a TSV that transmits a chip select signal / CS of another semiconductor chip CP in a plan view. The through via TVIA is not electrically connected to the TSV in order to suppress an increase in parasitic capacitance connected to the TSV.

[0015] Each semiconductor chip CP operates when the corresponding chip select signal / CS is activated to a low level, and in a read operation, it outputs 1024-bit data signals DQ in parallel, and in a write operation, it inputs 1024-bit data signals DQ in parallel. Since multiple chip select signals / CS are not activated to a low level at the same time, the semiconductor chips CP1-CP4 operate independently without overlapping. This prevents collisions between data signals DQ input / output to multiple semiconductor chips CP.

[0016] The semiconductor chips CP1-CP4 mounted on the semiconductor device 100 shown in FIG. 1 have different positions of the chip select terminals / CS and the through vias TVIA. Therefore, it is necessary to use different photomasks (reticles) for manufacturing the semiconductor chips CP1-CP4, and the manufacturing process is different for each of the semiconductor chips CP1-CP4. In addition, the manufactured semiconductor chips CP1-CP4 need to be managed separately, which complicates production management and increases management costs. As a result, the design cost and manufacturing cost of the semiconductor chips CP increase, and the manufacturing cost of the semiconductor device 100 increases.

[0017] (First embodiment) FIG. 2 is an exploded perspective view showing an example of a semiconductor device according to a first embodiment of the present invention. The same elements as those in FIG. 1 are given the same reference numerals, and detailed description thereof will be omitted. The semiconductor device 102 shown in FIG. 2 has four stacked semiconductor chips CP1-CP4. For example, each of the semiconductor chips CP1-CP4 is a DDR (Double Data Rate) type SDRAM chip having 1024-bit data terminals DQ (DQ0-DQ1023). In the semiconductor chips CP1-CP4, data terminals (pads PAD) having the same number are formed at the same position in a plan view, as in FIG. 1, and are connected to each other via a common TSV.

[0018] In addition, each of the semiconductor chips CP1-CP4 may be manufactured as a semiconductor wafer including a plurality of semiconductor chip portions, and then stacked in the wafer state, and the terminals of the plurality of semiconductor chip portions of the two semiconductor wafers may be connected to each other by TSVs each time the semiconductor chips are stacked. That is, the semiconductor device 102 may be manufactured by a WoW (Wafer on Wafer) method. In this case, as described later, each of the semiconductor chips CP1-CP4 is manufactured as a chip having the same circuit using a common photomask (reticle), so that an increase in design cost and manufacturing cost can be suppressed.

[0019] The semiconductor chips CP1-CP4 in Fig. 2 have chip select terminals / CS (pads PAD) that receive a common chip select signal / CS via a common TSV. The semiconductor chips CP1-CP4 in Fig. 2 also have die select terminals DS1, DS0 (pads PAD) that receive die select signals DS1, DS0 via two common TSVs. The chip select signal / CS is an example of a first selection signal, and the chip select terminal / CS is an example of a first selection terminal. The die select signals DS1, DS0 are an example of a second selection signal, and the die select terminals DS1, DS0 are an example of a second selection terminal.

[0020] In the semiconductor chips CP1-CP4, the chip select terminal / CS and the die select terminals DS1, DS0, which are connected to each other via TSVs, are formed at the same position in a plan view. In the following, when the die select signals DS1, DS0 and the die select terminals DS1, DS0 are described without distinction, they are also referred to as the die select signal DS and the die select terminal DS. Note that, to access the semiconductor chips CP1-CP4, control signals and clock signals other than the chip select signal / CS and the die select signals DS1, DS0 are also used, but are not described here.

[0021] Each of the semiconductor chips CP1-CP4 has a chip select decoder circuit CSDEC1 connected to a chip select terminal / CS and a die select terminal DS. The 2-bit value of the die select signals DS1 and DS0 indicates to which of the four semiconductor chips CP1-CP4 the chip select signal / CS is to be supplied.

[0022] The chip select decoder circuit CSDEC1 of each semiconductor chip CP outputs the chip select signal / CS to the internal circuit as the chip select signal CSX when the logical values ​​of the die select signals DS1 and DS0 indicate the semiconductor chip CP. The chip select decoder circuit CSDEC1 of each semiconductor chip CP masks the input of the chip select signal / CS when the logical values ​​of the die select signals DS1 and DS0 do not indicate the semiconductor chip CP. An example of the chip select decoder circuit CSDEC1 is shown in FIG. 3.

[0023] As shown in Fig. 2, in the semiconductor chips CP1-CP4, the data terminals DQ, the chip select terminals / CS, the die select terminals DS, and the clock terminals and other control terminals (not shown) are formed at the same positions as one another in a plan view. The chip select decoder circuits CSDEC1 of the semiconductor chips CP1-CP4 are switched in operation by a program element as described in Fig. 3, but are the same circuit as one another.

[0024] That is, the semiconductor chips CP1-CP4 mounted on the semiconductor device 102 are chips with the same circuits, using the same design data, and the semiconductor chips CP1-CP4 are manufactured without distinction using a common photomask (reticle). This makes it possible to use multiple semiconductor chips CP manufactured on a wafer using a semiconductor manufacturing process in any stacking stage of the semiconductor device 102. As a result, design costs and manufacturing costs can be reduced compared to the case where different semiconductor chips CP are designed and manufactured for each stacking stage. In addition, it is possible to prevent production management from becoming complicated, and to prevent an increase in management costs.

[0025] 3 is a diagram showing an example of the chip selection decoder circuit CSDEC1 of FIG. 2 and its operation. The chip selection decoder circuit CSDEC1 has a decoder circuit DEC1, four fuses F1-F4, an inverter IV, and a NAND gate. The decoder circuit DEC1 has two inverters IV and four NOR gates. The fuses F1-F4 are an example of a first program element, and the NAND gate is an example of a gate circuit.

[0026] The chip select decoder circuit CSDEC1 outputs a high level from one of four NOR gates according to the logical values ​​of the die select signals DS1 and DS0, and outputs a low level from the other NOR gates. In the chip select decoder circuit CSDEC1, the output of each NOR gate is an example of an output terminal, and the high level output by each NOR gate is an example of an effective level. The NAND gate receives the output levels of the fuses F1-F4 and a signal that is an inverted logical value of the chip select signal / CS, and outputs the chip select signal CSX.

[0027] The fuses F1-F4 are arranged between the outputs of the four NOR gates and one input of the NAND gate. The blowing specifications (program specifications) of the fuses F1-F4 are different for each of the semiconductor chips CP1-CP4. One input of the NAND gate is an example of a control input terminal.

[0028] As shown in the table in the lower left of FIG. 3, in the semiconductor chip CP1, the fuses F2-F4 are cut off and only the fuse F1 is maintained in a conductive state. In the semiconductor chip CP2, the fuses F1, F3, and F4 are cut off and only the fuse F2 is maintained in a conductive state. In the semiconductor chip CP3, the fuses F1, F2, and F4 are cut off and only the fuse F3 is maintained in a conductive state. In the semiconductor chip CP4, the fuses F1-F3 are cut off and only the fuse F4 is maintained in a conductive state.

[0029] The chip select decoder circuit CSDEC1 of the semiconductor chip CP1 sets one input of the NAND gate to a high level via the fuse F1 only when the logic level of the die select signals DS1 and DS0 is "LL", and outputs the chip select signal / CS as the chip select signal CSX. The chip select decoder circuit CSDEC1 of the semiconductor chip CP2 sets one input of the NAND gate to a high level via the fuse F2 only when the logic level of the die select signals DS1 and DS0 is "LH", and outputs the chip select signal / CS as the chip select signal CSX. The high level of one input of the NAND gate is an example of a valid level.

[0030] The chip select decoder circuit CSDEC1 of the semiconductor chip CP3 sets one input of the NAND gate to a high level via the fuse F3 only when the logic level of the die select signals DS1 and DS0 is "HL", and outputs the chip select signal / CS as the chip select signal CSX. The chip select decoder circuit CSDEC1 of the semiconductor chip CP4 sets one input of the NAND gate to a high level via the fuse F2 only when the logic level of the die select signals DS1 and DS0 is "HH", and outputs the chip select signal / CS as the chip select signal CSX.

[0031] 3, when the logic levels of the die select signals DS1 and DS0 are "LL," the semiconductor chip CP1 becomes selectable, and when the logic levels of the die select signals DS1 and DS0 are "LH," the semiconductor chip CP2 becomes selectable. When the logic levels of the die select signals DS1 and DS0 are "HL," the semiconductor chip CP3 becomes selectable, and when the logic levels of the die select signals DS1 and DS0 are "HH," the semiconductor chip CP4 becomes selectable.

[0032] Therefore, by stacking the four semiconductor chips CP after programming the fuses F1-F4 of the four semiconductor chips CP having the same circuit, each semiconductor chip CP can be selectively operated according to the logical values ​​of the die select signals DS1 and DS0. In other words, the chip select signal / CS common to the four semiconductor chips CP1-CP4 can be supplied to only one semiconductor chip CP.

[0033] The fuses F1-F4 mounted on the chip selection decoder circuit CSDEC1 may be programmed in a test process for testing the semiconductor chips CP in a wafer state after the pre-processing of the semiconductor chips CP is completed. The test process is included in the manufacturing process of the semiconductor chips CP.

[0034] For example, the semiconductor device 102 has a plurality of normal memory blocks including normal memory cells, a redundant memory block including redundant memory cells, a redundant circuit that replaces a normal memory block including a defective normal memory cell with the redundant memory block, and a fuse. For example, by programming the fuse corresponding to an address indicating the defective normal memory block, the defect can be relieved by the redundant circuit. The fuse used to relieve the defective normal memory block is an example of a second program element.

[0035] The fuses F1-F4, which are provided to operate the stacked semiconductor chips CP1-CP4 individually, are programmed when defective normal memory cells are relieved in the test process. By programming the fuses F1-F4 using the test process of the semiconductor chips CP1-CP4, it is possible to program the fuses F1-F4 that determine the stacking level without adding a new process. As a result, it is possible to suppress an increase in the manufacturing cost of the semiconductor chips CP.

[0036] The fuses of the redundant circuit and the fuses F1-F4 of the chip selection decoder circuit CSDEC1 are preferably of the same type. These fuses may be current fuses that cut off wiring with a current, OTPROMs (One Time Programmable Read Only Memory) that semi-permanently change the threshold value of a transistor, or laser fuses that are cut off with a laser.

[0037] When the semiconductor device 102 has two semiconductor chips CP, the two semiconductor chips CP are set to the program states of the fuses F1-F4 of the semiconductor chips CP1 and CP2 shown in the lower left of Fig. 3. This makes it possible to enable the chip select signal / CS of either the semiconductor chip CP1 or CP2 depending on the logical values ​​of the die select signals DS1 and DS0.

[0038] Similarly, when the semiconductor device 102 has three semiconductor chips CP, the three semiconductor chips CP are set to the program states of the fuses F1-F4 of the semiconductor chips CP1-CP3 shown in the lower left of Fig. 3. This makes it possible to enable the chip select signal / CS of any of the semiconductor chips CP1-CP3 according to the logical values ​​of the die select signals DS1 and DS0.

[0039] 3 on each semiconductor chip CP, it is possible to manufacture a semiconductor device 102 in which two to four semiconductor chips CP, which is equal to or less than the number of fuses F1-F4, are stacked. In other words, it is possible to manufacture semiconductor devices 102 with different memory capacities using semiconductor chips CP having the same circuits using the same design data.

[0040] Fig. 4 is a cross-sectional view showing an outline of the stacked structure of the semiconductor device 102 of Fig. 2. The semiconductor chips CP1-CP4 are stacked on a substrate such as an interposer INTP, and are connected to each other via TSVs. Signal terminals such as a chip select terminal / CS and a data terminal DQ, which are connected to each other via the TSVs, are commonly connected to the semiconductor chips CP1-CP4. The TSVs have through conductors TC that pass through through holes formed in each of the semiconductor chips CP1-CP4.

[0041] For example, the TSV of the semiconductor device 102 employs a bumpless TSV method that connects the semiconductor chips CP without arranging bumps. Therefore, compared to the case where the TSVs formed on each semiconductor chip CP are connected via bumps, the distance between the semiconductor chips CP can be made smaller, and the parasitic capacitance can be made smaller. Therefore, for example, even when the chip select signal / CS and the data signal DQ, etc. are each supplied to all the semiconductor chips CP1-CP4 via a common TSV, the parasitic capacitance of the TSV that transmits the chip select signal / CS can be made smaller. As a result, the performance degradation due to the increase in the parasitic capacitance of the TSV can be reduced.

[0042] In the bumpless TSV method, the wafer is polished to a thickness of several microns. Therefore, the diameter of the through-hole of the semiconductor chip CP forming the TSV can be set to, for example, about 1 to 5 microns, and the distance between the semiconductor chips CP can be set to about one tenth of the distance when bumps are formed. As a result, in the bumpless TSV method, the parasitic capacitance of the TSV can be reduced by one order of magnitude or more compared to the parasitic capacitance of the bumped TSV method, and performance degradation due to an increase in the parasitic capacitance of the TSV that supplies a common chip select signal / CS to the semiconductor chips CP1-CP4 can be reduced.

[0043] Each of the semiconductor chips CP1-CP4 has a substrate SUB on which elements such as transistors (not shown) are formed, and a wiring layer WL provided on the substrate SUB. Various wires W and pads PAD are formed in the wiring layer WL. Although only the wiring layer WL closest to the substrate SUB is shown in FIG. 4, the semiconductor device 102 has multiple wiring layers WL on the substrate SUB. The program state of the fuses F1-F4 of each of the semiconductor chips CP1-CP4 is the same as the program state shown in FIG.

[0044] Fig. 5 is a diagram showing an example of a command for operating the semiconductor device 102 of Fig. 1. In Fig. 5, the clock enable signal CKE, the chip select signal / CS, the row address strobe signal / RAS, the column address strobe signal / CAS, and the write enable signal / WE are shown as parts of the command. "-" indicates that either high level H or low level L is acceptable, and "n-1" of the clock enable signal CKE indicates the state one cycle before.

[0045] Hereinafter, the clock enable signal CKE, the chip select signal / CS, the row address strobe signal / RAS, the column address strobe signal / CAS, and the write enable signal / WE are also referred to as the CKE signal, the / CS signal, the / RAS signal, the / CAS signal, and the / WE signal. The CKE signal is assumed to be at high level H in the clock cycle before a command is supplied.

[0046] When the / CS signal supplied to the semiconductor chip CP is at high level H, the command decoder of the semiconductor chip CP detects a device deselect command DSEL that sets the semiconductor chip CP to a deselected state. When the / CS signal, / RAS signal, / CAS signal, and / WE signal supplied to the semiconductor chip CP are at low level L, low level L, high level H, and high level H, respectively, the command decoder of the semiconductor chip CP detects an active command ACTV. The semiconductor chip CP that detects the active command ACTV activates a word line indicated by an address signal received together with the active command ACTV.

[0047] When the / CS signal, / RAS signal, / CAS signal, and / WE signal supplied to the semiconductor chip CP are low level L, high level H, low level L, and high level H, respectively, the command decoder of the semiconductor chip CP detects a read command RD. The semiconductor chip CP that detects the read command RD reads out the data signal DQ held by the memory cell connected to the activated word line, and outputs it to the data terminal DQ.

[0048] When the / CS signal, / RAS signal, / CAS signal, and / WE signal supplied to the semiconductor chip CP are low level L, high level H, low level L, and low level L, respectively, the command decoder of the semiconductor chip CP detects a write command WR. The semiconductor chip CP that detects the write command WR writes the data signal DQ received at the data terminal DQ to a memory cell connected to an activated word line.

[0049] Fig. 6 is a timing chart showing an example of a read operation of the semiconductor device 102 of Fig. 1. Fig. 6 shows an example in which the read latency RL is set to "2" and the burst length is set to "4". It is assumed that the semiconductor chips CP1 and CP2 are in an active state.

[0050] The read latency RL indicates the number of clock cycles from when the read command RD is received until the data signal DQ is output to the data terminal DQ. The higher the frequency of the clock CK, the larger the read latency RL becomes. Some recent SDRAMs have a read latency RL of more than "5", but in Figure 6, the read latency RL is set to "2" to make the timing diagram easier to understand.

[0051] The burst length indicates the number of data signals DQ that are continuously output to the data terminals DQ in response to one read command RD. Since each semiconductor chip CP of the semiconductor device 102 is a DDR type SDRAM chip, the data signal DQ is output twice in one clock cycle.

[0052] At time t1, the semiconductor device 102 receives a read command RD along with die select signals DS1, DS0="LL". Due to the die select signals DS1, DS0="LL", the chip select signal / CS is supplied only to the semiconductor chip CP1. The semiconductor chip CP1 executes a read operation, and outputs data "D10", "D11", "D12", and "D13" to the data terminal DQ for two clock cycles from time t3 after the read latency RL. Each of the data "D10", "D11", "D12", and "D13" is 1024 bits and is output from the data terminal DQ of the semiconductor device 102 via the TSV.

[0053] At time t3, the semiconductor device 102 receives a read command RD together with die select signals DS1, DS0="LH". Due to the die select signals DS1, DS0="LH", the chip select signal / CS is supplied only to the semiconductor chip CP2. The semiconductor chip CP2 executes a read operation, and outputs data "D20", "D21", "D22", and "D23" to the data terminal DQ for two clock cycles from time t5 after the read latency RL. Each of the data "D20", "D21", "D22", and "D23" is 1024 bits and is output from the data terminal DQ of the semiconductor device 102 via the TSV.

[0054] 6, the semiconductor device 102 can continuously output data signals DQ read from different semiconductor chips CP1 and CP2 from the data terminal DQ by receiving a read command RD every two clock cycles. That is, an operation similar to the bank switching operation of a semiconductor memory having a plurality of banks can be realized. In other words, each of the semiconductor chips CP1 and CP2 can be operated as a bank. The read commands RD may be continuously supplied to the same semiconductor chip CP.

[0055] As described above, in this embodiment, by changing the program state of the fuses F1-F4 provided in each semiconductor chip CP for each semiconductor chip CP, even when semiconductor chips CP having identical circuits are stacked, one of the semiconductor chips CP can be selectively operated in accordance with the logical value of the die select signal DS.

[0056] This allows multiple semiconductor chips CP manufactured on a wafer using a semiconductor manufacturing process to be used in any stacking stage of the semiconductor device 102. As a result, it is possible to prevent production management from becoming complicated compared to a case in which semiconductor chips CP with different circuits are manufactured for each stacking stage, and it is possible to prevent an increase in management costs. Furthermore, by making it possible to stack semiconductor chips CP with the same circuits by ingenious circuit design, it is possible to prevent signal collisions and to prevent an increase in design costs and manufacturing costs.

[0057] By utilizing the test process for the semiconductor chip CP, which replaces defective circuits with redundant circuits by programming the fuses, it is possible to program the fuses F1-F4 that determine the stacking levels without adding a new process, thereby suppressing an increase in the manufacturing cost of the semiconductor chip CP.

[0058] The semiconductor chips CP whose number is equal to or less than the number of fuses F1-F4 provided in the chip selection decoder circuit CSDEC1 can be stacked to manufacture the semiconductor device 102. In other words, the semiconductor devices 102 having different memory capacities can be manufactured using the semiconductor chips CP having the same circuits and using the same design data.

[0059] By adopting the bumpless TSV method for the TSVs of the semiconductor device 102, it is possible to reduce the parasitic capacitance of the TSVs transmitting the chip select signal / CS and the data signal DQ, etc., even when a common chip select signal / CS and a data signal DQ, etc. are supplied to all the semiconductor chips CP via a common TSV. As a result, it is possible to reduce performance degradation due to an increase in the parasitic capacitance of the TSV.

[0060] Second Embodiment Fig. 7 is an exploded perspective view showing an example of a semiconductor device according to a second embodiment of the present invention. The same elements as those in Fig. 2 are given the same reference numerals and detailed description will be omitted. The semiconductor device 104 shown in Fig. 7 has eight semiconductor chips CP1-CP8 stacked on a substrate such as an interposer (not shown).

[0061] For example, each of the semiconductor chips CP1-CP8 is an SDRAM chip having 1024 bits DQ0-DQ1023, and is a semiconductor chip having the same circuit using the same design data. Each of the semiconductor chips CP1-CP8 is manufactured without distinction using a common photomask (reticle). Therefore, a plurality of semiconductor chips CP manufactured on a wafer using a semiconductor manufacturing process can be used in any stacking stage of the semiconductor device 104. As a result, as with the semiconductor device 102 in FIG. 2, it is possible to suppress the production management from becoming complicated and the management cost from increasing, compared to the case where semiconductor chips CP having different circuits are manufactured for each stacking stage.

[0062] Each of the semiconductor chips CP1-CP8 has the same configuration as each of the semiconductor chips CP1-CP4 in Fig. 2, except that it has three die select terminals DS2, DS1, and DS0, and has a chip select decoder circuit CSDEC2 instead of the chip select decoder circuit CSDEC1. The bumpless TSV method is also adopted for the TSV of the semiconductor device 104, as in the semiconductor device 102 in Fig. 2.

[0063] Each of the semiconductor chips CP1-CP8 may be manufactured as a semiconductor wafer including multiple semiconductor chip portions, similar to each of the semiconductor chips CP1-CP4 shown in Figure 2, and then stacked sequentially in wafer form, with the terminals of the multiple semiconductor chip portions of the two semiconductor wafers being connected to each other by TSVs each time they are stacked.

[0064] The number of stages of semiconductor chips CP stacked in the semiconductor device 104 is not limited to eight, as long as it is more than one. The die select terminal DS is set to a number of bits corresponding to the number of stages of semiconductor chips CP to be stacked, and the chip select decoder circuit is designed with logic corresponding to the number of stages of semiconductor chips CP to be stacked.

[0065] The number of die select terminals DS is preferably set according to the number of stacked semiconductor chips CP that is expected in advance. For example, by programming fuses F1-F8 of a chip selection decoder circuit CSDEC2 shown in FIG. 8, which will be described later, according to the number of stacked semiconductor chips CP, the number of stacked semiconductor chips CP can be set to any number of stages from 2 to 8. In other words, semiconductor devices 104 with various storage capacities can be manufactured and shipped according to the number of stacked chips having the same circuit using the same design data.

[0066] In addition, in the semiconductor device 104, since only one of the eight semiconductor chips CP1-CP8 operates, even when the number of stacked stages is increased to increase the memory capacity, the power consumption can be made equivalent to that of the semiconductor device 102 in Fig. 2. The commands for operating the semiconductor device 104 are the same as those in Fig. 5. The timing diagram of the read operation of the semiconductor device 104 is the same as that in Fig. 6, except that a die select signal DS2 is added.

[0067] FIG. 8 is a diagram showing an example of the chip selection decoder circuit CSDEC2 of FIG. 7 and its operation. The same elements as those in FIG. 3 are given the same reference numerals and detailed description is omitted. The chip selection decoder circuit CSDEC2 has a decoder circuit DEC2, eight fuses F1-F8, an inverter IV, and a NAND gate. The decoder circuit DEC2 has three inverters IV and eight NOR gates. The fuses F1-F8 are an example of a first program element.

[0068] The chip select decoder circuit CSDEC2 outputs a high level from one of eight NOR gates according to the logical values ​​of the die select signals DS2, DS1, and DS0, and outputs a low level from the other NOR gates. The NAND gate receives the output levels of the fuses F1-F8 and a signal that is the inverted logical value of the chip select signal / CS, and outputs the chip select signal CSX.

[0069] The fuses F1-F8 are arranged between the outputs of the eight NOR gates and one input of the NAND gate, and different fuses F1-F8 are cut (programmed) for each of the semiconductor chips CP1-CP8. The program states of the fuses F1-F8 for each of the semiconductor chips CP1-CP8 are shown in the table at the bottom left of FIG. 8. The relationship between the die select signals DS2, DS1, DS0 and the selected semiconductor chip CP is shown in the table at the bottom right of FIG. The fuses F1-F8 mounted in the chip selection decoder circuit CSDEC2 are programmed in a test process in which the semiconductor device 104 in a wafer state is tested after the semiconductor device 104 is manufactured.

[0070] In the semiconductor device 104, after the fuses F1-F8 of the eight semiconductor chips CP having the same circuit are programmed, the eight semiconductor chips CP are stacked in sequence, so that each semiconductor chip CP can be selectively operated according to the logical value of the die select signals DS2-DS0. The fuses F1-F8 are programmed according to which layer of the semiconductor device 102 they are to be used in when relieving defects in a test process for testing the semiconductor device 104 in a wafer state after the semiconductor device 104 is manufactured. The fuses F1-F8 may be current fuses, OTPROMs, or laser fuses.

[0071] When the semiconductor device 104 is made up of four stacked semiconductor chips CP, the fuses F1-F8 are set to the program states of the semiconductor chips CP1-CP4 in the table at the bottom left of Fig. 8, and the die select signal DS2 is fixed to a low level L. This makes it possible to manufacture a semiconductor device 104 having the same functions as the semiconductor device 102 in Fig. 2 in which the four stacked semiconductor chips CP are formed.

[0072] Furthermore, when the semiconductor device 104 stacks six semiconductor chips CP, the fuses F1-F8 are set to the program states of the semiconductor chips CP1-CP6 in the table at the bottom left of FIG. 8, and the die select signals DS2-DS0 use logic levels that select the semiconductor chips CP1-CP6 in the table at the bottom right of FIG. 8.

[0073] 9 is a cross-sectional view showing an outline of the stacked structure of the semiconductor device of FIG. 7. The same elements as those in FIG. 4 are given the same reference numerals and detailed description is omitted. The semiconductor chips CP1-CP8 are stacked on a substrate such as an interposer INTP and connected to each other via TSVs. Each signal terminal such as a chip select terminal / CS connected to each other via TSVs is commonly connected to the semiconductor chips CP1-CP4. The stacked structure shown in FIG. 9 is the same as the stacked structure shown in FIG. 4, except that a die select terminal DS2 is added.

[0074] As described above, this embodiment can also provide the same effects as the above-mentioned embodiment. For example, by changing the program state of the fuses F1-F8 provided in each semiconductor chip CP for each semiconductor chip CP, one of the semiconductor chips CP can be selectively operated. This allows a plurality of semiconductor chips CP with the same circuit to be used in any stacking stage of the semiconductor device 104, and makes it possible to suppress the complexity of production management compared to the case where semiconductor chips CP with different circuits are manufactured for each stacking stage, and thus makes it possible to suppress an increase in management costs. Furthermore, by making it possible to stack semiconductor chips CP with the same circuit by devising the circuit, it is possible to suppress signal collisions while suppressing an increase in design costs and manufacturing costs.

[0075] (Third embodiment) Fig. 10 is an exploded perspective view showing an example of a semiconductor device according to a third embodiment of the present invention. The same elements as those in Fig. 2 are given the same reference numerals, and detailed description will be omitted. The semiconductor device 106 shown in Fig. 10 has four semiconductor chips CP1-CP4 stacked on a substrate such as an interposer (not shown). The bumpless TSV method is also adopted for the TSVs of the semiconductor device 106, as in the semiconductor device 102 of Fig. 2.

[0076] Each of the semiconductor chips CP1-CP4 may be manufactured as a semiconductor wafer including multiple semiconductor chip portions, similar to each of the semiconductor chips CP1-CP4 shown in Figure 2, and then stacked sequentially in wafer form, with the terminals of the multiple semiconductor chip portions of the two semiconductor wafers being connected to each other by TSVs each time they are stacked.

[0077] For example, each of the semiconductor chips CP1-CP4 is an SDRAM chip having 256-bit data terminals DQ0-DQ255, receiving a common chip select signal / CS at the chip select terminal / CS, and is a chip with the same circuit using the same design data. The chip select terminal / CS is an example of a selection terminal, and the chip select signal / CS is an example of a selection signal.

[0078] The semiconductor chips CP1-CP4 are manufactured without distinction using a common photomask (reticle) in the same manner as the semiconductor device 102 in Fig. 2. Therefore, a plurality of semiconductor chips CP manufactured on a wafer using a semiconductor manufacturing process can be used in any stacking stage of the semiconductor device 106.

[0079] In each semiconductor chip CP of the semiconductor device 106, the TSVs transmitting the 256-bit data signals DQ0-DQ255 are connected to dummy pads PADs indicated by white rectangles in the other three semiconductor chips CP. In each semiconductor chip CP, the pads PADs connected to the TSVs transmitting the data signals DQ0-DQ255 are indicated by black rectangles.

[0080] That is, the 256 TSVs connected to the data terminals DQ0-DQ255 of each of the semiconductor chips CP1-CP4 are connected in parallel to all of the semiconductor chips CP1-CP4. The dummy pads PAD are described in Fig. 11. In the actual layout of the semiconductor chip CP, four pads PAD are arranged adjacent to each other for each data terminal DQ number.

[0081] When the semiconductor device 106 receives a chip select signal / CS at low level L to perform a read operation, it operates the four semiconductor chips CP simultaneously and causes each semiconductor chip CP to output a 256-bit data signal DQ. Then, the semiconductor device 106 outputs a 1024-bit data signal DQ to the outside.

[0082] In the semiconductor device 106, the total number of bits Nm of the data signal DQ input / output to the outside, the number of bits Nc of the data signal DQ of each semiconductor chip CP, and the number of stages P of the stacked semiconductor chips CP have the relationship shown in formula (1). That is, the number of stages P of the stacked semiconductor chips CP, the total number of bits Nm of the data signal DQ input / output to the outside, and the number of bits Nc of the data signal DQ are determined at the time of designing the semiconductor chip CP. In FIG. 10, the total number of bits Nm is 1024, the number of bits Nc is 256, and the number of stages P is 4. Nm = Nc × P (1)

[0083] Fig. 11 is a diagram showing an example of a connection between the internal data bus IBUS and pads PAD of the semiconductor chip CP of Fig. 10. Although semiconductor chips CP1 and CP2 are shown in Fig. 11, the semiconductor chips CP3 and CP4 are similar to Fig. 11. As in Fig. 10, pads PAD shown by black rectangles indicate real pads PADs connected to TSVs that transmit data signals DQ, and pads PAD shown by white rectangles indicate dummy pads PADs connected to TSVs that transmit data signals DQ of other semiconductor chips CP.

[0084] Each semiconductor chip CP has an internal data bus IBUS including 256-bit data lines connected to the column selection switches CSW corresponding to the 256-bit data terminals DQ in Fig. 10. Each of the data lines of the internal data bus IBUS is connected to four pads PAD via input / output terminals IO of four data input / output circuits DIOC. Then, in each semiconductor chip CP, the 1024 pads PAD are connected to the 1024 data terminals DQ0-DQ1024 of the semiconductor device 106 via TSVs, respectively. The four data input / output circuits DIOC connected to one data line of the internal data bus IBUS is an example of a data input / output group.

[0085] In the semiconductor chip CP1, the 256 real pads PAD are indicated by the symbol P1, and the 768 dummy pads PAD are indicated by the symbols P2 to P4. In the semiconductor chip CP2, the 256 real pads PAD are indicated by the symbol P2, and the 768 dummy pads PAD are indicated by the symbols P1, P3, and P4. The real pads PAD of each semiconductor chip CP correspond to the data terminals DQ0-DQ255 of the semiconductor chip CP.

[0086] In each semiconductor chip CP, a data input / output circuit DIOC indicated by a rectangle including an x ​​and having an input / output terminal IO connected to a dummy pad PAD does not input / output a data signal DQ to the dummy pad PAD and sets the input / output terminal IO to a high impedance state. A data input / output circuit DIOC indicated by a rectangle including a vertical line and having an input / output terminal IO connected to a real pad PAD inputs / outputs a data signal DQ to / from the real pad PAD via the input / output terminal IO.

[0087] Each data input / output circuit DIOC programs fuses F11 and F12 shown in FIG. 12, which will be described later, to set the input / output terminal IO to a high impedance state or to a state in which a data signal DQ can be input / output to / from the input / output terminal IO.

[0088] 2, although not shown, the internal data bus IBUS of each semiconductor chip CP has 1024 lines corresponding to the data terminals DQ0-DQ1024 of the semiconductor device 102. In contrast, in the semiconductor device 106 of FIG. 11, the internal data bus IBUS of each semiconductor chip CP requires only one-fourth the number of the data terminals DQ0-DQ1024 of the semiconductor device 106.

[0089] In this way, in the semiconductor device 106, the number of internal data buses IBUS of each semiconductor chip CP can be reduced compared to the semiconductor device 102 of Fig. 2, so that the area of ​​the wiring region for the internal data buses IBUS can be reduced and the chip size can be reduced. As a result, the yield of the semiconductor chips CP can be improved compared to Fig. 2, and the cost of the semiconductor chips CP can be reduced. As a result, the cost of the semiconductor device 106 can be reduced.

[0090] Fig. 12 is a circuit diagram showing an example of the data input / output circuit DIOC of Fig. 11. The data input / output circuit DIOC has a plurality of inverters IV, latches LT1, LT2, an output buffer OBUF, an input buffer IBUF, a NOR gate, and fuses F11, F12. The fuses F11, F12 are examples of first program elements.

[0091] The output buffer OBUF has a p-channel MOS transistor PM1 and an n-channel MOS transistor NM1 connected in series between a power supply line VDDQ and a ground line VSSQ. The power supply line VDDQ is a power supply line for the data signal DQ, and the ground line VSSQ is a ground line for the data signal DQ.

[0092] The drain of the p-channel MOS transistor PM1 and the drain of the n-channel MOS transistor NM1 correspond to the input / output terminal IO and are connected to the TSV (FIG. 10) via the data terminal DQ (pad PAD). Hereinafter, the p-channel MOS transistor PM1 and the n-channel MOS transistor NM1 will be simply referred to as transistors PM1 and NM1.

[0093] The latch LT1 has an inverter IV which receives a data output signal DOUT obtained by inverting the logical value of the data output signal DOUTX output to the data output line DOUTX from the memory core MCR in Fig. 10, and a NAND gate which feeds back the output of the inverter IV received at one input to the input of the inverter IV. The output of the latch LT1 is connected to the gate of the transistor PM1 of the output buffer OBUF via the inverter IV. The data output line DOUTX is commonly connected to the four data input / output circuits DIOC of the data input / output group.

[0094] The latch LT2 has an inverter IV that receives a data output signal DOUTX from the memory core MCR, and a NAND gate that feeds back the output of the inverter IV received at one input to the input of the inverter IV. The output of the latch LT2 is connected to the gate of the transistor NM1 of the output buffer OBUF.

[0095] The other input of the NAND gate of the latches LT1 and LT2 receives the data enable signal DQE output from the NOR gate. When the data enable signal DQE is at a high level, the latches LT1 and LT2 latch the logical values ​​of the data output signals DOUT and DOUTX and output the latched logical values ​​to the output buffer OBUF. When the data enable signal DQE is at a low level, the latches LT1 and LT2 output a low level to the output buffer OBUF regardless of the logical values ​​of the data output signals DOUT and DOUTX.

[0096] The input buffer IBUF has a NAND gate that receives a data signal DQ (write data) and a data enable signal DQE, and an inverter IV that is connected to the output of the NAND gate and outputs a data input signal DINX. When the data enable signal DQE is at a high level, the input buffer IBUF outputs the data signal DQ to the memory core MCR as a data input signal DINX, and when the data enable signal DQE is at a low level, the input buffer IBUF outputs a low-level data input signal DINX to the memory core MCR. The data input signal DINX is commonly connected to the four data input / output circuits DIOC of the data input / output group.

[0097] The fuses F11 and F12 are connected in series between a power supply line VDD and a ground line VSS via a node ND1. The NOR gate receives a data enable signal DQEX at one input and a voltage level generated at the node ND1 at the other input. The other input of the NOR gate connected to the node ND1 is an example of a control input terminal. The power supply line VDD is a power supply line for the logic circuit, and the ground line VSSQ is a ground line for the logic circuit.

[0098] When the function of the data input / output circuit DIOC is enabled, the fuse F11 is cut off and the fuse F12 is maintained in a conductive state. At this time, the node ND1 is fixed to a low level by the conductive fuse F12, and the NOR gate outputs a data enable signal DQE that is an inverted logical value of the data enable signal DQEX. As a result, the output buffer OBUF outputs a low level or a high level to the input / output terminal IO according to the data enable signal DQEX and the data signal read from the memory core MCR, or functions as a tri-state buffer that sets the input / output terminal IO to a high impedance state.

[0099] When the function of the data input / output circuit DIOC is disabled, the fuse F11 is maintained in a conductive state, and the fuse F12 is cut off. At this time, the node ND1 is fixed to a high level by the conductive fuse F11, and the NOR gate fixes the data enable signal DQE to a low level. As a result, the input / output terminal IO of the output buffer OBUF is set to a high impedance state. One of the fuses F11 and F12 is cut off to suppress a through current. The fuses F11 and F12 mounted on the data input / output circuit DIOC are programmed in a test process for testing the semiconductor device 106 in a wafer state after the semiconductor device 106 is manufactured. The test process includes a relief process for programming the fuses to replace a normal memory block including a defective normal memory cell with a redundant memory block including a redundant memory cell. The fuses F11 and F12 are programmed when a defect is relieved in the relief process.

[0100] Fig. 13 is a diagram showing a setting example of the data input / output circuit DIOC of Fig. 12. In the example shown in Fig. 13, the main parts of four data input / output circuits DIOC arranged corresponding to the data terminal DQ0 of the semiconductor chip CP2 are shown. As in Figs. 10 and 11, the pads PAD shown by black rectangles indicate true pads PAD (P2) connected to the TSV that transmits the data signal DQ, and the pads PAD shown by white rectangles indicate dummy pads PAD (P1, P3, P4) connected to the TSV that transmits the data signal DQ of another semiconductor chip CP. Note that Fig. 13 will explain the read operation that outputs the data signal DQ.

[0101] In the data input / output circuit DIOC connected to the true pad PAD (P2) of the semiconductor chip CP2, the fuse F11 is blown and the fuse F12 is maintained in a conductive state, so that one input (ND1) of the NOR gate is set to a low level, which is an effective level, the NOR gate outputs a data enable signal DQE, and the output buffer OBUF operates as a tri-state buffer capable of outputting a data signal DQ.

[0102] The output buffer OBUF is set to an enabled state in which it outputs high-level or low-level data when a high level is output from the latch LT1 and a low level is output from the latch LT2, or when a low level is output from the latch LT1 and a high level is output from the latch LT2. The output buffer OBUF is set to an disabled state in which it does not output data when low levels are output from the latches LT1 and LT2.

[0103] In the other three data input / output circuits DIOC connected to the disabled pads PAD (P1, P3 or P4) of the semiconductor chip CP2, the fuse F11 is maintained in a conductive state and the fuse F12 is blown. As a result, one input (ND1) of the NOR gate is set to a high level which is an inactive level, and the NOR gate fixes the data enable signal DQE to a low level L. As a result, the gate of the transistor PM1 is fixed to a high level H and turned off, the gate of the transistor NM1 is fixed to a low level L and turned off, the output buffer OBUF is in an inactive state, and the input / output terminal IO is set to a high impedance state Hi-Z.

[0104] As described above, this embodiment can also provide the same effects as the above-mentioned embodiments. For example, by changing the program states of the fuses F11 and F12 provided in the four data input / output circuits DIOC of the data input / output group for each stacking stage of the semiconductor chip CP, the same semiconductor chips CP can be used in any stacking stage of the semiconductor device 106.

[0105] As a result, compared to manufacturing semiconductor chips CP with different circuits for each stacking layer, it is possible to prevent production management from becoming complicated and to prevent an increase in management costs. In addition, by making it possible to stack semiconductor chips CP with the same circuits by ingenious circuit design, it is possible to prevent signal collisions and to prevent an increase in design costs and manufacturing costs.

[0106] Furthermore, in this embodiment, the number of internal data buses IBUS of each semiconductor chip CP can be reduced compared to the semiconductor device 102 in Fig. 2, so that the area of ​​the wiring region for the internal data buses IBUS can be reduced, and the chip size can be reduced. As a result, the yield of the semiconductor chips CP can be improved compared to Fig. 2, and the cost of the semiconductor chips CP can be reduced. As a result, the cost of the semiconductor device 106 can be reduced.

[0107] (Fourth embodiment) Fig. 14 is a circuit diagram showing an example of a data input / output circuit DIOC of each chip mounted on a semiconductor device 108 according to a fourth embodiment of the present invention. The same elements as those in Figs. 10 to 12 are given the same reference numerals and detailed description will be omitted. The semiconductor device 108 shown in Fig. 14 has four semiconductor chips CP1-CP4 stacked on a substrate such as an interposer (not shown), similar to Fig. 10.

[0108] Each of the semiconductor chips CP1-CP4 is an SDRAM chip having 256 data terminals DQ0-DQ255 (real pads PAD) for inputting and outputting data signals DQ and dummy pads PAD, and receiving a common chip select signal / CS. The semiconductor chips CP1-CP4 are chips with the same circuitry, using the same design data. An example of the connection between the internal data bus IBUS and the pads PAD of each of the semiconductor chips CP1-CP4 is the same as that shown in FIG. 11. The bumpless TSV method is also adopted for the TSV of the semiconductor device 108, as in the semiconductor device 102 of FIG. 2.

[0109] The data input / output circuit DIOC has the same circuit configuration as the data input / output circuit DIOC in Fig. 12, except that fuses F21 and F22 are provided instead of the fuses F11 and F12, and an inverter IV2 is provided instead of the NOR gate. The fuses F21 and F22 are an example of a first program element. The inverter IV2 inverts the logical value of the data enable signal DQEX and outputs it as the data enable signal DQE.

[0110] The fuses F21 and F22 are connected in series between the input / output terminal IO and the data terminal DQ. When the input / output terminal IO of the data input / output circuit DIOC is set to a high impedance state regardless of the logic of the data enable signal DQEX, both of the fuses F21 and F22 are cut off. When the fuses F21 and F22 are cut off, the output buffer OBUF is set to an invalid state in which the connection between the input / output terminal IO and the data terminal DQ is cut off. When the data input / output circuit DIOC is operated according to the logic of the data enable signal DQEX, the fuses F21 and F22 are not cut off and are maintained in a conductive state.

[0111] For example, the fuses F21 and F22 of the data input / output circuit DIOC connected to the real pad PAD indicated by the black rectangle in Fig. 11 are maintained in a conductive state, while the fuses F21 and F22 of the data input / output circuit DIOC connected to the dummy pad PAD indicated by the white rectangle in Fig. 11 are cut off.

[0112] The fuses F21 and F22 mounted on the data input / output circuit DIOC are programmed in a test process for testing the semiconductor device 108 in a wafer state after the semiconductor device 108 is manufactured. The test process includes a rescue process for replacing a normal memory block including defective normal memory cells with a redundant memory block including redundant memory cells by programming the fuses. The fuses F21 and F22 are programmed when relieving defects in the rescue process. Note that, in FIG. 14, two fuses F21 and F22 are arranged in series to reliably cut off the wiring between the input / output terminal IO and the data terminal DQ (pad PAD), but one fuse may be arranged if reliable cutting can be guaranteed.

[0113] The bumpless TSV method has less parasitic capacitance than the bumped TSV method, so the size of the transistors PM1 and NM1 in the output buffer OBUF can be reduced. By reducing the size of the transistors PM1 and NM1, the signal current of the data signal DQ can be reduced, so even when the fuses F21 and F22 are placed in the wiring for the data signal DQ, the effect of the resistance of the fuses F21 and F22 on the response characteristics of the data signal DQ is small.

[0114] In addition, since the signal current of the data signal DQ can be reduced, the wiring for the data signal DQ connected to the output buffer OBUF can be made thinner than in the bumped TSV method. For this reason, the fuses F21 and F22 may use the wiring itself without using a fuse material, and may function as a fuse by cutting the wiring.

[0115] In the data input / output circuit DIOC shown in Fig. 14, when the fuses F21, F21 are blown, the input / output terminal IO of the output buffer OBUF is disconnected from the data terminal DQ (i.e., the TSV). Since the parasitic capacitances of the transistors PM1, NM1 are not connected to the data terminal DQ, the parasitic capacitance of the data terminal DQ after stacking a plurality of semiconductor chips CP can be made smaller than that in the case of employing the data input / output circuit DIOC of Fig. 12. For example, if the data rate for each data terminal DQ is 1 Gb / s when the data input / output circuit DIOC of Fig. 12 is employed, the data rate for each data terminal DQ can be made 1.5 Gb / s when the data input / output circuit DIOC of Fig. 14 is employed.

[0116] As described above, this embodiment can also provide the same effects as the above-mentioned embodiment. For example, by changing the program state of the fuses F21 and F22 provided in the four data input / output circuits DIOC of the data input / output group for each stacking stage of the semiconductor chip CP, multiple semiconductor chips CP having the same circuit can be used for any stacking stage of the semiconductor device 108. As a result, it is possible to suppress the production management from becoming complicated compared to the case where semiconductor chips CP having different circuits are manufactured for each stacking stage, and it is possible to suppress an increase in management costs. And, by making it possible to stack semiconductor chips CP having the same circuit by devising the circuit, it is possible to suppress the increase in design costs and manufacturing costs while suppressing signal collisions.

[0117] Furthermore, in this embodiment, by disposing and cutting the fuses F21 and F22 in the wiring between the input / output terminal IO of the output buffer OBUF and the data terminal DQ, it is possible to prevent the parasitic capacitance of the transistors PM1 and NM1 from being connected to the data terminal DQ when the fuses F21 and F22 are cut. This makes it possible to reduce the parasitic capacitance of the data terminal DQ after stacking a plurality of semiconductor chips CP compared to the case where the data input / output circuit DIOC of Fig. 12 is used. Also, the fuses F21 and F22 can utilize the wiring itself without using a fuse material.

[0118] Although Figures 2 to 14 show examples in which bidirectional data (write data and read data) is input and output to the data terminal DQ, multiple semiconductor chips CP having input data terminals and output data terminals can also be stacked using the above-mentioned method.

[0119] 2 to 14, an example in which each semiconductor chip CP is a DDR type SDRAM chip has been described. However, each semiconductor chip CP may be a flash memory chip, a magnetoresistive memory (MRAM: Magnetoresistive Random Access Memory) chip, a resistive memory (ReRAM: Resistive Random Access Memory) chip, or the like.

[0120] Although the present invention has been described above based on the embodiments, the present invention is not limited to the requirements shown in the above embodiments. These points can be changed without departing from the spirit of the present invention, and can be appropriately determined according to the application form. [Explanation of symbols]

[0121] 100, 102, 104, 106, 108 Semiconductor device CP Semiconductor Chip / CS, / CS1- / CS4, CSX Chip select signal, chip select terminal CSDEC1, CSDEC2 Chip selection decoder circuit CSW Column Selection Switch DEC1, DEC2 decoder circuit DIOC Data input / output circuit DINX Data input signal DQ Data signal, data terminal DOUT, DOUTX Data output signals DQE, DQEX Data enable signal DS Die select signal, die select terminal F1-F4, F11, F12, F21, F22 Fuses IBUF Input Buffer IBUS Internal Data Bus INTP Interposer IO input / output terminal LT1, LT2 latches MCR Memory Core ND1 Node NM1 n-channel MOS transistor OBUF Output Buffer PAD PM1 p-channel MOS transistor TC through conductor TVIA Through Via W Wiring WL wiring layer

Claims

1. a plurality of semiconductor chips stacked on each other, each of the semiconductor chips having a first selection terminal for receiving a first selection signal and one or more second selection terminals for receiving a second selection signal; a plurality of through electrodes that penetrate the plurality of semiconductor chips and are respectively connected to the first selection terminals and the second selection terminals of the plurality of semiconductor chips; Each of the plurality of semiconductor chips includes: an internal circuit that operates upon receiving the first selection signal; a gate circuit having a control input terminal, the gate circuit outputting the first selection signal to the internal circuit when the control input terminal indicates a valid level; a decoder circuit having a plurality of output terminals, and setting one of the output terminals to an active level in response to a logical value of the second selection signal; a plurality of first program elements respectively disposed between the plurality of output terminals and the control input terminal; Each of the plurality of semiconductor chips has one of the plurality of first program elements set to a conductive state, the internal circuit of each of the plurality of semiconductor chips operates upon receiving the first selection signal output from the gate circuit when the first program element connected to the output terminal set to the effective level in response to the logical value of the second selection signal is in a conductive state; The semiconductor device according to claim 1, wherein the first program elements in a conductive state are different from one another in the plurality of semiconductor chips.

2. the plurality of semiconductor chips are memory chips having data terminals for inputting and outputting data; the internal circuit includes a memory circuit for storing data; the data terminals of the plurality of semiconductor chips are connected to the data terminals of the other semiconductor chips via through electrodes; 2. The semiconductor device according to claim 1, wherein the memory circuit of the memory chip corresponding to the logical value of the second selection signal inputs or outputs the data.

3. A plurality of semiconductor chips each having a selection terminal for receiving a selection signal and a plurality of data terminals for inputting or outputting data, the semiconductor chips being stacked on top of each other; a plurality of through electrodes that penetrate the plurality of semiconductor chips and are respectively connected to the selection terminals and the plurality of data terminals of the plurality of semiconductor chips; Each of the plurality of semiconductor chips includes: a data holding circuit which operates in response to the selection signal and holds the data; a plurality of data input / output circuits including an output buffer for outputting the data held in the data holding circuit; a data output line for commonly connecting an output of the data holding circuit to the plurality of data input / output circuits; a first program element provided in each of the plurality of data input / output circuits and configured to set the output buffer connected to the data output line to a valid state or an invalid state; the output buffer of any one of the plurality of data input / output circuits is set to the valid state in which the data can be output from the data holding circuit; the output buffer of the other data input / output circuit is set to the invalid state in which the data is not output; The semiconductor device according to claim 1, wherein the data terminals connected to the output buffers set to the valid state are different for each of the plurality of semiconductor chips.

4. Each of the plurality of semiconductor chips includes: A plurality of said data terminals; A plurality of said data output lines; a plurality of data input / output groups each including the data input / output circuits in a number equal to the number of stacked semiconductor chips; each of the plurality of data output lines is commonly connected to a plurality of the data input / output circuits of each of the plurality of data input / output groups; 4. The semiconductor device according to claim 3, wherein in each of the plurality of data input / output groups, the output buffer of any of the plurality of data input / output circuits is set to an enabled state in which the data can be output from the data holding circuit, and the output buffer of the other data input / output circuits is set to an disabled state in which the data is not output.

5. 5. The semiconductor device according to claim 4, wherein the number of said data terminals is equal to the product of the number of said semiconductor chips stacked and the number of said data output lines.

6. Each of the plurality of data input / output circuits includes a gate circuit that outputs an enable signal for setting the output buffer to the valid state or the invalid state when a control input terminal indicates a valid level, and outputs the enable signal for setting the output buffer to the invalid state when the control input terminal indicates an invalid level; 4. The semiconductor device according to claim 3, wherein the first program element is connected to the control input terminal of the gate circuit, and sets the control input terminal to the valid level or the invalid level depending on a program state of the first program element.

7. the first program element is connected in series between the output buffer and the data terminal; 4. The semiconductor device according to claim 3, wherein the output buffer is set to the invalid state by cutting off a connection between the output buffer and the data terminal by programming the first program element.

8. 4. The semiconductor device according to claim 3, wherein the plurality of semiconductor chips receive a common selection signal via a through electrode and are accessed simultaneously.

9. 9. The semiconductor device according to claim 1, wherein the plurality of semiconductor chips are manufactured using a common photomask and have the same circuit configuration.

10. 9. The semiconductor device according to claim 1, wherein the plurality of semiconductor chips are connected to the through electrodes without using bumps.

11. 8. The semiconductor device according to claim 1, wherein the first program element is programmed in a manufacturing process for forming the plurality of semiconductor chips on a semiconductor wafer.

12. each of the plurality of semiconductor chips has a second program element which is programmed when replacing a defective circuit with a redundant circuit; 12. The semiconductor device according to claim 11, wherein the first program element and the second program element are programmed in a test process in which the defective circuit is replaced with the redundant circuit.

13. A semiconductor chip having a first selection terminal for receiving a first selection signal and one or more second selection terminals for receiving a second selection signal, the semiconductor chip being stackable with another semiconductor chip connected via a through electrode, an internal circuit that operates upon receiving the first selection signal; a gate circuit having a control input terminal, the gate circuit outputting the first selection signal to the internal circuit when the control input terminal indicates a valid level; a decoder circuit having a plurality of output terminals, and setting one of the output terminals to an active level in response to a logical value of the second selection signal; a plurality of first program elements respectively disposed between the plurality of output terminals and the control input terminal; One of the first program elements is set to a conductive state; The semiconductor chip is characterized in that the internal circuit operates by receiving the first selection signal output from the gate circuit when the first program element connected to the output terminal set to the effective level in response to the logical value of the second selection signal is in a conductive state.

14. A semiconductor chip that has a selection terminal for receiving a selection signal and a plurality of data terminals for inputting or outputting data, and that can be stacked with another semiconductor chip connected via a through electrode, a data holding circuit which operates in response to the selection signal and holds the data; a plurality of data input / output circuits including an output buffer for outputting the data held in the data holding circuit; a data output line for commonly connecting an output of the data holding circuit to the plurality of data input / output circuits; a first program element provided in each of the plurality of data input / output circuits and configured to set the output buffer connected to the data output line to a valid state or an invalid state; the output buffer of any one of the plurality of data input / output circuits is set to the valid state in which the data can be output from the data holding circuit; The output buffer of the data input / output circuit is set to the invalid state in which the data is not output.

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