Oxide semiconductor thin film, thin film transistor, and sputtering target

Abstract

To provide an oxide semiconductor thin film that has high mobility and light stress resistance, as well as excellent S value and switching characteristics when formed into a transistor.SOLUTION: An oxide semiconductor thin film according to the present disclosure is an oxide semiconductor thin film containing metal elements, the metal elements are composed of In, Zn, Fe and unavoidable impurities, in which, relative to the total number of In, Zn and Fe atoms, the number of In atoms is 50 atm% or more and 80 atm% or less, the number of Zn atoms is 20 atm% or more and 48 atm% or less, and the number of Fe atoms is 1.5 atm% or more and 2.5 atm% or less, and the ratio of the number of In atoms to Zn atoms, In / Zn, is 1.5 or more and 2.5 or less.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to an oxide semiconductor thin film, a thin film transistor, and a sputtering target. [Background technology]

[0002] Amorphous oxide semiconductors have higher carrier mobility when forming thin film transistors (TFTs) than amorphous silicon semiconductors, for example. Amorphous oxide semiconductors also have a large optical band gap and are highly transparent to visible light. Furthermore, amorphous oxide semiconductor thin films can be formed at lower temperatures than amorphous silicon semiconductors. Taking advantage of these characteristics, amorphous oxide semiconductor thin films are expected to be applied to next-generation large displays that can be driven at high speed with high resolution, and flexible displays using resin substrates that require film formation at low temperatures.

[0003] In response to this, the inventors of the present disclosure have developed an oxide semiconductor thin film containing In, Zn, and Fe, a thin film transistor using the oxide semiconductor thin film, and a sputtering target for forming the oxide semiconductor thin film, as an amorphous oxide semiconductor thin film that has high carrier mobility in a thin film transistor and little shift in threshold voltage over time even when irradiated with light, that is, high light stress resistance (see Patent Documents 1 and 2). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2019-102793 A [Patent Document 2] JP 2020-194945 A Summary of the Invention [Problem to be solved by the invention]

[0005] When the above-mentioned thin-film transistor is adapted for a current-driven organic EL display, in addition to high mobility and light stress resistance, it is required that the transistor have excellent S value and switching characteristics.

[0006] The present disclosure has been made in light of the above-mentioned circumstances, and aims to provide an oxide semiconductor thin film that has high mobility and light stress resistance, as well as excellent S value and switching characteristics when a transistor is formed, a thin film transistor using this oxide semiconductor thin film, and a sputtering target for forming this oxide semiconductor thin film. [Means for solving the problem]

[0007] The present inventors have discovered that by controlling the number of atoms and the atomic ratio in an oxide semiconductor thin film containing In, Zn, and Fe within a predetermined range, it is possible to obtain an oxide semiconductor thin film for thin film transistors that has high carrier mobility and light stress resistance, and is excellent in S value and switching characteristics, which were previously thought to be unreliable according to the common sense of engineers in this field, and have completed the invention of the present disclosure.

[0008] That is, an oxide semiconductor thin film according to one embodiment of the present disclosure is an oxide semiconductor thin film containing metal elements, the metal elements being composed of In, Zn, Fe and unavoidable impurities, in which, relative to the total number of In, Zn and Fe atoms, the number of In atoms is 50 atm% or more and 80 atm% or less, the number of Zn atoms is 20 atm% or more and 48 atm% or less, and the number of Fe atoms is 1.5 atm% or more and 2.5 atm% or less, and the ratio of the number of In atoms to Zn atoms, In / Zn, is 1.5 or more and 2.5 or less.

[0009] A thin film transistor according to another embodiment of the present disclosure is a thin film transistor having the oxide semiconductor thin film of the present disclosure, and is used in an organic EL display.

[0010] A sputtering target according to another embodiment of the present disclosure is a sputtering target used for forming an oxide semiconductor thin film containing metal elements, wherein the metal elements consist of In, Zn, Fe, and unavoidable impurities, and relative to the total number of In, Zn, and Fe atoms, the number of In atoms is 50 atm% or more and 80 atm% or less, the number of Zn atoms is 20 atm% or more and 48 atm% or less, and the number of Fe atoms is 1.5 atm% or more and 2.5 atm% or less, and the ratio of the number of In atoms to Zn atoms, In / Zn, is 1.5 or more and 2.5 or less. Effect of the Invention

[0011] The oxide semiconductor thin film of the present disclosure has high mobility and light stress resistance, and is excellent in S value and switching characteristics when a transistor is formed. A thin film transistor of the present disclosure using this oxide semiconductor thin film has high mobility and light stress resistance, and is excellent in S value and switching characteristics. Furthermore, the sputtering target of the present disclosure can form this oxide semiconductor thin film. [Brief description of the drawings]

[0012] [Figure 1] FIG. 1 is a schematic cross-sectional view showing a thin film transistor according to an embodiment of the present disclosure formed on a substrate surface. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] [Description of the embodiments of the present disclosure] (1) An oxide semiconductor thin film according to one embodiment of the present disclosure is an oxide semiconductor thin film containing metal elements, the metal elements being composed of In, Zn, Fe, and unavoidable impurities, in which, relative to the total number of In, Zn, and Fe atoms, the number of In atoms is 50 atm% or more and 80 atm% or less, the number of Zn atoms is 20 atm% or more and 48 atm% or less, and the number of Fe atoms is 1.5 atm% or more and 2.5 atm% or less, and the ratio of the number of In atoms to Zn atoms, In / Zn, is 1.5 or more and 2.5 or less.

[0014] The oxide semiconductor thin film has high light stress resistance because the atomic numbers of In and Zn are within the above ranges and the atomic number of Fe is equal to or greater than the above lower limit. In addition, the oxide semiconductor thin film has the atomic number of Fe equal to or less than the above upper limit, so that the carrier mobility can be increased when a thin film transistor is formed using the oxide semiconductor thin film. Furthermore, the atomic ratio of In / Zn is equal to or greater than the above lower limit, so that the S value can be increased, and the atomic ratio is equal to or less than the above upper limit, so that the switching characteristics can be excellent.

[0015] (2) A thin-film transistor according to another embodiment of the present disclosure is a thin-film transistor having the oxide semiconductor thin film described in (1) above, and is used in an organic electroluminescence display.

[0016] The thin film transistor has the oxide semiconductor thin film, and therefore has excellent S value and switching characteristics in addition to high mobility and light stress resistance, and is therefore suitable for use in organic EL displays.

[0017] (3) In the thin film transistor described in (2) above, the S value is preferably 0.4 V / dec or more and 1.0 V / dec or less, and the threshold voltage is preferably 0.6 V or more. By setting the S value and the threshold voltage within the above ranges, the thin film transistor can be switched quickly and stably.

[0018] (4) In the thin film transistor according to (2) or (3), the carrier mobility is 25 cm 2 By setting the carrier mobility above the lower limit, the device can be suitably used for, for example, next-generation large-sized organic EL displays that require high speed performance.

[0019] (5) A sputtering target according to another embodiment of the present disclosure is a sputtering target used for forming an oxide semiconductor thin film containing metal elements, the metal elements being composed of In, Zn, Fe, and unavoidable impurities, in which, relative to the total number of In, Zn, and Fe atoms, the number of In atoms is 50 atm% or more and 80 atm% or less, the number of Zn atoms is 20 atm% or more and 48 atm% or less, and the number of Fe atoms is 1.5 atm% or more and 2.5 atm% or less, and the ratio of the number of In atoms to Zn atoms, In / Zn, is 1.5 or more and 2.5 or less.

[0020] The sputtering target contains In, Zn, and Fe whose atomic numbers are within the above ranges, and the ratio of the atomic numbers of In / Zn is within the above range. Therefore, by forming an oxide semiconductor thin film using the sputtering target and then forming a thin film transistor on the oxide semiconductor thin film, it is possible to manufacture a thin film transistor that has excellent S value and switching characteristics in addition to high mobility and light stress resistance.

[0021] Here, "carrier mobility" refers to the field effect mobility in the saturation region of a thin-film transistor, and "field effect mobility" refers to the gate voltage Vg [V], threshold voltage Vth [V], drain current Id [A], channel length L [m], channel width W [m], and capacitance C of the gate insulating film. ox [F], in the saturation region (Vg>Vd-Vth) of the current-voltage characteristic of the thin film transistor, μ FE [m 2 / Vs].

number

[0022] The "threshold voltage" of a thin-film transistor is the voltage at which the drain current of the transistor is 10 -9 This refers to the gate voltage at which A is reached.

[0023] In addition, the "S value" of a thin-film transistor refers to the minimum change in gate voltage required to increase the drain current by one order of magnitude.

[0024] [Details of the embodiment of the present disclosure] Hereinafter, an oxide semiconductor thin film, a thin film transistor, and a sputtering target according to an embodiment of the present disclosure will be described.

[0025] [Thin-film transistor] The thin film transistor shown in Fig. 1 can be used in the manufacture of display devices such as next-generation large displays and flexible displays, etc. In particular, the thin film transistor is preferably used for organic EL displays.

[0026] The thin-film transistor is a bottom-gate type transistor formed on the surface of a substrate X. The thin-film transistor includes a gate electrode 1, a gate insulating film 2, an oxide semiconductor thin film 3, an ESL (Etch Stop Layer) protective film 4, source and drain electrodes 5, a passivation insulating film 6, and a conductive film 7.

[0027] (substrate) The substrate X is not particularly limited, but may be, for example, a substrate used in a display device. Such substrate X may be a transparent substrate such as a glass substrate or a silicone resin substrate. The glass used for the glass substrate is not particularly limited, but may be, for example, non-alkali glass, high strain point glass, soda lime glass, etc. In addition, a metal substrate such as a stainless steel thin film or a resin substrate such as a polyethylene terephthalate (PET) film may also be used as the substrate X.

[0028] The average thickness of the substrate X is preferably 0.3 mm or more and 1.0 mm or less from the viewpoint of processability. The size and shape of the substrate X are appropriately determined according to the size and shape of the display device or the like to be used. Here, the "average thickness" refers to the average value calculated by measuring the thickness at any 10 points.

[0029] (gate electrode) The gate electrode 1 is formed on the surface of the substrate X and has electrical conductivity. The thin film constituting the gate electrode 1 is not particularly limited, but may be an Al alloy or an Al alloy having a thin film or alloy film of Mo, Cu, Ti, or the like laminated thereon.

[0030] The shape of the gate electrode 1 is not particularly limited, but from the viewpoint of controllability of the channel length and the channel width, a rectangular shape in a plan view with the channel length direction and the channel width direction of the thin film transistor are preferable. The size of the gate electrode 1 may be a size that can ensure the channel length and the channel width of the thin film transistor. Here, the channel length direction of the thin film transistor is the opposing direction of the source electrode 5a and the drain electrode 5b of the thin film transistor. Moreover, the channel width direction of the thin film transistor is a direction perpendicular to the channel length direction of the thin film transistor and parallel to the surface of the substrate X.

[0031] The lower limit of the average thickness of the gate electrode 1 is preferably 50 nm, more preferably 170 nm. On the other hand, the upper limit of the average thickness of the gate electrode 1 is preferably 500 nm, more preferably 400 nm. If the average thickness of the gate electrode 1 is less than the lower limit, the resistance of the gate electrode 1 is high, so that the power consumption of the gate electrode 1 may increase and disconnection may easily occur. On the other hand, if the average thickness of the gate electrode 1 exceeds the upper limit, it becomes difficult to planarize the gate insulating film 2 and the like laminated on the front surface side of the gate electrode 1, and the characteristics of the thin film transistor may deteriorate.

[0032] In order to improve the coverage of the gate insulating film 2, the cross section of the gate electrode 1 in the thickness direction may be tapered so as to expand toward the substrate X. When the gate electrode 1 is tapered, the taper angle is preferably 30° or more and 40° or less.

[0033] (Gate insulating film) The gate insulating film 2 is laminated on the front surface side of the substrate X so as to cover the gate electrode 1. The thin film constituting the gate insulating film 2 is not particularly limited, but examples thereof include a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and a metal oxide film such as Al2O3 or Y2O3. The gate insulating film 2 may have a single-layer structure of these thin films, or a multilayer structure in which two or more types of thin films are laminated.

[0034] The shape of the gate insulating film 2 is not limited as long as it covers the gate electrode 1. For example, the gate insulating film 2 may cover the entire surface of the substrate X.

[0035] The lower limit of the average thickness of the gate insulating film 2 is preferably 50 nm, more preferably 100 nm. The upper limit of the average thickness of the gate insulating film 2 is preferably 300 nm, more preferably 250 nm. If the average thickness of the gate insulating film 2 is less than the lower limit, the withstand voltage of the gate insulating film 2 may be insufficient, and the gate insulating film 2 may break down due to application of a gate voltage. Conversely, if the average thickness of the gate insulating film 2 exceeds the upper limit, the capacitance of the capacitor formed between the gate electrode 1 and the oxide semiconductor thin film 3 may be insufficient, and the drain current may be insufficient. Note that, when the gate insulating film 2 has a multi-layer structure, the "average thickness of the gate insulating film" refers to the average thickness of the total of the layers.

[0036] (Oxide semiconductor thin film) The oxide semiconductor thin film 3 itself is another embodiment of the present disclosure. The oxide semiconductor thin film 3 is an oxide semiconductor thin film containing metal elements. The metal elements are In, Zn, Fe, and unavoidable impurities. That is, the oxide semiconductor thin film 3 does not substantially contain metal elements other than In, Zn, and Fe.

[0037] The lower limit of the number of In atoms relative to the total number of In, Zn and Fe atoms is 50 atm%, more preferably 55 atm%, and even more preferably 60 atm%. On the other hand, the upper limit of the number of In atoms is 80 atm%, more preferably 75 atm%, and even more preferably 70 atm%. If the number of In atoms is less than the lower limit, the carrier mobility of the thin film transistor may decrease. Conversely, if the number of In atoms exceeds the upper limit, the leakage current of the oxide semiconductor thin film 3 may increase or the threshold voltage may shift to the negative side, so that the oxide semiconductor thin film 3 may become a conductor.

[0038] The lower limit of the number of Zn atoms relative to the total number of In, Zn and Fe atoms is 20 atm%, more preferably 25 atm%, and even more preferably 30 atm%. On the other hand, the upper limit of the number of Zn atoms is 48 atm%, more preferably 45 atm%, and even more preferably 40 atm%. If the number of Zn atoms is less than the lower limit, the number of other metal atoms becomes relatively large, and there is a risk of the conductor becoming. On the other hand, if the number of Zn atoms exceeds the upper limit, the carrier concentration is suppressed, and there is a risk of the carrier mobility of the thin film transistor decreasing.

[0039] The lower limit of the number of Fe atoms relative to the total number of In, Zn and Fe atoms is 1.5 atm%, more preferably 1.6 atm%, and even more preferably 1.7 atm%. On the other hand, the upper limit of the number of Fe atoms is 2.5 atm%, more preferably 2.4 atm%, and even more preferably 2.3 atm%. If the number of Fe atoms is less than the lower limit, the threshold voltage shift due to light irradiation may be large. Conversely, if the number of Fe atoms exceeds the upper limit, the carrier concentration may be suppressed, and the carrier mobility of the thin film transistor may be reduced.

[0040] The lower limit of the ratio of the number of In atoms to Zn atoms (In / Zn atomic ratio) is 1.5, more preferably 1.6, and even more preferably 1.7. On the other hand, the upper limit of the In / Zn atomic ratio is 2.5, more preferably 2.4, and even more preferably 2.3. If the In / Zn atomic ratio is less than the lower limit, the S value and carrier mobility may decrease. Conversely, if the In / Zn atomic ratio exceeds the upper limit, good switching characteristics may not be obtained.

[0041] The shape of the oxide semiconductor thin film 3 in a plan view is not particularly limited, but from the viewpoint of controllability of the channel length and channel width of the thin film transistor, it is preferable that the shape is the same as that of the gate electrode 1. The size of the oxide semiconductor thin film 3 in a plan view may be any size that can ensure the channel length and channel width of the thin film transistor.

[0042] In addition, the size of the oxide semiconductor thin film 3 in a plan view is preferably smaller than the size of the gate electrode 1 in a plan view in order to reliably dispose the oxide semiconductor thin film 3 directly above the gate electrode 1. The lower limit of the difference in the side lengths of the oxide semiconductor thin film 3 and the gate electrode 1 in the channel direction and the channel width direction is preferably 2 nm, more preferably 4 nm. On the other hand, the upper limit of the difference in the side lengths is preferably 10 nm, more preferably 8 nm. If the difference in the side lengths is less than the lower limit, a part of the oxide semiconductor thin film 3 may be displaced from directly above the gate electrode 1 due to a patterning shift or the like, which may result in deterioration of the flatness of the oxide semiconductor thin film 3 and deterioration of the characteristics of the thin film transistor. On the other hand, if the difference in the side lengths exceeds the upper limit, the thin film transistor may become unnecessarily large.

[0043] The average thickness of the oxide semiconductor thin film 3 can be determined based on the conditions under which the drain current can be turned off when the oxide semiconductor thin film 3 is used as a switching element. Specifically, it is preferable that the inside of the oxide semiconductor thin film 3 is completely depleted by applying a gate voltage. To achieve this, the dielectric constant of the insulating film is set to ε OX , the dielectric constant of the semiconductor is ε AOS, Fermi level of semiconductor is φ f [eV], and the electronic charge is q [C], the average thickness t ch [m] is the carrier concentration N C [m -3 In view of the relationship between the following formula (2) and a carrier concentration described later, and from the viewpoint of the accuracy of controlling the film thickness distribution during the manufacture of the oxide semiconductor thin film 3, the average thickness of the oxide semiconductor thin film 3 can be, for example, 20 nm or more and 60 nm or less.

number

[0044] In order to improve the coverage of the source and drain electrodes 5, the cross section of the oxide semiconductor thin film 3 in the thickness direction may be tapered toward the substrate X. When the oxide semiconductor thin film 3 is tapered, the taper angle is preferably 30° or more and 40° or less.

[0045] The lower limit of the carrier concentration of the oxide semiconductor thin film 3 is 1×10 12 cm -3 is preferred, and 1×10 13 cm -3 is more preferable, and 1×10 14 cm -3 On the other hand, the upper limit of the carrier concentration of the oxide semiconductor thin film 3 is preferably 1×10 20 cm -3 is preferred, and 1×10 19 cm -3 is more preferable, and 1×10 18 cm -3 is more preferable. If the carrier concentration of the oxide semiconductor thin film 3 is less than the lower limit, the drain current of the thin film transistor may be insufficient. Conversely, if the carrier concentration of the oxide semiconductor thin film 3 exceeds the upper limit, it becomes difficult to completely deplete the inside of the oxide semiconductor thin film 3, so that the threshold voltage shifts to the negative side, and the thin film transistor may not function as a switching element.

[0046] The hole mobility of the oxide semiconductor thin film 3 is 25 cm 2 / Vs is preferable, 27cm 2 / Vs is more preferable, 30cm 2 / Vs. If the hole mobility of the oxide semiconductor thin film 3 is below the lower limit, the switching characteristics of the thin film transistor may be degraded. On the other hand, the upper limit of the hole mobility of the oxide semiconductor thin film 3 is not particularly limited, but the hole mobility of the oxide semiconductor thin film 3 is usually 100 cm 2 / Vs or less. "Hall mobility" refers to carrier mobility obtained by Hall effect measurement.

[0047] (ESL protective film) The ESL protective film 4 is a protective film that prevents the oxide semiconductor thin film 3 from being damaged and the characteristics of the thin film transistor from being deteriorated when the source and drain electrodes 5 are formed by etching. The thin film constituting the ESL protective film 4 is not particularly limited, but a silicon oxide film is preferably used.

[0048] The lower limit of the average thickness of the ESL protective film 4 is preferably 50 nm, and more preferably 80 nm. On the other hand, the upper limit of the average thickness of the ESL protective film 4 is preferably 250 nm, and more preferably 200 nm. If the average thickness of the ESL protective film 4 is less than the above-mentioned lower limit, the effect of the ESL protective film 4 in protecting the oxide semiconductor thin film 3 may be insufficient. Conversely, if the average thickness of the ESL protective film 4 exceeds the above-mentioned upper limit, it may be difficult to flatten the passivation insulating film 6, and the wiring from the source and drain electrodes 5 may be easily broken.

[0049] (Source and drain electrodes) The source and drain electrodes 5 cover a portion of the gate insulating film 2 and the ESL protective film 4, and are electrically connected to the oxide semiconductor thin film 3 at both ends of the channel of the thin film transistor. A drain current of the thin film transistor flows between the source electrode 5a and the drain electrode 5b in response to the voltage between the gate electrode 1 and the source electrode 5a and the voltage between the source electrode 5a and the drain electrode 5b.

[0050] The thin film constituting the source and drain electrodes 5 is not particularly limited as long as it has conductivity, and for example, the same thin film as that of the gate electrode 1 can be used.

[0051] The lower limit of the average thickness of the source and drain electrodes 5 is preferably 100 nm, more preferably 150 nm. On the other hand, the upper limit of the average thickness of the source and drain electrodes 5 is preferably 400 nm, more preferably 300 nm. If the average thickness of the source and drain electrodes 5 is less than the lower limit, the resistance of the source and drain electrodes 5 is high, which may increase power consumption in the source and drain electrodes 5 or may easily cause disconnection. On the other hand, if the average thickness of the source and drain electrodes 5 exceeds the upper limit, it may become difficult to flatten the passivation insulating film 6, and wiring using the conductive film 7 may become difficult.

[0052] The distance between the source electrode 5a and the drain electrode 5b, i.e., the lower limit of the channel length of the thin film transistor, is preferably 5 μm, more preferably 10 μm. On the other hand, the upper limit of the channel length of the thin film transistor is preferably 50 μm, more preferably 30 μm. If the channel length of the thin film transistor is less than the lower limit, high-precision processing is required, which may reduce the manufacturing yield. Conversely, if the channel length of the thin film transistor exceeds the upper limit, the switching time of the thin film transistor may be longer.

[0053] The lower limit of the channel width of the source electrode 5a and the drain electrode 5b, that is, the channel width of the thin film transistor, is preferably 100 μm, more preferably 150 μm. On the other hand, the upper limit of the channel width of the thin film transistor is preferably 300 μm, more preferably 250 μm. If the channel width of the thin film transistor is less than the lower limit, the drain current may be insufficient. Conversely, if the channel width of the thin film transistor exceeds the upper limit, the drain current may be excessive, and the power consumption of the thin film transistor may increase unnecessarily.

[0054] (passivation insulating film) The passivation insulating film 6 covers the gate electrode 1, the gate insulating film 2, the oxide semiconductor thin film 3, the ESL protective film 4, the source electrode 5a, and the drain electrode 5b, and prevents the characteristics of the thin film transistor from deteriorating. The thin film constituting the passivation insulating film 6 is not particularly limited, but a silicon nitride film is preferably used, which has a relatively easy sheet resistance controllable by the hydrogen content. In order to further increase the controllability of the sheet resistance, the passivation insulating film 6 may have a two-layer structure of, for example, a silicon oxide film and a silicon nitride film.

[0055] The lower limit of the average thickness of the passivation insulating film 6 is preferably 100 nm, more preferably 250 nm. On the other hand, the upper limit of the average thickness of the passivation insulating film 6 is preferably 500 nm, more preferably 300 nm. If the average thickness of the passivation insulating film 6 is less than the lower limit, the effect of preventing deterioration of the characteristics of the thin film transistor may be insufficient. Conversely, if the average thickness of the passivation insulating film 6 exceeds the upper limit, the passivation insulating film 6 may become unnecessarily thick, which may increase the manufacturing cost of the thin film transistor and decrease the production efficiency. Note that, when the passivation insulating film 6 has a multi-layer structure, the "average thickness of the passivation insulating film" refers to the average thickness of the total.

[0056] Further, a contact hole 8 is formed in the passivation insulating film 6 to allow electrical connection with the drain electrode 5b. The shape and size of the contact hole 8 in a plan view are not particularly limited as long as electrical connection with the drain electrode 5b is ensured, but it may be, for example, a square with one side measuring 10 μm to 30 μm in a plan view.

[0057] (Conductive film) The conductive film 7 is connected to the drain electrode 5b via a contact hole 8 formed in the passivation insulating film 6. The conductive film 7 constitutes a wiring for acquiring a drain current from the thin film transistor.

[0058] The conductive film 7 is not particularly limited, and the same thin film as that of the gate electrode 1 can be used. Among them, a transparent conductive film suitable for application to a display is preferable. Examples of such a transparent conductive film include an ITO film and a ZnO film.

[0059] The position where the conductive film 7 is connected to the drain electrode 5b is preferably a position where the drain electrode 5b contacts the gate insulating film 2, and not directly above the gate electrode 1. By connecting the conductive film 7 to the drain electrode 5b at such a position, the flatness of the connection portion between the conductive film 7 and the drain electrode 5b is improved, and an increase in contact resistance can be suppressed.

[0060] The lower limit of the average wiring width of the conductive film 7 is preferably 5 μm, and more preferably 10 μm. On the other hand, the upper limit of the average wiring width of the conductive film 7 is preferably 50 μm, and more preferably 30 μm. If the average wiring width of the conductive film 7 is less than the lower limit, the wiring of the conductive film 7 may have high resistance, and the power consumption and voltage drop in the wiring of the conductive film 7 may increase. Conversely, if the average wiring width of the conductive film 7 exceeds the upper limit, the integration degree of the thin film transistor may decrease. Here, the "average wiring width of the conductive film" refers to the average width of the wiring portion of the conductive film 7 that is disposed on the surface of the passivation insulating film 6 and acquires the drain current from the thin film transistor.

[0061] The lower limit of the average thickness of the conductive film 7 is preferably 50 nm, more preferably 80 nm. On the other hand, the upper limit of the average thickness of the conductive film 7 is preferably 200 nm, more preferably 150 nm. If the average thickness of the conductive film 7 is less than the lower limit, the wiring made of the conductive film 7 has high resistance, and the power consumption and voltage drop in the wiring made of the conductive film 7 may increase. On the other hand, if the average thickness of the conductive film 7 exceeds the upper limit, the average thickness of the conductive film 7 becomes too large relative to the average wiring width of the wiring made of the conductive film 7, so that the wiring is likely to tilt, and the wiring itself may be broken or a short circuit with an adjacent wiring may easily occur. Here, the "average thickness of the conductive film" refers to the average thickness of the wiring portion of the conductive film 7 that is disposed on the surface of the passivation insulating film 6 and acquires a drain current from the thin film transistor.

[0062] (Thin-film transistor characteristics) The carrier mobility (electron mobility) of the thin-film transistor is 25 cm 2 / Vs is preferable, 27cm 2 / Vs is more preferable, 30cm 2 / Vs is more preferable. If the carrier mobility of the thin film transistor is less than the lower limit, the switching characteristics of the thin film transistor may be deteriorated. In addition, by making the carrier mobility exceed the lower limit, the thin film transistor can be suitably used in, for example, next-generation large organic EL displays that require high speed. On the other hand, the upper limit of the carrier mobility of the thin film transistor is not particularly limited, but the carrier mobility of the thin film transistor is usually 100 cm 2 / Vs or less.

[0063] The lower limit of the threshold voltage of the thin film transistor is preferably 0.6V, more preferably 1.0V. On the other hand, the upper limit of the threshold voltage of the thin film transistor is preferably 5V, more preferably 3V, and even more preferably 2V. If the threshold voltage of the thin film transistor is less than the lower limit, the leakage current in the off state as a switching element with no voltage applied to the gate electrode 1 increases, and the standby power of the thin film transistor may become too large. Conversely, if the threshold voltage of the thin film transistor exceeds the upper limit, the drain current in the on state as a switching element with a voltage applied to the gate electrode 1 may become insufficient.

[0064] The upper limit of the threshold voltage shift of the thin film transistor due to light irradiation is preferably 2V, more preferably 1.5V, and even more preferably 1V. If the threshold voltage shift exceeds the upper limit, when the thin film transistor is used in a display device, the performance of the thin film transistor may not be stable, and the required switching characteristics may not be obtained. The lower limit of the threshold voltage shift is preferably 0V, that is, the threshold voltage shift does not occur. Here, the "threshold voltage shift due to light irradiation" refers to the absolute value of the difference in threshold voltage before and after irradiation when the thin film transistor is irradiated with a white LED for 2 hours under the conditions of a substrate temperature of 60°C, a voltage of 10V between the source and drain of the thin film transistor, and -10V between the gate and source of the thin film transistor.

[0065] The lower limit of the S value (subthreshold swing value) of the thin film transistor is preferably 0.4 V / dec, more preferably 0.45 V / dec. On the other hand, the upper limit of the S value is preferably 1.0 V / dec, more preferably 0.7 V, and even more preferably 0.5 V. For example, when driving a current-driven display such as an organic EL display, if the S value is below the lower limit, a slight change in gate voltage may cause the current to change too much, making current control difficult. Conversely, if the S value exceeds the upper limit, it may take a long time to switch the thin film transistor.

[0066] [Method of manufacturing thin film transistors] The thin film transistor can be manufactured by a manufacturing method including, for example, a gate electrode forming step, a gate insulating film forming step, an oxide semiconductor thin film forming step, an ESL protective film forming step, a source and drain electrode forming step, a passivation insulating film forming step, a conductive film forming step, and a post-annealing treatment step.

[0067] <Gate electrode film formation process> In the gate electrode formation step, a gate electrode 1 is formed on the surface of a substrate X.

[0068] Specifically, a conductive film is first laminated to a desired thickness on the surface of the substrate X by a known method, for example, a sputtering method. The conditions for laminating the conductive film by the sputtering method are not particularly limited, but may be, for example, a substrate temperature of 20° C. to 50° C., and a deposition power density of 3 W / cm. 2 More than 4W / cm 2 The conditions are as follows: pressure is 0.1 Pa or more and 0.4 Pa or less, and carrier gas is Ar.

[0069] Next, the conductive film is patterned to form the gate electrode 1. The patterning method is not particularly limited, but for example, a method of performing photolithography followed by wet etching can be used. At this time, it is preferable to etch the cross section of the gate electrode 1 into a tapered shape that expands toward the substrate X so as to improve the coverage of the gate insulating film 2.

[0070] <Gate insulating film formation process> In the gate insulating film forming step, the gate insulating film 2 is formed on the front surface side of the substrate X so as to cover the gate electrode 1.

[0071] Specifically, first, an insulating film is laminated to a desired thickness on the front surface of the substrate X by a known method, for example, various CVD methods. For example, when a silicon oxide film is laminated by the plasma CVD method, the substrate temperature is set to 300° C. or higher and 400° C. or lower, and the film deposition power density is set to 0.7 W / cm. 2 More than 1.3W / cm 2Hereinafter, the process can be performed under conditions of a pressure of 100 Pa or more and 300 Pa or less, using a mixed gas of N2O and SiH4 as the source gas.

[0072] <Oxide semiconductor thin film deposition process> In the oxide semiconductor thin film formation step, the oxide semiconductor thin film 3 is formed on the surface of the gate insulating film 2 and directly above the gate electrode 1. Specifically, an oxide semiconductor layer is laminated on the surface of the substrate X, and then the oxide semiconductor layer is patterned to form the oxide semiconductor thin film 3.

[0073] (Stacking of oxide semiconductor layers) Specifically, first, for example, a known sputtering device is used to deposit an oxide semiconductor layer on the surface of the substrate X by a sputtering method. By using the sputtering method, it is possible to easily form an oxide semiconductor layer having excellent in-plane uniformity of its components and film thickness.

[0074] The sputtering target used in the sputtering method is itself another embodiment of the present disclosure. That is, the sputtering target is a sputtering target used for forming the oxide semiconductor thin film 3 containing metal elements, and the metal elements are composed of In, Zn, Fe, and inevitable impurities. A specific example of the sputtering target is an oxide target containing In, Zn, and Fe (IZFO target).

[0075] The lower limit of the number of In atoms relative to the total number of In, Zn and Fe atoms of the sputtering target is 50 atm%, more preferably 55 atm%, and even more preferably 60 atm%. On the other hand, the upper limit of the number of In atoms is 80 atm%, more preferably 75 atm%, and even more preferably 70 atm%. The lower limit of the number of Zn atoms relative to the total number of In, Zn and Fe atoms is 20 atm%, more preferably 25 atm%, and even more preferably 30 atm%. On the other hand, the upper limit of the number of Zn atoms is 48 atm%, more preferably 45 atm%, and even more preferably 40 atm%. The lower limit of the number of Fe atoms relative to the total number of In, Zn and Fe atoms is 1.5 atm%, more preferably 1.6 atm%, and even more preferably 1.7 atm%. On the other hand, the upper limit of the number of Fe atoms is 2.5 atm%, more preferably 2.4 atm%, and even more preferably 2.3 atm%. The lower limit of the In / Zn atomic ratio is 1.5, more preferably 1.6, and even more preferably 1.7. Meanwhile, the upper limit of the In / Zn atomic ratio is 2.5, more preferably 2.4, and even more preferably 2.3. By forming the oxide semiconductor thin film 3 using the sputtering target, it is possible to manufacture the thin film transistor having excellent S value and switching characteristics in addition to high mobility and light stress resistance.

[0076] The sputtering target is preferably made to have the same composition as that of a desired oxide semiconductor layer. By making the composition of the sputtering target the same as that of a desired oxide semiconductor layer, the compositional deviation of the oxide semiconductor layer to be formed can be suppressed, and therefore, an oxide semiconductor layer having a desired composition can be easily obtained.

[0077] The sputtering target can be manufactured by, for example, a powder sintering method.

[0078] The sputtering target for stacking the oxide semiconductor layer is not limited to the target containing In, Zn, and Fe described above, and multiple targets with different compositions may be used. In this case, the multiple targets are configured to contain In, Zn, and Fe as a whole. Also, each target may contain multiple elements of In, Zn, and Fe. The multiple targets may be oxide targets containing one or multiple elements of In, Zn, and Fe. The multiple targets can also be manufactured by, for example, a powder sintering method. When the multiple targets are used, a co-sputtering method in which the multiple targets are simultaneously discharged can be used as the sputtering method.

[0079] The conditions for stacking an oxide semiconductor layer by sputtering are not particularly limited. For example, the substrate temperature is 20° C. or higher and 50° C. or lower, and the deposition power density is 2 W / cm. 2 More than 3W / cm 2 The conditions are as follows: pressure is 0.1 Pa to 0.3 Pa, and carrier gas is Ar. In addition, oxygen may be contained in the atmosphere as an oxygen source. The oxygen content in the atmosphere may be 3 volume % to 5 volume %.

[0080] Note that the method for stacking the oxide semiconductor layers is not limited to a sputtering method, and a chemical film formation method such as a coating method may be used.

[0081] (Patterning) Next, the oxide semiconductor layer is patterned to form the oxide semiconductor thin film 3. The method for patterning the oxide semiconductor thin layer is not particularly limited, but for example, a method of performing photolithography followed by wet etching can be used.

[0082] After patterning, a pre-annealing treatment may be performed to reduce the density of trap states in the oxide semiconductor thin film 3. This can reduce the threshold voltage shift of the manufactured thin film transistor due to light irradiation.

[0083] As the lower limit of the temperature of the pre-annealing treatment, 300°C is preferable, and 350°C is more preferable. On the other hand, as the upper limit of the temperature of the annealing treatment, 450°C is preferable, and 400°C is more preferable. When the temperature of the pre-annealing treatment is less than the above lower limit, the effect of improving the electrical characteristics of the thin film transistor may be insufficient. Conversely, when the temperature of the pre-annealing treatment exceeds the above upper limit, the oxide semiconductor thin film 3 may be damaged by heat.

[0084] The conditions of the pressure and time of the annealing treatment are not particularly limited. For example, in an N2 atmosphere at atmospheric pressure (0.9 atm or more and 1.1 atm or less), the conditions of a time of 10 minutes or more and 60 minutes or less can be used.

[0085] <ESL protective film forming step> In the ESL protective film forming step, an ESL protective film 4 is formed on the portion of the surface of the oxide semiconductor thin film 3 where the source and drain electrodes 5 are not formed.

[0086] Specifically, first, an insulating film is laminated on the surface side of the substrate X to a desired film thickness by a known method, for example, various CVD methods. For example, when laminating a silicon oxide film by plasma CVD, the substrate temperature is 100°C or more and 300°C or less, the film forming power density is 0.2 W / cm 2 above 0.5 W / cm 2 below, and the pressure is 100 Pa or more and 300 Pa or less. It can be carried out using a mixed gas of N2O and SiH4 as the source gas.

[0087] <Source and drain electrode forming step> In the source and drain electrode forming step, a source electrode 5a and a drain electrode 5b that are electrically connected to the oxide semiconductor thin film 3 are formed at both ends of the channel of the thin film transistor.

[0088] Specifically, a conductive film is first laminated to a desired thickness on the surface of the substrate X by a known method, for example, a sputtering method. The conditions for laminating the conductive film by the sputtering method are not particularly limited, but may be, for example, a substrate temperature of 20° C. to 50° C., and a deposition power density of 3 W / cm. 2 More than 4W / cm 2 The conditions are as follows: pressure is 0.1 Pa or more and 0.4 Pa or less, and carrier gas is Ar.

[0089] Next, the conductive film is patterned to form the source electrode 5a and the drain electrode 5b. The patterning method is not particularly limited, but may be, for example, a method of performing photolithography followed by wet etching.

[0090] <Passivation insulating film deposition process> In the passivation insulating film forming step, a passivation insulating film 6 that covers the thin film transistor is formed.

[0091] Specifically, an insulating film is laminated to a desired thickness on the front surface of the substrate X by a known method, for example, various CVD methods. For example, the conditions for laminating a silicon nitride film by the plasma CVD method are a substrate temperature of 100° C. to 200° C. and a deposition power density of 0.2 W / cm. 2 More than 0.5W / cm 2 Hereinafter, the process can be performed under conditions of a pressure of 100 Pa or more and 300 Pa or less, using a mixed gas of NH3 and SiH4 as a source gas.

[0092] <Conductive film deposition process> In the conductive film forming step, the conductive film 7 that is electrically connected to the drain electrode 5b through the contact hole 8 is formed.

[0093] Specifically, first, a contact hole 8 is formed by a known method, for example, photolithography to pattern the contact portion with the drain electrode 5b, followed by dry etching. Next, a conductive film 7 that is electrically connected to the drain electrode 5b through the contact hole 8 is formed by a known method, for example, sputtering. The conditions for laminating the conductive film 7 by sputtering are not particularly limited, but may be, for example, a substrate temperature of 20° C. to 50° C., and a film formation power density of 3 W / cm. 2 More than 4W / cm 2 The conditions are as follows: pressure is 0.1 Pa or more and 0.4 Pa or less, and carrier gas is Ar.

[0094] <Post-annealing process> The post-annealing process is a process of performing a final heat treatment. This heat treatment can reduce the density of trap states formed at the interface between the oxide semiconductor thin film 3 and the gate insulating film 2 and at the interface between the oxide semiconductor thin film 3 and the ESL protective film 4. This can reduce the threshold voltage shift of the thin film transistor due to light irradiation.

[0095] The lower limit of the post-annealing temperature is preferably 200° C., more preferably 250° C. On the other hand, the upper limit of the post-annealing temperature is preferably 400° C., more preferably 350° C. If the post-annealing temperature is below the lower limit, the effect of improving the electrical characteristics of the thin film transistor may be insufficient. Conversely, if the post-annealing temperature is above the upper limit, the thin film transistor may be damaged by heat.

[0096] The pressure and time conditions of the post-annealing treatment are not particularly limited, but for example, atmospheric pressure (0.9 atm to 1.1 atm) and 10 minutes to 60 minutes can be used. The post-annealing treatment may be performed in an air atmosphere, but is preferably performed in an inert gas atmosphere such as nitrogen. By performing the post-annealing treatment in an inert gas atmosphere, it is possible to suppress variations in the quality of the thin film transistor caused by the binding of molecules contained in the atmosphere to the thin film transistor during the post-annealing treatment.

[0097] [advantage] The oxide semiconductor thin film 3 has a high light stress resistance because the number of In atoms is 50 atm% to 80 atm%, the number of Zn atoms is 20 atm% to 48 atm%, and the number of Fe atoms is 1.5 atm% or more, relative to the total number of In, Zn, and Fe atoms. Also, the oxide semiconductor thin film 3 has a number of Fe atoms of 2.5 atm% or less, so that the carrier mobility can be improved when a thin film transistor is formed using the oxide semiconductor thin film 3. Furthermore, the ratio of the number of In atoms to Zn atoms, In / Zn, is 1.5 or more, so that the S value can be increased, and is 2.5 or less, so that switching characteristics can be excellent.

[0098] Furthermore, the thin-film transistor has excellent S value and switching characteristics in addition to high mobility and light stress resistance, since it has the oxide semiconductor thin film 3. Therefore, the thin-film transistor is suitable for use in an organic EL display.

[0099] The sputtering target contains In, Zn, and Fe whose atomic numbers are within the above ranges, and the ratio of the atomic numbers of In / Zn is within the above range. Therefore, by forming an oxide semiconductor thin film 3 using the sputtering target and then forming a thin film transistor on the oxide semiconductor thin film 3, it is possible to manufacture a thin film transistor that has excellent S value and switching characteristics in addition to high mobility and light stress resistance.

[0100] [Other embodiments] The oxide semiconductor thin film, thin film transistor, and sputtering target of the present disclosure are not limited to the above-described embodiments.

[0101] In the above embodiment, the case where the thin film transistor is a bottom gate type transistor has been described, but a top gate type transistor may also be used.

[0102] In the above embodiment, the thin film transistor has an ESL protective film, but the ESL protective film is not an essential component. For example, when forming the source and drain electrodes by mask deposition or lift-off, the oxide semiconductor thin film is not easily damaged, so the ESL protective film can be omitted.

[0103] In the above embodiment, the oxide semiconductor thin film does not substantially contain any metal element other than In, Zn, and Fe, but may inevitably contain other metal elements, such as Sn. EXAMPLES

[0104] The present invention will be described in detail below with reference to examples. However, the present invention should not be construed as being limited to the description of these examples.

[0105] [Example 1] A glass substrate (Corning "EagleXG", diameter 6 inches, thickness 0.7 mm) was prepared, and a Mo thin film was formed on the surface of the glass substrate to an average thickness of 100 nm. The film formation conditions were a substrate temperature of 25°C (room temperature) and a film formation power density of 3.8 W / cm. 2 The pressure was 0.266 Pa, and the carrier gas was Ar. After the Mo thin film was formed, a gate electrode was formed by patterning.

[0106] Next, a silicon oxide film with an average thickness of 250 nm was formed as a gate insulating film by CVD so as to cover the gate electrode. A mixture of N2O and SiH4 was used as the source gas. The film formation conditions were a substrate temperature of 320°C and a film formation power density of 0.96 W / cm.2 , and the pressure was 133 Pa.

[0107] Next, an oxide semiconductor layer containing substantially only In, Zn, and Fe and having an average thickness of 40 nm was formed as an oxide semiconductor layer on the front surface side of the glass substrate by a sputtering method.

[0108] The sputtering method used was a method that has been established as a method for investigating the optimal composition ratio. Specifically, three targets, In2O3, ZnO, and In2O3 with Fe chips attached, were placed at different positions around the glass substrate, and sputtering was performed on the stationary glass substrate to form an oxide semiconductor layer. According to this method, three targets with different constituent elements are placed at different positions around the glass substrate, so the distance from each target varies depending on the position on the glass substrate. Since the amount of element supplied from the target decreases as it moves away from the sputtering target, for example, Zn is more than In at a position close to the ZnO target and far from the In2O3 target, and conversely, In is more than Zn at a position close to the In2O3 target and far from the ZnO target. In other words, an oxide semiconductor layer with a different composition ratio can be obtained depending on the position on the glass substrate.

[0109] A sputtering device (ULVAC's "CS200") was used, and the deposition conditions were a substrate temperature of 25°C (room temperature) and a deposition power density of 2.55 W / cm. 2 The pressure was 0.133 Pa, and the carrier gas was Ar. The oxygen content of the atmosphere was 4% by volume.

[0110] The obtained oxide semiconductor layer was patterned by photolithography and wet etching to form an oxide semiconductor thin film with different compositions depending on the position on the glass substrate. The wet etchant used was "ITO-07N" manufactured by Kanto Chemical Co., Ltd.

[0111] Here, in order to improve the film quality of this oxide semiconductor thin film, a pre-annealing treatment was carried out under the conditions of an air atmosphere (atmospheric pressure) at 300° C. for 60 minutes.

[0112] Next, a silicon oxide film was formed on the front surface of the glass substrate by CVD to an average thickness of 100 nm. A mixture of N2O and SiH4 was used as the source gas. The film formation conditions were a substrate temperature of 230°C and a film formation power density of 0.32 W / cm. 2 and the pressure was 133 Pa. After the silicon oxide film was formed, an ESL protective film was formed by patterning.

[0113] Next, a Mo thin film was formed on the front surface of the glass substrate to an average thickness of 200 nm. The film formation conditions were a substrate temperature of 25°C (room temperature) and a film formation power density of 3.8 W / cm. 2 The pressure was 0.266 Pa, and the carrier gas was Ar. After the Mo thin film was formed, a source electrode and a drain electrode were formed by patterning.

[0114] Next, a two-layered passivation insulating film consisting of a silicon oxide film (average thickness 100 nm) and a silicon nitride film (average thickness 150 nm) was formed on the front side of the glass substrate by CVD. A mixture of N2O and SiH4 was used as the source gas for forming the silicon oxide film, and a mixture of NH3 and SiH4 was used for forming the silicon nitride film. The film formation conditions were a substrate temperature of 150°C and a film formation power density of 0.32 W / cm. 2 , and the pressure was 133 Pa.

[0115] Next, a contact hole was formed by photolithography and dry etching, and a pad was provided for electrical connection to the drain electrode. By contacting a probe with this pad, electrical measurements of the thin-film transistor can be performed.

[0116] Finally, a post-annealing process was performed under the conditions of atmospheric pressure, N2 atmosphere, and 250°C for 30 minutes.

[0117] In this way, the thin film transistor of Example 1 was obtained. The channel length of this thin film transistor was 20 μm, and the channel width was 200 μm. The composition of the oxide semiconductor thin film in the thin film transistor of Example 1 was as shown in Table 1. The In / Zn ratio was determined according to the composition of the oxide semiconductor thin film. This ratio is also shown in Table 1.

[0118] [Examples 2 to 10, Comparative Examples 1 to 7] The thin film transistors of Examples 2 to 10 and Comparative Examples 1 to 7 were obtained in the same manner as in Example 1, except that the number of In, Zn, and Fe atoms relative to the total number of In, Zn, and Fe atoms in the sputtering target used, i.e., the number of In, Zn, and Fe atoms relative to the total number of In, Zn, and Fe atoms in the oxide semiconductor thin film formed, and the pre-annealing and post-annealing temperatures were changed as shown in Table 1.

[0119] [Measurement method] For the thin film transistors of Examples 1 to 10 and Comparative Examples 1 to 7, the carrier mobility, threshold voltage, and S value were measured.

[0120] All of these measurements were calculated from the static characteristics (Id-Vg characteristics) of the thin film transistor of the transistor. The static characteristics were measured using a semiconductor parameter analyzer (Agilent Technology's "HP4156C"). The measurement conditions were as follows: source voltage was fixed at 0V, drain voltage was fixed at 10V, and gate voltage was changed from -30V to 30V in 0.25V increments. The measurements were performed at room temperature (25°C). The measurement method is described below.

[0121] <Carrier mobility> The carrier mobility is the field effect mobility μ FE [m 2 / Vs]. This field effect mobility μ FE [m 2 / Vs] are the gate voltage Vg [V], the threshold voltage Vth [V], the drain current Id [A], the channel length L [m], the channel width W [m], and the capacitance C of the gate insulating filmox When [F] is used, in the saturation region (Vg > Vd - Vth) of the above static characteristics, μ shown in the following formula (3) FE [m 2 / Vs] is calculated. The results are shown in Table 1. [Number]

[0122] [Threshold voltage] The threshold voltage is the value calculated from the static characteristics of the thin film transistor where the drain current of the transistor becomes 10 -9 A. The results are shown in Table 1.

[0123] [S value] The S value is the change amount of the gate voltage required to increase the drain current by one digit from the above static characteristics, and the minimum value is used. The results are shown in Table 1.

[0124] [Evaluation] Based on the above measurement results, evaluation was performed according to the following criteria. Each result is shown in Table 1.

[0125] (Carrier mobility) Basically, the larger the carrier mobility, the better. Assuming the use of an organic EL display, it is preferably 25 m 2 / Vs or more. A: The carrier mobility is 25 m 2 / Vs or more. B: The carrier mobility is less than 25 m 2 / Vs.

[0126] (Threshold voltage) If the threshold voltage is too low, even when the gate potential is 0 V, it cannot be sufficiently turned off and the leakage current increases, and the controllability of the switching operation deteriorates. Also, considering the stabilization of the initial threshold voltage, the threshold voltage is preferably 0.6 V or more. A: The threshold voltage is 0.6 V or more. B: The threshold voltage is less than 0.6 V.

[0127] (S value) If the S value is too low, a slight change in gate voltage will cause a large change in current, making current control difficult. On the other hand, if the S value is too high, a large change in gate voltage will be required to obtain the required current, and switching of the thin-film transistor will take time. Taking these factors into consideration, the preferable range is set to 0.4V / dec or more and 1.0V / dec or less. A: The S value is between 0.4V / dec and 1.0V / dec. B: The S value is less than 0.4 V / dec or more than 1.0 V / dec.

[0128] (mobility x threshold voltage) Even if the mobility is high, if the threshold voltage is high, the carrier density will be small, and the switching characteristics will be degraded. Conversely, even if the threshold voltage is low, if the mobility is small, the switching characteristics will be degraded. As an index to evaluate this relationship, the product of mobility and threshold voltage is defined. When mobility × threshold voltage is 30 cm 2 / s or more 100cm 2 / s or less was judged to have excellent switching characteristics. A: Mobility × threshold voltage is 30cm 2 / s or more 100cm 2 / s or less. B:S value is 30cm 2 / s or less than 100cm 2 / s.

[0129] [Table 1]

[0130] As seen from Table 1, the thin film transistors of Examples 1 to 10 have high carrier mobility and are excellent in S value and switching characteristics. In contrast, the thin film transistors of Comparative Examples 1 to 5 are considered to have low carrier mobility mainly because the In / Zn atomic ratio is less than 1.5. Among them, Comparative Examples 1 and 2 are considered to have low S value mainly because the number of Zn atoms is more than 49 atm %. Furthermore, the thin film transistors of Comparative Examples 6 and 7 are considered to have poor switching characteristics, which are indexed by mobility x threshold voltage, mainly because the In / Zn atomic ratio is more than 2.5.

[0131] From the above, it can be seen that a thin-film transistor having excellent S value and switching characteristics in addition to high mobility can be formed by setting the number of In atoms to 50 atm% or more and 80 atm% or less, the number of Zn atoms to 20 atm% or more and 48 atm% or less, and the number of Fe atoms to 1.5 atm% or more and 2.5 atm% or less, relative to the total number of In, Zn, and Fe atoms in the oxide semiconductor thin film, and by setting the ratio of the number of In atoms to Zn atoms, In / Zn, to 1.5 or more and 2.5 or less. [Industrial Applicability]

[0132] As described above, the oxide semiconductor thin film of the present disclosure has high mobility and light stress resistance, and also has excellent S value and switching characteristics when a transistor is formed. A thin film transistor of the present disclosure using this oxide semiconductor thin film has high mobility and light stress resistance, and also has excellent S value and switching characteristics. Furthermore, the sputtering target of the present disclosure can form this oxide semiconductor thin film. [Explanation of symbols]

[0133] 1. Gate electrode 2. Gate insulating film 3. Oxide Semiconductor Thin Film 4 ESL protective film 5. Source and drain electrodes 5a Source electrode 5b Drain electrode 6 Passivation insulating film 7 Conductive Film 8 Contact Hole X-Board

Claims

1. An oxide semiconductor thin film containing a metal element, The metal elements consist of In, Zn, Fe and unavoidable impurities, With respect to the total number of In, Zn and Fe atoms, The number of In atoms is 50 atm % or more and 80 atm % or less, The number of Zn atoms is 20 atm % or more and 48 atm % or less, The number of Fe atoms is 1.5 atm % or more and 2.5 atm % or less, An oxide semiconductor thin film in which the ratio of the number of In atoms to the number of Zn atoms, In / Zn, is 1.5 or more and 2.5 or less.

2. A thin film transistor comprising the oxide semiconductor thin film according to claim 1 , A thin-film transistor used in organic EL displays.

3. The S value is 0.4 V / dec or more and 1.0 V / dec or less, 3. The thin film transistor according to claim 2, wherein the threshold voltage is 0.6 V or more.

4. Carrier mobility is 25 cm ２ The thin film transistor according to claim 2 or claim 3, wherein the Vs exceeds 1 / Vs.

5. A sputtering target used for forming an oxide semiconductor thin film containing a metal element, The metal elements consist of In, Zn, Fe and unavoidable impurities, With respect to the total number of In, Zn and Fe atoms, The number of In atoms is 50 atm % or more and 80 atm % or less, The number of Zn atoms is 20 atm % or more and 48 atm % or less, The number of Fe atoms is 1.5 atm % or more and 2.5 atm % or less, A sputtering target having a ratio of the number of In atoms to the number of Zn atoms, In / Zn, of 1.5 or more and 2.5 or less.

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