Hybrid memory system configurable to store neural memory weight data in either analog or digital form - Patent Application 20070122999

Abstract

Numerous embodiments of a hybrid memory system are disclosed. The hybrid memory can store weight data in an array in either analog form, for use in an analog neural memory system, or in digital form, for use in a digital neural memory system. The input and output circuits can support both forms of weight data.

Description

[Technical Field]

[0001] (Priority Claim) This application claims priority to U.S. Provisional Application No. 63 / 232,149, filed August 11, 2021, entitled "Hybrid Memory System Configurable to Store Neural Memory Weight Data in Analog or Digital Form," and U.S. Patent Application No. 17 / 519,241, filed November 4, 2021, entitled "Hybrid Memory System Configurable to Store Neural Memory Weight Data in Analog or Digital Form."

[0002] FIELD OF THE INVENTION Numerous embodiments of hybrid memory systems are disclosed. The hybrid memory can store weight data in an array in either analog form, when used in an analog neural memory system, or in digital form, when used in a digital neural memory system. The input and output circuits can support both forms of weight data. [Background technology]

[0003] Artificial neural networks mimic biological neural networks (the central nervous systems of animals, particularly the brain) and are used to estimate or approximate functions that may depend on multiple inputs and are generally unknown. Artificial neural networks generally contain layers of interconnected "neurons" that exchange messages between each other.

[0004] FIG. 1 shows an artificial neural network, where circles illustrate layers of inputs or neurons. Connections (called synapses) are represented by arrows and have numerical weights that can be tuned based on experience. This allows the neural network to adapt to the inputs and learn. Typically, a neural network contains multiple layers of inputs. There are typically one or more hidden layers of neurons, and an output layer of neurons that provide the neural network's output. At each level, neurons make decisions individually or collectively based on the data received from the synapses.

[0005] One of the major challenges in developing artificial neural networks for high-performance information processing is the lack of suitable hardware technology. In practice, practical neural networks rely on a very large number of synapses, which allows for high connectivity between neurons and therefore a very high degree of parallelization of computation. In principle, such complexity could be achieved using digital supercomputers or dedicated graphic processing unit clusters. However, in addition to high cost, these approaches also suffer from poor energy efficiency compared to biological networks, which primarily perform low-precision analog computations and therefore consume much less energy. While CMOS analog circuits have been used in artificial neural networks, most CMOS-implemented synapses are too bulky given the large number of neurons and synapses.

[0006] The applicant previously disclosed an artificial (analog) neural network utilizing one or more non-volatile memory arrays as synapses in U.S. Patent Application No. 15 / 594,439, which is incorporated by reference. The non-volatile memory array operates as an analog neural memory. The neural network device includes a first plurality of synapses configured to receive a first plurality of inputs and generate a first plurality of outputs therefrom, and a first plurality of neurons configured to receive the first plurality of outputs. The first plurality of synapses includes a plurality of memory cells, each including spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending therebetween, a floating gate disposed insulated above a first portion of the channel region, and a non-floating gate disposed insulated above a second portion of the channel region. Each of the plurality of memory cells is configured to store a weight value corresponding to a number of electrons in the floating gate. The plurality of memory cells is configured to generate the first plurality of outputs by multiplying the first plurality of inputs by the stored weight value. <Nonvolatile memory cell>

[0007] Nonvolatile memory is well known. For example, U.S. Pat. No. 5,029,130 ​​(the "'130 patent"), incorporated herein by reference, discloses an array of split-gate nonvolatile memory cells, which are a type of flash memory cell. Such a memory cell 210 is shown in FIG. 2. Each memory cell 210 includes a source region 14 and a drain region 16 formed in a semiconductor substrate 12, with a channel region 18 between the source region 14 and the drain region 16. A floating gate 20 is formed above a first portion of the channel region 18 (and controls the conductivity of the first portion of the channel region 18) and is insulated therefrom and above a portion of the source region 14. A word line terminal 22 (typically coupled to a word line) has a first portion disposed above and insulated therefrom (and controls the conductivity of the second portion of the channel region 18) and a second portion extending upward above the floating gate 20. A floating gate 20 and a wordline terminal 22 are insulated from the substrate 12 by a gate oxide. A bitline 24 is coupled to the drain region 16.

[0008] The memory cell 210 is erased (electrons are removed from the floating gate) by applying a high positive voltage to the word line terminal 22, which causes electrons in the floating gate 20 to pass via Fowler-Nordheim (FN) tunneling from the floating gate 20 to the word line terminal 22 through the insulator between them.

[0009] The memory cell 210 is programmed by hot electron source side injection (SSI) by applying a positive voltage to the word line terminal 22 and a positive voltage to the source region 14, where electrons are injected into the floating gate. Electrons flow from the drain region 16 toward the source region 14. The electrons accelerate and heat up when they reach the gap between the word line terminal 22 and the floating gate 20. Some of the heated electrons are injected into the floating gate 20 through the gate oxide due to electrostatic attraction from the floating gate 20.

[0010] The memory cell 210 is read by applying a positive read voltage to the drain region 16 and word line terminal 22 (turning on the portion of the channel region 18 below the word line terminal). When the floating gate 20 is positively charged (i.e., erased with electrons), the portion of the channel region 18 below the floating gate 20 is also turned on, and current flows through the channel region 18, which is sensed as an erased or "1" state. When the floating gate 20 is negatively charged (i.e., programmed with electrons), the portion of the channel region below the floating gate 20 is mostly or completely off, and no (or very little) current flows through the channel region 18, which is sensed as a programmed or "0" state.

[0011] Table 1 shows typical voltage / current ranges that can be applied to the terminals of memory cell 110 to perform read, erase, and program operations. Table 1: Operation of flash memory cell 210 of FIG. 3 [Table 1]

[0012] Other split-gate memory cell configurations, including other types of flash memory cells, are also known. For example, FIG. 3 shows a four-gate memory cell 310 including a source region 14, a drain region 16, a floating gate 20 above a first portion of a channel region 18, a select gate 22 (typically coupled to a word line, WL) above a second portion of the channel region 18, a control gate 28 above the floating gate 20, and an erase gate 30 above the source region 14. This configuration is described in U.S. Pat. No. 6,747,310, which is incorporated herein by reference for all purposes. Here, all gates, except for the floating gate 20, are non-floating gates, meaning they are electrically connected or connectable to a voltage source. Programming is performed by heated electrons injecting themselves from the channel region 18 into the floating gate 20. Erasing is performed by electrons tunneling from the floating gate 20 to the erase gate 30.

[0013] Table 2 shows typical voltage / current ranges that can be applied to the terminals of memory cell 310 to perform read, erase, and program operations. Table 2: Operation of the flash memory cell 310 of FIG. 3 [Table 2]

[0014] Figure 4 shows another type of flash memory cell, a three-gate memory cell 410. Memory cell 410 is identical to memory cell 310 of Figure 3, except that memory cell 410 does not have a separate control gate. Erase and read operations (erasure occurs through the use of an erase gate) are similar to those of Figure 3, except that no control gate bias is applied. Programming operations are also performed without a control gate bias, and as a result, a higher voltage must be applied to the source line during a program operation to compensate for the lack of control gate bias.

[0015] Table 3 shows typical voltage / current ranges that may be applied to the terminals of memory cell 410 to perform read, erase, and program operations. Table 3: Operation of flash memory cell 410 of FIG. 4 [Table 3]

[0016] Figure 5 shows another type of flash memory cell, a stacked gate memory cell 510. Memory cell 510 is similar to memory cell 210 of Figure 2, except that the floating gate 20 extends over the entire channel region 18, and a control gate 22 (where it is coupled to a word line) extends over the floating gate 20, separated by an insulating layer (not shown). Erasing is accomplished by FN tunneling of electrons from the FG to the substrate, and programming is accomplished by FN tunneling of electrons from the channel region This is accomplished by channel hot electron (CHE) injection in the region between source region 18 and drain region 16, by electrons flowing from source region 14 toward drain region 16, and by a read operation that is similar to the read operation of memory cell 210 with a higher control gate voltage.

[0017] Table 4 shows typical voltage ranges that may be applied to the terminals of memory cell 510 and substrate 12 to perform read, erase, and program operations. Table 4: Operation of flash memory cell 510 of FIG. 5 [Table 4]

[0018] The methods and means described herein may be applied to other non-volatile memory technologies such as, but not limited to, FINFET split-gate flash or stacked-gate flash memory, NAND flash, SONOS (silicon-oxide-nitride-oxide-silicon, charge traps in nitride), MONOS (metal-oxide-nitride-oxide-silicon, metal charge traps in nitride), ReRAM (resistive ram), PCM (phase change memory), MRAM (ferroelectric ram), FeRAM (ferroelectric ram), CT (charge trap) memory, CN (carbon-tube) memory, OTP (one time programmable, bi-level or multi-level) and CeRAM (correlated electron ram).

[0019] To utilize a memory array containing one of the non-volatile memory cell types in an artificial neural network, two modifications are made: First, as explained further below, the lines are configured so that each memory cell can be individually programmed, erased, and read without adversely affecting the memory state of other memory cells in the array; Second, continuous (analog) programming of the memory cells is provided.

[0020] Specifically, the memory state (i.e., the charge on the floating gate) of each memory cell in the array can be continuously changed from a fully erased state to a fully programmed state, independently and with minimal disturbance to other memory cells. In another embodiment, the memory state (i.e., the charge on the floating gate) of each memory cell in the array can be continuously changed from a fully programmed state to a fully erased state, and vice versa, independently and with minimal disturbance to other memory cells. This means that the cell storage is analog, or at a minimum, capable of storing one of a number of discrete values ​​(such as 16 or 64 different values), allowing every cell in the memory array to be tuned very precisely and individually, making the memory array ideal for storing and fine-tuning adjustments to the synaptic weights of a neural network. <Neural network using nonvolatile memory cell array>

[0021] 6 conceptually illustrates a non-limiting example of a neural network utilizing the non-volatile memory array of the present embodiments. This example uses a non-volatile memory array neural network for a face recognition application, although other suitable applications can also be implemented using a non-volatile memory array-based neural network.

[0022] S0 is the input layer, which in this example is a 32x32 pixel RGB image with 5-bit precision (i.e., three 32x32 pixel arrays, one for each color R, G, and B, with each pixel having 5-bit precision). Synapse CB1 going from input layer S0 to layer C1 scans the input image with overlapping 3x3 pixel filters (kernels), applying different sets of weights to some instances and shared weights to other instances, and shifts the filters by one pixel (or two or more pixels, depending on the model). Specifically, the values ​​of nine pixels in the 3x3 portion of the image (i.e., referred to as filters or kernels) are provided to synapse CB1, which multiplies these nine input values ​​by the appropriate weights and, after summing the outputs of the multiplications, determines a single output value, which is applied by the first synapse of CB1 to generate one pixel of layer C1's feature map. The 3x3 filter is then shifted one pixel to the right in input layer S0 (i.e., adding a column of three pixels to the right and dropping a column of three pixels on the left), so that the nine pixel values ​​of this newly positioned filter are provided to synapse CB1, where they are multiplied by the same weights as above to determine a second single output value by the associated synapse. This process continues until the 3x3 filter has scanned the entire 32x32 pixel image of input layer S0 for all three colors and all bits (precision values). The process is then repeated using different sets of weights to generate different feature maps for layer C1 until all of layer C1's feature maps have been calculated.

[0023] In this example, there are 16 feature maps in layer C1, each having 30x30 pixels. Each pixel is a new feature pixel extracted from the multiplication of the input and the kernel, and therefore each feature map is a two-dimensional array. Thus, in this example, layer C1 comprises 16 layers of two-dimensional arrays. (Note that the layers and arrays referred to herein are logical, not necessarily physical, relationships; i.e., the arrays are not necessarily oriented in a physical two-dimensional array.) Each of the 16 feature maps in layer C1 is generated by one of 16 different sets of synaptic weights applied to the filter scans. The C1 feature maps can all target different aspects of the same image feature, such as boundary identification. For example, a first map (generated using a first set of weights shared by all scans used to generate this first map) can identify circular edges, while a second map (generated using a second set of weights different from the first set of weights) can identify rectangular edges or the aspect ratio of a particular feature, etc.

[0024] Before going from layer C1 to layer S1, an activation function P1 (pooling) is applied, which pools values ​​from non-overlapping, contiguous 2x2 regions in each feature map. The purpose of pooling function P1 is to average nearby locations (or a max function can be used), e.g., to reduce dependency on edge locations, and to reduce data size before going to the next stage. In layer S1, there are 16 15x15 feature maps (i.e., 16 different arrays of 15x15 pixels each). Synapse CB2 going from layer S1 to layer C2 scans the maps in layer S1 with a 4x4 filter with a filter shift of 1 pixel. In layer C2, there are 22 12x12 feature maps. Before going from layer C2 to layer S2, an activation function P2 (pooling) is applied, which pools values ​​from non-overlapping, contiguous 2x2 regions in each feature map. In layer S2, there are 22 6x6 feature maps. At synapse CB3 going from layer S2 to layer C3, an activation function (pooling) is applied, where every neuron in layer C3 connects to every map in layer S2 through a respective synapse in CB3. There are 64 neurons in layer C3. Synapse CB4 going from layer C3 to output layer S3 fully connects C3 to S3, i.e., every neuron in layer C3 connects to every neuron in layer S3. The output at S3 includes 10 neurons, where the neuron with the highest output determines the class. This output can indicate, for example, the identification or classification of the content of the original image.

[0025] Each layer of the synapse is implemented using an array or portion of an array of non-volatile memory cells.

[0026] Figure 7 is a block diagram of an array that can be used for this purpose. A vector-by-matrix multiplication (VMM) array 32 contains nonvolatile memory cells and is utilized as a synapse between one layer and the next (such as CB1, CB2, CB3, and CB4 in Figure 6). Specifically, the VMM array 32 includes an array of nonvolatile memory cells 33, an erase gate and word line gate decoder 34, a control gate decoder 35, a bit line decoder 36, and a source line decoder 37, which decode the respective inputs to the nonvolatile memory cell array 33. Inputs to the VMM array 32 can come from the erase gate and word line gate decoder 34 or from the control gate decoder 35. The source line decoder 37 in this example also decodes the output of the nonvolatile memory cell array 33. Alternatively, the bit line decoder 36 can decode the output of the nonvolatile memory cell array 33.

[0027] The non-volatile memory cell array 33 serves two purposes. First, the non-volatile memory cell array 33 stores the weights used by the VMM array 32. Second, the non-volatile memory cell array 33 effectively multiplies the inputs by the weights stored in the non-volatile memory cell array 33 and sums them for each output line (source line or bit line) to produce an output that becomes the input to the next layer or the input to the last layer. Having the non-volatile memory cell array 33 perform the multiplication and addition functions eliminates the need for separate multiplication and addition logic and is also more power efficient due to in-memory computation.

[0028] The outputs of the non-volatile memory cell array 33 are fed to a differential summer (such as a summing op-amp or summing current mirror) 38, which sums the outputs of the non-volatile memory cell array 33 to create a single value for the convolution. The differential summer 38 is arranged to perform a summation of the positive and negative weights.

[0029] The summed output values ​​of the differential adder 38 are then provided to an activation function block 39, which rectifies the output. The activation function block 39 may provide a sigmoid, tanh, or ReLU function. The rectified output values ​​of the activation function block 39 become elements of a feature map as the next layer (e.g., C1 in FIG. 6) and are then applied to the next synapse to generate the next feature map layer or the final layer. Thus, in this example, the non-volatile memory cell array 33 constitutes multiple synapses (receiving input from a previous layer of neurons or from an input layer such as an image database), and the summing op-amps 38 and activation function block 39 constitute multiple neurons.

[0030] The inputs to the VMM array 32 of FIG. 7 (WLx, EGx, CGx, and optionally BLx and SLx) may be analog levels, binary levels, or digital bits (in which case a DAC is provided to convert the digital bits to the appropriate input analog levels), and the outputs may be analog levels, binary levels, or digital bits (in which case an output ADC is provided to convert the output analog levels to digital bits).

[0031] FIG. 8 is a block diagram illustrating the use of multiple layers of VMM array 32, labeled in the figure as VMM arrays 32a, 32b, 32c, 32d, and 32e. As shown in FIG. 8, input (denoted Inputx) is converted from digital to analog by digital-to-analog converter 31 and provided to input VMM array 32a. The converted analog input can be a voltage or current. The first layer's input D / A conversion can be performed by using a function or LUT (look up table) that maps input Inputx to the appropriate analog level of the matrix multiplier of input VMM array 32a. The input conversion can also be performed by an analog-to-analog (A / A) converter to convert an external analog input to the mapped analog input to input VMM array 32a.

[0032] The output generated by input VMM array 32a is then provided as input to the next VMM array (hidden level 1) 32b, which then generates an output that is provided as input to input VMM array (hidden level 2) 32c, and so on. The various layers of the VMM array 32 function as layers of synapses and neurons of a convolutional neural network (CNN). Each VMM array 32a, 32b, 32c, 32d, and 32e can be a standalone physical non-volatile memory array, or multiple VMM arrays can utilize different portions of the same physical non-volatile memory array, or multiple VMM arrays can utilize overlapping portions of the same physical non-volatile memory array. The example shown in FIG. 8 includes five layers (32a, 32b, 32c, 32d, and 32e): one input layer (32a), two hidden layers (32b and 32c), and two fully connected layers (32d and 32e). Those skilled in the art will appreciate that this is merely an example, and that the system may alternatively include more than two hidden layers and more than two fully connected layers. <Vector Matrix Multiplication (VMM) Array>

[0033] 9 shows a neuron VMM array 900 that is particularly suited for the memory cells 310 shown in FIG. 3 and that is utilized as part of the synapses and neurons between the input layer and the next layer. The VMM array 900 includes a memory array 901 of non-volatile memory cells and a reference array 902 of non-volatile reference memory cells (located at the top of the array). Alternatively, a separate reference array can be located at the bottom.

[0034] In VMM array 900, control gate lines, such as control gate line 903, run vertically (thus, row-oriented reference array 902 is orthogonal to control gate line 903), and erase gate lines, such as erase gate line 904, run horizontally. Here, inputs to VMM array 900 are provided to control gate lines (CG0, CG1, CG2, CG3), and outputs of VMM array 900 appear on source lines (SL0, SL1). In one embodiment, only even rows are used, and in another embodiment, only odd rows are used. The current in each source line (SL0, SL1, respectively) performs a function of the sum of all currents from memory cells connected to that particular source line.

[0035] As described herein for neural networks, the non-volatile memory cells of VMM array 900, ie, memory cells 310 of VMM array 900, are preferably configured to operate in the sub-threshold region.

[0036] The nonvolatile reference memory cells and nonvolatile memory cells described herein are biased in weak inversion (sub-threshold region) as follows: Ids=Io * e (Vg-Vth) / nVt =w * Io * e (Vg) / nVt In the formula, w=e (-Vth) / nVt and Ids is the drain-source current, Vg is the gate voltage of the memory cell, Vth is the threshold voltage of the memory cell, and Vt is the thermal voltage = k * where T / q, k is Boltzmann's constant, T is temperature in Kelvin, q is electron charge, n is slope coefficient = 1 + (Cdep / Cox), where Cdep = capacitance of the depletion layer, and Cox is capacitance of the gate oxide layer, Io is memory cell current at gate voltage equal to threshold voltage, and Io is (Wt / L) * u * Cox * (n-1) * Vt 2 where u is the carrier mobility, and Wt and L are the width and length of the memory cell, respectively.

[0037] When using an IV-log converter that converts input current to input voltage using a memory cell (such as a reference memory cell or peripheral memory cell) or transistor: Vg=n * Vt * log[Ids / wp * Io] where wp is the w of the reference or peripheral memory cell.

[0038] For a memory array used as a vector matrix multiplier VMM array with current inputs, the output current is: Iout=wa * Io * e (Vg) / nVt , i.e. Iout=(wa / wp) * Iin=W * Iin W=e (Vthp-Vtha) / nVt where wa=w of each memory cell in the memory array. Vthp is the effective threshold voltage of the peripheral memory cells, and Vtha is the effective threshold voltage of the main (data) memory cells. Note that the threshold voltage of a transistor is a function of the substrate body bias voltage, which is represented as Vsb, and can be modulated to compensate for various conditions at such temperature. The threshold voltage Vth can be expressed as: TIFF0007765596000005.tif22170

[0039] The word line or control gate can be used as the input of the memory cell for the input voltage.

[0040] Alternatively, the flash memory cells of the VMM arrays described herein can be configured to operate in the linear region. Ids=Beta * (Vgs-Vth) * Vds; beta = u * Cox * Wt / L W=α(Vgs-Vth) That is, the weight W in the linear region is proportional to (Vgs-Vth)

[0041] The word line or control gate or bit line or source line can be used as the input of a memory cell operating in the linear region, and the bit line or source line can be used as the output of the memory cell.

[0042] For the IV linear converter, memory cells (such as reference or peripheral memory cells) or transistors operating in the linear region can be used to linearly convert input and output currents to input and output voltages.

[0043] Alternatively, the memory cells of the VMM arrays described herein can be configured to operate in the saturation region. Ids=1 / 2 * beta * (Vgs-Vth) 2 ;beta=u * Cox * Wt / L W ∝ (Vgs-Vth) 2 , that is, the weight W is (Vgs-Vth) 2 is proportional to.

[0044] The word line, control gate, or erase gate can be used as the input of a memory cell operating in the saturation region, and the bit line or source line can be used as the output of an output neuron.

[0045] Alternatively, the memory cells of the VMM arrays described herein may be used in all domains or combinations thereof (subthreshold, linear, or saturation) for each layer or layers of a neural network.

[0046] 7 is described in U.S. Patent No. 10,748,630, which is incorporated herein by reference. As described in that application, the source lines or bit lines can be used as neuron outputs (current sum outputs).

[0047] FIG. 10 shows a neuron VMM array 1000 that is particularly suited for the memory cells 210 shown in FIG. 2 and is utilized as a synapse between an input layer and the next layer. The VMM array 1000 includes a memory array 1003 of nonvolatile memory cells, a reference array 1001 of first nonvolatile reference memory cells, and a reference array 1002 of second nonvolatile reference memory cells. The reference arrays 1001 and 1002, arranged in columns of the array, function to convert current inputs flowing into terminals BLR0, BLR1, BLR2, and BLR3 into voltage inputs WL0, WL1, WL2, and WL3. In practice, the first and second nonvolatile reference memory cells are diode-connected through a multiplexer 1014 (only partially shown) with current inputs flowing into them. The reference cells are tuned (e.g., programmed) to a target reference level, which is provided by a reference mini-array matrix (not shown).

[0048] Memory array 1003 serves two purposes. First, memory array 1003 stores the weights used by VMM array 1000 in each memory cell. Second, memory array 1003 effectively multiplies the inputs (i.e., the current inputs provided to terminals BLR0, BLR1, BLR2, and BLR3, which reference arrays 1001 and 1002 convert to input voltages and provide to word lines WL0, WL1, WL2, and WL3) by the weights stored in memory array 1003, and then adds all the results (memory cell currents) to generate outputs for each bit line (BL0-BLN), which serve as inputs to the next layer or the last layer. By performing the multiplication and addition functions, memory array 1003 eliminates the need for separate multiplication and addition logic and is also power efficient. Here, voltage inputs are provided to word lines WL0, WL1, WL2, and WL3, and outputs appear on respective bit lines BL0-BLN during a read (inference) operation. The current in each of the bit lines BL0-BLN performs a function of the sum of the currents from all the non-volatile memory cells connected to that particular bit line.

[0049] Table 5 shows the operating voltages and currents for the VMM array 1000. The columns in the table indicate the voltages applied to the word line of the selected cell, the word lines of the unselected cells, the bit lines of the selected cell, the bit lines of the unselected cells, the source lines of the selected cell, and the source lines of the unselected cells. The rows indicate the read, erase, and program operations. Table 5: Operation of VMM Array 1000 in Figure 10 [Table 5]

[0050] FIG. 11 shows a neuron VMM array 1100 that is particularly suited for the memory cells 210 shown in FIG. 2 and that is utilized as part of the synapses and neurons between the input layer and the next layer. The VMM array 1100 includes a memory array 1103 of non-volatile memory cells, a reference array 1101 of first non-volatile reference memory cells, and a reference array 1102 of second non-volatile reference memory cells. The reference arrays 1101 and 1102 extend in the row direction of the VMM array 1100. The VMM array is similar to the VMM 1000, except that the word lines extend vertically in the VMM array 1100. Here, the inputs are the word lines (WLA0, WLB0, WLA1, WLB2, WLB3, WLB4, WLB5, WLB6, WLB7, WLB8, WLB9, WLB10, WLB11, WLB12, WLB13, WLB14, WLB15, WLB16, WLB17, WLB18, WLB19, WLB20, WLB21, WLB22, WLB23, WLB24, WLB25, WLB26, WLB27, WLB28, WLB29, WLB30, WLB31, WLB32, WLB33, WLB34, WLB35, WLB36, WLB37, WLB38, WLB39, WLB40, WLB41, WLB42, WLB43, WLB44, WLB45, WLB46, WLB47, WLB48, WLB49, WLB50, WLB51, WLB52, WLB53, WLB54, WLB55, WLB56, WLB57, WLB58, WLB59, WLB61, WLB62, WLB63, WLB64, WLB65 1 , WLA2, WLB2, WLA3, WLB3) and the output appears on the source lines (SL0, SL1) during a read operation. The current on each source line performs a function of the sum of all the currents from the memory cells connected to that particular source line.

[0051] Table 6 shows the operating voltages and currents for VMM array 1100. The columns in the table indicate the voltages applied to the word line of the selected cell, the word lines of the unselected cells, the bit lines of the selected cell, the bit lines of the unselected cells, the source lines of the selected cell, and the source lines of the unselected cells. The rows indicate the read, erase, and program operations. Table 6: Operation of VMM Array 1100 in Figure 11 [Table 6]

[0052] 12 shows a neuron VMM array 1200 that is particularly suited for the memory cells 310 shown in FIG. 3 and that is utilized as part of the synapses and neurons between the input layer and the next layer. VMM array 1200 includes a memory array 1203 of nonvolatile memory cells, a reference array 1201 of first nonvolatile reference memory cells, and a reference array 1202 of second nonvolatile reference memory cells. Reference arrays 1201 and 1202 function to convert current inputs flowing into terminals BLR0, BLR1, BLR2, and BLR3 into voltage inputs CG0, CG1, CG2, and CG3. In effect, the first and second nonvolatile reference memory cells are diode-connected through multiplexer 1212 (only a portion of which is shown), with the current inputs flowing through BLR0, BLR1, BLR2, and BLR3. Multiplexers 1212 each include a respective multiplexer 1205 and cascoding transistor 1204 to ensure a constant voltage on each bit line (e.g., BLR0) of the first and second non-volatile reference memory cells during a read operation, in which the reference cells are tuned to a target reference level.

[0053] Memory array 1203 serves two purposes. First, memory array 1203 stores the weights used by VMM array 1200. Second, memory array 1203 effectively multiplies the weights stored in the memory array by the inputs (current inputs provided to terminals BLR0, BLR1, BLR2, and BLR3; reference arrays 1201 and 1202 convert these current inputs to input voltages provided to control gates (CG0, CG1, CG2, and CG3)), and then adds all the results (cell currents) to generate an output that appears on BL0-BLN and serves as the input to the next layer or the last layer. Having the memory array perform the multiplication and addition functions eliminates the need for separate multiplication and addition logic and is also power efficient. Here, the inputs are provided to the control gate lines (CG0, CG1, CG2, and CG3) and the outputs appear on the bit lines (BL0-BLN) during read operations. The current in each bit line is a function of the sum of all the currents from the memory cells connected to that particular bit line.

[0054] VMM array 1200 implements one-way tuning of the non-volatile memory cells in memory array 1203. That is, each non-volatile memory cell is erased and then partially programmed until the desired charge on the floating gate is reached. If too much charge is added to the floating gate (such as if an incorrect value is stored in the cell), the cell is erased and the series of partial programming operations starts over. As shown, two rows that share the same erase gate (such as EG0 or EG1) are erased together (known as a page erase), and then each cell is partially programmed until the desired charge on the floating gate is reached.

[0055] Table 7 shows the operating voltages and currents for VMM array 1200. The columns in the table indicate the voltages applied to the word line of the selected cell, the word lines of the unselected cells, the bit line of the selected cell, the bit lines of the unselected cells, the control gate of the selected cell, the control gates of the unselected cells in the same sector as the selected cell, the control gates of the unselected cells in a different sector from the selected cell, the erase gate of the selected cell, the erase gates of the unselected cells, the source line of the selected cell, and the source lines of the unselected cells. The rows indicate read, erase, and program operations. Table 7: Operation of VMM Array 1200 in Figure 12 [Table 7]

[0056] 13 shows a neuron VMM array 1300 that is particularly suited for memory cells 310 shown in FIG. 3 and is used as part of the synapses and neurons between the input layer and the next layer. The VMM array 1300 includes a memory array 1303 of non-volatile memory cells; of the first non-volatile reference memory cell Reference Array 130 1 and, and a second reference array 1302 of non-volatile reference memory cells. EG lines EGR0, EG0, EG1, and EGR1 extend vertically, while CG lines CG0, CG1, CG2, and CG3 and SL lines WL0, WL1, WL2, and WL3 extend horizontally. VMM array 1300 is similar to VMM array 1400 except that VMM array 1300 implements bidirectional tuning, such that each individual cell can be fully erased, partially programmed, or partially erased as needed to reach a desired amount of charge on its floating gate through the use of separate EG lines. As shown, reference arrays 1301 and 1302 convert input currents at terminals BLR0, BLR1, BLR2, and BLR3 into control gate voltages CG0, CG1, CG2, and CG3 (through the action of diode-connected reference cells via multiplexer 1314), which are applied to the memory cells in the row direction. The current outputs (neurons) are in bit lines BL0-BLN, each bit line summing all the currents from the non-volatile memory cells connected to that particular bit line.

[0057] Table 8 shows the operating voltages and currents for VMM array 1300. The columns in the table indicate the voltages applied to the word line of the selected cell, the word lines of the unselected cells, the bit line of the selected cell, the bit lines of the unselected cells, the control gate of the selected cell, the control gates of the unselected cells in the same sector as the selected cell, the control gates of the unselected cells in a different sector from the selected cell, the erase gate of the selected cell, the erase gates of the unselected cells, the source line of the selected cell, and the source lines of the unselected cells. The rows indicate read, erase, and program operations. Table 8: Operation of VMM Array 1300 in Figure 13 [Table 8]

[0058] 22 shows a neuron VMM array 2200 that is particularly suited to the memory cells 210 shown in FIG. 2 and that is used as part of the synapses and neurons between the input layer and the next layer. In the VMM array 2200, inputs INPUT0..., INPUTN are bit lines BL0, ...BL N and outputs OUTPUT1, OUTPUT2, OUTPUT3, and OUTPUT4 are generated on source lines SL0, SL1, SL2, and SL3, respectively.

[0059] 23 shows a neuron VMM array 2300 that is particularly suited for memory cells 210 shown in FIG. 2 and that is utilized as part of the synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, INPUT1, INPUT2, and INPUT3 are received on source lines SL0, SL1, SL2, and SL3, respectively, and outputs OUTPUT0, ...OUTPUT N are the bit lines BL0, ..., BL N is generated.

[0060] 24 shows a neuron VMM array 2400 that is particularly suited for the memory cells 210 shown in FIG. 2 and that is utilized as part of the synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0,..., INPUT M are the word lines WL0, ..., WL M Received and output OUTPUT0, ...OUTPUT N are the bit lines BL0, ..., BL N is generated.

[0061] 25 shows a neuron VMM array 2500 that is particularly suited for the memory cells 310 shown in FIG. 3 and that is utilized as part of the synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0,..., INPUT M are the word lines WL0, ..., WL M Received and output OUTPUT0, ...OUTPUT N are the bit lines BL0, ..., BL N is generated.

[0062] 26 shows a neuron VMM array 2600 that is particularly suited for the memory cells 410 shown in FIG. 4 and that is utilized as part of the synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0,..., INPUT n are the vertical control gate lines CG0, ..., CG N and outputs OUTPUT1 and OUTPUT2 are generated on source lines SL0 and SL1.

[0063] 27 shows a neuron VMM array 2700 that is particularly suited for the memory cells 410 shown in FIG. 4 and that is utilized as part of the synapses and neurons between the input layer and the next layer. In this example, the inputs INPUT0, ..., INPUT N are the bit lines BL0, ..., BL N , 2701-(N-1) and 2701-N, which are coupled to the source lines SL0 and SL1. Exemplary outputs OUTPUT1 and OUTPUT2 are generated on the source lines SL0 and SL1.

[0064] 28 shows a neuron VMM array 2800 that is particularly suited for memory cells 310 shown in FIG. 3, memory cells 510 shown in FIG. 5, and memory cells 710 shown in FIG. 7, and is utilized as part of the synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUT M are the word lines WL0, ..., WL M Received and output OUTPUT0, ..., OUTPUT N are the bit lines BL0, ..., BL N is generated.

[0065] 29 shows a neuron VMM array 2900 that is particularly suitable for memory cells 310 shown in FIG. 3, memory cells 510 shown in FIG. 5, and memory cells 710 shown in FIG. 7, and is used as part of the synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUTM are the control gate lines CG0, ..., CG M Received at OUTPUT0, ..., OUTPUT N are the vertical source lines SL0, ..., SL N and each source line SL i is coupled to the source lines of all memory cells in column i.

[0066] 30 shows a neuron VMM array 3000 that is particularly suitable for memory cells 310 shown in FIG. 3, memory cells 510 shown in FIG. 5, and memory cells 710 shown in FIG. 7, and is used as part of the synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUT M are the control gate lines CG0, ..., CG M Received at OUTPUT0, ..., OUTPUT N are the vertical bit lines BL0, ..., BL N and each bit line BL i is coupled to the bit lines of all memory cells in column i. <Long and short-term memory>

[0067] Prior art includes a concept known as long short-term memory (LSTM). LSTM units are often used within neural networks. LSTMs allow neural networks to store information for any given period of time and use that information in subsequent operations. A traditional LSTM unit includes a cell, an input gate, an output gate, and a forget gate. The three gates regulate the flow of information into and out of the cell and the duration for which information is stored within the LSTM. VMMs are particularly useful in LSTM units.

[0068] Figure 14 shows an example LSTM 1400. LSTM 1400 in this example includes cells 1401, 1402, 1403, and 1404. Cell 1401 receives input vector x0 and generates output vector h0 and cell state vector c0. Cell 1402 receives input vector x1, output vector (hidden state) h0 from cell 1401, and cell state c0 from cell 1401, and generates output vector h1 and cell state vector c1. Cell 1403 receives input vector x2, output vector (hidden state) h1 from cell 1402, and cell state c1 from cell 1402, and generates output vector h2 and cell state vector c2. Cell 1404 receives input vector x3, output vector (hidden state) h2 from cell 1403, and cell state c2 from cell 1403, and generates output vector h3. Additional cells can be used; an LSTM with four cells is just an example.

[0069] Figure 15 shows an example implementation of an LSTM cell 1500 that can be used for cells 1401, 1402, 1403, and 1404 in Figure 14. LSTM cell 1500 receives an input vector x(t), a cell state vector c(t-1) from a previous cell, and an output vector h(t-1) from a previous cell, and produces a cell state vector c(t) and an output vector h(t).

[0070] LSTM cell 1500 includes sigmoid function devices 1501, 1502, and 1503, each of which applies a number between 0 and 1 to control the degree to which each component of the input vector contributes to the output vector. LSTM cell 1500 also includes tanh devices 1504 and 1505 for applying a hyperbolic tangent function to the input vector, multiplier devices 1506, 1507, and 1508 for multiplying two vectors, and adder device 1509 for adding the two vectors. The output vector h(t) can be provided to the next LSTM cell in the system or can be accessed for other purposes.

[0071] FIG. 16 shows LSTM cell 1600, an example of one implementation of LSTM cell 1500. For the convenience of the reader, the same numbering scheme from LSTM cell 1500 is used in LSTM cell 1600. Sigmoid function devices 1501, 1502, and 1503 and tanh device 1504 each include multiple VMM arrays 1601 and activation function blocks 1602. VMM arrays, therefore, prove particularly useful in LSTM cells used in certain neural network systems. Multiplier devices 1506, 1507, and 1508 and adder device 1509 are implemented in digital or analog fashion. Activation function block 1602 can be implemented in digital or analog fashion.

[0072] An alternative example of LSTM cell 1600 (and another example of an implementation of LSTM cell 1500) is shown in Figure 17. In Figure 17, sigmoid function devices 1501, 1502, and 1503 and tanh device 1504 share the same physical hardware (VMM array 1701 and activation function block 1702) in a time-multiplexed manner. LSTM cell 1700 also includes a multiplier device 1703 for multiplying two vectors, an adder device 1708 for adding two vectors, a tanh device 1505 (which includes activation function block 1702), a register 1707 for storing the value i(t) as it is output from sigmoid function block 1702, and a register 1708 for storing the value f(t). * a register 1704 for storing c(t-1) as its value is output from the multiplier device 1703 via multiplexer 1710; * a register 1705 for storing u(t) as its value is output from the multiplier device 1703 via a multiplexer 1710; * It includes a register 1706 for storing {tilde over (c)}(t) as its value is output from the multiplier device 1703 via a multiplexer 1710, and a multiplexer 1709.

[0073] While LSTM cell 1600 includes multiple sets of VMM arrays 1601 and respective activation function blocks 1602, LSTM cell 1700 includes only one set of VMM arrays 1701 and activation function blocks 1702, which are used to represent multiple layers in embodiments of LSTM cell 1700. LSTM cell 1700 requires one-quarter the space for the VMMs and activation function blocks compared to LSTM cell 1600, and therefore LSTM cell 1700 requires less space than LSTM 1600.

[0074] It can be further appreciated that an LSTM unit typically includes multiple VMM arrays, each of which requires functionality provided by specific circuit blocks outside the VMM array, such as adder and activation function blocks and high-voltage generation blocks. Providing a separate circuit block for each VMM array would require a significant amount of space within a semiconductor device and would be somewhat inefficient. Accordingly, the embodiments described below reduce the circuitry required outside the VMM array itself. <Gated Recurrent Unit>

[0075] Analog VMM implementations can be used for gated recurrent unit (GRU) systems. GRUs are the gating mechanism within recurrent neural networks. GRUs are similar to LSTMs, except that GRU cells generally contain fewer components than LSTM cells.

[0076] 18 shows an exemplary GRU 1800. GRU 1800 in this example includes cells 1801, 1802, 1803, and 1804. Cell 1801 receives input vector x0 and generates output vector h0. Cell 1802 receives input vector x1 and output vector h0 from cell 1801 and generates output vector h1. Cell 1803 receives input vector x2 and output vector (hidden state) h1 from cell 1802 and generates output vector h2. Cell 1804 receives input vector x3 and output vector (hidden state) h2 from cell 1803 and generates output vector h3. Additional cells can be used; a GRU with four cells is merely an example.

[0077] FIG. 19 shows an example implementation of a GRU cell 1900 that may be used for cells 1801, 1802, 1803, and 1804 of FIG. 18. GRU cell 1900 receives an input vector x(t) and an output vector h(t-1) from a preceding GRU cell and generates an output vector h(t). GRU cell 1900 includes sigmoid function devices 1901 and 1902, each of which applies a number between 0 and 1 to components from the output vector h(t-1) and the input vector x(t). GRU cell 1900 also includes a tanh device 1903 for applying a hyperbolic tangent function to the input vector, multiple multiplier devices 1904, 1905, and 1906 for multiplying two vectors, an adder device 1907 for adding the two vectors, and a complement device 1908 for subtracting the input from 1 to generate the output.

[0078] FIG. 20 shows GRU cell 2000, which is an example of one implementation of GRU cell 1900. For the convenience of the reader, the same numbering scheme as GRU cell 1900 is used in GRU cell 2000. As can be seen from FIG. 20, sigmoid function devices 1901 and 1902 and tanh device 1903 each include multiple VMM arrays 2001 and activation function blocks 2002. Therefore, it can be seen that VMM arrays are particularly used in GRU cells used in certain neural network systems. Multiplier devices 1904, 1905, and 1906, adder device 1907, and complementary device 1908 are implemented in a digital or analog manner. Activation function block 2002 can be implemented in a digital or analog manner.

[0079] An alternative example of GRU cell 2000 (and another example of one implementation of GRU cell 1900) is shown in FIG. 21. In FIG. 21, GRU cell 2100 utilizes VMM array 2101 and activation function block 2102, which, when configured as a sigmoid function, applies a number between 0 and 1 to control the degree to which each component of the input vector contributes to the output vector. In FIG. 21, sigmoid function devices 1901 and 1902 and tanh device 1903 share the same physical hardware (VMM array 2101 and activation function block 2102) in a time-multiplexed manner. GRU cell 2100 also includes multiplier device 2103 for multiplying two vectors, adder device 2105 for adding two vectors, complement device 2109 for subtracting the input from 1 to generate the output, multiplexer 2104, and a value h(t-1). * a register 2106 for holding r(t) as its value is output from the multiplier device 2103 via multiplexer 2104; and a register 2106 for holding the value h(t-1) * a register 2107 for holding z(t) as its value is output from the multiplier device 2103 via multiplexer 2104; and a register 2108 for holding the value ĥ(t) *and a register 2108 for holding (1-z((t)) as its value is output from the multiplier device 2103 via multiplexer 2104.

[0080] While GRU cell 2000 includes multiple sets of VMM array 2001 and activation function block 2002, GRU cell 2100 includes only one set of VMM array 2101 and activation function block 2102, which are used to represent multiple layers in embodiments of GRU cell 2100. GRU cell 2100 requires one-third the space for the VMM and activation function block compared to GRU cell 2000, so GRU cell 2100 requires less space than GRU cell 2000.

[0081] It can be further appreciated that a GRU system typically includes multiple VMM arrays, each of which requires functionality provided by specific circuit blocks outside the VMM array, such as adder and activation function blocks and high-voltage generation blocks. Providing separate circuit blocks for each VMM array would require a significant amount of space within a semiconductor device and would be somewhat inefficient. Accordingly, the embodiments described below reduce the circuitry required outside the VMM array itself.

[0082] The input to the VMM array can be an analog level, a binary level, a pulse, a time modulated pulse, or a digital bit (in which case a DAC is required to convert the digital bit to the appropriate input analog level), and the output can be an analog level, a binary level, a timing pulse, a pulse, or a digital bit (in which case an output ADC is required to convert the output analog level to a digital bit).

[0083] In general, for each memory cell in the VMM array, each weight W can be implemented by a single memory cell, a differential cell, or two blended memory cells (the average of two cells). In the case of a differential cell, two memory cells are required to implement the weight W as a differential weight (W=W+-W-). In the case of two blended memory cells, two memory cells are required to implement the weight W as the average of two cells.

[0084] FIG. 31 illustrates a VMM system 3100. In some embodiments, the weights W stored in the VMM array are stored as a differential pair, W+ (positive weight) and W− (negative weight), where W=(W+)−(W−). In VMM system 3100, half of the bit lines are designated as W+ lines, i.e., bit lines connecting to memory cells that store a positive weight W+, and the other half of the bit lines are designated as W− lines, i.e., bit lines connecting to memory cells that implement a negative weight W−. W− lines are interspersed alternately among the W+ lines. Subtraction operations are performed by summing circuits, such as summing circuits 3101 and 3102, that receive current from the W+ and W− lines. The outputs of the W+ and W− lines are combined together to effectively provide W=W+−W− for each pair of (W+, W−) cells on every pair of (W+, W−) lines. Although described above with respect to W- lines interspersed alternately among W+ lines, in other embodiments the W+ and W- lines may be arbitrarily positioned anywhere within the array.

[0085] 32 shows another embodiment. In a VMM system 3210, the positive weights W+ are implemented in a first array 3211 and the negative weights W− are implemented in a second array 3212 that is separate from the first array, and the resulting weights are suitably combined together by a summing circuit 3213.

[0086] FIG. 33 illustrates a VMM system 3300. The weights W stored in the VMM array are stored as a differential pair, W+ (positive weight) and W− (negative weight), where W=(W+)−(W−). VMM system 3300 includes array 3301 and array 3302. Half of the bit lines in each of arrays 3301 and 3302 are designated as W+ lines, i.e., bit lines connecting to memory cells that store a positive weight W+, and the other half of the bit lines in each of arrays 3301 and 3302 are designated as W− lines, i.e., bit lines connecting to memory cells that implement a negative weight W−. W− lines are interspersed alternately among the W+ lines. Subtraction operations are performed by adder circuits, such as adder circuits 3303, 3304, 3305, and 3306, that receive current from the W+ and W− lines. The outputs on the W+ and W- lines from each array 3301, 3302 are combined together, respectively, to effectively give W = W+ - W- for each pair of (W+, W-) cells on every pair of (W+, W-) lines. Additionally, the W values ​​from each array 3301 and 3302 may be further combined via adder circuits 3307 and 3308, meaning that each W value is the result of subtracting the W value from array 3302 from the W value from array 3301, and the final result from adder circuits 3307 and 3308 is one of two difference values.

[0087] Each non-volatile memory cell used in an analog neural memory system must be erased and programmed to hold a very specific and precise amount of charge, i.e., number of electrons, in its floating gate. For example, each floating gate must hold one of N different values, where N is the number of different weights that can be represented by each cell. Examples of N include 16, 32, 64, 128, and 256.

[0088] Similarly, the read operation must be able to accurately distinguish between the N different levels.

[0089] A need exists for a flexible memory system that can operate as an analog neural memory system in one mode and as a digital neural memory system in another mode. Summary of the Invention

[0090] Numerous embodiments of hybrid memory systems are disclosed. The hybrid memory can store weight data in an array in either analog form, when used in an analog neural memory system, or in digital form, when used in a digital neural memory system. The input and output circuits can support both forms of weight data.

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[0129] [Brief explanation of the drawings]

[0130] [Figure 1] FIG. 1 illustrates an artificial neural network. [Figure 2]1 shows a prior art split-gate flash memory cell. [Figure 3] 1 illustrates another prior art split-gate flash memory cell. [Figure 4] 1 illustrates another prior art split-gate flash memory cell. [Figure 5] 1 illustrates another prior art split-gate flash memory cell. [Figure 6] FIG. 1 illustrates various levels of an exemplary artificial neural network that utilizes one or more non-volatile memory arrays. [Figure 7] FIG. 1 is a block diagram illustrating a vector matrix multiplication system. [Figure 8] FIG. 1 is a block diagram illustrating an exemplary artificial neural network utilizing one or more vector-matrix multiplication systems. [Figure 9] 1 illustrates another embodiment of a vector matrix multiplication system. [Figure 10] 1 illustrates another embodiment of a vector matrix multiplication system. [Figure 11] 1 illustrates another embodiment of a vector matrix multiplication system. [Figure 12] 1 illustrates another embodiment of a vector matrix multiplication system. [Figure 13] 1 illustrates another embodiment of a vector matrix multiplication system. [Figure 14] 1 shows a prior art long-term memory system. [Figure 15] An exemplary cell for use in a long-term memory system is shown. [Figure 16] 16 illustrates an embodiment of the exemplary cell of FIG. 15. [Figure 17] 16 illustrates another embodiment of the exemplary cell of FIG. 15. [Figure 18] 1 shows a prior art gated recurrent unit system. [Figure 19] 1 shows an exemplary cell for use in a gated recurrent unit system. [Figure 20]20 illustrates one embodiment of the exemplary cell of FIG. 19. [Figure 21] 20 illustrates another embodiment of the exemplary cell of FIG. 19. [Figure 22] 1 illustrates another embodiment of a vector matrix multiplication system. [Figure 23] 1 illustrates another embodiment of a vector matrix multiplication system. [Figure 24] 1 illustrates another embodiment of a vector matrix multiplication system. [Figure 25] 1 illustrates another embodiment of a vector matrix multiplication system. [Figure 26] 1 illustrates another embodiment of a vector matrix multiplication system. [Figure 27] 1 illustrates another embodiment of a vector matrix multiplication system. [Figure 28] 1 illustrates another embodiment of a vector matrix multiplication system. [Figure 29] 1 illustrates another embodiment of a vector matrix multiplication system. [Figure 30] 1 illustrates another embodiment of a vector matrix multiplication system. [Figure 31] 1 illustrates another embodiment of a vector matrix multiplication system. [Figure 32] 1 illustrates another embodiment of a vector matrix multiplication system. [Figure 33] 1 illustrates another embodiment of a vector matrix multiplication system. [Figure 34] 1 illustrates another embodiment of a vector matrix multiplication system. [Figure 35A] 1 illustrates a hybrid memory system. [Figure 35B] 1 illustrates another hybrid memory system. [Figure 36] 1 illustrates a hybrid memory operation method. [Figure 37] 1 illustrates a configurable macro circuit for use with a hybrid memory system. [Figure 38]A system comprising a plurality of hybrid array tiles is shown. [Figure 39] A reconfigurable current-voltage and analog-digital converter circuit is shown.

Best Mode for Carrying Out the Invention

[0131] The artificial neural network of the present invention utilizes a combination of CMOS technology and non-volatile memory arrays.

[0132] <Overview of the VMM System> FIG. 34 shows a block diagram of a VMM system 3400. The VMM system 3400 includes a VMM array 3401, a row decoder 3402, a high-voltage decoder 3403, a column decoder 3404, a bit-line driver 3405, an input circuit 3406, an output circuit 3407, control logic 3408, and a bias generator 3409. The VMM system 3400 further includes a high-voltage generation block 3410 that includes a charge pump 3411, a charge pump regulator 3412, and a high-voltage analog precision level generator 3413. The VMM system 3400 further includes a (program / erase, or weight adjustment) algorithm controller 3414, an analog circuit 3415, a control engine 3416 (which may include special functions such as arithmetic functions, startup functions, embedded microcontroller logic, etc., without limitation), and test control logic 3417. The systems and methods described below may be implemented in the VMM system 3400.

[0133] The input circuit 3406 may include circuits such as a DAC (digital to analog converter), a DPC (digital to pulses converter), an AAC (analog to analog converter, such as a current-to-voltage converter or a logarithmic converter), a PAC (pulse to analog level converter), or any other type of converter. The input circuit 3406 may implement normalization, linear or nonlinear up / downscaling functions, or arithmetic functions. The input circuit 3406 may implement a temperature compensation function for the input level. The input circuit 3406 may implement an activation function such as ReLU or sigmoid. The output circuitry 3407 may include circuits such as an ADC (analog to digital converter, for converting neuron analog output to digital bits), an AAC (analog to analog converter, such as a current to voltage converter or a logarithmic converter), an APC (analog to pulse converter, analog to time modulated pulse converter), or any other type of converter.

[0134] The output circuit 3407 may implement activation functions such as a rectified linear activation function (ReLU) or a sigmoid. The output circuit 3407 may implement statistical normalization, regularization, up / down scaling / gain functions, statistical rounding, or arithmetic functions (e.g., addition, subtraction, division, multiplication, shift, logarithm) of the neuron outputs. The output circuit 3407 may implement temperature compensation functions for the neuron outputs or array outputs (such as bit line outputs) to keep the power consumption of the array approximately constant or to increase the accuracy of the array (neuron) outputs, such as by keeping the IV slope approximately the same.

[0135] Figures 35A and 35B show hybrid memory systems 3500 and 3550, respectively, each of which can operate as a multi-level digital neural memory system for obtaining digital weight data from the array in a first mode, or as a multi-level analog neural memory system for obtaining analog weight data from the array in a second mode.

[0136] In FIG. 35A, hybrid memory system 3500 comprises hybrid array 3501 including an array of non-volatile memory cells arranged in rows and columns, configurable input circuitry 3502, and configurable output circuitry 3503.

[0137] Configurable input circuit 3502 provides input to hybrid array 3501 and includes a row register and digital-to-analog (DAC) block 3505 for use in the first mode and a row decoder block 3504 for use in the second mode.

[0138] Configurable output circuit 3503 provides an output in response to signals received from hybrid array 3501 and includes a current-to-voltage converter (ITV) and analog-to-digital converter (ADC) block 3506 for use in a first mode and a multi-state sense amplifier (MS SA) block 3507 for use in a second mode. ITV+ADC block 3506 includes multiple ITV circuits and multiple ADC circuits. MS SA block 3507 includes multiple MS SA circuits.

[0139] In a first mode, the hybrid array 3501 operates as a non-volatile memory storage device for storing or retrieving weight data in a multi-bit digital format (digital multi-level format, meaning that one physical memory cell can store one of multiple discrete levels, such as 4, 8, 16, or 32 levels, and the output of one cell is equivalent to 2, 3, 4, or 5 digital bits, respectively). For example, if each cell can store eight different values ​​(3-bit or 3b cells), the digital weight data can vary from 000 to 111. As another example, if each cell can store two different values, as in a binary memory cell (1-bit cell), the digital weight data can vary from 0 to 1.

[0140] In the first mode, the row register and digital-to-analog (DAC) block 3505 generates analog input signals for reading one or more rows in the hybrid array 3501 in response to a received digital signal. The digital MLC (multilevel cell) readout mode reads only one row at a time, while the neural readout mode reads two or more rows at a time, typically tens or hundreds of rows at a time. The ITV+ADC block 3506 receives analog (current) outputs from several or all columns of the hybrid array 3501 and generates a digital output representing a neural readout of the entire hybrid array 3501 (reading multiple rows and columns at once). One ITV circuit is used to read one bit line at a time to output an analog value, which can include multiple cells on the same bit line. The ITV is typically used to convert the array output current to a voltage. One ADC circuit is typically used to read one bit line at a time to output a digital bit, which can include multiple cells on the same bit line. An ADC circuit is typically used to convert a voltage into digital output bits. In one embodiment, an ADC circuit can be used to directly convert the array current into digital output bits. For example, in the case of a SAR ADC that uses a voltage reference, a current reference can be used instead for operation.

[0141] In the second mode, the hybrid array 3501 operates as a VMM in an analog neural memory, storing weight data in an analog multilevel format, meaning that each cell stores analog multilevels with continuous analog values ​​between levels. For example, for an 8-level digital multilevel cell, the cells have different levels: 1, 2, 3, 4, ..., 8. For an 8-level analog multilevel cell, the cells have continuous values ​​between levels, e.g., between 1 and 2, with analog values ​​of 1.001, 1.002, ..., 1.01, ..., 1.1, 1.2, ..., 1.999, 2.0. Analog multilevels are required for vector-matrix multiplier (VMM) applications for neural array memory applications.

[0142] In the second mode, row decoder block 3504 is used to select (enable) one row in hybrid array 3501 for a read, program, or erase operation. During a read or program operation, MS SA block 3507 is used to read or verify one or more cells in one or more columns in hybrid array 3501. One MS SA circuit is used to read one cell at a time.

[0143] Thus, hybrid memory system 3500 can operate as a multi-level digital neural memory system for obtaining digital weight data from the array in a first mode, or as a multi-level analog neural memory system for obtaining analog weight data from the array in a second mode.

[0144] In FIG. 35B, hybrid memory system 3550 comprises hybrid array 3551 including an array of non-volatile memory cells arranged in rows and columns, configurable input circuitry 3552, and configurable output circuitry 3553.

[0145] Configurable input circuit 3552 provides input to hybrid array 3551 and includes a row decoder, row registers, and digital-to-analog block 3554. That is, blocks 3504 and 3505 of FIG. 35A are combined into a single block 3554. Configurable output circuit 3552 5 35A provides an output in response to signals received from hybrid array 3551 and comprises a current-to-voltage converter, an analog-to-digital converter, and a sense amplifier block 3555. That is, blocks 3506 and 3507 from FIG. 35A are combined into a single block 3555.

[0146] In a first mode, hybrid array 3551 operates as a non-volatile memory storage device for storing weight data in multi-level digital form. Block 3554 generates analog input signals for reading one or more rows in hybrid array 3551 in response to received digital signals. Block 3555 receives analog (current) outputs from some or all of the columns of hybrid array 3551 to generate digital outputs representing the neural readings of at least a majority of the cells in hybrid array 3551.

[0147] In the second mode, hybrid array 3551 operates as a VMM in an analog neural memory to store weight data in a multi-level analog format. Block 3554 is used to select a row in hybrid array 3501 for a read, program, or erase operation by operating as a row decoder. Block 3555 is used to read or verify one or more cells in one or more columns in hybrid array 3551 by operating as a multi-state sense amplifier. Each MS SA circuit operates on one cell at a time (i.e., one cell per bit line is enabled).

[0148] In this manner, hybrid memory system 3550 can operate as a digital neural memory system for obtaining digital weight data from hybrid array 3551 in a first mode, or as an analog neural memory system for obtaining analog weight data from hybrid array 3551 in a second mode.

[0149] FIG. 36 illustrates a hybrid memory operating method 3600 that can be performed by the hybrid memory system 3500 of FIG. 35A or the hybrid memory system 3550 of FIG. 35B.

[0150] In step 3601, the system determines whether a VMM analog neural memory operation should be performed. If yes, the system proceeds to step 3602. If no, the system proceeds to step 3609.

[0151] In step 3602, the VMM analog neural operation begins. In step 3603, an input is provided by a digital-to-analog converter and a resulting output is provided by an analog-to-digital converter. The DAC may be a 1-bit DAC.

[0152] In step 3604, multiple rows are enabled.

[0153] In step 3605, multiple columns are enabled.

[0154] In step 3606, the output from the hybrid memory array is converted into a different format, such as digital output bits (analog weight data).

[0155] In step 3607, partial sum storage is performed.

[0156] In step 3608, summing, activation, and / or pooling actions are performed to generate a neural output.

[0157] In step 3609, a digital non-volatile memory operation is performed.

[0158] In step 3610, the input is provided by a row decoder and the output is provided by a multi-state sense amplifier.

[0159] In step 3611, the row is enabled.

[0160] In step 3612, the column is enabled.

[0161] In step 3613, the output from the hybrid memory array is converted into a different format, such as digital output bits (digital weight data).

[0162] In step 3614, the output from step 3613 is stored in a buffer memory, such as an SRAM memory.

[0163] In step 3615, the system determines whether all target rows have been operated on. If yes, the system proceeds to step 3616. If no, the system returns to step 3611 and performs the steps described above.

[0164] In step 3616, summing, activation, and / or pooling actions are performed to generate an output.

[0165] 37 shows a configurable memory system 3700 comprising a hybrid memory system 3500 or 3550 and a configurable macro circuit 3701. The configurable macro circuit 3701 can be configured to operate with a first mode or a second mode of the hybrid memory system 3500 or 3550. This configuration can occur during power-up or in real-time during operation. The configurable macro circuit 3701 optionally comprises an SRAM 3702, a SIMD (single instruction, multiple data) module 3703, an interconnect matrix 3704 (for connecting the configurable macro circuit 3701 to the hybrid memory system 3500 or 3550), and an eMCU (control unit) 3705.

[0166] FIG. 38 shows a system 3800 comprising a plurality of hybrid array tiles 3801 (each of which may comprise a hybrid memory system 3500 or 3550 or 3700), an interconnect 3802, a system level SIMD module 3803, an eMCU sys (system level controller) 3804, a system level memory 3805, and a system level interface IFTC 3806 (which may be a high speed interface such as OctoSPI, PCIe, Internet, etc.).

[0167] Figure 39 shows a reconfigurable ITV+ADC circuit 3900. The reconfigurable ITV+ADC circuit 3900 includes an adjustable current source 3901, a current source 3902 (which is a selected memory cell), a comparator 3903, and logic 3904. The reconfigurable ITV+ADC circuit 3900 can be implemented as a current SAR ADC using a current reference provided by current reference block 3901. For example, for an 8-bit current SAR ADC, IDAC 3901 provides 15 levels for 8 bits. The circuit is reconfigured for digital weight read or analog weight neural read by adjusting the IDAC reference value (e.g., for neural read, the IDAC reference value is larger depending on the number of rows enabled and what the maximum bitline current is for digital weight or analog weight neural read).

[0168] It should be noted that, as used herein, both the terms "over" and "on" are inclusive of "directly" (with no intermediate material, element, or gap disposed therebetween) and "indirectly" (with an intermediate material, element, or gap disposed therebetween). Similarly, the term "adjacent" includes "directly adjacent" (with no intermediate material, element, or gap disposed therebetween) and "indirectly adjacent" (with an intermediate material, element, or gap disposed therebetween); "attached" includes "directly attached" (with no intermediate material, element, or gap disposed therebetween) and "indirectly attached" (with an intermediate material, element, or gap disposed therebetween); and "electrically coupled" includes "directly electrically coupled" (with no intermediate material or element disposed therebetween that electrically connects the elements together) and "indirectly electrically coupled" (with an intermediate material or element disposed therebetween that electrically connects the elements together). For example, forming an element "over a substrate" can include forming the element directly on the substrate with no intermediate materials / elements therebetween, and forming the element indirectly on the substrate with one or more intermediate materials / elements therebetween.

Claims

1. 1. A system comprising: an array of non-volatile memory cells arranged in a plurality of rows and a plurality of columns; a configurable input circuit coupled to the array for providing an input to the array, the configurable input circuit comprising a row register and digital-to-analog converter block for use in a first mode and a row decoder block for use in a second mode; a configurable output circuit coupled to the array for providing an output in response to the input received from the array; In the first mode, the configurable output circuitry provides digital data from the array; In the second mode, the configurable output circuitry provides analog data from the array.

2. 2. The system of claim 1, wherein the digital data comprises digital weight data and the analog data comprises analog weight data.

3. the configurable output circuit comprises: a current-to-voltage converter and analog-to-digital converter block for use in said first mode; a multi-state sense amplifier block for use in said second mode.

4. 1. A system comprising: an array of non-volatile memory cells arranged in a plurality of rows and a plurality of columns; a configurable input circuit coupled to the array for providing an input to the array; a configurable output circuit coupled to the array to provide an output in response to the input received from the array, the configurable output circuit comprising a current-to-voltage converter and analog-to-digital converter block for use in a first mode and a multi-state sense amplifier block for use in a second mode; In the first mode, the configurable output circuitry provides digital data from the array; In the second mode, the configurable output circuitry provides analog data from the array.

5. The system of claim 1 , wherein the non-volatile memory cells are stacked gate flash memory cells.

6. The system of claim 1 , wherein the non-volatile memory cells are split-gate flash memory cells.

7. The system of claim 1 , wherein the system is an analog neural memory system.

8. A system comprising: an array of non-volatile memory cells arranged in a plurality of rows and a plurality of columns; an input circuit coupled to the array for providing an input to the array; an output circuit coupled to the array for providing an output received from the array; the input circuitry provides a digital input to the array in a first mode or an analog input to the array in a second mode; The input circuitry comprises a row register and digital-to-analog converter block for use in the first mode, and a row decoder block for use in the second mode.

9. The output circuit a current-to-voltage converter and analog-to-digital converter block for use in said first mode; a multi-state sense amplifier block for use in the second mode.

10. 1. A system comprising: an array of non-volatile memory cells arranged in a plurality of rows and a plurality of columns; an input circuit coupled to the array for providing an input to the array; an output circuit coupled to the array for providing an output received from the array; the input circuitry provides a digital input to the array in a first mode or an analog input to the array in a second mode; The output circuit comprises a current-to-voltage converter and an analog-to-digital converter block for use in the first mode, and a multi-state sense amplifier block for use in the second mode.

11. The system of claim 10 , wherein the non-volatile memory cells are stacked gate flash memory cells.

12. The system of claim 10 , wherein the non-volatile memory cells are split-gate flash memory cells.

13. The system of claim 10 , wherein the system is an analog neural memory system.

14. 1. A system comprising: an array of non-volatile memory cells arranged in a plurality of rows and a plurality of columns; an input circuit coupled to the array for providing input to the array, the input circuit comprising a row register and digital-to-analog converter block for use in a first mode and a row decoder block for use in a second mode; an output circuit coupled to the array for providing an output received from the array; The system wherein the output circuitry provides a digital bit output from the array in the first mode or an analog output from the array in the second mode.

15. 1. A system comprising: an array of non-volatile memory cells arranged in a plurality of rows and a plurality of columns; an input circuit coupled to the array for providing an input to the array; an output circuit coupled to the array for providing an output received from the array; a first output circuit for providing a digital bit output from the array in a first mode or an analog output from the array in a second mode, the output circuit comprising a current-to-voltage converter and an analog-to-digital converter block for use in the first mode and a multi-state sense amplifier block for use in the second mode;

16. 1. A system comprising: an array of non-volatile memory cells arranged in a plurality of rows and a plurality of columns; an input circuit coupled to the array for providing an input to the array; an output circuit coupled to the array for providing an output received from the array; a first output circuit for providing a digital bit output from the array in a first mode or an analog output from the array in a second mode, the output circuit comprising a current-to-voltage converter and an analog-to-digital converter block for use in the first mode and a multi-state sense amplifier block for use in the second mode;

17. 15. The system of claim 14, wherein the non-volatile memory cells are stacked gate flash memory cells.

18. 15. The system of claim 14, wherein the non-volatile memory cells are split-gate flash memory cells.

19. 15. The system of claim 14, wherein the system is an analog neural memory system.

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