Multi-instance block modeling for circuit component placement in integrated circuits

Abstract

Aspects of the present disclosure provide for eliminating or reducing block uniqueness in a chip-level graph of a computer chip, reducing the size of the graph while still encoding block-specific information. For each group of blocks in the graph generated from a multiple instantiation block (MIB), a block in the group is selected as a base block. The physical location of the base block is encoded in the reduced graph, and the physical locations of the remaining blocks are encoded as linear transformations of the physical locations of the base block across the face of the chip. Each group of blocks instantiated from the same MIB is represented as a single instance. The reduced graph can be provided to a device configured to perform a circuit component placement process to identify placement of circuit components for blocks in the chip according to one or more objectives.

Description

[Technical Field]

[0001] cross reference This application is a continuation of U.S. Patent Application No. 17 / 973,078, filed October 25, 2022, the disclosure of which is incorporated herein by reference. [Background technology]

[0002] background Electronic design automation (EDA) technology relates to the design of integrated circuits ("ICs" or "chips"). One part of EDA is chip floorplanning, which determines the physical locations of circuit components on a substrate for a chip. The physical locations of circuit components in an electronic design are often based on optimizing the physical characteristics desired for the IC on which the components will be implemented. The desired physical characteristics, such as the wire length between components or the density of components per square unit on the chip surface, correlate with improved chip performance and reduced power consumption. A placement engine is a device or software for planning the physical locations of circuit components and their respective interconnections according to these and other desired physical characteristics.

[0003] Because there can be billions of circuit components and potential interconnections on a modern chip, modern placement engines struggle to identify optimal placements of circuit components. Some placement engines are implemented using a divide-and-conquer approach, approaching placement modeling by representing the chip as a collection of independent functional units or blocks.

[0004] Modern circuit component placement systems typically place circuit components of blocks without necessarily considering how the represented blocks are instantiated and connected to each other. When a placement engine is configured to encode information about a block's instantiation or its interconnected neighbors, each block is uniquely organized so that separate instances of blocks are represented as separate nodes in a graph representing the chip floorplan. This uniqueization results in an increase in the number of nodes in the chip-level graph, making placement optimization computationally difficult at the scale required by modern chip design methodologies. Summary of the Invention [Means for solving the problem]

[0005] overview Aspects of the present disclosure provide for eliminating or reducing block uniqueness in a chip-level graph of a computer chip by reducing the size of the graph while still encoding block-specific information. For each group of blocks in a graph generated from a common template block, such as a multiply-instantiated block (MIB), a block is selected as a base block. The physical location of the base block is encoded in the reduced graph, and the physical locations of the remaining blocks are encoded as linear transformations of the base block's physical location across the face of the chip. Each group of blocks instantiated from the same MIB is represented as a single instance, and instance-specific pin location information is encoded as pin offsets in an added subgraph. The instance-specific information may also include the orientation of the block or its pins, for example, whether the block is rotated or flipped. The instance-specific information can also include the physical location of pins on the block and the interconnections between pins on the block and other circuit components. A system configured according to aspects of the present disclosure can generate a reduced graph to further encode instance-specific information, such as pin connections, as a subgraph as part of the chip-level graph. The reduced graph can be provided to a device configured to perform a circuit component placement process to identify physical locations of circuit components relative to blocks within a chip according to one or more objectives, such as reducing wire lengths for interconnecting the circuit components.

[0006] Because the reduced graph is represented using less data than the original graph, the computational resources required to process the graph and identify the physical locations of components within each block of the chip can be reduced. Adding subgraphs to encode instance-specific information (also called "block-specific") for non-unique blocks can reduce the overall size of the chip-level graph compared to a graph that represents each block as a unique instance. The physical locations of circuit components within each block can be identified as part of a circuit component placement process. The circuit component placement process can be performed to improve chip performance according to one or more desired objectives, such as reducing interconnect wirelengths on the chip.

[0007] One aspect of the present disclosure provides a method including: one or more processors receiving a first data structure including data representing a physical location of each block of a group of blocks in an integrated circuit (IC), the group of blocks including a first block and one or more second blocks, each block including one or more respective circuit components; the one or more processors generating a second data structure, the second data structure including data representing the physical locations of the one or more second blocks relative to the first block; and the one or more processors at least partially causing execution of one or more iterations of a circuit component placement process on the second data structure, the circuit component placement process including generating data representing the physical locations of circuit components of the blocks represented by the second data structure according to one or more purposes.

[0008] Other implementations of this aspect include corresponding computer systems, apparatus, and non-transitory computer-readable storage media recorded on one or more memory devices, each configured to perform the operations of the method.

[0009] The foregoing and other implementations can each optionally include one or more of the following features, alone or in combination: At least one implementation includes all of the following features in combination.

[0010] Generating the second data structure includes generating, for each circuit component in the second block, data representing the physical location of the circuit component and one or more offset values ​​relative to the physical location of the respective circuit component in the first block.

[0011] The physical location of each block is represented as a respective location on a floorplan of the integrated circuit, and generating the second data structure includes selecting a first block from the blocks in the group of blocks, and generating, for each second block, data representing the physical location of the second block, the data including a linear transformation of each of the physical locations of the first blocks along the floorplan of the integrated circuit.

[0012] The method further includes generating a second data structure, where generating the second data structure includes generating, as part of the second data structure, data representing block-specific interconnections of one or more second blocks, where the block-specific interconnections represent unique connections between the second blocks and another circuit component.

[0013] The method further includes receiving one or more offset values, the one or more offset values ​​being based at least in part on physical dimensions of the blocks in the group, and receiving, for each second block, a respective linear transformation of the physical position of the second block relative to the physical position of the first block and the one or more offset values.

[0014] The linear transformation represented in the generated data includes at least one of a horizontal translation along the floor plan, a vertical translation along the floor plan, a rotation along the floor plan, and a mirror flip along the floor plan.

[0015] The first data structure is generated at least in part using a circuit component placement process, the circuit component placement process including updating data representing physical locations of blocks in the first data structure according to one or more purposes.

[0016] The one or more objectives include at least one of improving the performance of the integrated circuit according to one or more predetermined metrics, reducing the power requirements of the integrated circuit, shortening the length of interconnections between circuit components of the integrated circuit, and reducing the physical area of ​​the integrated circuit on a substrate on which the integrated circuit is mounted.

[0017] Each block in the group of blocks represented by the first data structure is a uniqueized instance of a template block.

[0018] The template block is one of a multiple instantiation block (MIB), one or more intellectual property (IP) blocks, a memory macro, and one or more logic gates. [Brief explanation of the drawings]

[0019] [Figure 1] FIG. 1 is a block diagram of an exemplary chip placement generation system with a block deuniquing engine. [Figure 2] FIG. 1 is a flow diagram of an exemplary chip design pipeline with deuniquing, in accordance with aspects of the present disclosure. [Figure 3A] 1 is an exemplary chip-level graph of a chip, according to aspects of the present disclosure. [Figure 3B] 1 is another example of a chip-level graph of a chip, according to aspects of the present disclosure. [Figure 4A]1 is a flow diagram of an example process for deuniquing a data structure of a uniquified instance of a MIB, according to an aspect of the present disclosure. [Figure 4B] FIG. 10 is a flow diagram of an example process for generating a data structure including data representing the physical location of one or more blocks relative to a first block having a common MIB, according to an aspect of the present disclosure. [Figure 5] FIG. 1 is a block diagram of an exemplary environment for implementing a chip placement generation system according to aspects of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0020] Detailed Description overview Aspects of the present disclosure are directed to reducing the size of a chip-level graph, which represents the physical locations of circuit components of an integrated circuit ("IC" or "chip"), to facilitate performing a circuit component placement optimization process on the graph. A chip-level graph is a data structure that represents the physical placement of circuit components of an IC. The placement of physical components of an IC can be represented as blocks on a floorplan that refer to the faces or surfaces of the IC when fabricated on a substrate such as a wafer. Blocks of circuit components can be generated from a common template block, such as a multiple instantiation block (MIB), and may vary from instance to instance. To represent instance-specific differences between blocks, blocks in the chip-level graph are unified or duplicated within the graph, often with minor differences noted. Aspects of the present disclosure provide for eliminating unified instances without losing the instance-specific differences. In this disclosure, ununiqueness refers to the process by which ununiqued instances of template blocks are removed from the chip-level graph.

[0021] During chip design, especially in very large scale integration (VLSI), the placement of circuit components on or within a chip can have a significant impact on optimizing certain physical characteristics of the chip. Examples of physical characteristics that may be improved by optimizing the physical location of circuit components include shortening interconnect wire lengths between components and increasing component density, e.g., increasing the amount of components that can be placed on the same chip.

[0022] A chip-level graph is a model representation of a chip. Nodes in the graph are blocks or other circuit components, and edges between nodes are interconnects. Modern chip designs can contain millions or even billions of components, so chip-level graphs for modern chips can be large, with a large number of nodes and an exponential amount of edges due to the interconnections between the nodes. Blocks are logical abstractions of large amounts of circuit components, such as processing units or memory modules. Each block can be represented as its own internal graph, which can be large, e.g., millions of nodes. The large size of the chip-level graph can make it difficult or even computationally infeasible to perform processes to optimize the placement of circuit components within the blocks.

[0023] The increase in the size of the chip-level graph is due in part to the uniqueness of instances of common template blocks, such as MIBs. MIBs are circuit component template blocks that represent functional units on or within a chip as logical blocks. Examples of functional units that can be represented by MIBs include compute units and memory units. Instances of a MIB are blocks generated from the MIB and may be identical to the MIB or may deviate in some way from the MIB design. Examples of deviations include different locations or orientations within the chip, or interconnections between different blocks on the chip at different locations. Unique instances are treated as separate nodes in the chip-level graph, even if the differences between the instances are small, such as when one block is a shifted version of another block within the chip and all circuit components of that block are shifted in the same way.

[0024] Aspects of the present disclosure provide for avoiding uniqueness by having only a single graph representation for a MIB or other template block. Rather than a unique instance for each MIB, a single block, referred to herein as the base block, is selected for each group of blocks corresponding to each MIB.

[0025] A system configured according to aspects of the present disclosure can identify a linear transformation of a block relative to each of the other blocks in a group of blocks based on a fixed offset, such as a physical dimension, relative to the other blocks in the group. Treating a chip as a floorplan of blocks, the physical location of a block can be described as a linear transformation, such as a translation, rotation, or mirror, of a selected base block. For example, the physical location of a circuit component in a first block that borders or is adjacent to the base block can be represented by the physical location of the corresponding component in the base block shifted by a fixed offset across a face or surface on or within the chip. The physical location of a second block that borders or is adjacent to the first block can be represented by the physical location of the base block shifted by twice the fixed offset across a face or surface of the chip.

[0026] The reduced chip-level graph generated according to aspects of the present disclosure encodes each block of a group of blocks with a common template block relative to the group's respective base block. A fixed offset, e.g., an offset for translating or rotating the physical location of the base block, can be predetermined, and the system can identify each block in the group that has a common template block and a corresponding linear transformation for representing the block. Because blocks common to the template blocks have the same circuit components, the physical locations of the circuit components within the block can be represented as a linear transformation of the placement of the base circuit components in the corresponding base block.

[0027] Instance-specific or block-specific information, such as the interconnections between blocks and their pin locations in the block, can be encoded as a separate subgraph. For example, two blocks a and b from a common MIB A can be encoded as a separate subgraph. i1 and a i2Given a group, a block may have different connections to different adjacent blocks through different pins defined in MIB A. As described, the system may generate a subgraph to represent the interconnections of each block in the group and add the subgraph to data representing nodes in the chip-level graph of the base block of the group.

[0028] Adding the instance-specific interconnect graph is less computationally intensive than maintaining a unique instance of each template block individually, e.g., requires less memory or processing cycles to compute. The saved instance-specific information can be accessed later in a circuit component placement process that uses the information as part of optimizing the placement of circuit components within the block on a chip. In the circuit component placement process, all instances of the template block are treated as a single instance, rather than as separate instances with minor differences and redundant information.

[0029] Aspects of the present disclosure provide at least the following technical advantages: By reducing the size of a chip-level graph through deuniquing, as described herein, the circuit component placement process that receives the reduced chip-level graph can be performed more efficiently, e.g., as measured by fewer clock cycles or memory used, and / or as measured by reduced wall clock time for identifying improved physical locations for circuit components. Deuniquing a chip-level graph that would otherwise be computationally infeasible to optimize through placement of circuit components broadens the class of candidate chip designs. Increasing the amount of designs that can be optimized can identify improved circuit designs, such as, for example, more resource-efficient chips or chips with higher performance compared to previous chips.

[0030] Aspects of the present disclosure can be incorporated into existing chip design pipelines, for example, as an intermediate step between improving component placement at the chip block level and improving component placement within the chip's blocks. Deuniquing chip-level graphs before placement optimization can be a net positive in saving computational resources, which can be directed toward rapid chip prototyping, chip-scale performance optimization and estimation, and other improvements to existing chip design pipelines. These and other improvements scale with the size of chip designs and the amount of MIBs instantiating blocks. The more MIBs and MIB instances there are, the greater the performance gains and resource savings compared to processing chip-level graphs with ununiqued instances.

[0031] System example 1 is a block diagram of an exemplary chip placement generation system 100 with a block deuniquing engine 110. Chip placement generation system 100 can be implemented as one or more computer programs on one or more computers at one or more locations.

[0032] System 100 is configured to receive chip circuitry data 105 for a computer chip to be manufactured, such as a very large scale integrated (VLSI) chip, such as a central processing unit (CPU), or a hardware accelerator, such as a tensor processing unit (TPU) for machine learning acceleration. The computer chip may include integrated circuit components, such as transistors, resistors, capacitors, etc., depending on the chip's function. For example, the chip may be a special-purpose chip, such as an application-specific integrated circuit (ASIC) or a graphics processing unit (GPU), for machine learning calculations, video processing, encryption, or other computationally intensive functions.

[0033] Chip circuit component data 105 may include specifications for different circuit components that form part of a chip design. A circuit component is any component that can be part of an integrated circuit. Examples of components include processing units, memory, wires, buses, and individual or collections of circuits grouped to perform a function. A block is a logical configuration of one or more circuit components. Chip circuit component data 105 may include a netlist or other data structure that represents the logical or physical configuration of the circuit components of a chip design. A netlist is a data structure that can at least partially describe a chip-level graph and its subgraphs. A block may include different pins or other means of connecting to interconnects, such as wires, cables, or buses, for connecting and communicating data or power to different components or other devices of the system.

[0034] A block may include a macro component ("macro") that corresponds to a larger block of IC components, such as, for example, a static random access memory (SRAM) or other memory block. As another example, a node representing a macro component may include a hard macro comprised of a fixed number of standard cells, such as a macro comprised of a fixed number of instances of a register file. In some examples, a macro may include one or more nodes each representing a phase-locked loop (PLL) circuit located on the chip. In some examples, a macro may include a sensor located on the chip. A block may also be an intellectual property (IP) block.

[0035] A block may be an instance of a common template block, such as an MIB. An MIB can define a set of circuit components that may be frequently reused in a chip design. Examples of MIBs include computational units such as matrix or vector multipliers, accumulators, and systolic arrays. A block generated from a template block such as an MIB is an instance of that template block. Multiple blocks generated from the same template block are said to share that template block.

[0036] Multiple instances are considered to be unified if they share a common template block and are represented as individual blocks in a netlist or chip-level graph. Unified blocks may differ in the different pins connected to different blocks, for example, as described in more detail herein with reference to FIG. 3A.

[0037] The chip circuit component data 105 may be raw data or processed output generated from software and / or hardware for generating a chip design. For example, the chip circuit component data 105 may be generated using a programming language or framework for specifying a physical hardware design as a logic circuit. The programming language or framework may convert a particular programming language, such as C or C++, into a hardware description language (HDL), such as Verilog or VHDL, for specifying the circuit components of a computer chip. The chip circuit component data 105 may be the product of multiple conversion steps, such as converting high-level source code into a behavioral-based or digital logic-based description. The logic-based description may be further converted into specifications of logic gates and other circuit primitives required to implement the described logic. In general, any of a variety of tools and techniques for abstracting the hardware design to various degrees may be used to generate the component data 105.

[0038] System 100 can receive chip circuit component data 105 in any of a variety of ways. For example, system 100 can receive chip circuit component data 105 as an upload from a remote user of system 100 over a data communications network, such as using an application programming interface (API) provided by system 100. In some cases, system 100 can provide the output chip layout 104 to the remote user via the API provided by system 100, such as for use in manufacturing a chip according to the output chip layout 104. As another example, system 100 can be part of an electronic design automation (EDA) software tool and can receive chip circuit component data 105 from a user of the tool or from another part of the tool.

[0039] The system 100 can receive a netlist representing the physical locations of groups of circuit components on an integrated circuit. The netlist can be part of the chip circuit component data 105. A netlist is data describing the connectivity of integrated circuit components of a computer chip. A netlist can correspond to a description of the connectivity of an electronic circuit, such as a list of circuit components in the circuit and a list of nodes to which the circuit components are connected. For example, a node representing a memory macro can include nodes each representing a corresponding instance of an SRAM. As another example, a node representing a memory macro can include a hard macro composed of a fixed number of standard cells, such as a memory macro composed of a fixed number of instances of a register file. In some examples, a node representing a memory macro can include one or more nodes each representing a phase-locked loop (PLL) circuit disposed on the chip. In some examples, a node representing a memory macro can include one or more nodes each representing a sensor disposed on the chip.

[0040] Each node may correspond to a respective non-overlapping subset of integrated circuit components. For each node, the netlist may identify other nodes, if any, to which the node should be connected by one or more wires in the manufactured computer chip. Each node in the netlist may also correspond to a block. The netlist may at least partially define a graph representing the physical locations of blocks and other circuit components on the floorplan of the integrated circuit. Circuit components within a parent block may be represented as subgraphs within the node representing the parent block. Uniqued instances of a template block appear as separate nodes in the graph.

[0041] The placement engine 120 can receive chip circuit component data 105. If a netlist is not already provided, the placement engine 120 can generate a netlist from the component data 105. The placement engine 120 is configured to perform a circuit component placement process that places blocks on an integrated circuit floorplan according to one or more objectives to improve the performance of the integrated circuit. Exemplary objectives include reducing power consumption, minimizing interconnect wirelength, etc. A circuit component placement process can refer to any process for generating data describing the physical locations of blocks that improve the resulting physical chip according to one or more specified objectives. Exemplary techniques can include constraint-based techniques, graph-based techniques, and tree-based techniques.

[0042] The placement engine 120 may be configured to perform iterations of the circuit component placement process until some stopping criteria is met. Stopping criteria may include, for example, determining that a predetermined minimum improvement according to an objective has not been met. Another example of a stopping criterion is a maximum clock time allocation or a maximum computing resource allocation, e.g., a maximum amount of processing cycles allocated to perform the circuit component placement process.

[0043] Aspects of the present disclosure include a method that may be a downstream process for the first block of a circuit component placement process. Circuit components on or within a chip may be modeled to share a floorplan. In the floorplan, different blocks or other circuit components are placed according to some objective, such as minimizing or reducing wasted space, sometimes referred to as dead space, on the floorplan. The first step may be block-level placement, in which blocks are placed on the integrated circuit floorplan. The second step may be sub-component-level placement, in which circuit components ("sub-components") of a block are placed within the portion of the floorplan occupied by the circuit component's parent block.

[0044] Before performing the second block of the placement process, the placement engine 120 may generate a processed netlist 130 and pass the netlist to the deuniquing engine 110, as described herein. In some examples, the chip circuit component data 105 includes a processed netlist that has already been through a block-level placement process.

[0045] System 100 is configured to output a computer chip layout 104 that places some or all of the blocks in reduced netlist 140 at respective locations on the surface of a computer chip. The output chip layout 104 may identify respective locations on the surface of the computer chip for some or all of the nodes in reduced netlist 140 that correspond to the integrated circuit components represented by the nodes.

[0046] 2 is a flow diagram of an exemplary chip design pipeline 200 with deuniquing, according to aspects of the present disclosure. In some examples, system 100 may be part of or all of pipeline 200. In some examples, system 100 is part of a different pipeline that may include the same, more, fewer, or various stages as part of the design and manufacture of a chip.

[0047] In block 205, requirements for the chip are obtained. The requirements may specify, for example, the functions the chip should perform and whether there are any operational constraints, such as power limitations, maximum latency in data communication with a requesting device, etc. In block 210, logic to implement the requirements is designed. The logic may be designed, for example, as part of system 100 configured to receive the operational requirements and determine the logic and requirements for manufacturing a chip that meets those requirements. In block 215, a circuit is designed with the components necessary to implement the designed logic.

[0048] In block 220, system 100 may perform one or more iterations of a block-level placement process. As described with reference to Figure 1, the circuit component placement process may be divided into at least two stages: the block level in block 220 and the sub-component level in block 230. After block 220, the system may generate a netlist having blocks of the integrated circuit arranged to improve performance or power usage according to one or more objectives.

[0049] In block 225, the system 100 may perform a process to deunicate the netlist processed in block 220. For example, as described herein, the system may perform process 400A to remove ununiqued instances of template blocks and represent each instance with a single representation. The resulting reduced netlist may be provided as input to a device configured for sub-component level placement, as shown in block 230.

[0050] Performing sub-component level placement in block 230 results in a netlist with blocks having circuit components placed according to one or more objectives, e.g., reduced wire length, which can be used as part of a finalization / fabrication circuit step to produce a physical chip from the final design, as shown in block 235.

[0051] 3A is an example chip-level graph 300A of a chip 301A according to an embodiment of the present disclosure. The chip 301A includes blocks each instantiated from one of five MIBs: A, B, C, D, and E. For clarity, when referring to a particular circuit component within a block instantiated from an MIB, both the block and subcircuit component reference numerals are used. For example, circuit component a i1 .m a1 is block a i1 Circuit components in m a1 Circuit component a i1 .m a1 For example, block a i2 Parts in m a1 Circuit component a i2 .m a1 It is distinguished from.

[0052] Graph 300A shows the circuit component m a1 , m a2 , m a3 Three blocks a instantiated from MIB A each containing i1 , a i2 , a i3 Graph 300A also includes circuit component m b1 , m b2 Three blocks b instantiated from MIB B each containing i1 , b i2 , b i3 Contains block c i1 is instantiated from MIB C and consists of two circuit components m c1 and m c2 Contains block d i1 is instantiated from MIB D and the circuit component m d1 Contains Block e i1 is instantiated from MIB E, and the circuit component m e1 Including circuit components m f1 and m f2are also shown, which are not generated from template blocks but show that chip-level graphs can mix instantiated and non-instantiated circuit components.

[0053] If blocks on a chip are placed in predetermined fixed positions relative to each other, the location of a circuit component inside a block can be expressed as the location of a corresponding internal component in another block instantiated from the same MIB. This is possible because components inside blocks instantiated from the same MIB have the same relative positions. For example, block a i1 , a i2 , a i3 have the same width W, and the blocks are adjacent to each other on the chip as shown in graph 300A. i2 Circuit components in m a1 The position of block a i1 Circuit components in m a1 and an offset W, which corresponds to the width of the block in the chip. The offset H corresponds to the height of the block instantiated from MIB A. i2 .m a1 An example formulation of the physical location of is as follows:

[0054] a i2 .m a1 =a i1 .m a1 +W (1) Offset W is the offset of block a i1 and block a i2 and the offset W. Adding an offset W may be predefined to represent a horizontal translation, e.g., a translation to the right relative to the upper left corner of graph 300A. In other examples, addition, subtraction, or other operations may be defined to represent translations in different directions relative to a fixed point on graph 300A.

[0055] Another example is block a i3 Circuit component m in a1 The position of block ai1 Circuit component m in a1 and twice the offset W. i3 is a block a across an imaginary vertical axis. i1 In order to encode the reflection, the circuit component a i3 .m a1 We can invert the linear transformation that represents the position of

[0056] a i3 .m a1 =2W-a i1 .m a1 (2) Offset 2W is a i1 and a i3 In some examples, such as that shown in FIG. 2, the blocks may be spaced a fixed distance apart and not touching each other. In such examples, the width W may be the sum of the width of the blocks and a predetermined fixed distance between each block, shown as k in FIG. 2. The distance k is often zero to reduce dead space.

[0057] Block A i1 Although is selected as an exemplary base block in the above formulation, it is understood that other blocks can serve as base blocks that can represent the locations of circuit components in other blocks. For example, block a can be used as a base block. i2 Using the circuit component a i1 .m a1 One exemplary formulation for the position of can be as follows:

[0058] a i1 .m a1 =a i2 .m a2 -W (3) Comparing equations (1) and (3) shows that the exact transformations applied to represent the corresponding transformations of the circuit components can vary. For example, a translation to the right can be represented by adding a fixed offset (+). A translation to the left can be represented by subtracting a fixed offset (-). A mirror flip can be represented as a reversal of the position of the circuit component, as shown in equation (4). In some instances, other operations are used to define several ways to move the position of the circuit component across the chip.

[0059] The wires connecting different circuit components in the non-base blocks can also be represented as a function of the wires in the base block. 10 , w 11 , w 12 , w 13 , w 14 , w 15 , w 16 , w 17 , w 18 The wires w1 and w8 are connected to the base block a i1 Block a is connected to i3 Wire connected to 10 The physical location of can be expressed as a linear transformation of the physical location of wire w8 and the offset W. 10 An example of the formulation of the position is as follows:

[0060] w 10 =w8+2W (4) The system 100 is configured to receive a linear transformation for each circuit component on or within a chip. For example, the system can traverse a chip-level graph to identify groups of blocks instantiated from a common template block. The system can select a block from the group as a base block. To select the base block, the system can randomly select from the blocks in the group. In some examples, to select the base block, the system can identify the most centrally located block of the group, e.g., the block with the smallest average graph distance from each other block in the group. The distance metric for determining the graph distance can be the degree of separation the base block has from other blocks. In some examples, the base block is predetermined, e.g., the first instance of each template block.

[0061] 3A, we compare the structure of the chip-level graph before and after deuniquing, e.g., performing process 400A. One exemplary formulation of graph 300A may be (N,E), where N: {a i1 .m a1 ,a i1 .m a2 ,a i1 .m a3 ,a i2 .m a1 ,a i2 .m a2 ,a i2 .m a3 ,a i3 .m a1 ,a i3 .m a2 ,a i3 .m a3 , b i1 .m b1 ,b i1 .m b2 ,b i2 .m b1 ,b i2 .m b2 ,b i1 .mb3 ,b i3 .m b2 , c i1 .m c1 ,c i1 .m c2 d i1 .m d1 e i1 .m e1 m f1 m e1} Also, N: {w1,w2,w3,w4,w5,w6,w7,w8,w9,w 10 ,w 11 ,w 12 ,w 13 ,w 14 ,w 15 ,w 16 ,w 17 ,w 18 Interconnects i1 ),Interconnects(a i2 ),Interconnects(a i3 ), Interconnects(b i1 ),Interconnects(b i2 ),Interconnects(b i3 ), Interconnects(c i1 ), Interconnects(c i2 ), Interconnects(d i1 ), Interconnects(e i1 )} Here, Interconnects(x) is the set of all interconnections of circuit components in block x. For example, Interconnects(a i1 ) is {a i1 .s1,a i1 .s2,a i1 .s3}.

[0062] Each block in (N,E) is a uniqueized instance, and the graph (N,E) consumes more space than a reduced graph representation generated according to aspects of the present disclosure. The reduced graph representation (N',E',L) can retain the block information of the base blocks, leaving the remaining blocks represented as their respective linear transformations. An example formulation of N' may be as follows:

[0063] N': {a i1 .m a1 ,a i1 .m a2 ,a i1 .m a3 ,a i2 .m a1 , b i1 .m b1 ,b i1 .m b2 , c i1 .m c1 ,c i1 .m c2 d i1 .m d1 e i1 .m e1 m f1 m e1} In N', the base block, i.e., a i1 , b i1 , c i1 , d i1 , e i1 Only the circuit component m is encoded. f1 and m e1 is also encoded because it is instantiated only once in the circuit represented by graph 300A.

[0064] One formulation for E' can be as follows: N': +{w1,w2,w'3,w'4,w5,w6,w7,w8,w'9,w' 10 ,w 11 ,w12 ,w' 13 ,w' 14 ,w 15 ,w 16 ,w' 17 ,w 18 , Interconnects i1 ), Interconnects(b i1 ), Interconnects(c i1 ), Interconnects(d i1 ), Interconnects i1 )} In E', wires w1, w2, and w8 are connected to the base block a i1 are wires corresponding to wires w7, w 12 is base block b i1 are wires corresponding to wires w5, w 11 is the base block c i1 is the wire corresponding to wire w 16 is the base block d i1 is the wire corresponding to wire w 15 is block e i1 The wire w6 corresponds to the circuit component m f1 is the wire corresponding to wire w 18 is block m e1 The wires w'3, w'4, w'9, and w' 13 , w' 14 , and w' 17 corresponds to a non-base block and is expressed as a linear transformation of the corresponding base block wires as described with reference to Figure 3A. 13 , w' 14 , and w' 17, including their pin locations, is specific to each block and is used for location placement of the block's circuit components, as described herein. The reduced graph (N',E') represents graph 300A with less data than the graph representation (N,E) as a whole, while retaining its instance-specific information.

[0065] The interconnections of each base block in E' include the interconnections of blocks instantiated from the same MIB. Unique interconnections between components within the same non-base block are also encoded as base block interconnections. For example, if block a2 has a unique interconnection between two circuit components, that interconnection is encoded as Interconnects(a i1 )

[0066] The linear transformation L may be a list of linear transformations corresponding to each non-base block. For example, the linear transformation L may include the transformations shown with reference to equations (1), (2), and (4). In some examples, the linear transformation L may include lookup table values ​​for predetermined transformations, such as horizontal translations, rotations, etc., encoded as part of the system 100. The fixed offsets used may be included as part of the linear transformation L and / or may be determined based on block information for the base blocks. The block information may be encoded as part of the chip-level graph 300A and may include offsets such as width W, height H, and spacing k between blocks. In some examples, the linear transformation may be predetermined, for example, to include only horizontal translations relative to the base blocks. In these examples, the linear transformation L may be empty.

[0067] 3B is another example chip-level graph 300B of a chip 301B according to an embodiment of the present disclosure. i4 and a i5 From MIB A, wire w 20 ,w 21After the base block is selected, for each circuit component in each non-base block, the system can determine (i) the respective base circuit component within the base block, (ii) the offset value of the circuit component, and (iii) the transformation between the position of each base circuit component and the offset value to arrive at the position of the circuit component. As shown in examples 300A-C, different transformations include combinations of horizontal translation, vertical translation, mirror flip, and rotation. The system can be configured to apply specific operations to represent the possible transformations, such as addition / subtraction for horizontal / vertical translation. In some examples, linear transformations are determined manually and provided to system 100.

[0068] Linear transformations can also include rotations. Block a i5 The physical location of is block a i4 The block a is rotated 90 degrees relative to its physical position. i4 If is the base block, then block a i5 One formulation of the physical location of is as follows:

[0069] a i5 =a i4 +90° (5) In the example of equation (5), adding an angle can be a clockwise rotation of the base block, and subtracting an angle can be a counterclockwise rotation of the base block. Combinations of translation, mirroring, and rotation can be defined and applied in order, for example, the first term after the base block is a horizontal translation, the second term is a vertical translation, and the third term is a rotation angle, and the base block is multiplied by -1 to indicate a mirroring. An example format for representing the physical position of non-base block x2 relative to base block x1 is as follows:

[0070] x2=(±1)x1±h offset ±v offset ±rotation offset (6) where h offset is the horizontal offset, and voffset is the vertical offset, and rotation offset is the rotation offset (0 to 360 degrees).

[0071] Exemplary Methods 4A is a flow diagram of an example process 400A for deuniquing a data structure of a uniquified instance of a MIB according to an aspect of the present disclosure. The system can distribute chip floorplan operations across many different workers, which can include many different homogeneous or heterogeneous computing devices that perform computations using CPUs, GPUs, and / or ASICs. Some or all steps of process 400A can be performed in parallel by many different workers operating asynchronously with respect to one another. Different workers can also operate synchronously to perform some or all steps of processes 400A and / or 400B in parallel.

[0072] A system of one or more processors can receive a first data structure including data representing a physical location of each block of a group of blocks within an integrated circuit, the group including a first block and one or more second blocks, according to block 405. For example, system 100 can perform process 400A. Although process 400A is described with reference to a single group of blocks, process 400A can be repeated for each of multiple groups of blocks in a first data structure, such as a chip-level graph.

[0073] The first data structure may be a chip-level graph or other data structure that represents the physical locations of blocks or other circuit components of a chip design. For example, the first data structure may be netlist data 130 or chip circuit component data 105, as shown and described with reference to FIG.

[0074] The system generates a second data structure according to block 410 that includes data representing the physical location of one or more second blocks relative to the first block.

[0075] The first block may be a base block as described with reference to Figures 1 and 3A-3C. The second data structure may be a reduced chip-level graph in which each MIB or template block used to generate the instances in the first data structure is represented by a single instance. Figure 4B shows an example process 400B for generating a data structure including data representing the physical location of one or more blocks relative to the first block.

[0076] The system causes one or more iterations of a circuit component placement process to be performed on the second data structure according to block 415. A circuit component placement process such as that described herein with reference to FIG. 2 can be divided into two phases. The received first data structure can be netlist data generated as part of a first block of a circuit component placement process, in which the physical locations of blocks on or within a chip are optimized according to one or more objectives. The system can trigger one or more iterations or a second block of the circuit component placement process, in which the placement of circuit components within each block of the received chip-level graph is optimized according to one or more objectives. In some examples, the system can cause the execution of one or more iterations of the first phase, the second phase, or both the first and second blocks of the circuit component placement process using the second data structure as input.

[0077] The system can cause execution of one or more iterations of the circuit component placement process by sending a request including the second data structure to one or more devices configured to perform the circuit component placement process. In some examples, the system can receive output from the circuit component placement and perform further processing, for example, as part of a chip design pipeline. In some examples, the system can cause execution of the circuit component placement process by executing a process using one or more processors.

[0078] 4B is a flow diagram of an example process 400B for generating a data structure including data representing the physical location of one or more blocks relative to a first block having a common MIB, according to an aspect of the present disclosure. For example, system 100 can perform process 400B.

[0079] The system selects a first block in a group of blocks that share a common MIB, according to block 420. The common MIB is an example of a template block and can be used to generate a group of blocks that are instances of the template block. Although described with reference to MIBs, in some examples, the system can perform process 400B using blocks generated from memory macros, IP blocks, etc., as described herein with reference to FIG.

[0080] The system can select a first block as the base block of the group. This selection can be random or based on some heuristic, such as the physical proximity of the first block to other blocks as shown in a chip-level graph. For example, the system can perform a graph search to identify the centroid of a cluster containing the group of blocks and select the most "central" block of the group as the base block. The distance to the centroid can be measured, for example, as the separation or average separation between nodes representing blocks in the group. In another example, the first block of a netlist instantiated from a template block can be selected as the base block.

[0081] The system receives a fixed offset and a linear transformation according to block 425. The fixed offset can be based on a predetermined width, height, and gap distance between blocks in the group of blocks, for example, in the case of a horizontal translation or a vertical translation. To receive the linear transformation, the system can traverse a data structure, for example, a chip-level graph, to identify the spatial relationship between the selected base block and non-base blocks from the same instance. Spatial information about each circuit component, such as the physical location and orientation of each component, can be identified as part of the block-level placement process. Using the spatial information, the system can identify the relationship between the base block and other blocks in the group. For example, if a non-base block is three blocks away from the base block and each block has a fixed offset width of W, the linear transformation for representing the physical location of the non-base block has a horizontal translation of 3W. In some examples, the system can receive a predetermined linear transformation for the physical location of each non-base block in the group.

[0082] For each second block in the group of blocks, the system generates data representing the physical location of the second block according to block 430, where the data includes a linear transformation of each of the second blocks.

[0083] Example Computing Environment 5 is a block diagram of an exemplary environment 500 for implementing a chip placement generation system 100 according to aspects of the present disclosure. The system 100 may be implemented in one or more devices having one or more processors in one or more locations, such as a server computing device 515. The user computing device 512 and the server computing device 515 may be communicatively coupled to one or more storage devices 530 via a network 560. The storage device 530 may be a combination of volatile and non-volatile memory and may be in the same physical location as the computing devices 512, 515 or in a different physical location. For example, the storage device 530 may include any type of non-transitory computer-readable medium capable of storing information, such as a hard drive, a solid-state drive, a tape drive, an optical storage device, a memory card, ROM, RAM, DVD, CD-ROM, writable memory, and read-only memory.

[0084] The server computing device 515 may include one or more processors 513 and memory 514. The memory 514 may store information accessible by the processor 513, including instructions 521 that may be executed by the processor 513. The memory 514 may also include data 523 that may be retrieved, manipulated, or stored by the processor 513. The memory 514 may be a type of non-transitory computer-readable medium that can store information accessible by the processor 513, such as volatile and non-volatile memory. The processor 513 may include one or more central processing units (CPUs), graphics processing units (GPUs), field programmable gate arrays (FPGAs), and / or application specific integrated circuits (ASICs), such as tensor processing units (TPUs).

[0085] Instructions 521 may include one or more instructions that, when executed by processor(s) 513, cause one or more processors to perform operations defined by the instructions. Instructions 521 may be stored in object code format for direct processing by processor(s) 513, or in other formats, including interpretable scripts or a collection of independent source code modules that are interpreted on demand or pre-compiled. Instructions 521 may include instructions for implementing system 100 consistent with aspects of the present disclosure. System 100 may be executed using processor 513 and / or using other processors located remotely from server computing device 515.

[0086] Data 523 may be retrieved, stored, or modified by processor 513 in accordance with instructions 521. Data 523 may be stored in a computer register, a relational or non-relational database, as a table with multiple different fields and records, or as a JSON, YAML, proto, or XML document. Data 523 may also be formatted in a computer-readable format, such as, but not limited to, binary values, ASCII, or Unicode. Furthermore, data 523 may include sufficient information to identify related information, such as numbers, descriptive text, proprietary codes, pointers, references to data stored in other memory, including other network locations, or information used by a function to calculate the related data.

[0087] The user computing device 512 may also be configured like a server computing device 515, including one or more processors 516, memory 517, instructions 518, and data 519. The user computing device 512 may also include a user output 526 and a user input 524. The user input 524 may include any suitable mechanism or technology for receiving input from a user, such as a keyboard, a mouse, a mechanical actuator, a soft actuator, a touchscreen, a microphone, and a sensor.

[0088] The server computing device 515 may be configured to transmit data to the user computing device 512, which may be configured to display at least a portion of the received data on a display implemented as part of the user output 526. The user output 526 may also be used to display an interface between the user computing device 512 and the server computing device 515. The user output 526 may alternatively or additionally include one or more speakers, transducers, or other audio outputs, haptic interfaces, or other tactile feedback that provide non-visual and non-audible information to a user of the user computing device 512.

[0089] While FIG. 5 illustrates processors 513, 516 and memories 514, 517 as being within computing devices 515, 512, the components described herein, including processors 513, 516 and memories 514, 517, may include multiple processors and memories that may operate in different physical locations rather than within the same computing device. For example, some of the instructions 521, 518 and data 523, 519 may be stored on a removable SD card, while others may be stored in a read-only computer chip. Some or all of the instructions and data may be stored in a location physically separate from processors 513, 516 but still accessible by processors 513, 516. Similarly, processors 513, 516 may include a collection of processors capable of performing simultaneous and / or sequential operations. Computing devices 515, 512 may each include one or more internal clocks that provide timing information, which may be used to time operations and programs executed by computing devices 515, 512.

[0090] Server computing device 515 may be configured to receive requests to process data from user computing devices 512. For example, environment 500 may be part of a computing platform configured to provide various services to users via various user interfaces and / or APIs that expose platform services.

[0091] The devices 512, 515 may be capable of direct and indirect communication over the network 560. The devices 512, 512 may set up listening sockets capable of accepting initiating connections to send and receive information. The network 560 itself may include a variety of configurations and protocols, including the Internet, the World Wide Web, an intranet, a virtual private network, a wide area network, a local network, and a private network using one or more proprietary company communication protocols. The network 560 may support a variety of short- and long-range connections. The short- and long-range connections may occur over different bandwidths, such as 2.402 GHz to 2.480 GHz (commonly associated with the Bluetooth® standard), 2.4 GHz and 5 GHz (commonly associated with the Wi-Fi® communication protocol), or various communication standards, such as the LTE® standard for wireless broadband communication. The network 560 may additionally or alternatively support wired connections between the devices 512, 515, including some types of Ethernet® connections.

[0092] 5 depicts a single server computing device 515 and user computing device 512, it is understood that aspects of the disclosure may be implemented according to a variety of different configurations and quantities of computing devices, including paradigms for serial or parallel processing, or on a distributed network of multiple devices. In some implementations, aspects of the disclosure may be performed on a single device, and any combination thereof.

[0093] Aspects of the present disclosure may be implemented in digital circuitry, a computer-readable storage medium, one or more computer programs, or a combination of one or more of the foregoing. The computer-readable storage medium may be non-transitory, such as executable by a cloud computing platform and as one or more instructions stored on a tangible storage device.

[0094] As used herein, the phrase "configured to" is used in different contexts relating to a computer system, hardware, or part of a computer program, engine, or module. When a system is said to be configured to perform one or more operations, this means that the system has installed thereon appropriate software, firmware, and / or hardware that, when operated, causes the system to perform the one or more operations. When hardware is said to be configured to perform one or more operations, this means that the hardware includes one or more circuits that, when operated, receive inputs and, in accordance with the inputs, generate outputs corresponding to the one or more operations. When a computer program, engine, or module is said to be configured to perform one or more operations, this means that the computer program includes one or more program instructions that, when executed by one or more computers, cause the one or more computers to perform one or more operations.

[0095] Unless otherwise specified, the foregoing alternatives are not mutually exclusive and can be implemented in various combinations to achieve unique advantages. Because these and other variations and combinations of the features described above can be utilized without departing from the subject matter defined by the claims, the description of the foregoing embodiments should be taken for illustrative purposes, not for limiting the subject matter defined by the claims. Additionally, the provision of examples described herein, as well as phrases such as "such as," "including," and the like, should not be construed as limiting the subject matter of the claims to any particular example; rather, the example is intended to illustrate only one of many possible implementations. Furthermore, the same reference numbers in different drawings may identify the same or similar elements.

Claims

1. 1. A method comprising:

1. A method for implementing a method of implementing a method of implementing a first data structure comprising: one or more processors receiving a first data structure including data representing a physical location of each block of a group of blocks in an integrated circuit (IC), the group of blocks including a first block and one or more second blocks, each block including one or more respective circuit components; the first data structure being generated at least in part using a circuit component placement process, the circuit component placement process including updating the data representing the physical locations of the blocks in the first data structure according to one or more purposes; The one or more processors may generate a second data structure, the second data structure including data representing a physical location of the one or more second blocks relative to the first blocks, and the method may further include: the one or more processors at least partially causing execution of one or more iterations of the circuit component placement process on the second data structure, the circuit component placement process including generating data representing physical locations of circuit components of blocks represented by the second data structure in accordance with the one or more objectives.

2. generating the second data structure generating, for each circuit component of the second block, data representing the physical location of the circuit component and one or more offset values ​​relative to the physical location of a respective circuit component in the first block; The method of claim 1 , comprising:

3. generating the second data structure generating, as part of the second data structure, data representing block-specific interconnections of the one or more second blocks, the block-specific interconnections representing unique connections between the second blocks and another circuit component; The method of claim 1.

4. the physical location of each block is represented as a respective location on a floorplan of the integrated circuit; generating the second data structure selecting the first block from the group of blocks; generating, for each second block, data representative of the physical location of the second block, the data including a respective linear transformation of the physical location of the first block along the floorplan of the integrated circuit; Including, The method of claim 1.

5. the one or more processors receiving the one or more offset values ​​based at least in part on physical dimensions of the blocks within the group; for each second block, the one or more processors receiving the respective linear transformation of the physical location of the second block relative to the physical location of the first block and the one or more offset values; further comprising: The method of claim 4.

6. The linear transformation represented on the generated data is a horizontal translation along the floor plan, a vertical translation along the floor plan, a rotation along the floor plan, and a mirror flip along the floor plan; at least one of The method of claim 4.

7. The one or more objectives are: Improving the performance of the integrated circuit according to one or more predetermined metrics; reducing the power requirements of the integrated circuit; reducing the length of interconnections between circuit components of said integrated circuit; and reducing the physical area of ​​the integrated circuit on the substrate on which it is mounted; at least one of The method of claim 1.

8. causing execution of one or more iterations of the circuit component placement process includes the one or more processors executing the one or more iterations. The method of claim 1.

9. each block of the group of blocks represented by the first data structure is a uniqueized instance of a template block; The method of claim 1.

10. The template block is a Multiple Instantiation Block (MIB), one or more Intellectual Property (IP) blocks, a memory macro, or one or more logic gates; 10. The method of claim 9, wherein the

11. 1. A system including one or more processors, the one or more processors comprising: The method is configured to execute, by the one or more processors, receiving a first data structure including data representing a physical location of each block of a group of blocks in an integrated circuit (IC), the group of blocks including a first block and one or more second blocks, each block including one or more respective circuit components, the first data structure being generated at least in part using a circuit component placement process, the circuit component placement process including updating the data representing the physical locations of the blocks in the first data structure according to one or more purposes, and the one or more processors are further configured to execute, by the one or more processors, and configured to execute, by the one or more processors, generating a second data structure, the second data structure including data representing a physical location of the one or more second blocks relative to the first blocks, the one or more processors further configured to: and configured to at least partially cause, by the one or more processors, execution of one or more iterations of the circuit component placement process on the second data structure, the circuit component placement process including generating data representing physical locations of circuit components of blocks represented by the second data structure in accordance with the one or more objectives.

12. In generating the second data structure, the one or more processors: generating, for each circuit component of the second block, data representing the physical location of the circuit component and one or more offset values ​​relative to the physical location of a respective circuit component in the first block; and further configured to perform The system of claim 11.

13. In generating the second data structure, the one or more processors: and further configured to generate, as part of the second data structure, data representing block-specific interconnections of the one or more second blocks, the block-specific interconnections representing unique connections between the second blocks and another circuit component. The system of claim 11.

14. the physical location of each block is represented as a respective location on a floorplan of the integrated circuit; In generating the second data structure, the one or more processors: selecting the first block from the group of blocks; generating, for each second block, data representative of the physical location of the second block, the data including a respective linear transformation of the physical location of the first block along the floorplan of the integrated circuit; and further configured to perform The system of claim 11.

15. the one or more processors: receiving the one or more offset values ​​based at least in part on physical dimensions of blocks in the group; receiving, for each second block, the respective linear transformation of the physical location of the second block relative to the physical location of the first block and the one or more offset values; and further configured to perform The system of claim 14.

16. The linear transformation represented on the generated data is a horizontal translation along the floor plan, a vertical translation along the floor plan, a rotation along the floor plan, or a mirror flip along the floor plan; at least one of The system of claim 14.

17. The one or more objectives are: Improving the performance of the integrated circuit according to one or more predetermined metrics; reducing the power requirements of the integrated circuit; reducing the length of interconnections between circuit components of said integrated circuit; and reducing the physical area of ​​the integrated circuit on the substrate on which it is mounted; at least one of The system of claim 11.

18. One or more computer programs which, when executed by one or more processors, cause said one or more processors to perform the method of any one of claims 1 to 10.

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