Semiconductor equipment

Abstract

To provide a semiconductor device with reduced power consumption.SOLUTION: There is provided a semiconductor device including a first transistor and a second transistor. The first transistor is a p-channel transistor including silicon in a channel formation region, and the second transistor is an n-channel transistor including a metal oxide in a channel formation region. The metal oxide includes indium, an element M (e.g., gallium), and zinc. A gate of the first transistor is electrically connected to a gate of the second transistor, and one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor. The first transistor and the second transistor can each operate in a subthreshold region.SELECTED DRAWING: Figure 9

Description

[Technical Field]

[0001] One aspect of the present invention relates to a semiconductor device.

[0002] Furthermore, one aspect of the present invention is not limited to the above-mentioned technical field. The technical field of the invention disclosed herein relates to objects, driving methods, or manufacturing methods. Alternatively, one aspect of the present invention relates to processes, machines, manufactures, or compositions of matter. More specifically, examples of the technical field of one aspect of the present invention disclosed herein include semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, energy storage devices, imaging devices, memory devices, signal processing devices, processors, electronic devices, systems, methods for driving them, methods for manufacturing them, or methods for inspecting them. [Background technology]

[0003] Information terminals such as smartphones, tablet devices, and desktop PCs (personal computers) contain various semiconductor devices such as CPUs and memory devices. Furthermore, with the development of information technology, the amount of data handled by information terminals such as smartphones, tablet devices, and desktop PCs tends to increase, and it is desirable that these information terminals be equipped with semiconductor devices capable of high-speed processing to handle large amounts of data. As a result, the power consumption of information terminals is increasing along with the increase in the amount of data. On the other hand, it is known that the power consumption of the aforementioned devices, circuits, or sensors is low because the amount of current handled is small, for example, in electronic devices for IoT, circuits for energy harvesting, or sensors used in biomedical applications. In addition, low-power SAR-ADCs (Successive Regulator-Analog Converters) are sometimes used in the aforementioned devices, circuits, or sensors. Non-Patent Literature 1 discloses a SAR-ADC in which both the flip-flop circuit and the latch circuit are composed solely of logic circuits. [Prior art documents] [Non-patent literature]

[0004] [Non-Patent Document 1] S. Josephsen, “An Ultra-Low Power SAR-ADC in 65nm CMOS Technology,” [online], June 2013. Norwegian University of Science and Technology. [Retrieved June 25, 2021], Internet <URL:https: / / ntnuopen.ntnu.no / ntnu-xmlui / bitstream / handle / 11250 / 2433737 / 8707_FULLTEXT.pdf> [Overview of the project] [Problems that the invention aims to solve]

[0005] As described above, the SAR-ADC has a circuit configuration that includes a logic circuit, as an example. In this specification, a SAR-ADC that includes a logic circuit will be referred to as a SAR-ADC logic circuit.

[0006] Logic circuits include CMOS circuits as an example. CMOS circuits are preferred because of their high drive speed, but increasing the drive speed requires increasing the drive voltage input to the CMOS circuit. However, increasing the drive voltage increases the amount of current flowing through the CMOS circuit, resulting in higher power consumption.

[0007] Furthermore, in IoT electronic devices, energy harvesting circuits, or sensors used in biomedical applications, it may not be necessary to drive CMOS circuits at high speeds. In other words, in the aforementioned devices, circuits, or sensors, it may be possible to reduce the power consumption of the SAR-ADC logic circuit by configuring a CMOS circuit that can operate at a low drive voltage.

[0008] One aspect of the present invention aims to provide a semiconductor device with reduced power consumption. Alternatively, one aspect of the present invention aims to provide a novel semiconductor device. Alternatively, one aspect of the present invention aims to provide an electronic device including a novel semiconductor device.

[0009] It should be noted that the problems addressed by one aspect of the present invention are not limited to those listed above. The problems listed above do not preclude the existence of other problems. These other problems are those not mentioned in this section, as described below. Those not mentioned in this section can be derived from the description in the specification or drawings, etc., by those skilled in the art, and can be appropriately extracted from these descriptions. It should be noted that one aspect of the present invention solves at least one of the problems listed above and other problems. It should be noted that one aspect of the present invention does not need to solve all of the problems listed above and other problems. [Means for solving the problem]

[0010] (1) One aspect of the present invention is a semiconductor device having a first transistor and a second transistor. The first transistor is a p-channel type transistor containing silicon in its channel formation region, and the second transistor is an n-channel type transistor containing a metal oxide in its channel formation region. The metal oxide is indium, element M (element M is one or more selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium), and zinc. The gate of the first transistor is electrically connected to the gate of the second transistor, and either the source or drain of the first transistor is electrically connected to either the source or drain of the second transistor. Note that each of the first and second transistors may operate in the subthreshold region.

[0011] (2) Alternatively, one aspect of the present invention is a semiconductor device having a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor. The third transistor and the fifth transistor are each p-channel type transistors containing silicon in the channel formation region, and the fourth transistor and the sixth transistor are each n-channel type transistors containing a metal oxide in the channel formation region. The metal oxide is indium, element M (element M is one or more selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium), and zinc. The gate of the third transistor is electrically connected to the gate of the fourth transistor. Furthermore, one source or drain of the third transistor is electrically connected to one source or drain of the fifth transistor, one source or drain of the fourth transistor is electrically connected to one source or drain of the sixth transistor, and the other source or drain of the fifth transistor is electrically connected to the other source or drain of the sixth transistor. Note that each of the third through sixth transistors may operate in the subthreshold region.

[0012] (3) Alternatively, one aspect of the present invention is a semiconductor device having a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, and a twelfth transistor. The seventh transistor and the ninth transistor are each p-channel type transistors containing silicon in the channel formation region, and the eighth transistor, the tenth transistor, the eleventh transistor, and the twelfth transistor are each n-channel type transistors containing a metal oxide in the channel formation region. The metal oxide includes indium, element M (where element M is one or more selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium), and zinc. The gate of the 7th transistor is electrically connected to the gate of the 8th transistor and the gate of the 12th transistor, and the gate of the 9th transistor is electrically connected to the gate of the 10th transistor and the gate of the 11th transistor. In addition, one source or drain of the 7th transistor is electrically connected to one source or drain of the 8th transistor, one source or drain of the 9th transistor, and one source or drain of the 10th transistor, the other source or drain of the 8th transistor is electrically connected to one source or drain of the 11th transistor, and the other source or drain of the 10th transistor is electrically connected to one source or drain of the 12th transistor. Note that each of the 7th through 12th transistors includes cases where they operate in the subthreshold region.

[0013] (4) Alternatively, one aspect of the present invention is a semiconductor device having a 13th transistor, a 14th transistor, a 15th transistor, and a 16th transistor. The 13th and 15th transistors are p-channel transistors containing silicon in their channel formation region, and the 14th and 16th transistors are n-channel transistors containing a metal oxide in their channel formation region. The metal oxide includes indium, element M (where element M is one or more selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium), and zinc. The gate of the 13th transistor is electrically connected to the gate of the 14th transistor, and the gate of the 15th transistor is electrically connected to the gate of the 16th transistor. Furthermore, one of the sources or drains of the 13th transistor is electrically connected to one of the sources or drains of the 14th transistor and one of the sources or drains of the 16th transistor, and the other of the sources or drains of the 13th transistor is electrically connected to one of the sources or drains of the 15th transistor. Note that each of the 13th through 16th transistors may operate in the subthreshold region.

[0014] (5) One aspect of the present invention is a semiconductor device having a first circuit and a first inverter circuit. The first circuit has a first transistor and a first capacitor. The first transistor is an n-channel type transistor containing a metal oxide in its channel forming region. The metal oxide is indium, element M (element M is one or more selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium), and zinc. The output terminal of the first circuit is electrically connected to the input terminal of the first inverter circuit, and either the source or drain of the first transistor is electrically connected to the first terminal of the first capacitor and to the output terminal of the first circuit. The transistor included in the first inverter circuit also includes cases where it operates in the subthreshold region.

[0015] (6) Alternatively, in one aspect of the present invention, the configuration in (5) above may include a second circuit and a second inverter circuit. In particular, the second circuit preferably includes a second transistor and a second capacitor, and the second transistor is preferably an n-channel transistor containing a metal oxide in its channel formation region. Furthermore, it is preferable that the output terminal of the first inverter circuit is electrically connected to the input terminal of the second circuit, the output terminal of the second circuit is electrically connected to the input terminal of the second inverter circuit, and the output terminal of the second inverter circuit is electrically connected to the input terminal of the first circuit. Furthermore, it is preferable that the other of the source or drain of the first transistor is electrically connected to the input terminal of the first circuit, one of the source or drain of the second transistor is electrically connected to the first terminal of the second capacitor and the output terminal of the second circuit, and the other of the source or drain of the second transistor is electrically connected to the input terminal of the second circuit. Furthermore, it is preferable that the transistors included in the second inverter circuit include cases where they operate in the subthreshold region.

[0016] (7) Alternatively, one aspect of the present invention is a semiconductor device having a first circuit and a first inverter circuit. The first circuit has a first transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a first capacitor. The first, fourth, and sixth transistors are each n-channel transistors containing a metal oxide in their channel formation region. The metal oxide is indium, element M (element M is one or more selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium), and zinc. The third and fifth transistors are each p-channel transistors containing silicon in their channel formation region. The output terminal of the first circuit is electrically connected to the input terminal of the first inverter circuit, and one of the source or drain of the first transistor is electrically connected to the first terminal of the first capacitor and to the gate of the fourth transistor. Furthermore, one of the source or drain of the third transistor is electrically connected to one of the source or drain of the fourth transistor, to the gate of the fifth transistor and to the gate of the sixth transistor, and one of the source or drain of the fifth transistor is electrically connected to one of the source or drain of the sixth transistor and to the output terminal of the first circuit. In addition, each of the transistors included in the first inverter circuit, the third transistor, the fourth transistor, the fifth transistor and the sixth transistor, includes cases where they operate in the subthreshold region.

[0017] (8) Alternatively, in one aspect of the present invention, the configuration in (7) above may include a second circuit and a second inverter circuit. In particular, it is preferable that the second circuit includes a second transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, and a second capacitor. It is also preferable that each of the second transistor, the eighth transistor, and the tenth transistor is an n-channel type transistor containing a metal oxide in its channel formation region. Furthermore, it is preferable that each of the seventh transistor and the ninth transistor is a p-channel type transistor containing silicon in its channel formation region. It is also preferable that the output terminal of the first inverter circuit is electrically connected to the input terminal of the second circuit, the output terminal of the second circuit is electrically connected to the input terminal of the second inverter circuit, and the output terminal of the second inverter circuit is electrically connected to the input terminal of the first circuit. It is preferable that the source or drain of the first transistor is electrically connected to the input terminal of the first circuit, and one of the source or drain of the second transistor is electrically connected to the first terminal of the second capacitor and the gate of the eighth transistor. Furthermore, it is preferable that one of the sources or drains of the seventh transistor is electrically connected to one of the sources or drains of the eighth transistor, the gate of the ninth transistor, and the gate of the tenth transistor, and that one of the sources or drains of the ninth transistor is electrically connected to one of the sources or drains of the tenth transistor and the output terminal of the first circuit. It is also preferable that each of the transistors included in the second inverter circuit, the seventh transistor, the eighth transistor, the ninth transistor, and the tenth transistor, includes a case where they operate in the subthreshold region.

[0018] In this specification, a semiconductor device refers to a device that utilizes semiconductor properties, including circuits containing semiconductor elements (e.g., transistors, diodes, and photodiodes), and devices having such circuits. Furthermore, a semiconductor device refers to any device that can function by utilizing semiconductor properties. For example, integrated circuits, chips equipped with integrated circuits, and electronic components with chips housed in packages are all examples of semiconductor devices. Additionally, memory devices, display devices, light-emitting devices, lighting devices, and electronic devices may themselves be semiconductor devices or may contain semiconductor devices.

[0019] Furthermore, where it is stated in this specification that X and Y are connected, this specification shall include disclosures of cases where X and Y are electrically connected, functionally connected, and directly connected. Therefore, it shall not be limited to predetermined connection relationships, such as those shown in the figures or text, but shall also include connection relationships other than those shown in the figures or text. X and Y shall be objects (for example, devices, elements, circuits, wiring, electrodes, terminals, conductive films, or layers).

[0020] One example of a case where X and Y are electrically connected is that one or more elements that enable the electrical connection between X and Y (e.g., switches, transistors, capacitive elements, inductors, resistors, diodes, display devices, light-emitting devices, and loads) can be connected between X and Y. Note that a switch has the function of being controlled to be on or off. In other words, a switch has the function of controlling whether or not current flows by being in a conductive state (on state) or a non-conductive state (off state).

[0021] One example of a functional connection between X and Y is when one or more circuits that enable the functional connection between X and Y (for example, logic circuits (e.g., inverters, NAND gates, and NOR gates), signal conversion circuits (e.g., digital-to-analog conversion circuits, analog-to-digital conversion circuits, and gamma correction circuits), potential level conversion circuits (e.g., power supply circuits such as boost or buck converters, and level shifter circuits that change the potential level of a signal), voltage sources, current sources, switching circuits, amplification circuits (e.g., circuits that can increase signal amplitude or current, operational amplifiers, differential amplifiers, source follower circuits, and buffer circuits), signal generation circuits, memory circuits, and control circuits) can be connected between X and Y. Note that, as an example, even if another circuit is placed between X and Y, if a signal output from X is transmitted to Y, X and Y are considered functionally connected.

[0022] Furthermore, when it is explicitly stated that X and Y are electrically connected, this includes both cases where X and Y are electrically connected (i.e., connected with another element or circuit in between) and cases where X and Y are directly connected (i.e., connected without another element or circuit in between).

[0023] Furthermore, this specification deals with circuit configurations in which multiple elements are electrically connected to wiring (wiring that supplies a constant potential or wiring that transmits a signal). For example, if X and wiring are directly connected, and Y and the wiring are directly connected, this specification may state that X and Y are directly electrically connected.

[0024] Furthermore, for example, it can be expressed as, "X, Y, the source (which may be rephrased as either the first or second terminal) and the drain (which may be rephrased as either the first or second terminal) of the transistor are electrically connected to each other, and are electrically connected in the order of X, transistor source, transistor drain, and Y." Or, "The source of the transistor is electrically connected to X, and the drain of the transistor is electrically connected to Y, and X, transistor source, transistor drain, and Y are electrically connected in this order." Or, "X is electrically connected to Y via the source and drain of the transistor, and X, transistor source, transistor drain, and Y are provided in this connection order." By specifying the order of connections in the circuit configuration using similar methods of expression as these examples, the source and drain of the transistor can be distinguished and their technical scope can be determined. Note that these methods of expression are examples and are not limited to these methods of expression. Here, X and Y are objects (for example, devices, elements, circuits, wiring, electrodes, terminals, conductive films, or layers).

[0025] Even if independent components are shown as electrically connected in a circuit diagram, a single component may possess the functions of multiple components. For example, if part of a wire also functions as an electrode, a single conductive film possesses both the functions of a wire and an electrode. Therefore, in this specification, "electrically connected" includes cases where a single conductive film possesses the functions of multiple components.

[0026] Furthermore, in this specification, "resistive element" can refer to, for example, a circuit element having a resistance value higher than 0Ω, or wiring with a resistance higher than 0Ω. Therefore, in this specification, "resistive element" includes wiring with a resistance value, transistors, diodes, or coils through which current flows between the source and drain. Therefore, the term "resistive element" may be replaced with the terms "resistor," "load," or "region having a resistance value." Conversely, the terms "resistor," "load," or "region having a resistance value" may be replaced with the term "resistive element." The resistance value can be, for example, preferably 1mΩ or more and 10Ω or less, more preferably 5mΩ or more and 5Ω or less, and even more preferably 10mΩ or more and 1Ω or less. Also, for example, 1Ω or more and 1 × 10 9 It may also be less than or equal to Ω.

[0027] Furthermore, in this specification, "capacitive element" may refer to, for example, a circuit element having a capacitance value higher than 0F, a region of wiring having a capacitance value higher than 0F, parasitic capacitance, or the gate capacitance of a transistor. Also, the terms "capacitive element," "parasitic capacitance," or "gate capacitance" may be replaced with the term "capacitance." Conversely, the term "capacitance" may be replaced with terms such as "capacitive element," "parasitic capacitance," or "gate capacitance." In addition, a "capacitance" (including "capacitances" with three or more terminals) has a configuration that includes an insulator and a pair of conductors sandwiching the insulator. Therefore, the term "pair of conductors" in "capacitance" may be replaced with "pair of electrodes," "pair of conductive regions," "pair of regions," or "pair of terminals." Also, the terms "one of the pair of terminals" and "the other of the pair of terminals" may be referred to as the first terminal and the second terminal, respectively. The capacitance value may be, for example, 0.05fF or more and 10pF or less. Alternatively, it may be, for example, 1pF or more and 10μF or less.

[0028] Furthermore, in this specification, a transistor has three terminals called the gate, source, and drain. The gate is a control terminal that controls the conduction state of the transistor. The two terminals that function as either the source or the drain are the input and output terminals of the transistor. Depending on the conductivity type of the transistor (n-channel type, p-channel type) and the potential applied to the three terminals of the transistor, one of the two input and output terminals becomes the source and the other becomes the drain. For this reason, in this specification, the terms source and drain may be interchangeable. Also, in this specification, when describing the connection relationships of a transistor, the notation "one of the source or drain" (or first electrode or first terminal) and "the other of the source or drain" (or second electrode or second terminal) is used. Depending on the structure of the transistor, in addition to the three terminals described above, there may be a back gate. In this case, in this specification, one of the gate or back gate of the transistor may be called the first gate, and the other of the gate or back gate of the transistor may be called the second gate. Furthermore, in the same transistor, the terms "gate" and "back gate" may be interchangeable. Furthermore, if a transistor has three or more gates, in this specification, each gate may be referred to as the first gate, the second gate, or the third gate.

[0029] For example, in this specification, a transistor with a multi-gate structure having two or more gate electrodes can be used as an example of a transistor. In a multi-gate structure, the channel formation regions are connected in series, resulting in a structure in which multiple transistors are connected in series. Therefore, the multi-gate structure can reduce the off-current and improve the transistor's breakdown voltage (improve reliability). Alternatively, the multi-gate structure allows for a voltage-current characteristic with a flat slope, where the current between the drain and source does not change much even when the voltage between the drain and source changes during operation in the saturation region. By utilizing this flat voltage-current characteristic, an ideal current source circuit or an active load with a very high resistance can be realized. As a result, a differential circuit or current mirror circuit with good characteristics can be realized.

[0030] Furthermore, even if a single circuit element is depicted in a circuit diagram, that element may actually comprise multiple circuit elements. For example, if one resistor is shown in a circuit diagram, it includes cases where two or more resistors are electrically connected in series. Similarly, if one capacitor is shown in a circuit diagram, it includes cases where two or more capacitors are electrically connected in parallel. Similarly, if one transistor is shown in a circuit diagram, it includes cases where two or more transistors are electrically connected in series and the gates of each transistor are electrically connected to each other. Likewise, if one switch is shown in a circuit diagram, it includes cases where the switch has two or more transistors, and these two or more transistors are electrically connected in series or in parallel, and the gates of each transistor are electrically connected to each other.

[0031] Furthermore, in this specification, the term "node" can be replaced with "terminal," "wiring," "electrode," "conductive layer," "conductor," or "impurity region," depending on the circuit configuration and device structure. Also, "terminal" or "wiring" can be replaced with "node."

[0032] Furthermore, in this specification, "voltage" and "potential" may be used interchangeably as appropriate. "Voltage" is the potential difference from a reference potential. For example, if the reference potential is the ground potential (earth potential), then "voltage" can be replaced with "potential." Note that the ground potential does not necessarily mean 0V. Also, potential is relative, and as the reference potential changes, the potential applied to the wiring, the potential applied to the circuit, and the potential output from the circuit also change.

[0033] Furthermore, in this specification, the terms "high-level potential" and "low-level potential" do not refer to specific potentials. For example, if two wires are both described as "functioning as wires that supply a high-level potential," the high-level potentials provided by each wire do not have to be equal. Similarly, if two wires are both described as "functioning as wires that supply a low-level potential," the low-level potentials provided by each wire do not have to be equal.

[0034] Furthermore, "electric current" refers to the phenomenon of electric charge movement (electrical conduction). For example, the statement "electrical conduction of positively charged elements is occurring" can be rephrased as "electrical conduction of negatively charged elements is occurring in the opposite direction." Therefore, in this specification, unless otherwise specified, "electric current" refers to the phenomenon of electric charge movement associated with the movement of carriers (electrical conduction). Examples of carriers include electrons, holes, anions, cations, and complex ions, and the carriers differ depending on the system through which the current flows (e.g., semiconductors, metals, electrolytes, and vacuum). Also, the "direction of current" in wiring, etc., is the direction in which positively charged carriers move and is expressed as a positive current quantity. In other words, the direction in which negatively charged carriers move is the opposite direction to the direction of the current and is expressed as a negative current quantity. Therefore, in this specification, unless otherwise specified regarding the positive or negative (or direction) of the current, the statement "current flows from element A to element B" can be rephrased as "current flows from element B to element A." Furthermore, the statement "current is input to element A" can be rephrased as "current is output from element A."

[0035] Furthermore, in this specification, ordinal numbers such as "first," "second," and "third" are used to avoid confusion of constituent elements. Therefore, they do not limit the number of constituent elements, nor do they limit the order of the constituent elements. For example, a constituent element referred to as "first" in one embodiment of this specification may be referred to as "second" in another embodiment or in the claims. Also, for example, a constituent element referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0036] Furthermore, in this specification, phrases indicating placement such as "above" and "below" are sometimes used for convenience to explain the positional relationship between components with reference to the drawings. Also, the positional relationship between components changes as appropriate depending on the direction in which each component is depicted. Therefore, the phrases explained in the specification are not limited to those described and can be appropriately rephrased depending on the situation. For example, the expression "insulator located on the upper surface of the conductor" can be rephrased as "insulator located on the lower surface of the conductor" by rotating the orientation of the drawing shown by 180 degrees.

[0037] Furthermore, the terms "above" and "below" do not limit the positional relationship of the components to being directly above or directly below and in direct contact. For example, the expression "electrode B on insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude cases where other components are included between insulating layer A and electrode B. Similarly, for example, the expression "electrode B above insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude cases where other components are included between insulating layer A and electrode B. Similarly, for example, the expression "electrode B below insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude cases where other components are included between insulating layer A and electrode B.

[0038] Furthermore, in this specification, terms such as "rows" and "columns" may be used to describe matrix-like arrangements of components and their positional relationships. The positional relationships between components change as appropriate depending on the direction in which each component is depicted. Therefore, the terminology used is not limited to that described in the specification and can be appropriately rephrased depending on the context. For example, the expression "row direction" can sometimes be rephrased as "column direction" by rotating the orientation of the drawing shown by 90 degrees.

[0039] Furthermore, in this specification, terms such as "film" and "layer" can be interchanged as needed. For example, the term "conductive layer" may be changed to the term "conductive film." Or, for example, the term "insulating film" may be changed to the term "insulating layer." Alternatively, depending on the circumstances, the terms "film" and "layer" can be omitted and replaced with other terms. For example, the terms "conductive layer" or "conductive film" may be changed to the term "conductor." Or, for example, the terms "insulating layer" or "insulating film" may be changed to the term "insulator."

[0040] Furthermore, in this specification, the terms "electrode," "wiring," and "terminal" do not functionally limit these components. For example, "electrode" may be used as part of "wiring," and vice versa. Moreover, the terms "electrode" or "wiring" include cases where multiple "electrodes" or "wiring" are formed as a single unit. Similarly, for example, "terminal" may be used as part of "wiring" or "electrode," and vice versa. Furthermore, the term "terminal" also includes cases where multiple "electrodes," "wiring," or "terminals" are formed as a single unit. Therefore, for example, an "electrode" can be part of "wiring" or a "terminal," and for example, a "terminal" can be part of "wiring" or an "electrode." In addition, the terms "electrode," "wiring," or "terminal" may be replaced with the term "region" in some cases.

[0041] Furthermore, in this specification, terms such as "wiring," "signal line," and "power line" can be interchanged depending on the circumstances or situation. For example, the term "wiring" may be changed to the term "signal line." Similarly, the term "wiring" may be changed to the term "power line." The reverse is also true; the terms "signal line" or "power line" may be changed to the term "wiring." The term "power line" may be changed to the term "signal line." Similarly, the terms "signal line" and similar may be changed to the term "power line." Furthermore, the term "potential" applied to the wiring may be changed to the term "signal" depending on the circumstances or situation. Similarly, the term "signal" may be changed to the term "potential."

[0042] In this specification, semiconductor impurities refer to elements other than the main components constituting the semiconductor layer. For example, elements with a concentration of less than 0.1 atomic percent are impurities. The presence of impurities can cause, for example, an increase in the defect level density of the semiconductor, a decrease in carrier mobility, and a decrease in crystallinity. When the semiconductor is an oxide semiconductor, impurities that alter the properties of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components. In particular, examples include hydrogen (including water), lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. When the semiconductor is a silicon layer, examples of impurities that alter the properties of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, and Group 15 elements (excluding oxygen and hydrogen).

[0043] In this specification, a switch refers to a device that has the function of controlling whether or not to allow current to flow by being in a conductive (on) state or a non-conductive (off) state. Alternatively, a switch refers to a device that has the function of selecting and switching the path through which current flows. Therefore, a switch may have two or more terminals for conducting current in addition to control terminals. Examples include electrical switches and mechanical switches. In other words, a switch is not limited to any particular type, as long as it can control current.

[0044] Examples of electrical switches include transistors (e.g., bipolar transistors, MOS transistors), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes, diode-connected transistors), or logic circuits combining these. When a transistor is used as a switch, the "conducting state" of the transistor refers to a state where, for example, the source and drain electrodes of the transistor can be considered electrically short-circuited, or a state where current can flow between the source and drain electrodes. Conversely, the "non-conducting state" of the transistor refers to a state where the source and drain electrodes of the transistor can be considered electrically disconnected. When a transistor is used simply as a switch, the polarity (conductivity type) of the transistor is not particularly limited.

[0045] One example of a mechanical switch is a switch using MEMS (Micro-Electro-Mechanical Systems) technology. This switch has mechanically movable electrodes, and it operates by controlling the conduction and non-conductivity through the movement of these electrodes.

[0046] In this specification, "parallel" means a state in which two lines are positioned at an angle of -10° or more and 10° or less. Therefore, the case of -5° or more and 5° or less is also included. Furthermore, "approximately parallel" or "roughly parallel" means a state in which two lines are positioned at an angle of -30° or more and 30° or less. Furthermore, "perpendicular" means a state in which two lines are positioned at an angle of 80° or more and 100° or less. Therefore, the case of 85° or more and 95° or less is also included. Furthermore, "approximately perpendicular" or "roughly perpendicular" means a state in which two lines are positioned at an angle of 60° or more and 120° or less. [Effects of the Invention]

[0047] According to one aspect of the present invention, a semiconductor device with reduced power consumption can be provided. Alternatively, according to one aspect of the present invention, a novel semiconductor device can be provided. Alternatively, according to one aspect of the present invention, an electronic device including a novel semiconductor device can be provided.

[0048] The effects of one aspect of the present invention are not limited to those listed above. The effects listed above do not preclude the existence of other effects. These other effects are those described below and not mentioned in this section. Those not mentioned in this section can be derived from the description in the specification or drawings, etc., by those skilled in the art, and can be appropriately extracted from these descriptions. One aspect of the present invention has at least one of the effects listed above and other effects. Therefore, one aspect of the present invention may, in some cases, not have the effects listed above. [Brief explanation of the drawing]

[0049] [Figure 1] Figures 1(A) through 1(C) are circuit diagrams showing examples of circuit configurations included in semiconductor devices. [Figure 2] Figure 2 is a schematic diagram showing the gate-source voltage-drain current characteristics of a transistor. [Figure 3] Figure 3 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 4]Figures 4(A) and 4(B) are circuit diagrams showing example configurations of circuits included in semiconductor devices. [Figure 5] Figure 5 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 6] Figure 6 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 7] Figure 7 is a circuit diagram showing an example of a semiconductor device configuration. [Figure 8] Figures 8(A) through 8(C) are circuit diagrams showing example configurations of circuits included in semiconductor devices. [Figure 9] Figures 9(A) and 9(B) are circuit diagrams showing example configurations of circuits included in semiconductor devices. [Figure 10] Figure 10 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 11] Figure 11 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 12] Figure 12 is a schematic cross-sectional view showing an example of the configuration of a semiconductor device. [Figure 13] Figures 13(A) to 13(C) are schematic cross-sectional diagrams showing examples of transistor configurations. [Figure 14] Figure 14 is a schematic cross-sectional view showing an example of the configuration of a semiconductor device. [Figure 15] Figures 15(A) and 15(B) are schematic cross-sectional diagrams showing examples of transistor configurations. [Figure 16] Figure 16 is a schematic cross-sectional diagram showing an example of a transistor configuration. [Figure 17] Figure 17(A) illustrates the classification of crystal structures, Figure 17(B) illustrates the XRD spectrum of crystalline IGZO, and Figure 17(C) illustrates the micro-electron diffraction pattern of crystalline IGZO. [Figure 18] Figure 18(A) is a perspective view showing an example of a semiconductor wafer, Figure 18(B) is a perspective view showing an example of a chip, and Figures 18(C) and 18(D) are perspective views showing examples of electronic components. [Figure 19]Figure 19 is a block diagram illustrating the CPU. [Figure 20] Figures 20(A) through 20(I) are perspective views or schematic diagrams illustrating an example of a product. [Modes for carrying out the invention]

[0050] In this specification, "metal oxide" refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), and oxide semiconductors (also called oxide semiconductors or simply OS). For example, if a metal oxide is included in the channel formation region of a transistor, that metal oxide may be referred to as an oxide semiconductor. In other words, if a metal oxide can constitute the channel formation region of a transistor having one or more amplification, rectification, and switching functions selected from those, that metal oxide can be referred to as a metal oxide semiconductor. Furthermore, when referring to an OS transistor, it can be rephrased as a transistor having a metal oxide or oxide semiconductor.

[0051] Furthermore, in this specification, metal oxides containing nitrogen may also be collectively referred to as metal oxides. Alternatively, metal oxides containing nitrogen may be called metal oxynitrides.

[0052] Furthermore, in this specification, the configurations shown in each embodiment can be appropriately combined with the configurations shown in other embodiments to form one aspect of the present invention. Also, if multiple configuration examples are shown within one embodiment, these configuration examples can be appropriately combined with each other.

[0053] Furthermore, any content described in one embodiment (even partial content) may be applied to, combined with, or substituted for at least one of the contents described in another embodiment (even partial content) and one or more other embodiments (even partial content).

[0054] The content described in the embodiments refers to the content described using various figures or the content described using text in the specification in each embodiment.

[0055] Furthermore, a diagram (even a part of it) described in one embodiment can be combined with another part of that diagram, another diagram (even a part of it) described in the same embodiment, and at least one diagram (even a part of it) described in one or more other embodiments to form even more diagrams.

[0056] The embodiments described herein are explained with reference to the drawings. However, it will be readily apparent to those skilled in the art that the embodiments can be implemented in many different ways, and their form and details can be modified in various ways without departing from the spirit and scope thereof. Therefore, the present invention is not to be interpreted as being limited to the contents described in the embodiments. In the configuration of the invention in the embodiments, the same reference numerals are used in common across different drawings for the same parts or parts having similar functions, and repeated explanations may be omitted. Also, in perspective views and the like, some components may be omitted in order to ensure clarity of the drawings.

[0057] In this specification, when the same reference numeral is used for multiple elements, and especially when it is necessary to distinguish them, the reference numeral may be accompanied by an identifying numeral such as "_1", "[n]", or "[m,n]". In addition, in drawings, etc., when an identifying numeral such as "_1", "[n]", or "[m,n]" is accompanied by a reference numeral, the identifying numeral may be omitted in this specification if it is not necessary to distinguish them.

[0058] Furthermore, in the drawings of this specification, the size, layer thickness, or area may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale. The drawings are schematic representations of ideal examples and are not limited to the shapes or values ​​shown in the drawings. For example, they may include variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing differences.

[0059] (Embodiment 1) This embodiment describes a semiconductor device according to one aspect of the present invention.

[0060] <Configuration Example 1> The circuit 100 shown in Figure 1(A) is an example of an inverter circuit (sometimes called a phase inversion circuit or NOT circuit), and is a semiconductor device according to one aspect of the present invention.

[0061] Circuit 100, as an example, includes transistor TrS and transistor TrO.

[0062] The transistor TrO is preferably an OS transistor, for example. In addition, the channel-forming region of the transistor TrO is more preferably an oxide containing one or more elements selected from indium, gallium, and zinc. Alternatively, an oxide containing one or more elements selected from indium, element M (for example, one or more elements selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium) and zinc may be used.

[0063] Furthermore, the transistor TrS is preferably a transistor containing silicon in the channel formation region (hereinafter referred to as a Si transistor). As silicon, for example, amorphous silicon (sometimes referred to as hydrogenated amorphous silicon), microcrystalline silicon, polycrystalline silicon (including low-temperature polycrystalline silicon (LTPS)), and single-crystal silicon can be used.

[0064] Furthermore, as at least one of transistors TrS and TrO, in addition to OS transistors and Si transistors, transistors in which Ge or the like is included in the channel formation region, transistors in which compound semiconductors such as zinc selenide (ZnSe), cadmium sulfide (CdS), gallium arsenide (GaAs), indium phosphide (InP), gallium nitride (GaN), and silicon germanium (SiGe) are included in the channel formation region, transistors in which carbon nanotubes are included in the channel formation region, and transistors in which organic semiconductors are included in the channel formation region may be used.

[0065] Si transistors can be configured as either n-channel or p-channel types depending on the type of impurity doped into the semiconductor layer. On the other hand, while n-type semiconductors can be fabricated using metal oxides containing indium (e.g., In oxide) or zinc (e.g., Zn oxide), p-type semiconductors are difficult to fabricate in terms of mobility and reliability. When configuring a CMOS circuit (sometimes called a complementary circuit) including OS transistors, it is preferable to use OS transistors as n-channel transistors and Si transistors as p-channel transistors. In this embodiment, it is assumed that a Si transistor is used for transistor TrS and an OS transistor is used for transistor TrO.

[0066] The transistor TrO shown in Figure 1(A) is, as an example, a transistor with gates above and below the channel, and has a first gate and a second gate. For convenience, as an example, the first gate is described as the gate (sometimes referred to as the front gate) and the second gate as the back gate, but the first gate and the second gate can be interchanged. Therefore, in this specification, the term "gate" can be replaced with the term "back gate". Similarly, the term "back gate" can be replaced with the term "gate". As a specific example, the connection configuration "the gate is electrically connected to the first wiring and the back gate is electrically connected to the second wiring" can be replaced with the connection configuration "the back gate is electrically connected to the first wiring and the gate is electrically connected to the second wiring".

[0067] Furthermore, a semiconductor device according to one aspect of the present invention does not depend on the connection configuration of the transistor's back gate. The transistor TrO shown in Figure 1(A) has a back gate, and although the connection configuration of the back gate is not shown, the electrical connection destination of the back gate can be determined at the design stage. For example, in a transistor having a back gate, the gate and the back gate may be electrically connected in order to increase the on-current of the transistor. That is, for example, the gate and the back gate of transistor TrO may be electrically connected. Also, for example, in a transistor having a back gate, in order to vary the threshold voltage of the transistor or to reduce the off-current of the transistor, wiring electrically connected to an external circuit may be provided, for example, to apply a fixed or variable potential to the back gate of the transistor by the external circuit. This also applies to transistors described in other parts of the specification or other drawings, not just those in Figure 1(A).

[0068] Furthermore, the semiconductor device according to one aspect of the present invention does not depend on the structure of the transistors included in the circuit 100. For example, the transistor TrO shown in Figure 1(A) may be configured without a back gate, as shown in Figure 1(B), that is, a single-gate transistor. Alternatively, some transistors may have a back gate configuration, while others may not. This also applies to transistors described in other parts of the specification or illustrated in other drawings, not just those shown in Figure 1(A).

[0069] Furthermore, in Figure 1(A), transistor TrO is shown as an n-channel transistor as an example, and transistor TrS is shown as a p-channel transistor as an example.

[0070] Furthermore, unless otherwise specified, transistors TrS and TrO include cases where they operate in the subthreshold region (i.e., in transistor TrS or transistor TrO, the gate-source voltage is lower than the threshold voltage, more preferably the drain current increases exponentially with respect to the gate-source voltage). That is, the gate voltage, source voltage, and drain voltage of each of the transistors described above include cases where they are appropriately biased to voltages within the range in which they operate in the subthreshold region.

[0071] Furthermore, in this specification, the subthreshold region refers to the region in a graph showing the gate voltage (Vg)-drain current (Id) characteristics of a transistor where the gate voltage is lower than the threshold voltage. Alternatively, the subthreshold region refers to the region where current flows due to carrier diffusion, deviating from the gradient dual-channel approximation (a model that only considers drift current). Alternatively, the subthreshold region refers to the region where the drain current increases exponentially with increasing gate voltage. Alternatively, the subthreshold region includes regions that can be considered as the regions described in each of the above explanations.

[0072] Also, the drain current when the transistor operates in the subthreshold region is referred to as the subthreshold current. The subthreshold current increases exponentially with respect to the gate voltage regardless of the drain voltage. In circuit operations using the subthreshold current, the influence of variations in the drain voltage can be reduced.

[0073] Here, FIG. 2 is a schematic diagram showing the characteristics of the source-drain current (Ids) and the gate-source voltage (Vgs) of each of the Si transistor and the OS transistor. In the characteristics of FIG. 2, the threshold voltages (V th ) of the Si transistor (described as Si FET in FIG. 2) and the OS transistor (described as OS FET in FIG. 2) are assumed to be equal. Also, for example, each transistor operates in the linear region when Vgs is greater than the sum of the source-drain voltage Vds and V th , and operates in the saturation region when Vgs is greater than V th and less than or equal to the sum of the source-drain voltage Vds and V th , and operates in the subthreshold region when Vgs is less than or equal to V th .

[0074] As shown in FIG. 2, the OS transistor can have a larger range of gate voltages operating in the subthreshold region compared to the Si transistor. Specifically, for example, when the threshold voltage of the OS transistor is V th , in the subthreshold region, circuit operations can be performed using gate voltages in the voltage range of V th - 1.0V or higher and V th or lower, or V th - 0.5V or higher and V th or lower.

[0075] For example, transistor TrO has a gate-source voltage lower than the threshold voltage, less than 1×10 -20 A, less than 1×10 -22 A, or less than 1×10 -24In some cases, a drain current of less than A per 1 μm channel width can be passed. Note that in this specification, the operation of transistor TrO in this region may be considered to be in the off state. Also, in this case, the current flowing through transistor TrO may be referred to as the off-leak current. Furthermore, in the region where the gate-source voltage of transistor TrO is near the threshold voltage of transistor TrO, the current is 1.0 × 10⁻¹⁰ -8 A or less, 1.0×10 -12 A or less, or 1.0 × 10 -15 In some cases, a drain current of less than A per 1 μm of channel width can be passed.

[0076] The first terminal of transistor TrS is electrically connected to wiring VDE, the second terminal of transistor TrS is electrically connected to the first terminal of transistor TrO and terminal OT, and the gate of transistor TrS is electrically connected to the gate of transistor TrO and terminal IT. In addition, the second terminal of transistor TrO is electrically connected to wiring VGE.

[0077] Terminal IT of circuit 100 functions as an input terminal in circuit 100, for example. Similarly, terminal OT of circuit 100 functions as an output terminal in circuit 100, for example.

[0078] The wiring VDE shown in Figure 1(A) functions, as an example, as wiring to supply a high power supply potential (sometimes referred to as a high-level potential) to circuit 100.

[0079] The wiring VGE shown in Figure 1(A) functions, as an example, as wiring to supply a low power supply potential (sometimes referred to as a low-level potential) to circuit 100. The low power supply potential here can be, for example, ground potential, 0V, or a negative potential.

[0080] Furthermore, the inverter circuit according to one embodiment of the present invention is not limited to the configuration shown in Figures 1(A) and 1(B). The configuration of the inverter circuit according to one embodiment of the present invention may be modified depending on the circumstances.

[0081] For example, in the circuit 100 shown in Figure 1(A), transistors TrS and TrO may each be multi-gate transistors containing two or more front gates. The circuit 100 shown in Figure 1(C) is an example of a circuit configuration in which transistors TrS and TrO of the circuit 100 in Figure 1(A) are multi-gate transistors, in which transistor TrS has two transistors, transistor TrSa and transistor TrSb, and transistor TrO has two transistors, transistor TrOa and transistor TrOb. By configuring the inverter circuit as shown in the circuit 100 in Figure 1(C), the off-current of transistors TrS and TrO can be further reduced.

[0082] <Example of operation 1> Next, an example of the operation of circuit 100 in Figure 1(A) will be described. Note that both transistor TrS and transistor TrO are assumed to operate in the subthreshold region.

[0083] Furthermore, the potential supplied by wiring VDE to the first terminal of transistor TrS is defined as the high-level potential. Here, the high-level potential is set to 0.45V as an example. Also, the potential supplied by wiring VGE to the second terminal of transistor TrO is defined as the low-level potential. Here, the low-level potential is set to 0V as an example.

[0084] Furthermore, a high-level potential (0.45V) or a low-level potential (0V) is input to terminal IT of circuit 100.

[0085] Furthermore, the potential difference obtained by subtracting the high-level potential from the low-level potential (-0.45V) is assumed to be within the gate-source voltage range of transistor TrS, which allows transistor TrS to operate in the subthreshold region. Also, the potential difference obtained by subtracting the low-level potential from the high-level potential (0.45V) is assumed to be within the gate-source voltage range of transistor TrO, which allows transistor TrO to operate in the subthreshold region.

[0086] First, let's consider the case where a high-level potential (0.45V) is input to terminal IT. Let V be the gate-source voltage in transistor TrS. SGS When V SGS Since = 0, transistor TrS is in the off state. Also, the gate-source voltage of transistor TrO is V OGS When V OGS Since the value is 0.45, transistor TrO operates in the subthreshold region.

[0087] Since transistor TrS is in the off state, there is no conduction between wiring VDE and terminal OT.

[0088] Furthermore, at this time, transistor TrO is in the subthreshold region, so the current I flowing between the source and drain of transistor TrO O1DS This becomes the subthreshold current. As a result, the subthreshold current of transistor TrO flows from terminal OT to wiring VGE via transistor TrO. Consequently, the potential of terminal OT becomes the low-level potential (0V) supplied by wiring VGE.

[0089] Next, consider the case where a low-level potential (0V) is input to terminal IT. In this case, the gate-source voltage V in transistor TrS is... SGS Since this becomes -0.45V, transistor TrS operates in the subthreshold region. Also, the gate-source voltage V in transistor TrO OGS V OGS Since this becomes 0, transistor TrO is in the off state.

[0090] Since transistor TrO is in the off state, there is no conduction between wiring VGE and terminal OT. Also, because transistor TrS is operating in the subthreshold region, the subthreshold current of transistor TrS flows from wiring VDE to terminal OT via transistor TrS. As a result, the potential of terminal OT becomes the high-level potential (0.45V) supplied by wiring VDE.

[0091] Also, at this time, transistor TrO is in the off state, so the current I flowing between the source and drain of transistor TrO O1DS This becomes the off-leak current (sometimes called the off-current or leakage current). In particular, when transistor TrO is an OS transistor, the ratio of the on-current to the off-leak current is large, so the off-leak current flowing between the first and second terminals of transistor TrO in the off state can be made sufficiently small.

[0092] <Configuration Example 2> The circuit 100A shown in Figure 3 is an example of a clocked inverter circuit and is a semiconductor device according to one aspect of the present invention.

[0093] Circuit 100A, as an example, includes transistor TrS1, transistor TrS2, transistor TrO1, and transistor TrO2.

[0094] For transistors TrS1 and TrS2, for example, transistors applicable to transistor TrS described in Configuration Example 1 can be used.

[0095] Furthermore, transistors TrO1 and TrO2 can be, for example, transistors that can be applied to transistor TrO as described in Configuration Example 1.

[0096] Furthermore, unless otherwise specified, each of the transistors TrS1, TrS2, TrO1, and TrO2 shall include operation in the subthreshold region.

[0097] The first terminal of transistor TrS1 is electrically connected to wiring VDE, the second terminal of transistor TrS1 is electrically connected to the first terminal of transistor TrS2, and the gate of transistor TrS1 is electrically connected to the gate of transistor TrO1 and terminal IT. The second terminal of transistor TrS2 is electrically connected to the first terminal of transistor TrO2 and terminal OT, and the gate of transistor TrS2 is electrically connected to terminal CT. The second terminal of transistor TrO2 is electrically connected to the first terminal of transistor TrO1, and the gate of transistor TrO2 is electrically connected to terminal CTB. The second terminal of transistor TrO1 is electrically connected to wiring VGE.

[0098] Terminal IT of circuit 100A functions as an input terminal in circuit 100A, for example. Similarly, terminal OT of circuit 100A functions as an output terminal in circuit 100A, for example.

[0099] The wiring VDE shown in Figure 3 functions, as an example, as wiring to supply a high power potential to circuit 100A.

[0100] The wiring VGE shown in Figure 3 functions, as an example, as wiring to provide a low power supply potential to circuit 100A. The low power supply potential here can be, for example, ground potential, 0V, or a negative potential.

[0101] As shown in Figure 3, the terminal CT is electrically connected to a wiring that provides a pulse voltage (sometimes called a variable potential). In particular, this pulse voltage can be, for example, a pulse voltage (clock signal) that periodically repeats between high and low levels of potential.

[0102] As an example, terminal CTB shown in Figure 3 is electrically connected to wiring that provides a potential that is the inverted logic of the potential applied to terminal CT. For example, when a high-level potential is applied to terminal CT, a low-level potential is applied to terminal CTB, and when a low-level potential is applied to terminal CT, a high-level potential is applied to terminal CTB.

[0103] <Example of operation 2> Next, an example of the operation of circuit 100A in Figure 3 will be described. Note that each of the transistors TrS1, TrS2, TrO1, and TrO2 is assumed to operate in the subthreshold region.

[0104] Furthermore, the potential supplied by wiring VDE to the first terminal of transistor TrS1 is defined as the high-level potential. Here, the high-level potential is set to 0.45V as an example. Also, the potential supplied by wiring VGE to the second terminal of transistor TrO1 is defined as the low-level potential. Here, the low-level potential is set to 0V as an example.

[0105] Furthermore, a pulse voltage that periodically alternates between high and low levels is input from terminal CT to the gate of transistor TrS2. For example, the high level potential here is 0.45V and the low level potential is 0V. Also, a potential that is the inverse of the potential applied to terminal CT is input from terminal CTB to the gate of transistor TrO2. That is, when a potential of 0.45V is applied from terminal CT to the gate of transistor TrS2, a potential of 0V is applied from terminal CTB to the gate of transistor TrO2, and when a potential of 0V is applied from terminal CT to the gate of transistor TrS2, a potential of 0.45V is applied from terminal CTB to the gate of transistor TrO2.

[0106] Furthermore, a high-level potential (0.45V) or a low-level potential (0V) is input to terminal IT of circuit 100A.

[0107] Furthermore, the potential difference obtained by subtracting the high-level potential from the low-level potential (-0.45V) is assumed to be within the gate-source voltage range of transistors TrS1 and TrS2, which operate in the subthreshold region. Also, the potential difference obtained by subtracting the low-level potential from the high-level potential (0.45V) is assumed to be within the gate-source voltage range of transistors TrO1 and TrO2, which operate in the subthreshold region.

[0108] Furthermore, when the gate-source voltage of transistors TrS1, TrS2, TrO1, and TrO2 is 0V, the transistors are considered to be in the off state.

[0109] First, consider the case where a high-level potential (0.45V) is applied to terminal CT and a low-level potential (0V) is applied to terminal CTB.

[0110] In this case, when a high-level potential (0.45V) is input to terminal IT, a high-level potential (0.45V) is applied to the gates of transistors TrS1 and TrO1. The gate-source voltage in transistor TrS1 is V S1GS When V S1GS Since = 0, transistor TrS1 is in the off state. Also, the gate-source voltage of transistor TrO1 is V O1GS When V O1GS Since the value is 0.45, transistor TrO1 operates in the subthreshold region.

[0111] Since transistor TrS1 is in the off state, there is no conduction between the wiring VDE and the first terminal of transistor TrS2. Also, a subthreshold current flows between the source and drain of transistor TrO1.

[0112] A low-level potential (0V) from terminal CTB is applied to the gate of transistor TrO2, and a low-level potential (0V) from wiring VGE is applied to the second terminal of transistor TrO2. The gate-source voltage in transistor TrO2 is V O2GS When V O2GS Since this becomes =0, transistor TrO2 is in the off state.

[0113] The gate of transistor TrS2 is supplied with a high-level potential (0.45V) from terminal CT. At this time, the potentials of the first and second terminals of transistor TrS2 are undefined, but it is considered that the potentials of the first and second terminals of transistor TrS2 are above the low-level potential (0V) supplied by wiring VGE and below the high-level potential (0.45V) supplied by wiring VDE. Therefore, the gate-source voltage of transistor TrS2 is V S2GS When V S2GS The threshold voltage is considered to be between 0V and 0.45V. Therefore, when the threshold voltage of transistor TrS2 is negative, transistor TrS2 is in the off state. In this example, it is assumed that transistor TrS2 is turned off when a high-level potential (0.45V) is applied to its gate.

[0114] As described above, transistors TrS1, TrS2, and TrO2 are in the off state, and transistor TrO1 is in the on state. Therefore, there is no conduction between terminal OT and wiring VDE, and there is no conduction between terminal OT and wiring VGE. Consequently, while a high-level potential (0.45V) is applied to terminal CT and a low-level potential (0V) is applied to terminal CTB, the potential of terminal OT does not change even if the potential of terminal IT changes (even if a high-level potential (0.45V) is input).

[0115] Furthermore, when a low-level potential (0V) is input to terminal IT, a low-level potential (0V) is applied to the gates of transistors TrS1 and TrO1. The gate-source voltage V in transistor TrS1 is...S1GS Since this becomes -0.45V, transistor TrS1 operates in the subthreshold region. Also, the gate-source voltage V in transistor TrO1 O1GS Since the voltage becomes 0V, transistor TrO1 is in the off state.

[0116] Since transistor TrO1 is in the off state, there is no conduction between the wiring VGE and the second terminal of transistor TrO2. Also, a subthreshold current flows between the source and drain of transistor TrS1.

[0117] A high-level potential (0.45V) from terminal CT is applied to the gate of transistor TrS2, and a high-level potential (0.45V) from wiring VDE is applied to the first terminal of transistor TrS2. The gate-source voltage V in transistor TrS2 is S2GS Since the voltage becomes 0V, transistor TrS2 is turned off.

[0118] The gate of transistor TrO2 is supplied with a low-level potential (0V) from terminal CTB. At this time, the potentials of the first and second terminals of transistor TrO2 are undefined, but it is considered that the potentials of the first and second terminals of transistor TrO2 are above the low-level potential (0V) supplied by wiring VGE and below the high-level potential (0.45V) supplied by wiring VDE. Therefore, the gate-source voltage V in transistor TrO2 is O2GS This is considered to be between -0.45V and 0V. Therefore, when the threshold voltage of transistor TrO2 is positive, transistor TrO2 is in the off state. In this example of operation, it is assumed that transistor TrO2 is turned off when a low-level potential (0V) is applied to its gate.

[0119] As described above, transistors TrS2, TrO1, and TrO2 are in the off state, so there is no conduction between terminal OT and wiring VDE, and there is no conduction between terminal OT and wiring VGE. Therefore, as long as a high-level potential (0.45V) is applied to terminal CT and a low-level potential (0V) is applied to terminal CTB, the potential of terminal OT will not change even if the potential of terminal IT changes (even if a high-level potential (0.45V) is input).

[0120] Next, consider the case where a low-level potential (0V) is applied to terminal CT and a high-level potential (0.45V) is applied to terminal CTB.

[0121] In this case, when a high-level potential (0.45V) is input to terminal IT, a high-level potential (0.45V) is applied to the gates of transistors TrS1 and TrO1. The gate-source voltage V in transistor TrS1 is... S1GS Since the voltage becomes 0V, transistor TrS1 is in the off state. Also, the gate-source voltage of transistor TrO1 is V O1GS When V O1GS Since the value is 0.45, transistor TrO1 operates in the subthreshold region.

[0122] Since transistor TrS1 is in the off state, there is conduction between the wiring VGE and the second terminal of transistor TrO2. Also, a subthreshold current flows through transistor TrO1.

[0123] The gate of transistor TrO2 is supplied with a high-level potential (0.45V) from terminal CTB, and the second terminal of transistor TrO2 is supplied with a low-level potential (0V) from wiring VGE. The gate-source voltage in transistor TrO2 is V O2GS Since this becomes 0.45V, transistor TrO2 operates in the subthreshold region.

[0124] A low-level potential (0V) from terminal CT is applied to the gate of transistor TrS2, and a low-level potential (0V) from wiring VGE is applied to the second terminal of transistor TrS2. At this time, there is no conduction between the first terminal of transistor TrS2 and wiring VDE, so when the potential of the first terminal of transistor TrS2 reaches the potential obtained by adding the threshold voltage of transistor TrS2 to the potential of the second terminal of transistor TrS2 (0V), transistor TrS2 turns off.

[0125] As described above, transistors TrS1 and TrS2 are in the off state, and both transistors TrO1 and TrO2 operate in the subthreshold region. Therefore, there is no conduction between terminal OT and wiring VDE, and a subthreshold current flows from terminal OT to wiring VGE. Consequently, the potential of terminal OT becomes a low-level potential (0V).

[0126] Furthermore, when a low-level potential (0V) is input to terminal IT, a low-level potential (0V) is applied to the gates of transistors TrS1 and TrO1. The gate-source voltage V in transistor TrS1 is... S1GS Since this becomes -0.45V, transistor TrS1 operates in the subthreshold region. Also, the gate-source voltage V in transistor TrO1 O1GS Since the voltage becomes 0V, transistor TrO1 is in the off state.

[0127] Since transistor TrO1 is in the off state, there is no conduction between the wiring VGE and the second terminal of transistor TrO2, and there is conduction between the wiring VDE and the first terminal of transistor TrS2. Also, a subthreshold current flows between the source and drain of transistor TrS1.

[0128] The gate of transistor TrS2 is supplied with a low-level potential (0V) from terminal CT, and the first terminal of transistor TrS2 is supplied with a high-level potential (0.45V) from wiring VDE. The gate-source voltage in transistor TrS2 is V S2GS Since the voltage becomes -0.45V, the subthreshold current flows through transistor TrS2.

[0129] A high-level potential (0.45V) from terminal CTB is applied to the gate of transistor TrO2, and a high-level potential (0.45V) from wiring VDE is applied to the first terminal of transistor TrO2. At this time, there is no conduction between the first terminal of transistor TrO2 and wiring VGE, so when the potential of the second terminal of transistor TrO2 reaches the potential obtained by subtracting the threshold voltage of transistor TrO2 from the potential of the first terminal of transistor TrO2 (0.45V), transistor TrO2 turns off.

[0130] As described above, both transistors TrS1 and TrS2 are operating in the subthreshold region, and transistors TrO1 and TrO2 are in the off state. Therefore, there is no conduction between terminal OT and wiring VGE, and a subthreshold current flows from wiring VDE to terminal OT. Consequently, the potential of terminal OT becomes a high-level potential (0.45V).

[0131] Based on the above, the relationship between the potentials applied to terminals IT, CT, and CTB, respectively, and the potential output from terminal OT in circuit 100A in Figure 3 is as shown in the following table. In the following table, when a high-level potential (0.45V) is applied to terminal CT and a low-level potential (0V) is applied to terminal CTB, the potential of terminal OT is indicated as undefined.

[0132] [Table 1]

[0133] <Configuration Example 3> The circuit 100B shown in Figure 4(A) is an example of a NAND circuit and is a semiconductor device according to one aspect of the present invention.

[0134] Circuit 100B, as an example, includes transistors TrS3, TrS4, TrO3, TrO4, TrO5, and TrO6.

[0135] For transistors TrS3 and TrS4, for example, transistors applicable to transistor TrS described in Configuration Example 1 can be used.

[0136] Furthermore, transistors TrO3 through TrO6 can be, for example, transistors that can be applied to transistor TrO as described in Configuration Example 1.

[0137] Furthermore, unless otherwise specified, each of the transistors TrS3, TrS4, and TrO3 through TrO6 shall include operation in the subthreshold region.

[0138] The first terminal of transistor TrS3 is electrically connected to wiring VDE1, and the gate of transistor TrS3 is electrically connected to the gate of transistor TrO3, the gate of transistor TrO6, and terminal IT1. The first terminal of transistor TrS4 is electrically connected to wiring VDE2, and the gate of transistor TrS4 is electrically connected to the gate of transistor TrO4, the gate of transistor TrO5, and terminal IT2. The second terminal of transistor TrS3 is electrically connected to the first terminal of transistor TrO3, the second terminal of transistor TrS4, the first terminal of transistor TrO4, and terminal OT. The second terminal of transistor TrO3 is electrically connected to the first terminal of transistor TrO5. The second terminal of transistor TrO4 is electrically connected to the first terminal of transistor TrO6. The second terminal of transistor TrO5 is electrically connected to wiring VGE1. The second terminal of transistor TrO6 is electrically connected to wiring VGE2.

[0139] Terminals IT1 and IT2 of circuit 100B function, for example, as input terminals in circuit 100B. Similarly, terminal OT of circuit 100B functions, for example, as an output terminal in circuit 100B.

[0140] Wiring VDE1 shown in Figure 4(A) functions, for example, as wiring to supply a high power supply potential to circuit 100B. Similarly, wiring VDE2 shown in Figure 4(A) functions, for example, as wiring to supply a high power supply potential to circuit 100B. It is preferable that the potentials supplied by wiring VDE1 and wiring VDE2 are equal. However, depending on the circumstances, the potentials supplied by wiring VDE1 and wiring VDE2 may be different.

[0141] Wiring VGE1 shown in Figure 4(A) functions, for example, as wiring to provide a low power supply potential to circuit 100B. Similarly, wiring VGE2 shown in Figure 4(A) functions, for example, as wiring to provide a low power supply potential to circuit 100B. It is preferable that the potentials provided by wiring VGE1 and wiring VGE2 are equal. In this case, the low power supply potentials provided by wiring VGE1 and wiring VGE2 can be, for example, ground potential, 0V, or a negative potential. However, depending on the situation, the potentials provided by wiring VGE1 and wiring VGE2 may be different.

[0142] Furthermore, the NAND circuit according to one embodiment of the present invention is not limited to the configuration shown in Figure 4(A). The configuration of the NAND circuit according to one embodiment of the present invention may be modified depending on the circumstances.

[0143] For example, transistors TrS3 and TrS4 in circuit 100B shown in Figure 4(A) may be multi-gate transistors that include two or more front gates. Circuit 100B shown in Figure 4(B) is an example of a circuit configuration in which transistors TrS3 and TrS4 in circuit 100B of Figure 4(A) are each multi-gate transistors, with transistor TrS3 having two transistors, TrS3a and TrS3b, and transistor TrS4 having two transistors, TrS4a and TrS4b. By configuring the NAND circuit as shown in circuit 100B in Figure 4(B), the off-current of transistors TrS3 and TrS4 can be further reduced.

[0144] <Example of operation 3> Next, an example of the operation of circuit 100B in Figure 4(A) will be described. Note that each of transistors TrS3, TrS4, and TrO3 through TrO6 will be considered to operate in the subthreshold region.

[0145] Furthermore, the potential supplied by wiring VDE1 to the first terminal of transistor TrS3, and the potential supplied by wiring VDE2 to the first terminal of transistor TrS4, are both defined as high-level potentials. For example, the high-level potential here is 0.45V. Also, the potential supplied by wiring VGE1 to the second terminal of transistor TrO5, and the potential supplied by wiring VGE2 to the second terminal of transistor TrO6, are both defined as low-level potentials. For example, the low-level potential here is 0V.

[0146] Additionally, a high-level potential (0.45V) or a low-level potential (0V) is input to terminal IT1 of circuit 100B. Similarly, a high-level potential (0.45V) or a low-level potential (0V) is input to terminal IT2 of circuit 100B.

[0147] Furthermore, the potential difference obtained by subtracting the high-level potential from the low-level potential (-0.45V) is assumed to be within the range of gate-source voltages of transistors TrS3 and TrS4, which operate in the subthreshold region. Also, the potential difference obtained by subtracting the low-level potential from the high-level potential (0.45V) is assumed to be within the range of gate-source voltages of transistors TrO3 through TrO6, which operate in the subthreshold region.

[0148] Furthermore, when the gate-source voltage of transistors TrS3, TrS4, TrO3 through TrO6 is 0V, the transistor is considered to be in the off state.

[0149] First, consider the case where a low-level potential (0V) is input to terminals IT1 and IT2, respectively. The gate-source voltage in transistor TrS3 is V S3GS When V S3GS Since the value is -0.45, transistor TrS3 operates in the subthreshold region. Also, the gate-source voltage of transistor TrO6 is V O6GS When V O6GSSince = 0, transistor TrO6 is in the off state. Also, the gate-source voltage of transistor TrO5 is V O5GS When V O5GS Since = 0, transistor TrO5 is in the off state. Also, the gate-source voltage of transistor TrS4 is V S4GS When V O4GS Since the value is -0.45, transistor TrS4 operates in the subthreshold region.

[0150] Furthermore, although the potential of the second terminal of transistor TrO3 is undefined at this time, it is considered that the potential of the second terminal of transistor TrO3 is above the low-level potential (0V) provided by either wiring VGE1 or wiring VGE2, and below the high-level potential (0.45V) provided by either wiring VDE1 or wiring VDE2. For this reason, the gate-source voltage in transistor TrO3 is set to V O3GS When V O3GS The threshold voltage is considered to be between -0.45V and 0V. Therefore, when the threshold voltage of transistor TrO3 is positive, transistor TrO3 is in the off state. In this example, it is assumed that transistor TrO3 is turned off when a low-level potential (0V) is applied to its gate.

[0151] Similarly, although the potential of the second terminal of transistor TrO4 is undefined, it is considered that the potential of the second terminal of transistor TrO4 is above the low-level potential (0V) provided by either wiring VGE1 or wiring VGE2, and below the high-level potential (0.45V) provided by either wiring VDE1 or wiring VDE2. Therefore, the gate-source voltage in transistor TrO4 is V O4GS When V O4GS This is considered to be between -0.45V and 0V. Therefore, when the threshold voltage of transistor TrO4 is positive, transistor TrO4 is in the off state. In this example of operation, it is assumed that transistor TrO4 is turned off when a low-level potential (0V) is applied to its gate.

[0152] As described above, transistors TrO3 and TrO4 are in the off state, so there is no conduction between terminal OT and wire VGE1, and between terminal OT and wire VGE2. Also, since subthreshold current flows between the source and drain of transistors TrS3 and TrS4, the potential of terminal OT becomes a high-level potential (0.45V).

[0153] Next, consider the case where a low-level potential (0V) is input to terminal IT1 and a high-level potential (0.45V) is input to terminal IT2. The gate-source voltage V in transistor TrS3 is... S3GS Since the voltage is -0.45V, transistor TrS3 operates in the subthreshold region. Also, the gate-source voltage V in transistor TrO6 O6GS Since the voltage becomes 0V, transistor TrO6 is in the off state. Also, the gate-source voltage V in transistor TrO5 O5GS Since this becomes 0.45V, transistor TrO5 operates in the subthreshold region. Also, the gate-source voltage V in transistor TrS4 S4GS Since the voltage becomes 0V, transistor TrS4 is in the off state.

[0154] Furthermore, at this time, a low-level potential (0V) from terminal IT1 is applied to the gate of transistor TrO3, and a low-level potential (0V) from wiring VGE1 is applied to the second terminal of transistor TrO3. The gate-source voltage in transistor TrO3 is V O3GS When V O3GS Since this becomes =0, transistor TrO3 is in the off state.

[0155] Furthermore, although the potential of the second terminal of transistor TrO4 is undefined, it is considered that the potential of the second terminal of transistor TrO4 is above the low-level potential (0V) provided by either wiring VGE1 or wiring VGE2, and below the high-level potential (0.45V) provided by either wiring VDE1 or wiring VDE2. Therefore, the gate-source voltage V in transistor TrO4 isO4GS This is considered to be between -0.45V and 0V. Therefore, when the threshold voltage of transistor TrO4 is positive, transistor TrO4 is in the off state.

[0156] As described above, transistors TrS4, TrO3, TrO4, and TrO6 are in the off state, so there is no conduction between terminal OT and wire VDE2, between terminal OT and wire VGE1, and between terminal OT and wire VGE2. Also, a subthreshold current flows between the source and drain of transistor TrS3, so the potential of terminal OT is at a high level potential (0.45V). Although a subthreshold current also flows between the source and drain of transistor TrO5, since transistor TrO3 is in the off state, no current can be assumed to flow from terminal OT to wire VGE1.

[0157] Next, consider the case where a high-level potential (0.45V) is input to terminal IT1 and a low-level potential (0V) is input to terminal IT2. The gate-source voltage V in transistor TrS3 is... S3GS Since the voltage becomes 0V, transistor TrS3 is in the off state. Also, the gate-source voltage V in transistor TrO6 O6GS Since the voltage is 0.45V, transistor TrO6 operates in the subthreshold region. Also, the gate-source voltage V in transistor TrO5 O5GS Since the voltage becomes 0V, transistor TrO5 is in the off state. Also, the gate-source voltage V in transistor TrS4 S4GS Since the voltage becomes -0.45V, transistor TrS4 operates in the subthreshold region.

[0158] Furthermore, at this time, a low-level potential (0V) from terminal IT2 is applied to the gate of transistor TrO4, and a low-level potential (0V) from wiring VGE2 is applied to the second terminal of transistor TrO4. The gate-source voltage in transistor TrO4 is V O4GS When V O4GSSince this becomes =0, transistor TrO4 is in the off state.

[0159] Furthermore, although the potential of the second terminal of transistor TrO3 is undefined, it is considered that the potential of the second terminal of transistor TrO3 is above the low-level potential (0V) provided by either wiring VGE1 or wiring VGE2, and below the high-level potential (0.45V) provided by either wiring VDE1 or wiring VDE2. Therefore, the gate-source voltage V in transistor TrO3 is O3GS This is considered to be between -0.45V and 0V. Therefore, when the threshold voltage of transistor TrO3 is positive, transistor TrO3 is in the off state. In this example, it is assumed that transistor TrO3 is turned off when a low-level potential (0V) is applied to its gate.

[0160] As described above, transistors TrS3, TrO3 through TrO5 are in the off state, so there is no conduction between terminal OT and wire VDE1, terminal OT and wire VGE1, and terminal OT and wire VGE2. Also, a subthreshold current flows between the source and drain of transistor TrS4, so the potential of terminal OT is at a high level (0.45V). Although a subthreshold current also flows between the source and drain of transistor TrO6, since transistor TrO4 is in the off state, no current flows from terminal OT to wire VGE2.

[0161] Next, consider the case where a high-level potential (0.45V) is input to terminals IT1 and IT2, respectively. The gate-source voltage V in transistor TrS3 S3GS Since the voltage becomes 0V, transistor TrS3 is in the off state. Also, the gate-source voltage V in transistor TrO6 O6GS Since the voltage is 0.45V, transistor TrO6 operates in the subthreshold region. Also, the gate-source voltage V in transistor TrO5 O5GSSince this becomes 0.45V, transistor TrO5 operates in the subthreshold region. Also, the gate-source voltage V in transistor TrS4 S4GS Since the voltage becomes 0V, transistor TrS4 is in the off state.

[0162] Furthermore, at this time, a high-level potential (0.45V) from terminal IT1 is applied to the gate of transistor TrO3, and a low-level potential (0V) from wiring VGE1 is applied to the second terminal of transistor TrO3. Gate-source voltage V in transistor TrO3 O3GS Since the voltage is 0.45V, transistor TrO3 operates in the subthreshold region.

[0163] Similarly, the gate of transistor TrO4 is supplied with a high-level potential (0.45V) from terminal IT2, and the second terminal of transistor TrO4 is supplied with a low-level potential (0V) from wiring VGE2. The gate-source voltage in transistor TrO4 is V O4GS Since the voltage is 0.45V, transistor TrO4 operates in the subthreshold region.

[0164] As described above, transistors TrS3 and TrS4 are in the off state, so there is no conduction between terminal OT and wire VDE1, and between terminal OT and wire VDE2. Also, since a subthreshold current flows between the source and drain of transistors TrO3 through TrO6, the potential of terminal OT is at a low level (0V).

[0165] Based on the above, the relationship between the potentials applied to terminals IT1 and IT2, respectively, and the potential output from terminal OT in circuit 100B of Figure 4(A) is as shown in the following table.

[0166] [Table 2]

[0167] In particular, consider the case where transistors TrO3 through TrO6 are OS transistors. By passing a subthreshold current between the source and drain of each of the transistors TrO3 through TrO6, power consumption can be reduced compared to transistors operating in the saturation region. Also, when any of the transistors TrO3 through TrO6 are in the off state, the off-leak current flowing between the source and drain of that transistor is smaller compared to that of an Si transistor, thus reducing power consumption due to the off-leak current.

[0168] <Configuration Example 4> The circuit 100C shown in Figure 5 is an example of a NOR circuit and is a semiconductor device according to one aspect of the present invention.

[0169] Circuit 100C, as an example, includes transistors TrS5, TrS6, TrO7, and TrO8.

[0170] For transistors TrS5 and TrS6, for example, transistors applicable to transistor TrS described in Configuration Example 1 can be used.

[0171] Furthermore, transistors TrO7 and TrO8 can be, for example, transistors that can be applied to transistor TrO as described in Configuration Example 1.

[0172] Furthermore, unless otherwise specified, each of the transistors TrS5, TrS6, TrO7, and TrO8 is assumed to operate in the subthreshold region.

[0173] The first terminal of transistor TrS5 is electrically connected to wiring VDE, the second terminal of transistor TrS5 is electrically connected to the first terminal of transistor TrS6, and the gate of transistor TrS5 is electrically connected to the gate of transistor TrO7 and terminal IT1. The second terminal of transistor TrS6 is electrically connected to the first terminal of transistor TrO7, the first terminal of transistor TrO8 and terminal OT, and the gate of transistor TrS6 is electrically connected to the gate of transistor TrO8 and terminal IT2. The second terminal of transistor TrO7 is electrically connected to wiring VGE1, and the second terminal of transistor TrO8 is electrically connected to wiring VGE2.

[0174] Terminals IT1 and IT2 of circuit 100C function as input terminals in circuit 100C, for example. Similarly, terminal OT of circuit 100C functions as an output terminal in circuit 100C, for example.

[0175] The wiring VDE shown in Figure 5 functions, as an example, as wiring to supply a high power supply potential to circuit 100C.

[0176] Furthermore, the wiring VGE1 shown in Figure 5 functions, for example, as wiring to provide a low power supply potential to circuit 100C. Similarly, the wiring VGE2 shown in Figure 5 functions, for example, as wiring to provide a low power supply potential to circuit 100C. It is preferable that the potentials provided by wiring VGE1 and wiring VGE2 are equal. In this case, the low power supply potentials provided by wiring VGE1 and wiring VGE2 can be, for example, ground potential, 0V, or a negative potential. Also, depending on the situation, the potentials provided by wiring VGE1 and wiring VGE2 may be different.

[0177] <Example of operation 4> Next, an example of the operation of circuit 100C in Figure 5 will be described. Note that transistors TrS5, TrS6, TrO7, and TrO8 each include cases where they operate in the subthreshold region.

[0178] Furthermore, the potential supplied by wiring VDE to the first terminal of transistor TrS5 is defined as the high-level potential. Here, the high-level potential is set to 0.45V as an example. Also, the potential supplied by wiring VGE1 to the second terminal of transistor TrO7, and the potential supplied by wiring VGE2 to the second terminal of transistor TrO8, are defined as the low-level potentials. Here, the low-level potential is set to 0V as an example.

[0179] Additionally, a high-level potential (0.45V) or a low-level potential (0V) is input to terminal IT1 of circuit 100C. Similarly, a high-level potential (0.45V) or a low-level potential (0V) is input to terminal IT2 of circuit 100C.

[0180] Furthermore, the potential difference obtained by subtracting the high-level potential from the low-level potential (-0.45V) is assumed to be within the gate-source voltage range of transistors TrS5 and TrS6, which operate in the subthreshold region. Also, the potential difference obtained by subtracting the low-level potential from the high-level potential (0.45V) is assumed to be within the gate-source voltage range of transistors TrO7 and TrO8, which operate in the subthreshold region.

[0181] Furthermore, when the gate-source voltage of transistors TrS5, TrS6, TrO7, and TrO8 is 0V, the transistors are considered to be in the off state.

[0182] First, consider the case where a low-level potential (0V) is input to terminals IT1 and IT2, respectively. The gate-source voltage in transistor TrS5 is V S5GS When V S5GSSince the value is -0.45, transistor TrS5 operates in the subthreshold region. Also, the gate-source voltage of transistor TrO7 is V O7GS When V O7GS Since = 0, transistor TrO7 is in the off state. Also, the gate-source voltage of transistor TrO8 is V O8GS When V O8GS Since this becomes 0, transistor TrO8 is in the off state.

[0183] Furthermore, at this time, a low-level potential (0V) from terminal IT2 is applied to the gate of transistor TrS6, and a high-level potential (0.45V) from wiring VDE is applied to the first terminal of transistor TrS6. The gate-source voltage in transistor TrS6 is V S6GS When V S6GS Since the value is -0.45, transistor TrS6 operates in the subthreshold region.

[0184] As described above, transistors TrO7 and TrO8 are in the off state, so there is no conduction between terminal OT and wire VGE1, and between terminal OT and wire VGE2. Also, since subthreshold current flows between the source and drain of transistors TrS5 and TrS6, the potential of terminal OT becomes a high-level potential (0.45V).

[0185] Next, consider the case where a low-level potential (0V) is input to terminal IT1 and a high-level potential (0.45V) is input to terminal IT2. The gate-source voltage V in transistor TrS5 is... S5GS Since the voltage is -0.45V, transistor TrS5 operates in the subthreshold region. Also, the gate-source voltage V in transistor TrO7 O7GS Since the voltage becomes 0V, transistor TrO7 is in the off state. Also, the gate-source voltage V in transistor TrO8 O8GS Since the voltage is 0.45V, transistor TrO8 operates in the subthreshold region.

[0186] Also, at this time, a high-level potential (0.45 V) from the terminal IT2 is applied to the gate of the transistor TrS6, and a high-level potential (0.45 V) from the wiring VDE is applied to the first terminal of the transistor TrS6. Therefore, the gate-source voltage V S6GS in the transistor TrS6 becomes 0 V, so the transistor TrS6 is in the off state.

[0187] From the above, since the transistor TrS6 and the transistor TrO7 are in the off state, the between the terminal OT and the wiring VGE1 and between the terminal OT and the wiring VGE2 are in the non-conducting state, respectively. Also, since a subthreshold current flows between the source and drain of the transistor TrO8, the potential of the terminal OT becomes a low-level potential (0 V). Although a subthreshold current also flows between the source and drain of the transistor TrS5, since the transistor TrS6 is in the off state, it can be assumed that no current flows from the wiring VDE to the terminal OT.

[0188] Next, consider the case where a high-level potential (0.45 V) is input to the terminal IT1 and a low-level potential (0 V) is input to the terminal IT2. The gate-source voltage V S5GS in the transistor TrS5 becomes 0 V, so the transistor TrS5 is in the off state. Also, the gate-source voltage V O7GS in the transistor TrO7 becomes 0.45 V, so the transistor TrO7 operates in the subthreshold region. Also, the gate-source voltage V O8GS in the transistor TrO8 becomes 0 V, so the transistor TrO8 is in the off state.

[0189] Furthermore, a low-level potential (0V) from terminal IT2 is applied to the gate of transistor TrS6. At this time, the connection between the first terminal of transistor TrS6 and the wiring VDE is non-conductive. Therefore, when the potential of the first terminal of transistor TrO6 reaches the potential obtained by adding the threshold voltage of transistor TrO6 to the potential of the second terminal of transistor TrO6 (0V), transistor TrO6 turns off.

[0190] As described above, transistors TrS5, TrS6, and TrO8 are in the off state, so there is no conduction between terminal OT and wiring VDE, and between terminal OT and wiring VGE2. Also, since a subthreshold current flows between the source and drain of transistor TrO7, the potential of terminal OT is at a low level (0V). Note that even if a subthreshold current flows between the source and drain of transistor TrS6, or if transistor TrS6 is in the off state, since transistor TrS5 is in the off state, no current can be expected to flow from wiring VDE to terminal OT.

[0191] Next, consider the case where a high-level potential (0.45V) is input to terminals IT1 and IT2, respectively. The gate-source voltage V in transistor TrS5 S5GS Since the voltage becomes 0V, transistor TrS5 is in the off state. Also, the gate-source voltage V in transistor TrO7 O7GS Since the voltage is 0.45V, transistor TrO7 operates in the subthreshold region. Also, the gate-source voltage V in transistor TrO8 O8GS Since the voltage is 0.45V, transistor TrO8 operates in the subthreshold region.

[0192] Furthermore, at this time, a high-level potential (0.45V) from terminal IT2 is applied to the gate of transistor TrS6. Although the potential of the first terminal of transistor TrS6 is undefined, it is considered that the potential of the first terminal of transistor TrS6 is above the low-level potential (0V) provided by either wiring VGE1 or wiring VGE2, and below the high-level potential (0.45V) provided by wiring VDE. Therefore, the gate-source voltage V in transistor TrS6 is S6GS The threshold voltage is considered to be between 0V and 0.45V. Therefore, when the threshold voltage of transistor TrS6 is negative, transistor TrS6 is in the off state. In this example, it is assumed that transistor TrS6 is turned off when a high-level potential (0.45V) is applied to its gate.

[0193] As described above, transistors TrS5 and TrS6 are in the off state, so there is no conduction between terminal OT and wiring VDE. Also, since subthreshold current flows between the source and drain of transistors TrO7 and TrO8, the potential of terminal OT becomes a low level potential (0V).

[0194] Based on the above, the relationship between the potentials applied to terminals IT1 and IT2 and the potential output from terminal OT in circuit 100C of Figure 5 is as shown in the following table.

[0195] [Table 3]

[0196] In particular, consider the case where transistors TrO7 and TrO8 are OS transistors. By passing a subthreshold current between the source and drain of each transistor, TrO7 or TrO8, power consumption can be reduced compared to transistors operating in the saturation region. Also, when transistors TrO7 or TrO8 are in the off state, the off-leak current flowing between their source and drain is smaller compared to Si transistors, thus reducing power consumption due to off-leak current.

[0197] Furthermore, the circuit configurations described in this embodiment can be combined with each other as appropriate.

[0198] Furthermore, this embodiment can be appropriately combined with other embodiments shown herein.

[0199] (Embodiment 2) This embodiment describes an example configuration of a switch including a transistor and a bootstrap circuit for stably operating the switch.

[0200] The logic circuit described in Embodiment 1 uses a transistor that operates in both the subthreshold region and the off state where an off-leak current smaller than the subthreshold current flows. Therefore, this logic circuit can reduce power consumption compared to a logic circuit that includes a transistor operating in the saturation region.

[0201] Incidentally, the voltage input to terminal IT, terminal CT, and terminal CTB, as described in the logic circuit of Embodiment 1, are within the voltage range required to operate the transistors included in the logic circuit in the subthreshold region. In other words, the voltage input to terminal IT, terminal CT, and terminal CTB are lower than the voltages required to operate the transistors in the linear region and the saturation region.

[0202] Therefore, when a circuit is configured that includes a switch containing a transistor, such as the logic circuit of Embodiment 1, it is preferable to operate the transistor in the linear region or the saturation region in order to stably drive the transistor included in the switch. Conversely, if a voltage in the range that operates the transistor in the subthreshold region is applied to the transistor, the switch may not be able to reach a sufficiently on state or a sufficiently off state.

[0203] In other words, when driving the logic circuit and the switch in Embodiment 1, it is necessary to apply different voltages to each. Alternatively, it is necessary to boost the voltage applied to the switch within the operating range of the subthreshold region using a bootstrap circuit or the like.

[0204] <Example Configuration> The circuit 150 shown in Figure 6 is an example of a bootstrap circuit that boosts the voltage supplied to the transistor OSW included in the switch. The circuit 150 includes transistors TrS11 to TrS13, transistors TrO14 to TrO20, and transistor OSW.

[0205] For transistors TrS11 to TrS13, for example, transistors applicable to transistor TrS described in Configuration Example 1 of Embodiment 1 can be used.

[0206] Furthermore, for transistors TrS11 to TrS13, for example, p-channel transistors with an SOI (Silicon On Insulator) structure can be used. Also, not all of transistors TrS11 to TrS13, but at least one may be a p-channel transistor with an SOI structure.

[0207] Furthermore, transistors TrO14 through TrO20 can be, for example, transistors that can be applied to transistor TrO as described in Configuration Example 1.

[0208] Also, each of transistors TrS11 to TrS13 and transistors TrO14 to TrO20 is assumed to operate in the subthreshold region unless otherwise specified.

[0209] The first terminal of transistor TrS11 is electrically connected to wiring VDE11, the second terminal of transistor TrS11 is electrically connected to the first terminal of transistor TrO14 and the gate of transistor TrS13, and the gate of transistor TrS11 is electrically connected to wiring CK and the gate of transistor TrO14. The first terminal of transistor TrS12 is electrically connected to wiring VDE12, the gate of transistor TrS12 is electrically connected to the first terminal of transistor TrS13, the first terminal of transistor TrO19, the gates of transistors TrO16 and TrO17, and the gate of transistor OSW, and the second terminal of transistor TrS12 is electrically connected to the back gate of transistor TrS12, the second terminal of transistor TrS13, the back gate of transistor TrS13, and the first terminal of capacitor CN. The gate of transistor TrO19 is electrically connected to wiring VDE13, and the second terminal of transistor TrO19 is electrically connected to the first terminal of transistor TrO20. The gate of transistor TrO20 is electrically connected to wiring CKB, and the second terminal of transistor TrO20 is electrically connected to wiring VGE13.

[0210] The first terminal of transistor TrO15 is electrically connected to the second terminal of transistor TrO14, the first terminal of transistor TrO16, the back gate of transistor TrO16, and the second terminal of capacitor CN. The gate of transistor TrO15 is electrically connected to wiring CKB and the gate of transistor TrO18. The second terminal of transistor TrO15 is electrically connected to wiring VGE11. The first terminal of transistor TrO17 is electrically connected to the second terminal of transistor TrO16, the first terminal of transistor OSW, and terminal IT. The second terminal of transistor TrO17 is electrically connected to the first terminal of transistor TrO18 and the back gate of transistor OSW. The second terminal of transistor TrO18 is electrically connected to wiring VGE12. The second terminal of transistor OSW is electrically connected to terminal OT.

[0211] Terminal IT of circuit 150 functions as an input terminal in circuit 150 as an example. Also, terminal OT of circuit 150 functions as an output terminal in circuit 150 as an example. That is, terminal IT of circuit 150 corresponds to one of the pair of terminals of the switch including transistor OSW, and terminal OT of circuit 150 corresponds to the other of the pair of terminals of the switch including transistor OSW.

[0212] Wiring VDE11 functions as a wiring for supplying a high power supply potential (which may be referred to as a high level potential) to circuit 150 as an example. Also, wiring VDE12 functions as a wiring for supplying a high power supply potential to circuit 150 as an example. Also, wiring VDE13 functions as a wiring for supplying a high power supply potential to circuit 150 as an example. It is preferable that the potentials supplied by each of wirings VDE11 to VDE13 are equal to each other. Also, depending on the situation, the potentials supplied by each of wirings VDE11 to VDE13 may be different from each other.

[0213] Wiring VGE11 functions, for example, as wiring to provide a low power supply potential (sometimes referred to as a low-level potential) to circuit 150. Similarly, wiring VGE12 functions, for example, as wiring to provide a low power supply potential to circuit 150. Wiring VGE13 functions, for example, as wiring to provide a low power supply potential to circuit 150. It is preferable that the potentials provided by wiring VGE11 to VGE13 are equal to each other. In this case, the low power supply potentials provided by wiring VGE11 to VGE13 can be, for example, ground potential, 0V, negative potential, etc. Also, depending on the situation, the potentials provided by wiring VGE11 to VGE13 may be different to each other.

[0214] The wiring CK shown in Figure 6 functions, for example, as wiring to supply a pulse voltage to circuit 150. In particular, this pulse voltage can be, for example, a pulse voltage (clock signal) that periodically repeats between high-level potential and low-level potential.

[0215] The wiring CKB shown in Figure 6 functions, as an example, to provide a potential that is the inverse of the potential supplied by wiring CK. For example, when a high-level potential is supplied to wiring CK, a low-level potential is supplied to wiring CKB, and when a low-level potential is supplied to wiring CK, a high-level potential is supplied to wiring CKB.

[0216] <Example of operation> Next, we will explain an example of the operation of circuit 150 in Figure 6.

[0217] In this example, the high-level potential supplied to wiring VDE11 to VDE13 is, for example, 0.45V. The low-level potential supplied to wiring VGE11 to VGE13 is, for example, 0V.

[0218] First, a low-level potential (0V) is applied to wiring CK. This low-level potential can be, for example, ground potential, 0V, or a negative potential. In this example, the low-level potential is set to 0V. When wiring CK is given a low-level potential, wiring CKB is given a high-level potential. In this example, the high-level potential is set to 0.45V.

[0219] When a low-level potential (0V) is applied to wiring CK, transistor TrS11 operates in the subthreshold region, and transistor TrO14 is turned off. As a result, a subthreshold current flows from wiring VDE11 through transistor TrS11 to the gate of transistor TrS13, and the potential at the gate of transistor TrS13 becomes 0.45V. Therefore, transistor TrS13 is turned off.

[0220] Furthermore, by applying a high-level potential (0.45V) to the wiring CKB, transistors TrO15, TrO18, and TrO20 each operate in the subthreshold region.

[0221] As transistor TrO15 operates in the subthreshold region, a low-level potential (0V) from wiring VGE11 is applied to the second terminal of transistor TrO14, the second terminal of capacitor CN, the first terminal of transistor TrO16, and the back gate of transistor TrO16.

[0222] Furthermore, because transistor TrO18 operates in the subthreshold region, a low-level potential (0V) from wiring VGE12 is applied to the second terminal of transistor TrO17 and the back gate of transistor OSW.

[0223] Further, when the transistor TrO20 operates in the subthreshold region, a low-level potential from the wiring VGE13 is applied to the second terminal of the transistor TrO19. As a result, the potential of the second terminal of the transistor TrO19 becomes 0V. Also, since a high-level potential (0.45V) is applied to the gate of the transistor TrO19, the transistor TrO19 operates in the subthreshold region. Therefore, a low-level potential (0V) from the wiring VGE13 is applied to the gate of the transistor TrS12, the first terminal of the transistor TrS13, the gate of the transistor TrO16, the gate of the transistor TrO17, and the gate of the transistor OSW.

[0224] Since a low-level potential (0V) is applied to the gate of the transistor TrS12, the transistor TrS12 operates in the subthreshold region, and a high-level potential (0.45V) from the wiring VDE12 is applied to the first terminal of the capacitor CN and the second terminal of the transistor TrS13.

[0225] Since a low-level potential (0V) is applied to the gate of the transistor TrO16 and the gate of the transistor TrO17, each of the transistor TrO16 and the transistor TrO17 is turned off.

[0226] Also, at this time, it is assumed that a potential V sig is input as an electrical signal to the terminal IT of the circuit 150.

[0227] Next, consider the case where the low-level potential (0V) applied to the wiring CK changes to a high-level potential (0.45V). At this time, the high-level potential (0.45V) applied to the wiring CKB changes to a low-level potential (0V).

[0228] When a high-level potential (0.45 V) is applied to the wiring CK, the transistor TrS11 is turned off, and the transistor TrO14 operates in the subthreshold region. Therefore, a subthreshold current flows between the source and drain of the transistor TrO14, and the potential of the gate of the transistor TrS13 becomes lower than 0.45 V. As a result, when the gate-source voltage of the transistor TrS13 becomes lower than the threshold voltage, the transistor TrS13 is turned on.

[0229] Also, when a low-level potential (0 V) is applied to the wiring CKB, the transistor TrO20 is turned off.

[0230] When the transistor TrS13 is turned on, the charges charged on the first terminal of the capacitor CN are distributed to the gates of the transistor TrO16, the transistor TrO17, and the gate of the transistor OSW, etc. Since the transistor TrO20 is turned off, the charges distributed to the gates of the transistor TrO16, the transistor TrO17, and the gate of the transistor OSW, etc. are not discharged. Also, as a result, the potential of the gate of the transistor TrS12 becomes high, and when the gate-source voltage of the transistor TrS12 becomes higher than the threshold voltage, the transistor TrS12 is turned off.

[0231] Also, since the potential of the gate of the transistor TrO16 becomes high, when the gate-source voltage of the transistor TrO16 becomes higher than the threshold voltage, the transistor TrO16 operates in the subthreshold region. Similarly, since the potential of the gate of the transistor TrO17 becomes high, when the gate-source voltage of the transistor TrO17 becomes higher than the threshold voltage, the transistor TrO17 operates in the subthreshold region.

[0232] Also, when a low-level potential (0 V) is applied to the wiring CKB, the transistors TrO15 and TrO18 are turned off.

[0233] At this time, the V supplied to terminal IT of circuit 150 sig This is input to the back gate of transistor OSW and the second terminal of capacitor CN.

[0234] In some cases, applying a potential Vsig, the same as the first terminal of the OSW transistor, to the back gate of the OSW transistor can increase the on-current flowing through the OSW transistor.

[0235] Also, V is connected to the second terminal of capacitance CN. sig As a result of the given conditions, the potential of the first terminal of capacitor CN increases due to capacitive coupling. Additionally, because transistor TrS13 is operating in the subthreshold region, the increased potential of the first terminal of capacitor CN also increases the potentials of the gates of transistors TrO16, TrO17, and OSW.

[0236] Furthermore, since transistors TrO15 and TrO18 are in the off state, there is no conduction between terminal IT and wire VGE11, and between terminal IT and wire VGE12. In other words, no current flows between terminal IT and wire VGE11, and between terminal IT and wire VGE12.

[0237] This allows the gate potential of transistor OSW to be increased, which may allow transistor OSW to operate within the linear or saturation region. Therefore, by turning on transistor OSW, circuit 150 receives the potential V input from terminal OT to terminal IT. sig It can output a potential that is almost equal to that.

[0238] Furthermore, this embodiment can be appropriately combined with other embodiments shown herein.

[0239] (Embodiment 3) This embodiment describes a SAR-ADC logic circuit that can be incorporated into electronic devices.

[0240] The circuit 200 shown in Figure 7 is a circuit diagram illustrating an example configuration of a SAR-ADC logic circuit. Circuit 200 includes, as an example, circuit SH, comparator CMP, circuit SARL, and digital-to-analog conversion circuit NDAC. Circuit 200 also has a terminal INT that functions as an input terminal and a terminal LOT that functions as an output terminal.

[0241] The input terminal of circuit SH is electrically connected to terminal INT. The output terminal of circuit SH is electrically connected to the + terminal of comparator CMP. The output terminal of comparator CMP is electrically connected to terminal CIT of circuit SARL. Terminal DOT of circuit SARL is electrically connected to terminal LOT and to the input terminal of digital-to-analog conversion circuit NDAC. The output terminal of digital-to-analog conversion circuit NDAC is electrically connected to the - terminal of comparator CMP.

[0242] For example, an analog potential is input to terminal INT of circuit 200.

[0243] Circuit SH functions, for example, as a sample-and-hold circuit. In circuit 200, circuit SH can temporarily hold the analog potential input from terminal INT. Furthermore, circuit SH can output the held analog potential to the + terminal of comparator CMP.

[0244] The comparator CMP has the function of comparing the magnitudes of the analog potentials input to the + terminal and the - terminal, respectively, and outputting the result to the comparator CMP's output terminal. For example, if the analog potential input to the + terminal is higher than the analog potential input to the - terminal, the comparator CMP outputs a high-level potential from its output terminal. Conversely, if the analog potential input to the + terminal is lower than the analog potential input to the - terminal, the comparator CMP outputs a low-level potential from its output terminal.

[0245] Circuit SARL is a circuit that corresponds to a logic circuit in the SAR-ADC logic circuit, and for example, it has a flip-flop circuit and a latch circuit. Circuit SARL has terminal CIT and terminal DOT. Terminal CIT acquires the potential output from the output terminal of comparator CMP, and terminal DOT outputs the digital potential converted by circuit 200 to terminal LOT of circuit 200 and the input terminal of the digital-to-analog conversion circuit NDAC.

[0246] The digital-to-analog conversion circuit NDAC has the function of converting the digital potential output from terminal DOT of circuit SARL into an analog potential and outputting that analog potential to the negative terminal of the comparator.

[0247] Incidentally, the circuit SARL may output the digital potential output from terminal DOT as a complementary signal. In this case, the digital-to-analog conversion circuit NDAC may be configured as a pair, with one of the complementary signals being input to one digital-to-analog conversion circuit NDAC and the other complementary signal being input to the other digital-to-analog conversion circuit NDAC.

[0248] Next, the configuration of the SARL circuit will be described. Figure 8(A) is a block diagram showing an example of the configuration of the SARL circuit, and the SARL circuit shown in Figure 8(A) has a flip-flop circuit FF[0] to flip-flop circuit FF[n] (where n is an integer of 1 or more) and a latch circuit BC[1] to latch circuit BC[n].

[0249] Each of the flip-flop circuits FF[0] to FF[n] shown in Figure 8(A) has a D terminal, a Q terminal, and an R terminal. Each of the flip-flop circuits FF[0] to FF[n] is also electrically connected to wiring CK and wiring CKB.

[0250] The D terminal of each flip-flop circuit FF[0] through FF[n] functions as an input terminal to which a data signal (potential) is input. The Q terminal of each flip-flop circuit FF[0] through FF[n] functions as an output terminal to which a data signal (potential) is output.

[0251] The R terminals of each flip-flop circuit FF[0] through FF[n] function as input terminals for receiving control signals to erase the data held in each of the flip-flop circuits FF[0] through FF[n]. Figure 8(A) also illustrates the wiring RST as the wiring that provides this control signal.

[0252] The wiring CK shown in Figure 8(A) functions, as an example, as wiring that provides a pulse voltage. In particular, this pulse voltage can be, for example, a pulse voltage (clock signal) that periodically repeats between high-level potential and low-level potential.

[0253] The wiring CKB shown in Figure 8(A) functions, as an example, to provide a potential that is the inverse of the potential given to wiring CK. For example, when a high-level potential is given to wiring CK, a low-level potential is given to wiring CKB, and when a low-level potential is given to wiring CK, a high-level potential is given to wiring CKB.

[0254] Each of the latch circuits BC[1] through BC[n] shown in Figure 8(A) has a terminal LIN. Each of the latch circuits BC[1] through BC[n] also has two output terminals. For example, in Figure 8(A), these output terminals are denoted as terminals LOTP[1] through LOTP[n] and terminals LOTN[1] through LOTN[n]. Also in Figure 8(A), terminals LOTP[1] through LOTP[n] and terminals LOTN[1] through LOTN[n] are collectively referred to as terminal LOT. Each of the latch circuits BC[1] through BC[n] is electrically connected to wiring CMOP and wiring CMON.

[0255] Furthermore, in the circuit SARL shown in Figure 8(A), each of the pairs of terminals LOTP[1] and LOTN[1], and terminals LOTP[n] and LOTN[n], functions as an output terminal that outputs a digital potential as a complementary signal.

[0256] The flip-flop circuits FF[0] through FF[n] are connected in sequence such that the Q terminal of the preceding flip-flop circuit is electrically connected to the D terminal of the subsequent flip-flop circuit. The D terminal of the first flip-flop circuit FF[0] is electrically connected to terminal VST. The Q terminal of the second flip-flop circuit FF[1] is electrically connected to terminal LIN of the latch circuit BC[1], and the Q terminal of the (n+1)th flip-flop circuit FF[n] is electrically connected to terminal LIN of the latch circuit BC[n].

[0257] A constant potential is input to terminal VST, for example. This constant potential can be, for example, ground potential, 0V, or a negative potential.

[0258] Here, we will describe the configurations of the flip-flop circuits FF[0] through FF[n]. Figure 8(B) shows example configurations of flip-flop circuits that can be applied to each of the flip-flop circuits FF[0] through FF[n].

[0259] The flip-flop circuit FF shown in Figure 8(B) includes, as an example, circuits 100A_1 to 100A_4, circuit 100_1, circuit 100_2, and transistor TrS30.

[0260] Each of circuits 100A_1 to 100A_4 functions as a clocked inverter circuit, for example. Therefore, each of circuits 100A_1 to 100A_4 can be, for example, fitted with circuit 100A described in Embodiment 1.

[0261] Circuit 100_1 and circuit 100_2 each function as an inverter circuit, for example. Therefore, for each of circuits 100_1 and 100_2, for example, circuit 100 described in Embodiment 1 can be applied.

[0262] For transistor TrS30, for example, a transistor applicable to transistor TrS described in Configuration Example 1 of Embodiment 1 can be used.

[0263] The input terminal of circuit 100A_1 is electrically connected to the D terminal of the flip-flop circuit FF. The output terminal of circuit 100A_1 is electrically connected to the output terminal of circuit 100_1, the input terminal of circuit 100A_2, and the input terminal of circuit 100A_3. The output terminal of circuit 100A_2 is electrically connected to the input terminal of circuit 100_1. The output terminal of circuit 100A_3 is electrically connected to the output terminal of circuit 100_2, the input terminal of circuit 100A_4, the first terminal of transistor TrS30, and the Q terminal of the flip-flop circuit FF. The output terminal of circuit 100A_4 is electrically connected to the input terminal of circuit 100_2. The second terminal of transistor TrS30 is electrically connected to wiring VDE30.

[0264] Furthermore, wiring CK is electrically connected to terminal CT of circuit 100A_1, terminal CTB of circuit 100A_2, terminal CTB of circuit 100A_3, and terminal CT of circuit 100A_4. Similarly, wiring CKB is electrically connected to terminal CTB of circuit 100A_1, terminal CT of circuit 100A_2, terminal CT of circuit 100A_3, and terminal CTB of circuit 100A_4.

[0265] Wiring VDE30 functions, for example, as wiring to supply a high power supply potential (sometimes referred to as a high-level potential) to a flip-flop circuit (FF).

[0266] Next, the configurations of latch circuits BC[1] through BC[n] will be described. Figure 8(C) shows example configurations of latch circuit BC that can be applied to each of latch circuits BC[1] through BC[n].

[0267] The latch circuit BC shown in Figure 8(C) includes, as an example, circuits 100B_1 to 100B_4, circuits 100C_1, 100C_2, and 100_3.

[0268] Each of circuits 100B_1 to 100B_4 functions as a NAND gate, for example. Therefore, each of circuits 100B_1 to 100B_4 can be fitted with, for example, the circuit 100B described in Embodiment 1.

[0269] The latch circuit BC, for example, has terminals LOTP and LOTN. The potential output from terminal LOTN is the inverted logic of the potential output from terminal LOTP. Although terminal LOTN is not shown in circuit SARL in Figure 8(A), the potential output by circuit 200 may be the potential output by terminal LOTN included in each of the latch circuits BC[2] to BC[n].

[0270] Circuit 100C_1 and circuit 100C_2 each function as a NOR circuit, for example. Therefore, for each of circuits 100C_1 and 100C_2, for example, circuit 100C described in Embodiment 1 can be applied.

[0271] Circuit 100_3 functions as an inverter circuit, for example. Therefore, for example, circuit 100 described in Embodiment 1 can be applied to circuit 100_3.

[0272] The first input terminal of circuit 100B_1 is electrically connected to wiring CMOP, and the output terminal of circuit 100B_1 is electrically connected to the first input terminal of circuit 100B_3. The first input terminal of circuit 100B_2 is electrically connected to wiring CMON, and the output terminal of circuit 100B_2 is electrically connected to the first input terminal of circuit 100B_4. The terminal LIN of latch circuit BC is electrically connected to the second input terminal of circuit 100B_1, the second input terminal of circuit 100B_2, and the input terminal of circuit 100_3. The output terminal of circuit 100_3 is electrically connected to the second input terminal of circuit 100B_3 and the second input terminal of circuit 100B_4.

[0273] The output terminal of circuit 100B_3 is electrically connected to the first input terminal of circuit 100C_1. The output terminal of circuit 100B_4 is electrically connected to the first input terminal of circuit 100C_2. The output terminal of circuit 100C_1 is electrically connected to terminal LOTP and the second input terminal of circuit 100C_2. The output terminal of circuit 100C_2 is electrically connected to terminal LOTN and the second input terminal of circuit 100C_1.

[0274] As described above, by applying the semiconductor device described in Embodiment 1 to the logic circuit (for example, circuit SARL) included in the SAR-ADC logic circuit, a SAR-ADC logic circuit with low power consumption can be realized.

[0275] Furthermore, the semiconductor device according to one aspect of the present invention is not limited to the circuit configuration described above, and may be modified as appropriate.

[0276] For example, the flip-flop circuit FF shown in Figure 8(B) may be modified to the configuration of the flip-flop circuit FFA shown in Figure 9(A). The flip-flop circuit FFA is an example of a modification of the flip-flop circuit FF and differs from the flip-flop circuit FF in that it has circuits SH_1 to SH_4.

[0277] Each of circuits SH_1 to SH_4 has a terminal IP, a terminal OP, and a terminal SP. In each of circuits SH_1 to SH_4, for example, terminal IP functions as an input terminal, terminal OP functions as an output terminal, and terminal SP functions as a control terminal.

[0278] Each of circuits SH_1 to SH_4 has the function of acquiring the potential input to terminal IP and outputting that potential to terminal OP when the potential input to terminal SP transitions from a low level potential to a high level potential. In addition, each of circuits SH_1 to SH_4 has the function of stopping the input of potential to terminal IP when the potential input to terminal SP transitions from a high level potential to a low level potential. However, in this case, the potential output from terminal OP does not change before and after the transition from a high level potential to a low level potential at terminal SP. In other words, each of circuits SH_1 to SH_4 functions as a sample-and-hold circuit.

[0279] The specific circuit configuration of the flip-flop circuit FFA will be explained. The input terminal of circuit 100A_1 is electrically connected to the D terminal of the flip-flop circuit FF. The output terminal of circuit 100A_1 is electrically connected to the output terminal of circuit 100_1 and to terminal IP of circuit SH_1. Terminal OP of circuit SH_1 is electrically connected to the input terminal of circuit 100A_2 and to the input terminal of circuit 100A_3. The output terminal of circuit 100A_2 is electrically connected to terminal IP of circuit SH_2, and terminal OP of circuit SH_2 is electrically connected to the input terminal of circuit 100_1. The output terminal of circuit 100A_3 is electrically connected to the output terminal of circuit 100_2, to terminal IP of circuit SH_3, and to the first terminal of transistor TrS30. Terminal OP of circuit SH_3 is electrically connected to the input terminal of circuit 100A_4 and to terminal Q of the flip-flop circuit FF. Furthermore, the output terminal of circuit 100A_4 is electrically connected to terminal IP of circuit SH_4, and terminal OP of circuit SH_4 is electrically connected to the input terminal of circuit 100_2.

[0280] Furthermore, wiring CK is electrically connected to terminal CT of circuit 100A_1, terminal CTB of circuit 100A_2, terminal CTB of circuit 100A_3, and terminal CT of circuit 100A_4. Similarly, wiring CKB is electrically connected to terminal CTB of circuit 100A_1, terminal CT of circuit 100A_2, terminal CT of circuit 100A_3, and terminal CTB of circuit 100A_4.

[0281] Furthermore, terminal SP of circuit SH_1 and terminal SP of circuit SH_4 are electrically connected to wiring DK. Also, terminal SP of circuit SH_2 and terminal SP of circuit SH_3 are electrically connected to wiring DKB.

[0282] The wiring DK shown in Figure 9(A) functions, as an example, as wiring that provides a pulse voltage. In particular, this pulse voltage can be, for example, a pulse voltage (clock signal) that periodically repeats between high-level potential and low-level potential.

[0283] As an example, the wiring DKB shown in Figure 9(A) functions to provide a potential that is the inverse of the potential given to wiring DK. For example, when a high-level potential is given to wiring DK, a low-level potential is given to wiring DKB, and when a low-level potential is given to wiring DK, a high-level potential is given to wiring DKB.

[0284] Next, we will describe examples of the circuit configurations of circuits SH_1 to SH_4. Note that circuits SH_1 to SH_4 may have the same circuit configuration as each other, or they may have different circuit configurations.

[0285] Figure 9(B) shows example configurations of circuits SH_1 and SH_2. Figure 9(B) also illustrates example configurations of circuits 100A_1 and 100A_2.

[0286] Furthermore, the circuits 100A_1 and 100A_2 shown in Figure 9(B) apply the configuration of circuit 100A shown in Figure 3. Therefore, for circuits 100A_1 and 100A_2 in Figure 9(B), refer to the explanation of circuit 100A in Figure 3.

[0287] In Figure 9(B), each of circuits SH_1 and SH_2 includes a transistor TrO30 and a capacitor CSH.

[0288] For transistor TrO30, for example, a transistor applicable to transistor TrO described in Configuration Example 1 can be used.

[0289] Furthermore, transistor TrO30 functions as a switching element, for example. Incidentally, since it is desirable for the transistors included in the flip-flop circuit FFA to operate in the subthreshold region, it is preferable to input a potential within the range that allows operation in the subthreshold region to the source and gate of the transistor. On the other hand, if a potential within the range that allows operation in the subthreshold region is applied to the source and gate of transistor TrO30, the potential difference between the first and second terminals of transistor TrO30 may become large. One way to bring transistor TrO30 into a sufficiently ON state is, for example, to apply the bootstrap circuit described in Embodiment 2.

[0290] The first terminal of transistor TrO30 is electrically connected to terminal IP, the second terminal of transistor TrO30 is electrically connected to the first terminal of capacitor CSH and terminal OP, and the gate of transistor TrO30 is electrically connected to terminal SP. The second terminal of capacitor CSH is electrically connected to wiring VGE20.

[0291] The wiring VGE20 shown in Figure 9(B) functions, as an example, as wiring to supply a low power supply potential (sometimes referred to as a low-level potential) to circuits SH_1 and SH_2. The low power supply potential can be, for example, ground potential, 0V, or a negative potential. In Figure 9(B), wiring VGE20 is electrically connected to both circuits SH_1 and SH_2, but the wiring VGE20 for circuit SH_1 and the wiring VGE20 for circuit SH_2 may be different from each other. In this case, the potential supplied by wiring VGE20 for circuit SH_1 and the potential supplied by wiring VGE20 for circuit SH_2 may be equal or different from each other.

[0292] Note that the configurations of circuits SH_3 and SH_4 may be the same as the configurations of circuits SH_1 and SH_2 shown in Figure 9(B). Specifically, for example, circuit SH_1 in Figure 9(B) may be read as circuit SH_3, and circuit SH_2 in Figure 9(B) may be read as circuit SH_4. In this case, circuit 100A_1 in Figure 9(B) may be read as circuit 100A_3, and circuit 100A_2 in Figure 9(B) may be read as circuit 100A_4.

[0293] Next, we will explain an example of the operation of the flip-flop circuit (FF) shown in Figure 9(A).

[0294] For the operation of circuits 100A_1 and 100A_2, please refer to the description in Operation Example 2 of Embodiment 1.

[0295] First, consider the case where a high-level potential is input to both wiring CK and wiring DK. As a result, a low-level potential is input to both wiring CKB and wiring DKB.

[0296] As described above, a high-level potential is input to terminal CT of circuit 100A_1, and a low-level potential is input to terminal CTB of circuit 100A_1. Therefore, circuit 100A_1 outputs a potential to terminal OT that is the inverted logic of the potential input to terminal IT.

[0297] Furthermore, in circuit SH_1, a high-level potential is input to terminal SP. Therefore, transistor TrO30 operates in the subthreshold region. Also, the potential output from terminal OT of circuit 100A_1 is input to the first terminal of capacitor CSH and terminal IT of circuit 100A_2 via transistor TrO30. At this time, an amount of charge corresponding to the potential output from terminal OT of circuit 100A_1 is accumulated at the first terminal of capacitor CSH, and this potential is output to terminal OP.

[0298] Furthermore, a low-level potential is input to terminal CT of circuit 100A_2, and a high-level potential is input to terminal CTB of circuit 100A_2, causing circuit 100A_2 to cease functioning as an inverter circuit. Specifically, the potential at terminal OT of circuit 100A_2 may not be the potential obtained by inverting the logic of the potential input to terminal IT, but rather the potential at terminal OT before the low-level potential is input to terminal CT (before the high-level potential is input to terminal CTB).

[0299] Furthermore, in circuit SH_2, a low-level potential is input to terminal SP. As a result, transistor TrO30 is in the off state. Therefore, the potential output from terminal OT of circuit 100A_2 is not input to the first terminal of capacitor CSH via transistor TrO30. Circuit SH_2 outputs the potential of the first terminal of capacitor CSH from terminal OP.

[0300] Next, consider the case where a low-level potential is input to wiring CK and a low-level potential is input to wiring DK. In this case, a high-level potential is input to wiring CKB and a high-level potential is input to wiring DKB.

[0301] As described above, a low-level potential is input to terminal CT of circuit 100A_1, and a high-level potential is input to terminal CTB of circuit 100A_1, causing circuit 100A_2 to cease functioning as an inverter circuit. Specifically, the potential at terminal OT of circuit 100A_1 may not be the potential obtained by inverting the logic of the potential input to terminal IT, but rather the potential at terminal OT before the low-level potential is input to terminal CT (before the high-level potential is input to terminal CTB).

[0302] Furthermore, in circuit SH_1, a low-level potential is input to terminal SP. As a result, transistor TrO30 is in the off state. Therefore, the potential output from terminal OT of circuit 100A_1 is not input to the first terminal of capacitor CSH via transistor TrO30.

[0303] Furthermore, because transistor TrO30 of circuit SH_1 is turned off, the potential of terminal OT of circuit 100A_1, which was present before a low-level potential was input to terminal SP, is held at the first terminal of capacitor CSH of circuit SH_1. Circuit SH_1 outputs this potential from terminal OP.

[0304] Furthermore, since a high-level potential is input to terminal CT of circuit 100A_2 and a low-level potential is input to terminal CTB of circuit 100A_2, circuit 100A_2 outputs a potential to terminal OT that is the logic inverted of the potential input to terminal IT. In particular, since the potential held at the first terminal of capacitor CSH of circuit SH_1 is input to terminal IT, circuit 100A_2 outputs a potential from terminal OT that is the logic inverted of that potential.

[0305] Furthermore, in circuit SH_2, a high-level potential is input to terminal SP. Therefore, transistor TrO30 operates in the subthreshold region. Also, the potential output from terminal OT of circuit 100A_2 is input to the first terminal of capacitor CSH and the input terminal of circuit 100_1 (see Figure 9(A)) via transistor TrO30. At this time, an amount of charge corresponding to the potential output from terminal OT of circuit 100A_2 is accumulated at the first terminal of capacitor CSH, and this potential is output to terminal OP.

[0306] As shown in the above example of operation, even if the inverter circuit function of circuit 100A_1 stops, circuit SH_1 can hold the potential output from terminal OT of circuit 100A_1 using its capacitance CSH, and can also output the potential held by capacitance CSH of circuit SH_1 to terminal OP. Similarly, even if the inverter circuit function of circuit 100A_2 stops, circuit SH_2 can hold the potential output from terminal OT of circuit 100A_2 using its capacitance CSH, and can also output the potential held by capacitance CSH of circuit SH_2 to terminal OP.

[0307] In Figure 9(B), if circuits SH_1 and SH_2 are not provided (in the case of the flip-flop circuit FF in Figure 8(B)), when the inverter function of either circuit 100A_1 or circuit 100A_2 stops, the terminal OT of that circuit temporarily becomes floating, and the potential of terminal OT may change over time. As a result, the potential input to the input terminal of the logic circuit (circuit 100A_2 or circuit 100_1) electrically connected to terminal OT changes, and therefore the potential output from the output terminal of that logic circuit may also change. Therefore, as shown in Figures 9(A) and 9(B), by providing circuit SH_1 to the flip-flop circuit, the potential output by circuit 100A_1 can be stably input to circuit 100A_2. Similarly, by providing circuit SH_2 to the flip-flop circuit, the potential output by circuit 100A_2 can be stably input to circuit 100_1.

[0308] Furthermore, the circuit configurations of circuits SH_1 and SH_2 shown in Figure 9(B) may be modified depending on the circumstances. For example, circuits SH_1 and SH_2 in Figure 9(B) may be changed to the circuit configuration shown in Figure 10.

[0309] Circuit SH_1 shown in Figure 10 differs from circuit SH_1 in Figure 9(B) in that it includes transistors TrS31, TrS32, TrO31, and TrO32. Similarly, circuit SH_2 shown in Figure 10 differs from circuit SH_2 in Figure 9(B) in that it includes transistors TrS31, TrS32, TrO31, and TrO32.

[0310] In circuits SH_1 and SH_2 of Figure 10, the first terminal of transistor TrO30 is electrically connected to terminal IP, the second terminal of transistor TrO30 is electrically connected to the first terminal of capacitor CSH and the gate of transistor TrO31, and the gate of transistor TrO30 is electrically connected to terminal SP. The second terminal of capacitor CSH is electrically connected to wiring VGE20.

[0311] The first terminal of transistor TrS31 is electrically connected to wiring VDE, and the second terminal of transistor TrS31 is electrically connected to the gate of transistor TrS31, the first terminal of transistor TrO31, the gate of transistor TrS32, and the gate of transistor TrO32. Also, the second terminal of transistor TrO31 is electrically connected to wiring VGE. The first terminal of transistor TrS32 is electrically connected to wiring VDE, and the second terminal of transistor TrS32 is electrically connected to the first terminal of transistor TrO32 and terminal OP. The second terminal of transistor TrO32 is electrically connected to wiring VGE.

[0312] The wiring VDE included in circuits SH_1 and SH_2 in Figure 10 functions, for example, as wiring to supply a high power supply potential (sometimes referred to as a high-level potential) to circuits SH_1 and SH_2. Note that in Figure 10, the wiring VDE of circuit SH_1 or circuit SH_2 and the wiring VDE of circuit 100A_1 or circuit 100A_2 may be different from each other. Furthermore, it is preferable that the potentials supplied by the respective VDEs of circuits SH_1, SH_2, 100A_1, and 100A_2 are equal to each other.

[0313] Furthermore, the wiring VGE included in circuits SH_1 and SH_2 in Figure 10 functions, for example, as wiring to supply a low power supply potential (sometimes referred to as a low-level potential) to circuits SH_1 and SH_2. This low power supply potential can be, for example, ground potential, 0V, or a negative potential. Note that in Figure 10, the wiring VGE of circuit SH_1 or circuit SH_2 and the wiring VGE of circuit 100A_1 or circuit 100A_2 may be different wirings from each other. It is also preferable that the potentials supplied by the respective VGEs of circuits SH_1, SH_2, 100A_1, and 100A_2 are equal to each other.

[0314] In circuits SH_1 and SH_2 of Figure 10, an inverter circuit is formed by transistors TrS31 and TrO31. In the inverter circuit consisting of transistors TrS31 and TrO31, for example, when a high-level potential is input to transistor TrO31, transistor TrO31 turns on, and a low-level potential from the wiring VGE is applied to the first terminal of transistor TrO31, the gate of transistor TrS32, and the gate of transistor TrO31. At this time, a low-level potential is also input to the gate of transistor TrS31, so transistor TrS31 turns on, and transistor TrS31 functions as a resistor with a potential difference between the high-level potential and the low-level potential between its first and second terminals.

[0315] Furthermore, the inverter circuit consisting of transistors TrS31 and TrO31, for example, when a low-level potential is input to transistor TrO31, turns off transistor TrO31, and applies a high-level potential from wiring VDE to the first terminal of transistor TrO31, the gate of transistor TrS32, and the gate of transistor TrO32, respectively.

[0316] In circuits SH_1 and SH_2 of Figure 10, the inverter circuit is composed of transistors TrS32 and TrO32. For the configuration of this inverter circuit, please refer to the descriptions in Configuration Example 1 and Operation Example 1 of Embodiment 1.

[0317] Based on the above, it can be said that each of the circuits SH_1 and SH_2 in Figure 10 has two inverter circuits connected in series. In other words, each of the circuits SH_1 and SH_2 in Figure 10 is configured to output a potential to terminal OP that is approximately equal to the potential of the first terminal of capacitor CSH.

[0318] In circuits SH_1 and SH_2 in Figure 10, if transistors TrS31, TrS32, TrO31, and TrO32 are not provided (as in the circuit configuration of Figure 9(B)), the first terminal of the capacitor CSH is directly electrically connected to the gate of transistor TrS1 included in circuits 100A_2 and 100_1. When transistor TrS1 is a Si transistor, leakage current may flow between the gate and source or between the gate and drain of the Si transistor, causing the potential held at the first terminal of the capacitor CSH to fluctuate due to this leakage current. Therefore, as shown in Figure 10, by providing two inverter circuits connected in series to each of circuits SH_1 and SH_2, it is possible to prevent fluctuations in the potential held at the first terminal of the capacitor CSH due to leakage current between the gate and source or between the gate and drain of transistor TrS1.

[0319] Furthermore, the configurations of circuits SH_1 and SH_2 in Figure 10 can be the same as the configurations of the circuits shown in Figure 11. Circuits SH_1 and SH_2 shown in Figure 11 are configured in which transistors TrS32 and TrO32 included in circuits SH_1 and SH_2 in Figure 10, respectively, are replaced with circuit 100_4, which functions as an inverter circuit. For example, circuits 100 and 100A described in Embodiment 1 can be applied to circuit 100_4.

[0320] This embodiment can be appropriately combined with other embodiments shown in this specification.

[0321] (Embodiment 4) This embodiment describes an example of the configuration of a semiconductor device as described in the above embodiment, and an example of the configuration of a transistor that can be applied to the semiconductor device as described in the above embodiment.

[0322] <Example of semiconductor device configuration> Figure 12 shows a semiconductor device having a memory cell including a capacitive element, the semiconductor device comprising a transistor 300, a transistor 500, and a capacitive element 600. Figure 13(A) shows a cross-sectional view of transistor 500 in the channel length direction, Figure 13(B) shows a cross-sectional view of transistor 500 in the channel width direction, and Figure 13(C) shows a cross-sectional view of transistor 300 in the channel width direction.

[0323] Transistor 500 is an OS transistor (OS transistor) having a metal oxide in its channel formation region. Transistor 500 has the characteristics of low off-current and low field-effect mobility even at high temperatures. By applying transistor 500 to a semiconductor device, such as transistor TrO, or transistors TrO1 to TrO8 as described in the above embodiment, a semiconductor device can be realized that does not experience a decrease in operating capability even at high temperatures. In particular, by utilizing the characteristic of low off-current and applying transistor 500 to, for example, transistor TrO, or transistors TrO1 to TrO8, power consumption due to off-leak current can be suppressed.

[0324] Transistor 500 is provided, for example, above transistor 300, and capacitive element 600 is provided, for example, above transistors 300 and 500. Capacitive element 600 can be, for example, a capacitive element that holds a potential corresponding to the data written to the memory cell. Depending on the circuit configuration, the capacitive element 600 shown in Figure 12 does not necessarily have to be provided.

[0325] The transistor 300 is provided on a substrate 310 and has an element isolation layer 312, a conductor 316, an insulator 315, a semiconductor region 313 consisting of a part of the substrate 310, a low-resistance region 314a that functions as a source region or a drain region, and a low-resistance region 314b. The transistor 300 can be applied to, for example, the transistor TrS, transistor TrS1 to transistor TrS6 described in the above embodiment. In Figure 12, the gate of the transistor 300 is shown to be electrically connected to either the source or the drain of the transistor 500 via a pair of electrodes of the capacitive element 600. However, in one embodiment of the semiconductor device configuration of the present invention, either the source or the drain of the transistor 300 can be electrically connected to either the source or the drain of the transistor 500, or either the source or the drain of the transistor 300 can be electrically connected to the gate of the transistor 500, or each terminal of the transistor 300 can be configured not to be electrically connected to each terminal of the transistor 500 or each terminal of the capacitive element 600. Furthermore, the capacitive element 600 is not necessarily required in the configuration shown in Figure 12.

[0326] Furthermore, it is preferable to use a semiconductor substrate (for example, a single crystal substrate or a silicon substrate) as the substrate 310.

[0327] As shown in Figure 13(C), the transistor 300 has its semiconductor region 313's top surface and side surface in the channel width direction covered by a conductor 316 via an insulator 315. By making the transistor 300 a Fin type in this way, the effective channel width can be increased, thereby improving the on-characteristics of the transistor 300. In addition, the contribution of the gate electrode's electric field can be increased, thus improving the off-characteristics of the transistor 300.

[0328] Note that transistor 300 can be either a p-channel or n-channel type.

[0329] In the low-resistance region 314a and low-resistance region 314b, which are the channel-forming region of the semiconductor region 313, the region near it, the source region, or the drain region, it is preferable that a silicon-based semiconductor is included, and it is particularly preferable that single-crystal silicon is included. Alternatively, each of the above-mentioned regions may be formed from a material having germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), aluminum gallium arsenide (GaAlAs), or GaN (gallium nitride). Furthermore, each of the above-mentioned regions may be configured using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing. Alternatively, the transistor 300 may be, for example, a HEMT (High Electron Mobility Transistor) using gallium arsenide and aluminum gallium arsenide.

[0330] The low-resistance region 314a and the low-resistance region 314b include, in addition to the semiconductor material applied to the semiconductor region 313, an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron.

[0331] The conductor 316, which functions as a gate electrode, can be made of a conductive material such as silicon, a semiconductor material, a metallic material, an alloy material, or a metal oxide material containing an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron.

[0332] Furthermore, since the work function is determined by the material of the conductor, the threshold voltage of the transistor can be adjusted by selecting the material of the conductor. Specifically, it is preferable to use titanium nitride and tantalum nitride, or both, as the conductor. In addition, in order to achieve both conductivity and embedding properties, it is preferable to use tungsten and aluminum, or both, as laminated materials for the conductor, and using tungsten is particularly preferable in terms of heat resistance.

[0333] The element isolation layer 312 is provided to separate multiple transistors formed on the substrate 310. The element isolation layer can be formed using, for example, the LOCOS (Local Oxidation of Silicon) method, the STI (Shallow Trench Isolation) method, or the mesa isolation method.

[0334] Note that the transistor 300 shown in Figure 12 is just one example, and its structure is not limited to this example. Any appropriate transistor may be used depending on the circuit configuration, driving method, etc. For example, the transistor 300 may have a planar structure instead of the FIN type shown in Figure 13(C). Also, for example, if the semiconductor device is a unipolar circuit consisting only of OS transistors, the configuration of transistor 300 may be the same as that of transistor 500 which uses an oxide semiconductor, as shown in Figure 14. Details of transistor 500 will be described later. In this specification, a unipolar circuit refers to a circuit that includes a transistor with only one polarity, such as an n-channel transistor or a p-channel transistor.

[0335] In Figure 14, the transistor 300 is mounted on a substrate 310A. In this case, the substrate 310A may be a semiconductor substrate, similar to the substrate 310 of the semiconductor device in Figure 12. The substrate 310A can be, for example, an SOI substrate, a glass substrate, a quartz substrate, a plastic substrate, a sapphire glass substrate, a metal substrate, a stainless steel substrate, a substrate with stainless steel foil, a tungsten substrate, a substrate with tungsten foil, a flexible substrate, a laminated film, paper containing fibrous material, or a base film. Examples of glass substrates include barium borosilicate glass, aluminoborosilicate glass, or soda-lime glass. Examples of flexible substrates, laminated films, and base films include plastics such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), and polytetrafluoroethylene (PTFE). Alternatively, another example is a synthetic resin such as acrylic. Alternatively, other examples include polypropylene, polyester, polyvinyl fluoride, and polyvinyl chloride. Alternatively, other examples include polyamide, polyimide, aramid, epoxy resin, inorganic vapor-deposited film, or paper.

[0336] As shown in Figure 12, the transistor 300 is provided with insulators 320, 322, 324, and 326 stacked in order from the substrate 310 side.

[0337] For insulators 320, 322, 324, and 326, for example, silicon oxide, silicon oxide nitride, silicon oxide nitride, silicon nitride, aluminum oxide, aluminum oxide nitride, aluminum oxide nitride, or aluminum nitride may be used.

[0338] In this specification, silicon oxidizide refers to a material in which the oxygen content is greater than the nitrogen content, and silicon nitride refers to a material in which the nitrogen content is greater than the oxygen content. Furthermore, in this specification, aluminum oxidizide refers to a material in which the oxygen content is greater than the nitrogen content, and aluminum nitride refers to a material in which the nitrogen content is greater than the oxygen content.

[0339] The insulator 322 may also function as a planarizing film that flattens steps caused by the insulator 320 and the transistor 300 covered by the insulator 322. For example, the upper surface of the insulator 322 may be planarized by a planarizing treatment using chemical mechanical polishing (CMP) to improve its flatness.

[0340] Furthermore, it is preferable to use a film for the insulator 324 that has barrier properties to prevent impurities such as hydrogen from diffusing from the substrate 310 or the transistor 300 to the region where the transistor 500 is provided.

[0341] As an example of a film having hydrogen barrier properties, silicon nitride formed by the CVD method can be used. However, when hydrogen diffuses into a semiconductor element having an oxide semiconductor, such as transistor 500, the characteristics of the semiconductor element may deteriorate. Therefore, it is preferable to use a film that suppresses hydrogen diffusion between transistor 500 and transistor 300. Specifically, a film that suppresses hydrogen diffusion is a film that has a low hydrogen desorption rate.

[0342] The amount of hydrogen desorption can be analyzed, for example, using a thermal desorption gas analysis (TDS) method. For example, in TDS analysis, the amount of hydrogen desorption from insulator 324, when the film surface temperature is in the range of 50°C to 500°C, is calculated as 10 × 10¹⁶ hydrogen atoms per unit area of ​​insulator 324. 15 atoms / cm 2 The following is preferably 5 × 10 15 atoms / cm2 The following is acceptable.

[0343] Furthermore, it is preferable that the dielectric constant of the insulator 326 is lower than that of the insulator 324. For example, the relative permittivity of the insulator 326 is preferably less than 4, and more preferably less than 3. Also, for example, the relative permittivity of the insulator 326 is preferably 0.7 times or less, and more preferably 0.6 times or less, than that of the relative permittivity of the insulator 324. By using a material with a low dielectric constant as the interlayer film, parasitic capacitance occurring between wiring can be reduced.

[0344] Furthermore, insulators 320, 322, 324, and 326 have conductors 328 and 330 embedded in them, which are connected to the capacitive element 600 or the transistor 500. Conductors 328 and 330 have the function of a plug or wiring. Conductors that have the function of a plug or wiring may be grouped together and assigned the same reference numeral. Also, in this specification, the wiring and the plug connected to the wiring may be an integrated unit. That is, there may be cases where a part of the conductor functions as wiring, and cases where a part of the conductor functions as a plug.

[0345] The plugs and wiring (conductors 328 and 330) can be made of conductive materials such as metals, alloys, metal nitrides, or metal oxides, either in a single layer or in a laminated form. It is preferable to use high-melting-point materials such as tungsten or molybdenum, which offer both heat resistance and conductivity, with tungsten being preferred. Alternatively, it is preferable to form them from low-resistance conductive materials such as aluminum or copper. Using low-resistance conductive materials can reduce wiring resistance.

[0346] A wiring layer may be provided on the insulator 326 and the conductor 330. For example, in Figure 12, insulators 350, 352, and 354 are sequentially stacked on top of insulators 326 and conductor 330. Conductors 356 are formed on insulators 350, 352, and 354. Conductors 356 function as plugs or wiring for connecting to transistor 300. Conductors 356 can be provided using the same material as conductors 328 and 330.

[0347] For example, it is preferable that insulator 350, like insulator 324, is an insulator that has barrier properties against impurities such as hydrogen and water. Also, as insulators 352 and 354, it is preferable to use insulators with relatively low dielectric constants, like insulator 326, in order to reduce parasitic capacitance that occurs between the wiring. Furthermore, it is preferable that conductor 356 contains a conductor that has barrier properties against impurities such as hydrogen and water. In particular, a conductor that has barrier properties against hydrogen is formed in the openings of insulator 350 that has barrier properties against hydrogen. With this configuration, transistor 300 and transistor 500 can be separated by the barrier layer, and the diffusion of hydrogen from transistor 300 to transistor 500 can be suppressed.

[0348] For example, tantalum nitride can be used as the conductor that has barrier properties against hydrogen. Furthermore, by laminating tantalum nitride with highly conductive tungsten, it is possible to suppress the diffusion of hydrogen from the transistor 300 while maintaining conductivity as wiring. In this case, it is preferable that the tantalum nitride layer, which has barrier properties against hydrogen, is in contact with the insulator 350, which also has barrier properties against hydrogen.

[0349] Furthermore, insulator 360, insulator 362, and insulator 364 are stacked in order on insulator 354 and conductor 356.

[0350] It is preferable that the insulator 360, like the insulator 324, is an insulator that has barrier properties against impurities such as water and hydrogen. Therefore, as the insulator 360, for example, a material that can be applied to the insulator 324 can be used.

[0351] Insulators 362 and 364 function as interlayer insulating films and planarizing films, respectively. Furthermore, it is preferable that insulators 362 and 364, like insulator 324, be insulators that have barrier properties against impurities such as water and hydrogen. Therefore, one or both of insulators 362 and 364 can be made from materials applicable to insulator 324.

[0352] Furthermore, openings are formed in the regions of insulators 360, 362, and 364 that overlap with a portion of the conductor 356, and the conductor 366 is provided to fill these openings. The conductor 366 is also formed on insulator 362. The conductor 366 functions, for example, as a plug or wiring for connecting to transistor 300. The conductor 366 can be provided using the same material as conductors 328 and 330.

[0353] Insulators 510, 512, 514, and 516 are sequentially layered on the insulator 364 and the conductor 366. It is preferable that one of the insulators 510, 512, 514, and 516 is made of a material that has barrier properties against oxygen and hydrogen.

[0354] For example, it is preferable to use a film for insulators 510 and 514 that has barrier properties to prevent impurities such as hydrogen from diffusing from the substrate 310 or the region where the transistor 300 is provided to the region where the transistor 500 is provided. Therefore, the same material as that used for insulator 324 can be used.

[0355] As an example of a film having hydrogen barrier properties, silicon nitride formed by the CVD method can be used. However, when hydrogen diffuses into a semiconductor element having an oxide semiconductor, such as transistor 500, the characteristics of the semiconductor element may deteriorate. Therefore, it is preferable to use a film that suppresses hydrogen diffusion between transistor 500 and transistor 300. Specifically, a film that suppresses hydrogen diffusion is a film that has a low hydrogen desorption rate.

[0356] Furthermore, for the film having barrier properties against hydrogen, it is preferable to use metal oxides such as aluminum oxide, hafnium oxide, or tantalum oxide for insulators 510 and 514.

[0357] In particular, aluminum oxide exhibits a high barrier effect, preventing the permeation of both oxygen and impurities such as hydrogen and moisture, which can cause fluctuations in the electrical properties of transistors. Therefore, aluminum oxide can prevent the ingress of impurities such as hydrogen and moisture into the transistor 500 during and after the transistor manufacturing process. It can also suppress the release of oxygen from the oxides constituting the transistor 500. For this reason, it is suitable for use as a protective film for transistor 500.

[0358] Furthermore, for example, the same materials as those used for insulator 320 can be used for insulator 512 and insulator 516. Additionally, by applying materials with relatively low dielectric constants to these insulators, parasitic capacitance between wiring can be reduced. For example, silicon oxide films or silicon oxynitride films can be used for insulator 512 and insulator 516.

[0359] Furthermore, insulators 510, 512, 514, and 516 have a conductor 518 and a conductor constituting the transistor 500 (for example, the conductor 503 shown in Figures 13(A) and 13(B)) embedded in them. The conductor 518 functions as a plug or wiring for connecting to the capacitive element 600 or the transistor 300. The conductor 518 can be provided using the same material as the conductors 328 and 330.

[0360] In particular, the conductor 518 in the region in contact with the insulator 510 and the insulator 514 is preferably a conductor having barrier properties against oxygen, hydrogen, and water. With this configuration, transistor 300 and transistor 500 can be separated by a layer having barrier properties against oxygen, hydrogen, and water, and the diffusion of hydrogen from transistor 300 to transistor 500 can be suppressed.

[0361] A transistor 500 is provided above the insulator 516.

[0362] As shown in Figures 13(A) and 13(B), the transistor 500 comprises an insulator 516 on an insulator 514, a conductor 503 (conductor 503a and conductor 503b) arranged to be embedded in the insulator 514 or insulator 516, an insulator 522 on the insulator 516 and on the conductor 503, an insulator 524 on the insulator 522, an oxide 530a on the insulator 524, an oxide 530b on the oxide 530a, a conductor 542a on the oxide 530b, an insulator 571a on the conductor 542a, and acid The device includes a conductor 542b on oxide 530b, an insulator 571b on conductor 542b, an insulator 552 on oxide 530b, an insulator 550 on insulator 552, an insulator 554 on insulator 550, a conductor 560 (conductor 560a and conductor 560b) located on insulator 554 and overlapping with a portion of oxide 530b, and an insulator 544 arranged on insulator 522, insulator 524, oxide 530a, oxide 530b, conductor 542a, conductor 542b, insulator 571a, and insulator 544 on insulator 571b. Here, as shown in Figures 13(A) and 13(B), insulator 552 is in contact with the top surface of insulator 522, the side surface of insulator 524, the side surface of oxide 530a, the side surface and top surface of oxide 530b, the side surface of conductor 542 (conductor 542a and conductor 542b), the side surface of insulator 571 (insulator 571a and insulator 571b), the side surface of insulator 544, the side surface of insulator 580, and the bottom surface of insulator 550. The top surface of conductor 560 is positioned so as to be roughly the same height as the top of insulator 554, the top of insulator 550, the top of insulator 552, and the top surface of insulator 580. Insulator 574 is in contact with at least a portion of the top surface of conductor 560, the top of insulator 552, the top of insulator 550, the top of insulator 554, and the top surface of insulator 580.

[0363] Insulators 580 and 544 are provided with openings that reach oxide 530b. Insulators 552, 550, 554, and 560 are arranged within these openings. In addition, in the channel length direction of transistor 500, conductors 560, 552, 550, and 554 are provided between insulators 571a and conductor 542a, and between insulators 571b and conductor 542b. Insulator 554 has a region in contact with the side surface of conductor 560 and a region in contact with the bottom surface of conductor 560.

[0364] Preferably, the oxide 530 has an oxide 530a disposed on the insulator 524 and an oxide 530b disposed on top of the oxide 530a. By having the oxide 530a below the oxide 530b, the diffusion of impurities from structures formed below the oxide 530a to the oxide 530b can be suppressed.

[0365] Although the transistor 500 is shown as having a configuration in which oxide 530 consists of two layers, oxide 530a and oxide 530b, the present invention is not limited to this. For example, the transistor 500 can have a single layer of oxide 530b or a stacked structure of three or more layers. Alternatively, the oxide 530a and oxide 530b can each have a stacked structure.

[0366] Conductor 560 functions as the first gate (also called the top gate) electrode, and conductor 503 functions as the second gate (also called the back gate) electrode. Insulators 552, 550, and 554 function as the first gate insulators, and insulators 522 and 524 function as the second gate insulators. Note that gate insulators are sometimes called gate insulating layers or gate insulating films. Conductor 542a functions as either the source or the drain, and conductor 542b functions as either the source or the drain. At least a portion of the region of oxide 530 that overlaps with conductor 560 functions as a channel-forming region.

[0367] Here, an enlarged view of the vicinity of the channel formation region in Figure 13(A) is shown in Figure 15(A). When oxygen is supplied to the oxide 530b, a channel formation region is formed in the region between the conductor 542a and the conductor 542b. Therefore, as shown in Figure 15(A), the oxide 530b has a region 530bc that functions as the channel formation region of the transistor 500, and regions 530ba and 530bb that are provided so as to sandwich region 530bc and function as the source region or drain region. At least a portion of region 530bc is superimposed on the conductor 560. In other words, region 530bc is provided in the region between the conductor 542a and the conductor 542b. Region 530ba is provided superimposed on the conductor 542a, and region 530bb is provided superimposed on the conductor 542b.

[0368] Region 530bc, which functions as a channel-forming region, has more oxygen vacancies than regions 530ba and 530bb (in this specification, oxygen vacancies in metal oxides are defined as V O This region is sometimes referred to as (oxygen vacancy). Because the amount of (oxygen) is small or the impurity concentration is low, it is a high-resistance region with a low carrier concentration. Therefore, region 530bc can be said to be type i (intrinsic) or substantially type i.

[0369] In transistors using metal oxides, impurities or oxygen vacancies (V) can be found in the region where the channel is formed within the metal oxide. O The presence of oxygen deficiency (V) can cause fluctuations in electrical properties and reduce reliability. O ) Nearby hydrogen, oxygen vacancy (V O A defect in which hydrogen has entered (hereinafter referred to as V O Sometimes referred to as H, it can form a channel and generate electrons that become carriers. For this reason, if the region in the metal oxide where the channel is formed contains oxygen vacancies, the transistor is prone to becoming normally-on (a state in which the channel exists and current flows through the transistor even without applying voltage to the gate electrode). Therefore, in the region in the metal oxide where the channel is formed, impurities, oxygen vacancies, and V OIt is preferable that H be reduced as much as possible.

[0370] Furthermore, regions 530ba and 530bb, which function as source or drain regions, are oxygen-deficient (V O This region has a high concentration of ) or high concentrations of impurities such as hydrogen, nitrogen, and metallic elements, which increases the carrier concentration and lowers the resistance. In other words, regions 530ba and 530bb are n-type regions with higher carrier concentrations and lower resistance compared to region 530bc.

[0371] Here, the carrier concentration in region 530bc, which functions as a channel-forming region, is 1 × 10⁻⁶. 18 cm -3 The following is preferable: 1 × 10 17 cm -3 It is more preferable that it be less than 1 × 10 16 cm -3 It is even more preferable that it be less than 1 × 10 13 cm -3 It is even more preferable that it be less than 1 × 10 12 cm -3 It is even more preferable that it be less than . There are no particular limitations on the lower limit of the carrier concentration in the region 530bc that functions as a channel-forming region, but for example, 1 × 10 -9 cm -3 It can be done this way.

[0372] Furthermore, a region may be formed between region 530bc and region 530ba or region 530bb, where the carrier concentration is equal to or lower than that of region 530ba and region 530bb, and equal to or higher than that of region 530bc. In other words, this region functions as a junction region between region 530bc and region 530ba or region 530bb. The hydrogen concentration in this junction region may be equal to or lower than that of region 530ba and region 530bb, and equal to or higher than that of region 530bc. Also, the oxygen deficiency in this junction region may be equal to or less than that of region 530ba and region 530bb, and equal to or greater than that of region 530bc.

[0373] Figure 15(A) shows an example in which regions 530ba, 530bb, and 530bc are formed in oxide 530b, but the present invention is not limited to this. For example, each of the above regions may be formed not only in oxide 530b but also in oxide 530a.

[0374] Furthermore, in oxide 530, it can be difficult to clearly detect the boundaries between each region. The concentrations of metal elements, as well as impurity elements such as hydrogen and nitrogen, detected within each region may not be limited to stepwise changes between regions, but may also change continuously within each region. In other words, the closer a region is to the channel formation region, the lower the concentrations of metal elements, as well as impurity elements such as hydrogen and nitrogen should be.

[0375] In transistor 500, it is preferable to use a metal oxide (hereinafter also referred to as an oxide semiconductor) that functions as a semiconductor for the oxide 530 (oxide 530a and oxide 530b) which includes the channel formation region.

[0376] Furthermore, it is preferable to use a metal oxide that functions as a semiconductor and has a band gap of 2 eV or more, preferably 2.5 eV or more. By using a metal oxide with a large band gap in this way, the off-current of the transistor can be reduced.

[0377] As oxide 530, for example, a metal oxide such as In-M-Zn oxide having indium, element M, and zinc (element M is one or more selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium) may be used. Alternatively, In-Ga oxide, In-Zn oxide, or indium oxide may be used for oxide 530.

[0378] Here, it is preferable that the atomic ratio of In to element M in the metal oxide used for oxide 530b is greater than the atomic ratio of In to element M in the metal oxide used for oxide 530a.

[0379] In this way, by placing oxide 530a below oxide 530b, the diffusion of impurities and oxygen from structures formed below oxide 530a to oxide 530b can be suppressed.

[0380] Furthermore, because oxides 530a and 530b share a common element other than oxygen (as a main component), the defect level density at the interface between oxide 530a and oxide 530b can be reduced. Because the defect level density at the interface between oxide 530a and oxide 530b can be reduced, the influence of interfacial scattering on carrier conduction is small, resulting in a high on-current.

[0381] The oxide 530b is preferably crystalline. In particular, it is preferable to use CAAC-OS (c-axis aligned crystalline oxide semiconductor) as the oxide 530b.

[0382] CAAC-OS has a highly crystalline, dense structure and is free from impurities and defects (e.g., oxygen deficiencies (V)). O It is a metal oxide with few impurities (such as). In particular, by heat-treating the metal oxide after its formation at a temperature that does not cause polycrystallization of the metal oxide (for example, between 400°C and 600°C), the CAAC-OS can be made to have a more crystalline and dense structure. By increasing the density of the CAAC-OS in this way, the diffusion of impurities or oxygen in the CAAC-OS can be further reduced.

[0383] On the other hand, because it is difficult to identify clear grain boundaries in CAAC-OS, the decrease in electron mobility caused by grain boundaries is less likely to occur. Therefore, metal oxides containing CAAC-OS have stable physical properties. Consequently, metal oxides containing CAAC-OS are highly heat resistant and reliable.

[0384] In transistors using oxide semiconductors, the electrical properties tend to fluctuate and reliability may be poor if impurities and oxygen vacancies are present in the region where the channel is formed in the oxide semiconductor. Furthermore, hydrogen near the oxygen vacancy can fill the oxygen vacancy, creating a defect (hereinafter referred to as V). O Sometimes called H, it forms a channel and generates electrons that become carriers. For this reason, if the region where the channel is formed in the oxide semiconductor contains oxygen vacancies, the transistor is likely to exhibit normally-on characteristics (a characteristic in which the channel exists and current flows through the transistor even without applying voltage to the gate electrode). Therefore, in the region where the channel is formed in the oxide semiconductor, impurities, oxygen vacancies, and V are likely to be present. O It is preferable that H is reduced as much as possible. In other words, it is preferable that the region in the oxide semiconductor where the channel is formed has a reduced carrier concentration and is type i (intrinsed) or substantially type i.

[0385] In contrast, by placing an insulator containing oxygen that is released by heating (hereinafter sometimes referred to as excess oxygen) near the oxide semiconductor and performing heat treatment, oxygen is supplied from the insulator to the oxide semiconductor, eliminating oxygen deficiencies and V O H can be reduced. However, if an excessive amount of oxygen is supplied to the source or drain region, it may cause a decrease in the on-current of transistor 500 or a decrease in the field-effect mobility. Furthermore, variations in the amount of oxygen supplied to the source or drain region within the substrate surface will result in variations in the characteristics of the semiconductor device containing the transistor.

[0386] Therefore, in an oxide semiconductor, the region 530bc, which functions as a channel-forming region, preferably has a reduced carrier concentration and is i-type or substantially i-type, while the regions 530ba and 530bb, which function as a source region or drain region, preferably have a high carrier concentration and are n-type. In other words, oxygen vacancies in region 530bc of the oxide semiconductor, and V O It is preferable to reduce H so that an excessive amount of oxygen is not supplied to regions 530ba and 530bb.

[0387] Therefore, in this embodiment, with the conductor 542a and conductor 542b placed on the oxide 530b, microwave treatment is performed in an oxygen-containing atmosphere to eliminate oxygen deficiencies in region 530bc, and V O The aim is to reduce H. Here, microwave processing refers to processing using a device that has a power supply that generates high-density plasma using microwaves, for example.

[0388] By performing microwave processing in an oxygen-containing atmosphere, the oxygen gas can be transformed into plasma using microwaves or high-frequency waves such as RF, and this oxygen plasma can be applied. At this time, microwaves or high-frequency waves such as RF can also be irradiated into region 530bc. Due to the action of plasma, microwaves, etc., the V of region 530bc O By cleaving H, hydrogen H is removed from region 530bc, and oxygen is lost V. OIt can be supplemented with oxygen. In other words, in region 530bc, "V O H → H + V O The following reaction occurs, which reduces the hydrogen concentration in region 530bc. Therefore, the oxygen deficiency in region 530bc, and V O This can reduce H and lower the carrier concentration.

[0389] Furthermore, when performing microwave processing in an oxygen-containing atmosphere, the effects of microwaves, high frequencies such as RF, and oxygen plasma are shielded by conductors 542a and 542b and do not reach regions 530ba and 530bb. In addition, the effects of oxygen plasma can be reduced by insulators 571 and 580, which are provided covering oxide 530b and conductor 542. As a result, during microwave processing, V O This prevents a decrease in H and avoids excessive oxygen supply, thus preventing a drop in carrier concentration.

[0390] Furthermore, it is preferable to perform microwave treatment in an oxygen-containing atmosphere after the deposition of the insulating film that will become the insulator 552, or after the deposition of the insulating film that will become the insulator 550. By performing microwave treatment in an oxygen-containing atmosphere via the insulator 552 or insulator 550 in this way, oxygen can be efficiently injected into region 530bc. In addition, by arranging the insulator 552 in contact with the side surface of the conductor 542 and the surface of region 530bc, the injection of more oxygen than necessary into region 530bc can be suppressed, thereby suppressing oxidation of the side surface of the conductor 542. Furthermore, oxidation of the side surface of the conductor 542 can be suppressed when the insulating film that will become the insulator 550 is deposited.

[0391] Furthermore, the oxygen injected into region 530bc can take various forms, such as oxygen atoms, oxygen molecules, and oxygen radicals (also called O radicals, which are atoms or molecules with unpaired electrons, or ions). It is preferable that the oxygen injected into region 530bc be one or more of the above forms, and particularly preferable that it be oxygen radicals. Additionally, the film quality of insulators 552 and 550 can be improved, thereby increasing the reliability of transistor 500.

[0392] In this way, oxygen vacancies are selectively created in the oxide semiconductor region 530bc, and V O By removing H, region 530bc can be made i-type or substantially i-type. Furthermore, it is possible to suppress the supply of excess oxygen to regions 530ba and 530bb, which function as source or drain regions, and maintain the state of the n-type region before microwave processing. This suppresses variations in the electrical characteristics of transistor 500 and reduces variations in the electrical characteristics of transistor 500 within the substrate plane.

[0393] By adopting the above configuration, it is possible to provide a semiconductor device with minimal variation in transistor characteristics. Furthermore, it is possible to provide a semiconductor device with good reliability and excellent electrical characteristics.

[0394] Furthermore, as shown in Figure 13(B), in a cross-sectional view of the transistor 500 in the channel width direction, there may be a curved surface between the side surface and the top surface of the oxide 530b. In other words, the ends of the side surface and the ends of the top surface may be curved (hereinafter also referred to as rounded).

[0395] The radius of curvature of the curved surface is preferably greater than 0 nm and less than the film thickness of the oxide 530b in the region overlapping with the conductor 542, or less than half the length of the region without the curved surface. Specifically, the radius of curvature of the curved surface is greater than 0 nm and 20 nm or less, preferably 1 nm to 15 nm, and more preferably 2 nm to 10 nm. By adopting such a shape, the coverage of the oxide 530b by the insulator 552, insulator 550, insulator 554, and conductor 560 can be improved.

[0396] The oxide 530 preferably has a laminated structure of multiple oxide layers with different chemical compositions. Specifically, in the metal oxide used for oxide 530a, it is preferable that the atomic ratio of element M to the main metal element is greater than the atomic ratio of element M to the main metal element in the metal oxide used for oxide 530b. Furthermore, in the metal oxide used for oxide 530a, it is preferable that the atomic ratio of element M to In is greater than the atomic ratio of element M to In in the metal oxide used for oxide 530b. Furthermore, in the metal oxide used for oxide 530b, it is preferable that the atomic ratio of In to element M is greater than the atomic ratio of In to element M in the metal oxide used for oxide 530a.

[0397] Furthermore, it is preferable that the oxide 530b is a crystalline oxide such as CAAC-OS. Crystalline oxides such as CAAC-OS have few impurities and defects (such as oxygen deficiencies), and possess a dense structure with high crystallinity. Therefore, the extraction of oxygen from the oxide 530b by the source electrode or drain electrode can be suppressed. As a result, even when heat treatment is performed, the extraction of oxygen from the oxide 530b can be reduced, and the transistor 500 is stable against high temperatures (so-called thermal budget) in the manufacturing process.

[0398] Here, at the junction of oxide 530a and oxide 530b, the lower end of the conduction band changes smoothly. In other words, the lower end of the conduction band at the junction of oxide 530a and oxide 530b can be said to change continuously or to be a continuous junction. To achieve this, it is desirable to lower the defect level density of the mixed layer formed at the interface between oxide 530a and oxide 530b.

[0399] Specifically, by having oxides 530a and 530b share a common element other than oxygen as a main component, a mixed layer with a low defect level density can be formed. For example, if oxide 530b is In-M-Zn oxide, oxide 530a may be In-M-Zn oxide, M-Zn oxide, an oxide of element M, In-Zn oxide, or indium oxide.

[0400] Specifically, for oxide 530a, a metal oxide with an atomic ratio of In:M:Zn = 1:3:4 or a similar composition, or an atomic ratio of In:M:Zn = 1:1:0.5 or a similar composition, may be used. Similarly, for oxide 530b, a metal oxide with an atomic ratio of In:M:Zn = 1:1:1 or a similar composition, or an atomic ratio of In:M:Zn = 4:2:3 or a similar composition, may be used. Note that "similar composition" includes a range of ±30% of the desired atomic ratio. Furthermore, it is preferable to use gallium as element M.

[0401] Furthermore, when depositing metal oxide films by sputtering, the above atomic ratio is not limited to the atomic ratio of the deposited metal oxide film, but may also be the atomic ratio of the sputtering target used for depositing the metal oxide film.

[0402] Furthermore, as shown in Figure 13(A), by providing an insulator 552 made of aluminum oxide or the like in contact with the top and side surfaces of the oxide 530, the indium contained in the oxide 530 may be unevenly distributed at and near the interface between the oxide 530 and the insulator 552. As a result, the atomic ratio near the surface of the oxide 530 becomes similar to that of indium oxide, or similar to that of In-Zn oxide. In this way, increasing the atomic ratio of indium near the surface of the oxide 530, especially oxide 530b, can improve the field-effect mobility of the transistor 500.

[0403] By configuring oxides 530a and 530b as described above, the defect level density at the interface between oxide 530a and oxide 530b can be reduced. As a result, the influence of interface scattering on carrier conduction is reduced, and transistor 500 can obtain a large on-current and high frequency characteristics.

[0404] It is preferable that one or more insulators selected from insulators 512, 514, 544, 571, 574, 576, and 581 function as a barrier insulating film that suppresses the diffusion of impurities such as water or hydrogen from the substrate side or from above the transistor 500 into the transistor 500. Therefore, it is preferable that one or more insulators selected from insulators 512, 514, 544, 571, 574, 576, and 581 be an insulating material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (e.g., N2O, NO, or NO2), and copper atoms (i.e., the above impurities do not easily permeate). Alternatively, it is preferable to use an insulating material that has the function of suppressing the diffusion of oxygen (e.g., at least one such as oxygen atoms or oxygen molecules) (i.e., the above oxygen does not easily permeate).

[0405] In this specification, a barrier insulating film refers to an insulating film that has barrier properties. In this specification, barrier properties refer to the function of suppressing the diffusion of the corresponding substance (also called low permeability), or the function of capturing and fixing the corresponding substance (also called gettering).

[0406] For insulators 512, 514, 544, 571, 574, 576, and 581, it is preferable to use insulators that have the function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen. For example, aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, or silicon nitride oxide can be used. For example, silicon nitride, which has higher hydrogen barrier properties, is preferable for insulators 512, 544, and 576. Also, for example, aluminum oxide or magnesium oxide, which has high hydrogen capture and hydrogen fixation functions, is preferable for insulators 514, 571, 574, and 581. This makes it possible to suppress the diffusion of impurities such as water and hydrogen from the substrate side to the transistor 500 side via insulators 512 and 514. Alternatively, it is possible to suppress the diffusion of impurities such as water and hydrogen from the interlayer insulating film located outside the insulator 581 towards the transistor 500. Alternatively, it is possible to suppress the diffusion of oxygen contained in the insulator 524, etc., towards the substrate side via the insulators 512 and 514. Alternatively, it is possible to suppress the diffusion of oxygen contained in the insulator 580, etc., upward from the transistor 500 via the insulator 574. Thus, it is preferable to have a structure in which the transistor 500 is surrounded by insulators 512, 514, 571, 544, 574, 576, and 581, which have the function of suppressing the diffusion of impurities such as water or hydrogen, and oxygen.

[0407] Here, it is preferable to use oxides having an amorphous structure as insulators 512, 514, 544, 571, 574, 576, and 581. For example, AlO x (x is any number greater than 0), or MgO y It is preferable to use a metal oxide such as (y is any number greater than 0). In such an amorphous metal oxide, oxygen atoms have dangling bonds, and these dangling bonds may have the property of capturing or fixing hydrogen. By using such an amorphous metal oxide as a component of the transistor 500, or by providing it around the transistor 500, hydrogen contained in the transistor 500, or hydrogen present around the transistor 500, can be captured or fixed. It is particularly preferable to capture or fix hydrogen contained in the channel formation region of the transistor 500. By using an amorphous metal oxide as a component of the transistor 500, or by providing it around the transistor 500, it is possible to manufacture a transistor 500 and a semiconductor device that have good characteristics and are highly reliable.

[0408] Furthermore, while insulators 512, 514, 544, 571, 574, 576, and 581 are preferably amorphous, they may also have regions of polycrystalline structure. In addition, insulators 512, 514, 544, 571, 574, 576, and 581 may have a multilayer structure in which an amorphous layer and a polycrystalline layer are stacked. For example, a stacked structure in which a polycrystalline layer is formed on top of an amorphous layer may also be possible.

[0409] The insulators 512, 514, 544, 571, 574, 576, and 581 may be deposited using, for example, a sputtering method. Since the sputtering method does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration of insulators 512, 514, 544, 571, 574, 576, and 581 can be reduced. The deposition method is not limited to sputtering, and chemical vapor deposition (CVD), molecular beam epitaxy (MBE), pulsed laser deposition (PLD), or atomic layer deposition (ALD) may be used as appropriate.

[0410] Furthermore, it may be preferable to lower the resistivity of insulators 512, 544, and 576. For example, the resistivity of insulators 512, 544, and 576 may be approximately 1 × 10⁻⁶. 13 By setting the resistivity to Ωcm, insulators 512, 544, and 576 can mitigate charge-up of conductors 503, 542, and 560 during plasma processing in semiconductor device manufacturing. The resistivity of insulators 512, 544, and 576 is preferably 1 × 10⁻⁶. 10 Ωcm or more, 1 × 10 15 The density should be less than or equal to Ωcm.

[0411] Furthermore, it is preferable that insulators 516, 574, 580, and 581 have a lower dielectric constant than insulator 514. By using a material with a low dielectric constant as the interlayer film, parasitic capacitance between wirings can be reduced. For example, silicon oxide, silicon oxynitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, and porous silicon oxide may be used as insulators 516, 580, and 581 as appropriate.

[0412] Furthermore, it is preferable that the insulator 581 functions as an interlayer film and / or a planarization film, for example.

[0413] The conductor 503 is arranged to overlap with the oxide 530 and the conductor 560. Here, it is preferable that the conductor 503 is embedded in an opening formed in the insulator 516. In some cases, a portion of the conductor 503 may be embedded in the insulator 514.

[0414] The conductor 503 comprises a conductor 503a and a conductor 503b. Conductor 503a is provided in contact with the bottom surface and side wall of the opening. Conductor 503b is provided so as to be embedded in a recess formed in conductor 503a. Here, the upper height of conductor 503b is approximately equal to the upper height of conductor 503a and the upper height of insulator 516.

[0415] Here, it is preferable to use a conductive material for the conductor 503a that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (e.g., N2O, NO, and NO2), and copper atoms. Alternatively, it is preferable to use a conductive material that has the function of suppressing the diffusion of oxygen (e.g., either or both of oxygen atoms and oxygen molecules).

[0416] By using a conductive material that has the function of reducing hydrogen diffusion for the conductor 503a, it is possible to prevent impurities such as hydrogen contained in the conductor 503b from diffusing into the oxide 530 via the insulator 524. Furthermore, by using a conductive material that has the function of suppressing oxygen diffusion for the conductor 503a, it is possible to suppress oxidation of the conductor 503b and a decrease in conductivity. For example, it is preferable to use titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, or ruthenium oxide as the conductive material that has the function of suppressing oxygen diffusion. Therefore, the conductor 503a may be a single layer or a laminate of the above conductive material. For example, titanium nitride may be used for the conductor 503a.

[0417] Furthermore, it is preferable that the conductor 503b be a conductive material mainly composed of tungsten, copper, or aluminum. For example, tungsten may be used for the conductor 503b.

[0418] The conductor 503 may function as a second gate electrode. In this case, the threshold voltage (Vth) of transistor 500 can be controlled by changing the potential applied to conductor 503 independently of the potential applied to conductor 560, rather than in conjunction with it. In particular, by applying a negative potential to conductor 503, it is possible to increase the Vth of transistor 500 and reduce the off-current. Therefore, applying a negative potential to conductor 503 reduces the drain current when the potential applied to conductor 560 is 0V compared to not applying a negative potential.

[0419] Furthermore, if the oxide 530 is made of high-purity intrinsic material and impurities are removed from the oxide 530 as much as possible, it may be possible to normally turn off the transistor 500 (make the threshold voltage of the transistor 500 greater than 0V) without applying a potential to one or both of the conductors 503 and 560. In this case, it is preferable to connect the conductor 560 and the conductor 503 so that they are given the same potential.

[0420] Furthermore, the electrical resistivity of the conductor 503 is designed considering the potential applied to the conductor 503, and the film thickness of the conductor 503 is set to match this electrical resistivity. The film thickness of the insulator 516 is approximately the same as that of the conductor 503. Here, it is preferable to make the film thicknesses of the conductor 503 and the insulator 516 as thin as possible within the limits permitted by the design of the conductor 503. By making the film thickness of the insulator 516 thin, the absolute amount of impurities such as hydrogen contained in the insulator 516 can be reduced, thereby reducing the diffusion of these impurities into the oxide 530.

[0421] Furthermore, the conductor 503 should be larger than the area of ​​the oxide 530 that does not overlap with the conductors 542a and 542b when viewed from above. In particular, as shown in Figure 13(B), it is preferable that the conductor 503 extends to the area outside the ends of the oxide 530a and oxide 530b in the channel width direction. That is, it is preferable that the conductor 503 and the conductor 560 are superimposed on the outside of the side surface of the oxide 530 in the channel width direction, with an insulator in between. With this configuration, the channel formation region of the oxide 530 can be electrically surrounded by the electric field of the conductor 560 which functions as the first gate electrode and the electric field of the conductor 503 which functions as the second gate electrode. In this specification, a transistor structure in which the channel formation region is electrically surrounded by the electric fields of the first gate and the second gate is called a surrounded channel (S-channel) structure.

[0422] In this specification, an S-channel transistor refers to a transistor structure in which the channel formation region is electrically surrounded by the electric fields of one and the other of a pair of gate electrodes. Furthermore, the S-channel structure disclosed in this specification is different from the Fin-type structure and the Planar-type structure. By adopting an S-channel structure, it is possible to create a transistor that has improved resistance to short-channel effects, or in other words, a transistor in which short-channel effects are less likely to occur.

[0423] By setting transistor 500 to normally off and adopting the above-described S-Channel structure, the channel formation region can be electrically surrounded. Therefore, transistor 500 can also be considered as a GAA (Gate All Around) structure or an LGAA (Lateral Gate All Around) structure. By making transistor 500 an S-Channel, GAA, or LGAA structure, the channel formation region formed at or near the interface between oxide 530 and the gate insulating film can be the entire bulk of oxide 530. In other words, by making transistor 500 an S-Channel, GAA, or LGAA structure, it can be made into a so-called bulk-flow type, using the entire bulk as the carrier path. By adopting a bulk-flow type transistor structure, it is possible to improve the current density flowing through the transistor, and thus an improvement in the transistor's on-current or an increase in the transistor's field-effect mobility can be expected.

[0424] Furthermore, as shown in Figure 13(B), the conductor 503 is extended to function as wiring. However, the configuration is not limited to this, and a conductor that functions as wiring may be provided beneath the conductor 503. Also, it is not necessary to provide one conductor 503 for each transistor. For example, the conductor 503 may be shared by multiple transistors.

[0425] In the transistor 500, the conductor 503 is shown as a stacked structure of conductor 503a and conductor 503b, but the present invention is not limited to this. For example, the conductor 503 may be provided as a single layer or as a stacked structure of three or more layers.

[0426] Insulators 522 and 524 function as gate insulators.

[0427] Preferably, the insulator 522 has the function of suppressing the diffusion of hydrogen (e.g., hydrogen atoms and / or hydrogen molecules). Furthermore, preferably, the insulator 522 has the function of suppressing the diffusion of oxygen (e.g., oxygen atoms and / or oxygen molecules). For example, it is preferable that the insulator 522 has a function of suppressing the diffusion of hydrogen and / or oxygen more effectively than the insulator 524.

[0428] The insulator 522 may be an insulator containing an oxide of either or both of the insulating materials aluminum and hafnium. Preferably, the insulator is an oxide containing aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate). When the insulator 522 is formed using such a material, the insulator 522 functions as a layer that suppresses the release of oxygen from the oxide 530 to the substrate side and the diffusion of impurities such as hydrogen from the periphery of the transistor 500 to the oxide 530. Therefore, by providing the insulator 522, it is possible to suppress the diffusion of impurities such as hydrogen into the inside of the transistor 500 and suppress the generation of oxygen vacancies in the oxide 530. In addition, it is possible to suppress the reaction of the conductor 503 with the oxygen contained in the insulator 524 or the oxide 530.

[0429] Alternatively, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to the above-mentioned insulator. Alternatively, these insulators may be subjected to nitriding treatment. Furthermore, insulator 522 may be used by laminating silicon oxide, silicon oxide nitride, or silicon nitride onto these insulators.

[0430] Furthermore, the insulator 522 may be a single-layer or multi-layer insulator containing so-called high-k materials, such as aluminum oxide, hafnium oxide, tantalum oxide, or zirconium oxide. As transistors become smaller and more integrated, thinning of the gate insulator can lead to problems such as leakage current. By using a high-k material as the insulator that functions as the gate insulator, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness. In addition, materials with high dielectric constants, such as lead zirconate titanate (PZT), strontium titanate (SrTiO3), and (Ba,Sr)TiO3 (BST), may also be used as the insulator 522.

[0431] The insulator 524 in contact with the oxide 530 may be, for example, silicon oxide or silicon oxide nitride as appropriate.

[0432] Furthermore, during the manufacturing process of the transistor 500, it is preferable to perform a heat treatment while the surface of the oxide 530 is exposed. This heat treatment may be performed at, for example, 100°C to 600°C, more preferably 350°C to 550°C. The heat treatment should be performed in an atmosphere of nitrogen gas or an inert gas, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, it is preferable to perform the heat treatment in an oxygen atmosphere. This supplies oxygen to the oxide 530, thereby preventing oxygen deficiency (V O This can reduce the amount of oxygen released. The heat treatment may also be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere of nitrogen gas or an inert gas, and then in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to replenish the oxygen that has been removed. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas, and then continuously in an atmosphere of nitrogen gas or an inert gas.

[0433] Furthermore, by performing an oxygenation treatment on oxide 530, oxygen deficiencies in oxide 530 are repaired by the supplied oxygen, or in other words, "V OThis can accelerate the reaction "+O→null". Furthermore, the oxygen supplied reacts with the hydrogen remaining in oxide 530, removing the hydrogen as H2O (dehydration). As a result, the hydrogen remaining in oxide 530 recombines with the oxygen vacancy and V O This can suppress the formation of H.

[0434] Furthermore, the insulators 522 and 524 may have a laminated structure of two or more layers. In this case, the laminated structure is not limited to being made of the same material, but may be made of different materials. Also, the insulator 524 may be superimposed with the oxide 530a to form an island-like structure. In this case, the insulator 544 will be in contact with the side surface of the insulator 524 and the upper surface of the insulator 522.

[0435] Conductors 542a and 542b are provided in contact with the upper surface of oxide 530b. Conductors 542a and 542b function as the source electrode or drain electrode of transistor 500, respectively.

[0436] For the conductor 542 (conductor 542a and conductor 542b), it is preferable to use, for example, a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, or a nitride containing titanium and aluminum. In one embodiment of the present invention, a nitride containing tantalum is particularly preferred. Alternatively, for example, ruthenium oxide or ruthenium nitride may be used. Alternatively, for example, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel may be used. These materials are preferred because they are conductive materials that are resistant to oxidation or materials that maintain conductivity even when absorbing oxygen.

[0437] Furthermore, hydrogen contained in oxide 530b, etc., may diffuse into conductor 542a or conductor 542b. In particular, by using tantalum-containing nitrides for conductor 542a and conductor 542b, hydrogen contained in oxide 530b, etc., is more likely to diffuse into conductor 542a or conductor 542b, and the diffused hydrogen may combine with nitrogen present in conductor 542a or conductor 542b. In other words, hydrogen contained in oxide 530b, etc., may be absorbed by conductor 542a or conductor 542b.

[0438] Furthermore, it is preferable that no curved surface is formed between the side surface of the conductor 542 and the top surface of the conductor 542. By using a conductor 542 without such a curved surface, the cross-sectional area of ​​the conductor 542 in the channel width direction can be increased. This increases the conductivity of the conductor 542 and increases the on-current of the transistor 500.

[0439] The insulator 571a is provided in contact with the upper surface of the conductor 542a, and the insulator 571b is provided in contact with the upper surface of the conductor 542b. It is preferable that the insulator 571 functions as at least a barrier insulating film against oxygen. Therefore, it is preferable that the insulator 571 has a function to suppress the diffusion of oxygen. For example, it is preferable that the insulator 571 has a function to suppress the diffusion of oxygen more than the insulator 580. For the insulator 571, for example, a silicon-containing nitride such as silicon nitride may be used. It is also preferable that the insulator 571 has a function to capture impurities such as hydrogen. In that case, it is preferable that the insulator 571 is a metal oxide having an amorphous structure (for example, an insulator such as aluminum oxide or magnesium oxide). In particular, it is preferable to use aluminum oxide having an amorphous structure, or aluminum oxide with an amorphous structure, as the insulator 571, because it may be possible to capture or fix hydrogen more effectively. This makes it possible to manufacture a transistor 500 and semiconductor device with good characteristics and high reliability.

[0440] The insulator 544 is provided so as to cover the insulator 524, oxide 530a, oxide 530b, conductor 542, and insulator 571. Preferably, the insulator 544 has the function of capturing and fixing hydrogen. In that case, preferably the insulator 544 contains silicon nitride or a metal oxide having an amorphous structure (for example, an insulator such as aluminum oxide or magnesium oxide). Alternatively, for example, the insulator 544 may be a laminated film of aluminum oxide and silicon nitride on the aluminum oxide.

[0441] By providing the insulators 571 and 544 as described above, the conductor 542 can be surrounded by an insulator that has barrier properties against oxygen. In other words, the oxygen contained in insulators 524 and 580 can be prevented from diffusing into the conductor 542. This prevents the conductor 542 from being directly oxidized by the oxygen contained in insulators 524 and 580, which would increase its resistivity and reduce the on-current.

[0442] The insulator 552 functions as part of the gate insulator. It is preferable to use an oxygen barrier insulating film for the insulator 552. The insulator 552 may be any insulator that can be used for the insulator 574 described above. The insulator 552 may be an insulator containing an oxide of either or both aluminum and hafnium. Suitable insulators include aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), an oxide containing hafnium and silicon (hafnium silicate), and the like. In this embodiment, aluminum oxide is used for the insulator 552. In this case, the insulator 552 is an insulator containing at least oxygen and aluminum.

[0443] As shown in Figure 13(B), the insulator 552 is provided in contact with the top and side surfaces of oxide 530b, the side surface of oxide 530a, the side surface of insulator 524, and the top surface of insulator 522. In other words, the regions of oxide 530a, oxide 530b, and insulator 524 that overlap with the conductor 560 are covered by the insulator 552 in the cross-section in the channel width direction. This allows the insulator 552, which has an oxygen barrier property, to block the desorption of oxygen from oxide 530a and oxide 530b during heat treatment, etc. Thus, the formation of oxygen vacancies (Vo) in oxide 530a and oxide 530b can be reduced. O H can be reduced. Therefore, the electrical characteristics of transistor 500 can be improved, and its reliability can be enhanced.

[0444] Conversely, even if an excess amount of oxygen is present in the insulator 580 and insulator 550, it is possible to suppress the excessive supply of such oxygen to oxides 530a and 530b. Therefore, it is possible to suppress the excessive oxidation of regions 530ba and 530bb via region 530bc, which would otherwise cause a decrease in the on-current of transistor 500 or a decrease in field-effect mobility.

[0445] Furthermore, as shown in Figure 13(A), the insulator 552 is provided in contact with the sides of the conductor 542, the insulator 544, and the insulator 580. Therefore, oxidation of the side surface of the conductor 542 and the formation of an oxide film on that side surface can be reduced. This makes it possible to suppress a decrease in the on-current of the transistor 500 or a decrease in the field-effect mobility.

[0446] Furthermore, the insulator 552, along with the insulator 554, the insulator 550, and the conductor 560, must be provided in the opening formed in the insulator 580 or the like. When miniaturizing the transistor 500, it is preferable that the film thickness of the insulator 552 be thin. The film thickness of the insulator 552 is preferably 0.1 nm or more, 0.5 nm or more, or 1.0 nm or more, and preferably 1.0 nm or less, 3.0 nm or less, or 5.0 nm or less. The above-mentioned lower and upper limits can be combined. In this case, it is sufficient that the insulator 552 has a region with the above-mentioned film thickness in at least a part of it. Furthermore, it is preferable that the film thickness of the insulator 552 is thinner than the film thickness of the insulator 550. In this case, it is sufficient that the insulator 552 has a region with a thinner film thickness than the insulator 550 in at least a part of it.

[0447] To deposit the insulator 552 with a thin film thickness as described above, it is preferable to use the ALD method. ALD methods include thermal ALD, which uses only thermal energy for the reaction between the precursor and reactant, and PEALD (Plasma Enhanced ALD), which uses a plasma-excited reactant. The PEALD method is preferable in some cases because the use of plasma allows for film deposition at lower temperatures.

[0448] The ALD method allows for the deposition of atoms layer by layer, resulting in several advantages: the ability to deposit extremely thin films, films on structures with high aspect ratios, films with fewer defects such as pinholes, films with excellent coverage, and films at low temperatures. Therefore, the insulator 552 can be deposited with good coverage on the sides of openings formed in the insulator 580, etc., with the thin film thickness described above.

[0449] Note that precursors used in the ALD method may contain carbon and other impurities. Therefore, films formed by the ALD method may contain more carbon and other impurities compared to films formed by other film deposition methods. The quantity of impurities can be quantified using secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectroscopy (XPS).

[0450] The insulator 550 functions as part of the gate insulator. It is preferable that the insulator 550 is placed in contact with the upper surface of the insulator 552. The insulator 550 can be silicon oxide, silicon oxynitride, silicon nitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, or silicon oxide with vacancies. In particular, silicon oxide and silicon oxynitride are preferred because they are stable with respect to heat. In this case, the insulator 550 will be an insulator having at least oxygen and silicon.

[0451] Similar to the insulator 524, it is preferable that the concentration of impurities such as water and hydrogen in the insulator 550 is reduced. The film thickness of the insulator 550 is preferably 1 nm or more, or 0.5 nm or more, and preferably 15 nm or less, or 20 nm or less. The lower and upper limits mentioned above can be combined. In this case, it is sufficient that the insulator 550 has a region with the above-mentioned film thickness in at least a part of it.

[0452] Figures 13(A) and 13(B) show a configuration in which the insulator 550 is a single layer, but the present invention is not limited to this, and a laminated structure of two or more layers is also possible. For example, as shown in Figure 15(B), the insulator 550 may be a laminated structure of two layers: an insulator 550a and an insulator 550b on top of the insulator 550a.

[0453] As shown in Figure 15(B), when the insulator 550 has a two-layer laminated structure, it is preferable that the lower insulator 550a is formed using an insulator that is permeable to oxygen, and the upper insulator 550b is formed using an insulator that has the function of suppressing the diffusion of oxygen. With this configuration, it is possible to suppress the diffusion of oxygen contained in the insulator 550a to the conductor 560. In other words, it is possible to suppress the reduction in the amount of oxygen supplied to the oxide 530. Furthermore, it is possible to suppress the oxidation of the conductor 560 by the oxygen contained in the insulator 550a. For example, the insulator 550a may be made using a material that can be used for the insulator 550 as described above, and the insulator 550b may be an insulator containing an oxide of either aluminum or hafnium or both. As such an insulator, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), an oxide containing hafnium and silicon (hafnium silicate), etc., can be used. In this embodiment, hafnium oxide is used as the insulator 550b. In this case, the insulator 550b is an insulator having at least oxygen and hafnium. Furthermore, the film thickness of the insulator 550b is preferably 0.5 nm or more, or 1.0 nm or more, and preferably 3.0 nm or less, or 5.0 nm or less. The above-mentioned lower and upper limits can be combined. In this case, the insulator 550b only needs to have a region with the above-mentioned film thickness in at least a portion of it.

[0454] Furthermore, when silicon oxide, silicon oxynitride, or the like is used for insulator 550a, insulator 550b may be an insulating material that is a high-k material with a high dielectric constant. By making the gate insulator a laminated structure of insulator 550a and insulator 550b, a laminated structure that is stable against heat and has a high dielectric constant can be made. Therefore, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical film thickness of the gate insulator. In addition, it is possible to make the equivalent oxide film thickness (EOT) of the insulator that functions as a gate insulator thinner. Thus, the dielectric breakdown voltage of insulator 550 can be increased.

[0455] The insulator 554 functions as part of the gate insulator. Preferably, a barrier insulating film against hydrogen is used as the insulator 554. This prevents impurities such as hydrogen contained in the conductor 560 from diffusing into the insulator 550 and oxide 530b. The insulator 554 can be any insulator that can be used for the insulator 576 described above. For example, silicon nitride deposited by the PEALD method can be used as the insulator 554. In this case, the insulator 554 will be an insulator containing at least nitrogen and silicon.

[0456] Furthermore, the insulator 554 may also have barrier properties against oxygen. This can suppress the diffusion of oxygen contained in the insulator 550 into the conductor 560.

[0457] Furthermore, the insulator 554, along with the insulator 552, the insulator 550, and the conductor 560, must be provided in an opening formed in the insulator 580 or the like. In order to miniaturize the transistor 500, it is preferable that the film thickness of the insulator 554 be thin. The film thickness of the insulator 554 is preferably 0.1 nm or more, 0.5 nm or more, or 1.0 nm or more, and preferably 3.0 nm or less, or 5.0 nm or less. The above-mentioned lower and upper limits can be combined. In this case, it is sufficient that the insulator 554 has a region with the above-mentioned film thickness in at least a part of it. Furthermore, it is preferable that the film thickness of the insulator 554 is thinner than the film thickness of the insulator 550. In this case, it is sufficient that the insulator 554 has a region with a thinner film thickness than the insulator 550 in at least a part of it.

[0458] The conductor 560 functions as the first gate electrode of the transistor 500. Preferably, the conductor 560 has a conductor 560a and a conductor 560b disposed on top of the conductor 560a. For example, it is preferable that the conductor 560a is arranged to enclose the bottom and sides of the conductor 560b. Also, as shown in Figures 13(A) and 13(B), the height of the top of the conductor 560 roughly coincides with the height of the top of the insulator 550. In Figures 13(A) and 13(B), the conductor 560 is shown as a two-layer structure of conductor 560a and conductor 560b, but the conductor 560 can also have a single-layer structure or a stacked structure of three or more layers.

[0459] It is preferable to use a conductive material for the conductor 560a that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, or copper atoms. Alternatively, it is preferable to use a conductive material that has the function of suppressing the diffusion of oxygen (for example, one or more selected from oxygen atoms and oxygen molecules).

[0460] Furthermore, because the conductor 560a has the function of suppressing oxygen diffusion, it is possible to suppress the oxidation of the conductor 560b by the oxygen contained in the insulator 550, which would otherwise reduce its conductivity. For the conductive material that has the function of suppressing oxygen diffusion, it is preferable to use, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, or ruthenium oxide.

[0461] Furthermore, since the conductor 560 also functions as wiring, it is preferable to use a conductor with high conductivity. For example, the conductor 560b can be a conductive material mainly composed of tungsten, copper, or aluminum. The conductor 560b can also be in a laminated structure. Specifically, for example, the conductor 560b can be a laminated structure of titanium, or titanium nitride, and the above conductive material.

[0462] Furthermore, in transistor 500, the conductor 560 is formed self-aligningly to fill the openings formed in the insulator 580 and the like. By forming the conductor 560 in this way, the conductor 560 can be reliably positioned in the region between the conductors 542a and 542b without the need for alignment.

[0463] Furthermore, as shown in Figure 13(B), in the channel width direction of the transistor 500, it is preferable that the height of the bottom surface of the region of the conductor 560 that does not overlap with the oxide 530b, with reference to the bottom surface of the insulator 522, is lower than the height of the bottom surface of the oxide 530b. By configuring the conductor 560, which functions as a gate electrode, to cover the side and top surfaces of the channel formation region of the oxide 530b via an insulator 550 or the like, it becomes easier to apply the electric field of the conductor 560 to the entire channel formation region of the oxide 530b. Therefore, the on-current of the transistor 500 can be increased and the frequency characteristics can be improved. With respect to the bottom surface of the insulator 522, the difference between the height of the bottom surface of the conductor 560 and the height of the bottom surface of oxide 530b in the region where the oxides 530a and 530b and the conductor 560 do not overlap is preferably 0 nm or more, 3 nm or more, or 5 nm or more, and preferably 20 nm or less, 50 nm or less, or 100 nm or less. The above-mentioned lower and upper limits can be combined.

[0464] The insulator 580 is provided on the insulator 544, and openings are formed in the regions where the insulator 550 and the conductor 560 are provided. The upper surface of the insulator 580 may also be flattened.

[0465] The insulator 580, which functions as an interlayer film, preferably has a low dielectric constant. By using a material with a low dielectric constant as the interlayer film, parasitic capacitance occurring between wiring can be reduced. The insulator 580 is preferably made of the same material as the insulator 516, for example. Silicon oxide and silicon oxynitride are particularly preferred because they are thermally stable. Materials such as silicon oxide, silicon oxynitride, and silicon oxide with vacancies are particularly preferred because they can easily form regions containing oxygen that is desorbed by heating.

[0466] Preferably, the insulator 580 has reduced concentrations of impurities such as water and hydrogen. For example, the insulator 580 may be made of silicon oxide or silicon oxidnitride, which is a silicon-containing oxide.

[0467] The insulator 574 preferably functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen into the insulator 580 from above, and preferably has the function of capturing impurities such as hydrogen. Furthermore, the insulator 574 preferably functions as a barrier insulating film that suppresses the permeation of oxygen. As the insulator 574, an amorphous metal oxide, such as aluminum oxide, may be used. In this case, the insulator 574 will be an insulator having at least oxygen and aluminum. By providing an insulator 574 in the region sandwiched between the insulator 512 and the insulator 580, in contact with the insulator 580, and having the function of capturing impurities such as hydrogen, impurities such as hydrogen contained in the insulator 580 can be captured, and the amount of hydrogen in that region can be kept constant. In particular, using amorphous aluminum oxide as the insulator 574 is preferable because it may be possible to capture or fix hydrogen more effectively. This makes it possible to manufacture a transistor 500 and a semiconductor device with good characteristics and high reliability.

[0468] The insulator 576 functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen into the insulator 580 from above. The insulator 576 is placed on top of the insulator 574. Preferably, the insulator 576 is a silicon-containing nitride such as silicon nitride or silicon nitride oxide. For example, silicon nitride deposited by sputtering may be used as the insulator 576. By depositing the insulator 576 by sputtering, a high-density silicon nitride film can be formed. Alternatively, as the insulator 576, silicon nitride deposited by PEALD or CVD may be laminated on top of the silicon nitride deposited by sputtering.

[0469] Furthermore, one of the first or second terminals of transistor 500 is electrically connected to conductor 540a, which functions as a plug, and the other of the first or second terminal of transistor 500 is electrically connected to conductor 540b. In this specification, conductors 540a and conductor 540b are collectively referred to as conductor 540.

[0470] As an example, the conductor 540a is provided in a region that overlaps with the conductor 542a. Specifically, in the region that overlaps with the conductor 542a, openings are formed in the insulators 571, 544, 580, 574, 576, and 581 shown in Figure 13(A), as well as insulators 582 and 586 shown in Figure 12, and the conductor 540a shown in Figure 13(A) is provided inside these openings. Furthermore, as an example, the conductor 540b is provided in a region that overlaps with the conductor 542b. Specifically, in the region overlapping with the conductor 542b, openings are formed in the insulators 571, 544, 580, 574, 576, and 581 shown in Figure 13(A), as well as insulators 582 and 586 shown in Figure 12, and the conductor 540b is provided inside these openings. Insulators 582 and 586 will be described later.

[0471] Furthermore, as shown in Figure 13(A), an insulator 541a may be provided between the side surface of the opening in the region overlapping with the conductor 542a and the conductor 540a, as an insulator that provides a barrier against impurities. Similarly, an insulator 541b may be provided between the side surface of the opening in the region overlapping with the conductor 542b and the conductor 540b, as an insulator that provides a barrier against impurities. In this specification, insulators 541a and 541b will be collectively referred to as insulator 541.

[0472] It is preferable that the conductors 540a and 540b are made of conductive materials mainly composed of tungsten, copper, or aluminum. Furthermore, the conductors 540a and 540b may be arranged in a laminated structure.

[0473] Furthermore, when the conductor 540 has a laminated structure, it is preferable to use a conductive material that has the function of suppressing the permeation of impurities such as water and hydrogen for the first conductor arranged in the vicinity of the insulators 574, 576, 581, 580, 544, and 571. For example, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide. The conductive material that has the function of suppressing the permeation of impurities such as water and hydrogen may also be used in a single layer or a laminate. In addition, it is possible to suppress the mixing of impurities such as water and hydrogen contained in the layer above insulator 576 into the oxide 530 through conductor 540a and conductor 540b.

[0474] As insulators 541a and 541b, any barrier insulating film that can be used for insulator 544 and the like may be used. For example, insulators 541a and 541b may be silicon nitride, aluminum oxide, or silicon nitride oxide. Since insulators 541a and 541b are provided in contact with insulators 574, 576, and 571, it is possible to suppress the mixing of impurities such as water and hydrogen contained in insulator 580 and the like into the oxide 530 through conductors 540a and 540b. Silicon nitride is particularly suitable because it has high blocking properties for hydrogen. In addition, it is possible to prevent oxygen contained in insulator 580 from being absorbed by conductors 540a and 540b.

[0475] When the insulators 541a and 541b are arranged in a laminated structure as shown in Figure 13(A), it is preferable that the first insulator in contact with the inner wall of the opening, such as the insulator 580, and the second insulator inside it, use a combination of an oxygen barrier insulating film and a hydrogen barrier insulating film.

[0476] For example, aluminum oxide deposited by the ALD method can be used as the first insulator, and silicon nitride deposited by the PEALD method can be used as the second insulator. This configuration suppresses oxidation of the conductor 540 and further reduces the incorporation of hydrogen into the conductor 540.

[0477] While the transistor 500 shows a configuration in which the first insulator and the second conductor of the insulator 541 are stacked, the present invention is not limited thereto. For example, the insulator 541 may be provided as a single layer or as a stacked structure of three or more layers. Similarly, while the transistor 500 shows a configuration in which the first conductor and the second conductor of the conductor 540 are stacked, the present invention is not limited thereto. For example, the conductor 540 may be provided as a single layer or as a stacked structure of three or more layers.

[0478] Furthermore, as shown in Figure 12, conductors 610 and 612 may be placed in contact with the upper part of conductor 540a and the upper part of conductor 540b, respectively, to function as wiring. It is preferable that conductors 610 and 612 be made of conductive materials mainly composed of tungsten, copper, or aluminum. The conductors may also be in a laminated structure. Specifically, for example, the conductor may be a laminate of titanium or titanium nitride and the conductive material. The conductors may also be formed to be embedded in an opening provided in the insulator.

[0479] The structure of the transistor included in one embodiment of the present invention is not limited to the transistor 500 shown in Figures 12, 13(A), 13(B), and 14. The structure of the transistor included in one embodiment of the present invention may be changed depending on the circumstances.

[0480] For example, the transistor 500 shown in Figures 12, 13(A), 13(B), and 14 may have the configuration shown in Figure 16. The transistor in Figure 16 differs from the transistor 500 shown in Figures 12, 13(A), 13(B), and 14 in that it has oxide 543a and oxide 543b. In this specification, oxide 543a and oxide 543b will be collectively referred to as oxide 543. Furthermore, the cross-sectional configuration in the channel width direction of the transistor in Figure 16 can be the same as the cross-sectional configuration of the transistor 500 shown in Figure 13(B).

[0481] The oxide 543a is provided between the oxide 530b and the conductor 542a, and the oxide 543b is provided between the oxide 530b and the conductor 542b. Here, it is preferable that the oxide 543a is in contact with the upper surface of the oxide 530b and the lower surface of the conductor 542a. It is also preferable that the oxide 543b is in contact with the upper surface of the oxide 530b and the lower surface of the conductor 542b.

[0482] It is preferable that the oxide 543 has the function of suppressing oxygen permeation. Placing the oxide 543, which has the function of suppressing oxygen permeation, between the conductor 542, which functions as a source electrode or drain electrode, and the oxide 530b is preferable because it reduces the electrical resistance between the conductor 542 and the oxide 530b. With such a configuration, it may be possible to improve the electrical characteristics, field effect mobility, and reliability of the transistor 500.

[0483] Furthermore, a metal oxide containing element M may be used as oxide 543. In particular, element M may be aluminum, gallium, yttrium, or tin. It is also preferable that oxide 543 has a higher concentration of element M than oxide 530b. Gallium oxide may also be used as oxide 543. Furthermore, a metal oxide such as In-M-Zn oxide may be used as oxide 543. Specifically, in the metal oxide used for oxide 543, it is preferable that the atomic ratio of element M to In is greater than the atomic ratio of element M to In in the metal oxide used for oxide 530b. Furthermore, the film thickness of oxide 543 is preferably 0.5 nm or more, or 1 nm or more, and preferably 2 nm or less, 3 nm or less, or 5 nm or less. The above-mentioned lower and upper limits can be combined. Furthermore, it is preferable that oxide 543 is crystalline. When oxide 543 is crystalline, the release of oxygen in oxide 530 can be suitably suppressed. For example, if oxide 543 has a hexagonal crystal structure, it may be possible to suppress the release of oxygen from oxide 530.

[0484] An insulator 582 is provided on the insulator 581, and an insulator 586 is provided on the insulator 582.

[0485] It is preferable to use a material that provides barrier properties against oxygen and hydrogen for the insulator 582. Therefore, the same material as that used for the insulator 514 can be used for the insulator 582. For example, it is preferable to use a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide for the insulator 582.

[0486] Furthermore, the insulator 586 can be made of the same material as the insulator 320. Additionally, by applying materials with relatively low dielectric constants to these insulators, parasitic capacitance between wirings can be reduced. For example, a silicon oxide film or a silicon oxynitride film can be used as the insulator 586.

[0487] Next, we will describe the capacitive element 600 and its surrounding wiring or plug, which are included in the semiconductor device shown in Figures 12 and 14. Note that the capacitive element 600, wiring, and / or plug are provided above the transistor 500 shown in Figures 12 and 14.

[0488] The capacitive element 600 includes, as an example, a conductor 610, a conductor 620, and an insulator 630.

[0489] A conductor 610 is provided on either the conductor 540a or the conductor 540b, the conductor 546, and the insulator 586. The conductor 610 functions as one of the pair of electrodes of the capacitive element 600.

[0490] Furthermore, a conductor 612 is provided on the other of the conductor 540a or conductor 540b, and on the insulator 586. The conductor 612 functions as a plug, wire, or terminal that electrically connects the transistor 500 with circuit elements, wiring, etc., arranged above it.

[0491] Note that the conductor 612 and the conductor 610 may be formed at the same time.

[0492] Conductors 612 and 610 can be made of a metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, or scandium, or a metal nitride film (tantalum nitride film, titanium nitride film, molybdenum nitride film, tungsten nitride film) composed of the above elements. Alternatively, conductive materials such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide with added silicon oxide can also be used.

[0493] In Figure 12, the conductors 612 and 610 are shown as single-layer structures, but the configuration is not limited to this, and a laminated structure of two or more layers is also possible. For example, a conductor with high adhesion to both the barrier conductor and the highly conductive conductor may be formed between the barrier conductor and the highly conductive conductor.

[0494] An insulator 630 is provided on the insulator 586 and the conductor 610. The insulator 630 functions as a dielectric sandwiched between the pair of electrodes of the capacitive element 600.

[0495] For example, the insulator 630 can be silicon oxide, silicon oxide nitride, silicon oxide nitride, silicon nitride, aluminum oxide, aluminum oxide nitride, aluminum oxide nitride, aluminum nitride, hafnium oxide, hafnium oxide nitride, hafnium oxide nitride, hafnium nitride, or zirconium oxide. The insulator 630 can also be provided as a laminate or a single layer using the above-mentioned materials.

[0496] Furthermore, for example, the insulator 630 may be a laminated structure of a material with high dielectric strength, such as silicon oxidnitride, and a high dielectric constant (high-k) material. With this configuration, the capacitive element 600 can secure sufficient capacitance by having a high dielectric constant (high-k) insulator, and the dielectric strength is improved by having an insulator with high dielectric strength, thereby suppressing electrostatic discharge breakdown of the capacitive element 600.

[0497] Examples of high-dielectric constant (high-k) materials (materials with a high relative permittivity) that act as insulators include gallium oxide, hafnium oxide, and zirconium oxide. Other examples include oxides having aluminum and hafnium, oxidized nitrides having aluminum and hafnium, oxides having silicon and hafnium, oxidized nitrides having silicon and hafnium, or nitrides having silicon and hafnium.

[0498] Alternatively, the insulator 630 may be a single-layer or multi-layer insulator containing a high-k material such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST). Furthermore, the insulator 630 may be a compound containing hafnium and zirconium. As semiconductor devices become more miniaturized and integrated, thinning of the dielectric material used for the gate insulator and capacitive elements can lead to problems such as leakage current in transistors or capacitive elements. By using high-k materials for the gate insulator and the dielectric material used for capacitive elements, it becomes possible to reduce the gate potential during transistor operation and ensure the capacitance of the capacitive element while maintaining the physical film thickness.

[0499] In particular, by using a material that can have ferroelectric properties for the insulator 630, for example, the capacitive element 600 can be used as a ferroelectric capacitor.

[0500] A conductor 620 is provided so as to be superimposed on the conductor 610 via an insulator 630. The conductor 610 functions as one of a pair of electrodes of the capacitive element 600.

[0501] The conductor 620 can be made of conductive materials such as metal materials, alloy materials, or metal oxide materials. It is preferable to use high-melting-point materials such as tungsten or molybdenum, which offer both heat resistance and conductivity, and tungsten is particularly preferred. When forming the conductor simultaneously with other structures such as conductors, low-resistance metallic materials such as Cu (copper) or Al (aluminum) may be used. For example, the conductor 620 can be made of a material applicable to the conductor 610. Furthermore, the conductor 620 may be a laminated structure of two or more layers, rather than a single-layer structure.

[0502] An insulator 640 is provided on the conductor 620 and the insulator 630. For the insulator 640, it is preferable to use a film with barrier properties that prevents impurities such as hydrogen from diffusing into the region where the transistor 500 is located. Therefore, the same material as that used for the insulator 324 can be used.

[0503] An insulator 650 is provided on the insulator 640. The insulator 650 can be provided using the same material as the insulator 320. The insulator 650 may also function as a planarizing film that covers the uneven shape below it. Therefore, the insulator 650 can be made of a material that can be applied to, for example, the insulator 324.

[0504] Incidentally, although the capacitive element 600 shown in Figures 12 and 14 is of the planar type, the shape of the capacitive element is not limited to this. The capacitive element 600 may be of a cylindrical type, for example, instead of a planar type.

[0505] Furthermore, a wiring layer may be provided above the capacitive element 600. For example, in Figure 12, insulators 411, 412, 413, and 414 are provided in order above the insulator 650. The figure also shows a configuration in which a conductor 416, which functions as a plug or wiring, is provided on insulators 411, 412, and 413. In addition, the conductor 416 can be provided in a region that overlaps with the conductor 660, which will be described later, as an example.

[0506] Furthermore, the insulators 630, 640, and 650 are provided with openings in the regions that overlap with the conductor 612, and the conductor 660 is provided to fill these openings. The conductor 660 functions as a plug and wiring that electrically connects to the conductor 416 included in the wiring layer described above.

[0507] For insulators 411 and 414, it is preferable to use insulators that have barrier properties against impurities such as water and hydrogen, similar to insulator 324. Therefore, for insulators 411 and 414, materials applicable to insulator 324 can be used, for example.

[0508] For insulators 412 and 413, it is preferable to use insulators with a relatively low dielectric constant, similar to insulator 326, in order to reduce parasitic capacitance between the wires.

[0509] Furthermore, the conductors 612 and 416 can be provided using, for example, the same materials as those used for conductors 328 and 330.

[0510] This embodiment can be appropriately combined with other embodiments shown in this specification.

[0511] (Embodiment 5) This embodiment describes metal oxides (hereinafter also referred to as oxide semiconductors) that can be used in the OS transistor described in the above embodiment.

[0512] The metal oxide preferably contains at least indium or zinc. It is particularly preferable that it contains indium and zinc. In addition, it is preferable that it contains aluminum, gallium, yttrium, and tin. It may also contain one or more selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and cobalt.

[0513] <Classification of crystal structures> First, we will explain the classification of crystal structures in oxide semiconductors using Figure 17(A). Figure 17(A) is a diagram illustrating the classification of crystal structures in oxide semiconductors, specifically IGZO (a metal oxide containing In, Ga, and Zn).

[0514] As shown in Figure 17(A), oxide semiconductors are broadly classified into "Amorphous," "Crystalline," and "Crystal." "Amorphous" includes completely amorphous semiconductors. "Crystalline" includes CAAC (c-axis-aligned crystalline), nc (nanocrystalline), and CAC (Cloud-Aligned Composite) (excluding single crystal and polycrystal). Note that single crystal, polycrystal, and completely amorphous semiconductors are excluded from the "Crystalline" classification. "Crystal" includes single crystal and polycrystal semiconductors.

[0515] The structure within the thick frame shown in Figure 17(A) is an intermediate state between "Amorphous" and "Crystal," and belongs to a new boundary region (New crystalline phase). In other words, this structure can be described as being completely different from the energetically unstable "Amorphous" and "Crystal" states.

[0516] The crystal structure of a film or substrate can be evaluated using X-ray diffraction (XRD) spectroscopy. Figure 17(B) shows the XRD spectrum obtained by GIXD (Grazing-Incidence XRD) measurement of a CAAC-IGZO film classified as "Crystalline" (the horizontal axis is 2θ [deg.], and the vertical axis represents intensity in arbitrary units (au)). The GIXD method is also known as the thin-film method or the Seemann-Bohlin method. Hereafter, the XRD spectrum obtained by the GIXD measurement shown in Figure 17(B) may simply be referred to as the XRD spectrum. The composition of the CAAC-IGZO film shown in Figure 17(B) is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. The thickness of the CAAC-IGZO film shown in Figure 17(B) is 500 nm.

[0517] As shown in Figure 17(B), the XRD spectrum of the CAAC-IGZO film shows a peak indicating clear crystallinity. Specifically, the XRD spectrum of the CAAC-IGZO film shows a peak indicating c-axis orientation near 2θ=31°. As shown in Figure 17(B), the peak near 2θ=31° is asymmetrical with respect to the angle at which the peak intensity was detected.

[0518] Furthermore, the crystal structure of a film or substrate can be evaluated by the diffraction pattern (also called the nano-beam electron diffraction pattern) observed by nano-beam electron diffraction (NBED). The diffraction pattern of a CAAC-IGZO film is shown in Figure 17(C). Figure 17(C) shows the diffraction pattern observed by NBED with the electron beam incident parallel to the substrate. The composition of the CAAC-IGZO film shown in Figure 17(C) is approximately In:Ga:Zn=4:2:3 [atomic ratio]. In nano-beam electron diffraction, electron diffraction is performed with a probe diameter of 1 nm.

[0519] As shown in Figure 17(C), the diffraction pattern of the CAAC-IGZO film shows multiple spots indicating c-axis orientation.

[0520] <<Oxide semiconductor structure>> Note that when focusing on the crystal structure, oxide semiconductors may be classified differently from those shown in Figure 17(A). For example, oxide semiconductors can be divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the aforementioned CAAC-OS and nc-OS. Non-single-crystal oxide semiconductors also include polycrystalline oxide semiconductors, pseudo-amorphous oxide semiconductors (a-like OS), and amorphous oxide semiconductors.

[0521] Here, we will explain the details of the CAAC-OS, nc-OS, and a-like OS mentioned above.

[0522] [CAAC-OS] CAAC-OS is an oxide semiconductor having multiple crystalline regions, the c-axis of which is oriented in a specific direction. This specific direction is the thickness direction of the CAAC-OS film, the normal direction to the surface on which the CAAC-OS film is formed, or the normal direction to the surface of the CAAC-OS film. A crystalline region is a region with periodic atomic arrangement. If we consider the atomic arrangement as a lattice arrangement, then a crystalline region is also a region with a aligned lattice arrangement. Furthermore, CAAC-OS has regions where multiple crystalline regions are connected in the ab-plane direction, and these regions may exhibit distortion. Distortion refers to a point in the connected region where the orientation of the lattice arrangement changes between a region with a aligned lattice arrangement and another region with a aligned lattice arrangement. In short, CAAC-OS is an oxide semiconductor that is c-axis oriented and does not exhibit clear orientation in the ab-plane direction.

[0523] Each of the multiple crystalline regions described above is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of a single minute crystal, the maximum diameter of that crystalline region is less than 10 nm. When a crystalline region is composed of many minute crystals, the size of that crystalline region may be around several tens of nanometers.

[0524] Furthermore, in In-M-Zn oxides (where element M is one or more elements selected from aluminum, gallium, yttrium, tin, titanium, etc.), CAAC-OS tends to have a layered crystalline structure (also called a layered structure) consisting of layers containing indium (In) and oxygen (hereinafter referred to as the In layer) and layers containing element M, zinc (Zn), and oxygen (hereinafter referred to as the (M,Zn) layer). Note that indium and element M are mutually substitutable. Therefore, the (M,Zn) layer may contain indium. Also, the In layer may contain element M. Also, the In layer may contain Zn. This layered structure can be observed, for example, as a lattice image in high-resolution TEM images.

[0525] When structural analysis of a CAAC-OS film is performed using an XRD instrument, for example, out-of-plane XRD measurements using θ / 2θ scanning show a peak indicating c-axis orientation at 2θ = 31° or nearby. Note that the position of the c-axis orientation peak (value of 2θ) may vary depending on the type and composition of the metal elements constituting the CAAC-OS.

[0526] Furthermore, for example, multiple bright spots are observed in the electron diffraction pattern of a CAAC-OS film. These spots are observed at point-symmetric positions with respect to the incident electron beam spot (also called the direct spot) that passed through the sample.

[0527] When the crystal region is observed from the specific direction described above, the lattice arrangement within that crystal region is based on a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be non-regular hexagonal. Furthermore, the strain may have lattice arrangements such as pentagons or heptagons. Moreover, in CAAC-OS, clear grain boundaries cannot be observed even near the strain. In other words, it can be seen that the formation of grain boundaries is suppressed by the strain in the lattice arrangement. This is thought to be because CAAC-OS can tolerate strain due to factors such as the non-dense arrangement of oxygen atoms in the ab-plane direction and the change in interatomic bond distances due to the substitution of metal atoms.

[0528] A crystal structure in which clear grain boundaries are observed is called a polycrystal. Grain boundaries act as recombination centers, trapping carriers and potentially causing a decrease in transistor on-current and field-effect mobility. Therefore, CAAC-OS, in which clear grain boundaries are not observed, is one of the crystalline oxides with a suitable crystal structure for the semiconductor layer of a transistor. In addition, a structure containing Zn is preferred for the composition of CAAC-OS. For example, In-Zn oxide and In-Ga-Zn oxide are preferred because they suppress the generation of grain boundaries more than In oxide.

[0529] CAAC-OS is an oxide semiconductor with high crystallinity and no clearly defined grain boundaries. Therefore, CAAC-OS is less susceptible to the decrease in electron mobility caused by grain boundaries. Furthermore, since the crystallinity of oxide semiconductors can decrease due to the inclusion of impurities and the generation of defects, CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Consequently, oxide semiconductors containing CAAC-OS have stable physical properties. Therefore, oxide semiconductors containing CAAC-OS are heat-resistant and highly reliable. In addition, CAAC-OS is stable even at high temperatures (so-called thermal budget) during the manufacturing process. Therefore, using CAAC-OS in OS transistors allows for greater flexibility in the manufacturing process.

[0530] [nc-OS] nc-OS exhibits periodicity in atomic arrangement in minute regions (e.g., regions between 1 nm and 10 nm, particularly between 1 nm and 3 nm). In other words, nc-OS contains minute crystals. These minute crystals are also called nanocrystals because their size is, for example, between 1 nm and 10 nm, particularly between 1 nm and 3 nm. Furthermore, nc-OS shows no regularity in crystal orientation between different nanocrystals. Therefore, no orientation is observed throughout the film. Consequently, depending on the analytical method, nc-OS may be indistinguishable from a-like OS and amorphous oxide semiconductors. For example, when structural analysis of an nc-OS film is performed using an XRD instrument, no peaks indicating crystallinity are detected in out-of-plane XRD measurements using θ / 2θ scanning. Also, when electron diffraction (also called limited-field electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter larger than that of the nanocrystals (e.g., 50 nm or larger), a diffraction pattern resembling a halo pattern is observed. On the other hand, when electron diffraction (also called nanobeam electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter close to or smaller than the size of the nanocrystal (for example, 1 nm to 30 nm), an electron diffraction pattern may be obtained in which multiple spots are observed within a ring-shaped region centered on a direct spot.

[0531] [a-like OS] a-like OS is an oxide semiconductor having a structure between nc-OS and amorphous oxide semiconductors. a-like OS has porous or low-density regions. That is, a-like OS has lower crystallinity compared to nc-OS and CAAC-OS. Also, a-like OS has a higher hydrogen concentration in the film compared to nc-OS and CAAC-OS.

[0532] <<Oxide Semiconductor Composition>> Next, we will explain the details of CAC-OS mentioned above. Note that CAC-OS refers to the material composition.

[0533] [CAC-OS] CAC-OS is a material composition in which, for example, the elements constituting the metal oxide are unevenly distributed in sizes of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or close to that size. In the following, a state in which one or more metal elements are unevenly distributed in a metal oxide, and the regions containing these metal elements are mixed in sizes of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or close to that size, is also referred to as a mosaic or patchy state.

[0534] Furthermore, CAC-OS is a composite metal oxide having a mosaic-like structure formed by the separation of the material into a first region and a second region, with the first region distributed within the film (hereinafter also referred to as a cloud-like structure). In other words, CAC-OS is a composite metal oxide having a structure in which the first region and the second region are mixed.

[0535] Here, the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in In-Ga-Zn oxide are denoted as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS of In-Ga-Zn oxide, the first region is the region where [In] is greater than the [In] in the composition of the CAC-OS film. The second region is the region where [Ga] is greater than the [Ga] in the composition of the CAC-OS film. Alternatively, for example, the first region is the region where [In] is greater than the [In] in the second region, and [Ga] is smaller than the [Ga] in the second region. The second region is the region where [Ga] is greater than the [Ga] in the first region, and [In] is smaller than the [In] in the first region.

[0536] Specifically, the first region described above is a region whose main components are indium oxide, indium zinc oxide, etc. The second region described above is a region whose main components are gallium oxide, gallium zinc oxide, etc. In other words, the first region can be rephrased as a region whose main component is In. Similarly, the second region can be rephrased as a region whose main component is Ga.

[0537] Furthermore, a clear boundary may not be observed between the first region and the second region described above.

[0538] For example, in the case of CAC-OS in In-Ga-Zn oxide, EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX) confirms that it has a structure in which regions mainly composed of In (first region) and regions mainly composed of Ga (second region) are unevenly distributed and mixed.

[0539] When CAC-OS is used in a transistor, the conductivity due to the first region and the insulation due to the second region work complementaryly to give CAC-OS a switching function (on / off function). In other words, CAC-OS has conductive function in part of the material, insulating function in part of the material, and semiconductor function as a whole. By separating the conductive function and the insulating function, both functions can be maximized. Therefore, by using CAC-OS in a transistor, a high on-current (I) can be achieved. on This enables high field-effect mobility (μ) and good switching operation.

[0540] Oxide semiconductors can take on diverse structures, each possessing different properties. One embodiment of the present invention may include two or more of the following: amorphous oxide semiconductors, polycrystalline oxide semiconductors, a-like OS, CAC-OS, nc-OS, and CAAC-OS.

[0541] <Transistors containing oxide semiconductors> Next, we will explain the case where the above oxide semiconductor is used in a transistor.

[0542] By using the above-mentioned oxide semiconductor in transistors, it is possible to realize transistors with high field-effect mobility. Furthermore, it is possible to realize highly reliable transistors.

[0543] It is preferable to use an oxide semiconductor with a low carrier concentration for the transistor. For example, the carrier concentration of an oxide semiconductor is 1 × 10⁻⁶. 17 cm -3 The following is preferably 1 × 10 15 cm -3 More preferably 1 × 10 13 cm -3 More preferably 1 × 10 11 cm -3 More preferably 1 × 10 10 cm -3 It is less than 1 × 10 -9 cm-3 This concludes the explanation. Furthermore, when lowering the carrier concentration of an oxide semiconductor film, the impurity concentration in the oxide semiconductor film should be lowered to reduce the defect level density. In this specification, a low impurity concentration and low defect level density are referred to as high-purity intrinsic or substantially high-purity intrinsic. Note that oxide semiconductors with low carrier concentrations may also be referred to as high-purity intrinsic or substantially high-purity intrinsic oxide semiconductors.

[0544] Furthermore, oxide semiconductor films that are highly pure or substantially highly pure have a low defect level density, which may result in a low trap level density.

[0545] Furthermore, charges trapped in the trap levels of oxide semiconductors can take a long time to disappear, sometimes behaving like fixed charges. Therefore, transistors in which channel formation regions are formed in oxide semiconductors with a high trap level density may exhibit unstable electrical properties.

[0546] Therefore, reducing the impurity concentration in the oxide semiconductor is effective in stabilizing the electrical characteristics of the transistor. Furthermore, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in adjacent films. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0547] <Impurities> Here, we will explain the effects of various impurities in oxide semiconductors.

[0548] In oxide semiconductors, the presence of silicon and carbon, which are Group 14 elements, leads to the formation of defect levels within the oxide semiconductor. Therefore, the concentrations of silicon and carbon in the oxide semiconductor and the concentrations of silicon and carbon near the interface with the oxide semiconductor (concentrations obtained by secondary ion mass spectrometry (SIMS)) are compared by 2 × 10⁻⁶. 18 atoms / cm 3 The following is preferably 2 × 1017 atoms / cm 3 The following applies:

[0549] Furthermore, if an oxide semiconductor contains alkali metals or alkaline earth metals, it may form defect levels and generate carriers. Therefore, transistors using oxide semiconductors containing alkali metals or alkaline earth metals tend to exhibit normally-on characteristics. For this reason, the concentration of alkali metals or alkaline earth metals in the oxide semiconductor obtained by SIMS should be set to 1 × 10⁻⁶. 18 atoms / cm 3 The following is preferably 2 × 10 16 atoms / cm 3 Do the following:

[0550] Furthermore, in oxide semiconductors, the presence of nitrogen generates electrons, which act as carriers, increasing the carrier concentration and making it easier for the semiconductor to become n-type. As a result, transistors using oxide semiconductors containing nitrogen tend to exhibit normally-on characteristics. Alternatively, the presence of nitrogen in oxide semiconductors can lead to the formation of trap levels. As a result, the electrical properties of the transistor may become unstable. For this reason, the nitrogen concentration in oxide semiconductors obtained by SIMS should be set to 5 × 10⁻⁶. 19 atoms / cm 3 Less than 5 × 10 18 atoms / cm 3 More preferably 1 × 10 18 atoms / cm 3 More preferably 5 × 10 17 atoms / cm 3 Do the following:

[0551] Furthermore, hydrogen contained in oxide semiconductors can react with oxygen bonded to metal atoms to form water, potentially creating oxygen vacancies. Hydrogen can then fill these vacancies, generating electrons, which act as carriers. Additionally, some of the hydrogen can combine with oxygen bonded to metal atoms to generate electrons. Therefore, transistors using oxide semiconductors containing hydrogen tend to exhibit normally-on characteristics. For this reason, it is preferable to reduce the hydrogen content in oxide semiconductors as much as possible. Specifically, in oxide semiconductors, the hydrogen concentration obtained by SIMS should be 1 × 10⁻⁶. 20 atoms / cm 3 Less than 1 × 10 19 atoms / cm 3 Less than 5x10 18 atoms / cm 3 Less than 1 × 10 18 atoms / cm 3 Make it less than.

[0552] By using an oxide semiconductor with sufficiently reduced impurities in the channel formation region of a transistor, stable electrical characteristics can be provided.

[0553] This embodiment can be appropriately combined with other embodiments shown in this specification.

[0554] (Embodiment 6) This embodiment shows an example of a semiconductor wafer including the semiconductor device shown in the above embodiment, and an example of an electronic component incorporating the semiconductor device.

[0555] <Semiconductor wafers> First, an example of a semiconductor wafer, including semiconductor devices, will be explained using Figure 18(A).

[0556] The semiconductor wafer 4800 shown in Figure 18(A) comprises a wafer 4801 and a plurality of circuit sections 4802 provided on the upper surface of the wafer 4801. The portion of the upper surface of the wafer 4801 without circuit sections 4802 is the spacing 4803, which is the region for dicing.

[0557] The semiconductor wafer 4800 can be manufactured by forming multiple circuit sections 4802 on the surface of wafer 4801 in a previous process. Alternatively, the opposite side of wafer 4801 from where the circuit sections 4802 are formed may be ground to thin the wafer 4801. This process reduces warping of the wafer 4801, enabling miniaturization of the component.

[0558] The next step is the dicing process. Dicing is performed along the scribe lines SCL1 and SCL2 (sometimes called dicing lines or cutting lines) indicated by the dashed lines. In order to facilitate the dicing process, it is preferable to arrange the spacing 4803 so that multiple scribe lines SCL1 are parallel, multiple scribe lines SCL2 are parallel, and scribe lines SCL1 and SCL2 are perpendicular.

[0559] By performing the dicing process, a chip 4800a, as shown in Figure 18(B), can be cut from the semiconductor wafer 4800. The chip 4800a has a wafer 4801a, a circuit section 4802, and spacing 4803a. It is preferable to make the spacing 4803a as small as possible. In this case, the width of the spacing 4803 between adjacent circuit sections 4802 should be approximately the same length as the cutting allowance of the scribe line SCL1 or the cutting allowance of the scribe line SCL2.

[0560] The shape of the element substrate in one embodiment of the present invention is not limited to the shape of the semiconductor wafer 4800 shown in Figure 18(A). For example, it may be a rectangular semiconductor wafer. The shape of the element substrate can be appropriately changed depending on the manufacturing process of the element and the apparatus for manufacturing the element.

[0561] <Electronic Components> Figure 18(C) shows a perspective view of the electronic component 4700 and the substrate (mounted substrate 4704) on which the electronic component 4700 is mounted. The electronic component 4700 shown in Figure 18(C) has a chip 4800a within a mold 4711. Note that the chip 4800a shown in Figure 18(C) has a configuration in which a circuit section 4802 is stacked. For example, the circuit section 4802 can be a circuit including the semiconductor device described in the above embodiment. Figure 18(C) is partially omitted to show the inside of the electronic component 4700. The electronic component 4700 has a land 4712 on the outside of the mold 4711. The land 4712 is electrically connected to an electrode pad 4713, and the electrode pad 4713 is electrically connected to the chip 4800a by a wire 4714. The electronic component 4700 is mounted on, for example, a printed circuit board 4702. Multiple such electronic components are combined and electrically connected on the printed circuit board 4702 to complete the mounting board 4704.

[0562] Figure 18(D) shows a perspective view of electronic component 4730. Electronic component 4730 is an example of a SiP (System in package) or MCM (Multi Chip Module). Electronic component 4730 has an interposer 4731 on a package substrate 4732 (printed circuit board), and a semiconductor device 4735 and multiple semiconductor devices 4710 are provided on the interposer 4731.

[0563] Electronic component 4730 includes a semiconductor device 4710. The semiconductor device 4710 can be, for example, a memory device such as a high-bandwidth memory (HBM). The semiconductor device 4735 can be an integrated circuit (semiconductor device) such as a CPU, GPU, FPGA, or memory device.

[0564] The package substrate 4732 can be a ceramic substrate, a plastic substrate, or a glass epoxy substrate, etc. The interposer 4731 can be a silicon interposer, a resin interposer, etc.

[0565] The interposer 4731 has multiple wirings and functions to electrically connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 4731 also functions to electrically connect integrated circuits provided on the interposer 4731 to electrodes provided on the package substrate 4732. For these reasons, the interposer is sometimes called a "redistribution board" or "intermediate board". In addition, through electrodes may be provided on the interposer 4731, and these through electrodes may be used to electrically connect the integrated circuits and the package substrate 4732. Furthermore, in silicon interposers, TSVs (Through Silicon Vias) can be used as through electrodes.

[0566] It is preferable to use a silicon interposer as the interposer 4731. Since silicon interposers do not require active elements, they can be manufactured at a lower cost than integrated circuits. On the other hand, since the wiring of a silicon interposer can be formed using a semiconductor process, it is easy to form fine wiring, which is difficult with resin interposers.

[0567] In HBMs, many connections are necessary to achieve a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted requires fine and high-density wiring. For this reason, it is preferable to use a silicon interposer for mounting the HBM.

[0568] Furthermore, in SiP or MCM using a silicon interposer, reliability degradation due to differences in expansion coefficients between the integrated circuit and the interposer is less likely to occur. In addition, because silicon interposers have high surface flatness, connection failures between the integrated circuit and the silicon interposer are less likely to occur. In particular, in 2.5D packages (2.5-dimensional packaging) where multiple integrated circuits are arranged side by side on the interposer, it is preferable to use a silicon interposer.

[0569] Alternatively, a heat sink (heat dissipation plate) may be provided on top of the electronic component 4730. If a heat sink is provided, it is preferable to align the heights of the integrated circuits provided on the interposer 4731. For example, in the electronic component 4730 shown in this embodiment, it is preferable to align the heights of the semiconductor device 4710 and the semiconductor device 4735.

[0570] To mount the electronic component 4730 onto another substrate, electrodes 4733 may be provided at the bottom of the package substrate 4732. Figure 18(D) shows an example in which electrodes 4733 are formed with solder balls. By providing solder balls in a matrix at the bottom of the package substrate 4732, BGA (Ball Grid Array) mounting can be achieved. Alternatively, electrodes 4733 may be formed with conductive pins. By providing conductive pins in a matrix at the bottom of the package substrate 4732, PGA (Pin Grid Array) mounting can be achieved.

[0571] The electronic component 4730 can be mounted on other boards using various mounting methods, not limited to BGA and PGA. For example, it can be mounted using SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), or QFN (Quad Flat Non-leaded package).

[0572] This embodiment can be appropriately combined with other embodiments shown in this specification.

[0573] (Embodiment 7) This embodiment describes a CPU that can be equipped with the semiconductor device of the above embodiment.

[0574] Figure 19 is a block diagram showing the configuration of an example CPU that partially uses the semiconductor device described in the above embodiment.

[0575] The CPU shown in Figure 19 has an ALU 1191 (ALU: Arithmetic logic unit), an ALU controller 1192, an instruction decoder 1193, an interrupt controller 1194, a timing controller 1195, a register 1196, a register controller 1197, a bus interface 1198 (Bus I / F), a rewritable ROM 1199, and a ROM interface 1189 (ROM I / F) on a substrate 1190. The substrate 1190 can be a semiconductor substrate, an SOI substrate, a glass substrate, etc. The ROM 1199 and ROM interface 1189 may be provided on a separate chip. Of course, the CPU shown in Figure 19 is merely one example of a simplified configuration, and actual CPUs have a wide variety of configurations depending on their application. For example, the configuration including the CPU or arithmetic circuit shown in Figure 19 may be considered as one core, and a configuration including multiple such cores, where each core operates in parallel, may be used, i.e., a configuration like a GPU. Furthermore, the number of bits that the CPU can handle in its internal arithmetic circuitry and data bus can be, for example, 8 bits, 16 bits, 32 bits, or 64 bits.

[0576] Instructions input to the CPU via the bus interface 1198 are input to the instruction decoder 1193, decoded, and then input to the ALU controller 1192, interrupt controller 1194, register controller 1197, and timing controller 1195.

[0577] The ALU controller 1192, interrupt controller 1194, register controller 1197, and timing controller 1195 perform various controls based on the decoded instructions. Specifically, the ALU controller 1192 generates signals to control the operation of the ALU 1191. The interrupt controller 1194 processes interrupt requests from external input / output devices and peripheral circuits during CPU program execution, based on their priority and mask state. The register controller 1197 generates the address of register 1196 and reads or writes to register 1196 depending on the state of the CPU.

[0578] Furthermore, the timing controller 1195 generates signals that control the timing of the operation of the ALU 1191, ALU controller 1192, instruction decoder 1193, interrupt controller 1194, and register controller 1197. For example, the timing controller 1195 includes an internal clock generation unit that generates an internal clock signal based on a reference clock signal, and supplies the internal clock signal to the various circuits mentioned above.

[0579] In the CPU shown in Figure 19, a memory cell is provided in register 1196. Register 1196 may include, for example, a semiconductor device as shown in the previous embodiment.

[0580] In the CPU shown in Figure 19, the register controller 1197 selects a data retention operation in register 1196 according to instructions from ALU 1191. Specifically, it selects whether to retain data in the memory cell of register 1196 using a flip-flop or a capacitive element. If data retention using a flip-flop is selected, a power supply voltage is supplied to the memory cell in register 1196. If data retention using a capacitive element is selected, data is rewritten to the capacitive element, and the power supply voltage to the memory cell in register 1196 can be stopped.

[0581] This embodiment can be appropriately combined with other embodiments shown in this specification.

[0582] (Embodiment 8) This embodiment describes an example of an electronic device having the semiconductor device described in the above embodiment. Figures 20(A) to 20(I) illustrate how the electronic component 4700 having the semiconductor device is included in each electronic device.

[0583] [mobile phone] The information terminal 5500 shown in Figure 20(A) is a type of information terminal, specifically a mobile phone (smartphone). The information terminal 5500 has a housing 5510 and a display unit 5511. For input interfaces, a touch panel is provided on the display unit 5511, and buttons are provided on the housing 5510.

[0584] By applying the semiconductor device described in the above embodiment, the power consumption of the information terminal 5500 can be reduced.

[0585] [Wearable devices] Figure 20(B) also shows an information terminal 5900, which is an example of a wearable device. The information terminal 5900 has a housing 5901, a display unit 5902, operation buttons 5903, an operating element 5904, and a band 5905.

[0586] Similar to the information terminal 5500 mentioned above, the power consumption of a wearable device can be reduced by applying the semiconductor device described in the above embodiment.

[0587] [Information terminal] Furthermore, Figure 20(C) illustrates a notebook-type information terminal 5300. As an example, the notebook-type information terminal 5300 shown in Figure 20(C) is equipped with a display unit 5331 in the housing 5330a and a keyboard unit 5350 in the housing 5330b.

[0588] Similar to the aforementioned information terminal 5500, the power consumption of the notebook-type information terminal 5300 can be reduced by applying the semiconductor device described in the above embodiment.

[0589] In the above, smartphones, wearable devices, and notebook computers were used as examples of electronic devices and illustrated in Figures 20(A) to 20(C), respectively. However, other types of information terminals can also be applied. Examples of other types of information terminals include PDAs (Personal Digital Assistants), desktop computers, and workstations.

[0590] [electric appliances] Figure 20(D) also shows an electric refrigerator-freezer 5800 as an example of an electrical appliance. The electric refrigerator-freezer 5800 has a casing 5801, a refrigerator door 5802, and a freezer door 5803.

[0591] By applying the semiconductor device described in the above embodiment to the electric refrigerator 5800, the electric refrigerator 5800 can be used, for example, as an IoT (Internet of Things) device. By using IoT, the electric refrigerator 5800 can send and receive information such as the food stored in the electric refrigerator 5800 and the expiration date of that food to information terminals as described above via the internet. In addition, the electric refrigerator 5800 can reduce the power consumption when transmitting such information.

[0592] In this example, an electric refrigerator was described as an electrical appliance, but other electrical appliances include, for example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, induction cooktops, water dispensers, heating and cooling appliances including air conditioners, washing machines, dryers, and audiovisual equipment.

[0593] [Game console] Figure 20(E) also shows a portable game console 5200, which is an example of a game console. The portable game console 5200 has a housing 5201, a display unit 5202, and buttons 5203.

[0594] Furthermore, the video output from the 5200 portable game console can be displayed on a display device such as a television system, a personal computer display, a game display, or a head-mounted display.

[0595] By applying the semiconductor device described in the above embodiment to the portable game console 5200, a low-power portable game console 5200 can be realized. Furthermore, because the low power consumption reduces heat generation from the circuit, the impact of heat on the circuit itself, peripheral circuits, and modules can be minimized.

[0596] Figure 20(E) shows a portable game console as an example of a game console, but the electronic devices of one aspect of the present invention are not limited to this. Examples of electronic devices of one aspect of the present invention include a stationary game console, an arcade game machine installed in an entertainment facility (game center, amusement park, etc.), or a pitching machine for batting practice installed in a sports facility.

[0597] [Mobile] The semiconductor device described in the above embodiment can be applied to a mobile vehicle and the area around the driver's seat of the vehicle.

[0598] Figure 20(F) shows an example of a mobile device, the automobile 5700.

[0599] The driver's seat area of ​​the automobile 5700 is equipped with an instrument panel that provides various information by displaying the speedometer, tachometer, odometer, fuel gauge, gear status, and air conditioning settings. Furthermore, a display device for showing this information may also be provided around the driver's seat.

[0600] In particular, by displaying images from an imaging device (not shown) installed in the automobile 5700 on the display device, it is possible to compensate for the view obstructed by pillars and other obstructions, as well as blind spots in the driver's seat, thereby enhancing safety.

[0601] The semiconductor device described in the above embodiment can be used, for example, as a memory device for holding necessary temporary information in an autonomous driving system for an automobile 5700, or in a system that performs road guidance, hazard prediction, etc.

[0602] While the above uses automobiles as an example of a moving object, the definition of a moving object is not limited to automobiles. For example, other examples of moving objects include trains, monorails, ships, and flying objects (helicopters, unmanned aerial vehicles (drones), airplanes, and rockets).

[0603] [camera] The semiconductor device described in the above embodiment can be applied to a camera.

[0604] Figure 20(G) shows a digital camera 6240, which is an example of an imaging device. The digital camera 6240 has a housing 6241, a display unit 6242, operation buttons 6243, a shutter button 6244, etc., and a detachable lens 6246 is attached to the digital camera 6240. In this example, the digital camera 6240 is configured so that the lens 6246 can be removed from the housing 6241 and replaced, but the lens 6246 and housing 6241 may be integrated. Furthermore, the digital camera 6240 may be configured to allow for the attachment of a strobe device, viewfinder, etc. separately.

[0605] By applying the semiconductor device described in the above embodiment to the digital camera 6240, a low-power digital camera 6240 can be realized. Furthermore, because the low power consumption reduces heat generation from the circuit, the impact of heat on the circuit itself, peripheral circuits, and modules can be minimized.

[0606] [ICD] The semiconductor device described in the above embodiment can be applied to an implantable cardioverter-defibrillator (ICD).

[0607] Figure 20(H) is a schematic cross-sectional view showing an example of an ICD. The ICD unit 5400 includes at least a battery 5401, electronic components 4700, a regulator, a control circuit, an antenna 5404, a wire 5402 to the right atrium, and a wire 5403 to the right ventricle.

[0608] The ICD unit 5400 is surgically implanted in the body, and two wires are routed through the subclavian vein 5405 and superior vena cava 5406 so that one wire tip is placed in the right ventricle and the other wire tip is placed in the right atrium.

[0609] The ICD unit 5400 functions as a pacemaker, pacing the heart if the heart rate falls outside the specified range. If pacing does not improve the heart rate (e.g., in cases of rapid ventricular tachycardia or ventricular fibrillation), treatment with an electric shock is administered.

[0610] The ICD unit 5400 needs to constantly monitor the heart rate in order to properly perform pacing and electric shocks. Therefore, the ICD unit 5400 has a sensor for detecting the heart rate. In addition, the ICD unit 5400 can store heart rate data acquired by the sensor, the number of times pacing treatment was performed, the duration, etc., in the electronic component 4700.

[0611] Furthermore, the antenna 5404 can receive power, which is then used to charge the battery 5401. The ICD unit 5400 also benefits from having multiple batteries, thus enhancing safety. Specifically, even if some of the batteries in the ICD unit 5400 fail, the remaining batteries can still function, thus acting as an auxiliary power source.

[0612] In addition, the system may have an antenna capable of transmitting physiological signals, separate from the power receiving antenna 5404. For example, a system may be configured to monitor cardiac activity so that physiological signals such as pulse rate, respiratory rate, heart rate, and body temperature can be checked on an external monitoring device.

[0613] [Extension devices for PCs] The semiconductor device described in the above embodiment can be applied to computers such as PCs (Personal Computers) and expansion devices for information terminals.

[0614] Figure 20(I) shows an example of such an expansion device, an external expansion device 6100 for a PC, equipped with a portable chip capable of storing information. The expansion device 6100 can store information using the chip by connecting to a PC, for example, via USB (Universal Serial Bus). Although Figure 20(I) illustrates a portable form of the expansion device 6100, the expansion device according to one aspect of the present invention is not limited to this, and may be a relatively large form of expansion device equipped with, for example, a cooling fan.

[0615] The expansion device 6100 comprises a housing 6101, a cap 6102, a USB connector 6103, and a circuit board 6104. The circuit board 6104 is housed in the housing 6101. The circuit board 6104 is provided with circuits including semiconductor devices as described in the above embodiment. For example, the circuit board 6104 is fitted with electronic components 4700 and a controller chip 6106. The USB connector 6103 functions as an interface for connecting to an external device.

[0616] Furthermore, although not shown in the diagrams, the semiconductor device described in the above embodiment can also be applied to SD cards, SSDs (Solid State Drives), and other devices that can be attached to computers such as PCs (Personal Computers) and information terminals.

[0617] A novel electronic device can be provided by applying the semiconductor device described in Embodiment 1 or Embodiment 2 to the memory device included in the above-mentioned electronic device.

[0618] This embodiment can be appropriately combined with other embodiments shown in this specification. [Explanation of symbols]

[0619] TrS: Transistor, TrSa: Transistor, TrSb: Transistor, TrS1: Transistor, TrS2: Transistor, TrS3: Transistor, TrS3a: Transistor, TrS3b: Transistor, TrS4: Transistor, TrS4a: Transistor, TrS4b: Transistor, TrS5: Transistor, TrS6: Transistor, TrS11: Transistor, TrS12: Transistor, TrS13: Transistor, TrS30: Transistor, TrS31: Transistor, TrS32: Transistor, TrO: Transistor, TrOa: Transistor, TrOb: Transistor, TrO1: Transistor, TrO2: Transistor, TrO3: Transistor, TrO4: Transistor, TrO5: Transistor, TrO6: Transistor, TrO7: Transistor, TrO8: Transistor, TrO14: Transistor, TrO15: Transistor, TrO16: Transistor, TrO17: Transistor, TrO18: Transistor, TrO19: Transistor, TrO20: Transistor, TrO30: Transistor, TrO31: Transistor, TrO32: Transistor OSW: Transistor, CN: Capacitance, CSH: Capacitance, VDE: Wiring, VDE1: Wiring, VDE2: Wiring, VDE3: Wiring, VDE11: Wiring, VDE12: Wiring, VDE13: Wiring, VDE30: Wiring, VGE: Wiring, VGE1: Wiring, VGE2: Wiring, VGE11: Wiring, VGE12: Wiring, VGE13: Wiring, VGE20: Wiring, CK: Wiring, CKB: Wiring, DK: Wiring, DKB: Wiring, RST: Wiring, CMON: Wiring, CMOP: Wiring, IT: Terminal, IT1: Terminal, IT2: Terminal, OT: Terminal, CT: Terminal, CTB: Terminal, INT: Terminal, C IT: Terminal, DOT: Terminal, LOT: Terminal, VST: Terminal, LIN: Terminal, LOTP: Terminal, LOTP[1]: Terminal, LOTP[n]: Terminal, LOTN: Terminal, LOTN[1]: Terminal, LOTN[n]: Terminal, IP: Terminal, OP: Terminal, SP: Terminal, SH: Circuit, SH_1: Circuit, SH_2: Circuit, SH_3: Circuit, SH_4: Circuit, CMP: Comparator, SARL: Circuit, NDAC: Digital-to-Analog Converter, FF: Flip-flop Circuit, FF[0]: Flip-flop Circuit, FF[1]: Flip-flop Circuit, FF[n]: Flip-flop Circuit,FFA: Flip-flop circuit, BC: Latch circuit, BC[1]: Latch circuit, BC[n]: Latch circuit, 100: Circuit, 100_1: Circuit, 100_2: Circuit, 100_3: Circuit, 100_4: Circuit, 100A: Circuit, 100A_1: Circuit, 100A_2: Circuit, 100A_3: Circuit, 100A_4: Circuit, 100B: Circuit, 100B_1: Circuit, 100B_2: Circuit, 100B_3: Circuit, 100B_4: Circuit, 100C: Circuit, 100C_1: Circuit, 100C_2: Circuit, 150: Circuit, 200: Circuit, 300: Transistor, 310: Circuit board 310A: Substrate, 312: Element isolation layer, 313: Semiconductor region, 314a: Low resistance region, 314b: Low resistance region, 315: Insulator, 316: Conductor, 320: Insulator, 322: Insulator, 324: Insulator, 326: Insulator, 328: Conductor, 330: Conductor, 350: Insulator, 352: Insulator, 354: Insulator, 356: Conductor, 360: Insulator, 362: Insulator, 364: Insulator, 366: Conductor, 411: Insulator, 412: Insulator, 413: Insulator, 414: Insulator, 416: Conductor, 500: Transistor, 503: Conductor, 503a: Conductor 503b: Conductor, 510: Insulator, 512: Insulator, 514: Insulator, 516: Insulator, 518: Conductor, 522: Insulator, 524: Insulator, 530: Oxide, 530a: Oxide, 530b: Oxide, 530ba: Region, 530bb: Region, 530bc: Region, 540: Conductor, 540a: Conductor, 540b: Conductor, 541: Insulator, 541a: Insulator, 541b: Insulator, 542: Conductor, 542a: Conductor, 542b: Conductor, 543: Oxide, 543a: Oxide, 543b: Oxide, 544: Insulator, 546: Conductor, 550: Insulator, 5 50a: Insulator, 550b: Insulator, 552: Insulator, 554: Insulator, 560: Conductor, 560a: Conductor, 560b: Conductor, 571: Insulator, 571a: Insulator, 571b: Insulator, 574: Insulator, 576: Insulator, 580: Insulator, 581: Insulator, 582: Insulator, 586: Insulator, 600: Capacitive element, 610: Conductor, 612: Conductor, 620: Conductor, 630: Insulator, 640: Insulator, 650: Insulator, 660: Conductor, 1189: ROM interface, 1190: Circuit board, 1191: ALU, 1192: ALU controller,1193: Instruction decoder, 1194: Interrupt controller, 1195: Timing controller, 1196: Register, 1197: Register controller, 1198: Bus interface, 1199: ROM, 4700: Electronic components, 4702: Printed circuit board, 4704: Assembly board, 4710: Semiconductor device, 4711: Mold, 4712: Land, 4713: Electrode pad, 4714: Wire 4730: Electronic components, 4731: Interposers, 4732: Package substrates, 4733: Electrodes, 4735: Semiconductor equipment, 4800: Semiconductor wafers, 4800a: Chips, 4801: Wafers, 4801a: Wafers, 4802: Circuit sections, 4803: Spacing, 4803a: Spacing, 5200: Portable game consoles, 5201: Enclosures, 5202: Display sections, 5203: Buttons, 5300: Notebook-type information terminals, 533 0a: Housing, 5330b: Housing, 5331: Display unit, 5350: Keyboard unit, 5400: ICD main unit, 5401: Battery, 5402: Wire, 5403: Wire, 5404: Antenna, 5405: Subclavian vein, 5406: Superior vena cava, 5500: Information terminal, 5510: Housing, 5511: Display unit, 5700: Automobile, 5800: Electric refrigerator / freezer, 5801: Housing, 5802: Door for refrigerator compartment, 5803: Door for freezer compartment, 5900: Information terminal, 5901: Housing, 5902: Display unit, 5903: Operation buttons, 5904: Control unit, 5905: Band, 6100: Expansion device, 6101: Housing, 6102: Cap, 6103: USB connector, 6104: Circuit board, 6106: Controller chip, 6240: Digital camera, 6241: Housing, 6242: Display unit, 6243: Operation buttons, 6244: Shutter button, 6246: Lens,

Claims

1. It has a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor. Each of the first transistor and the third transistor is a p-channel type transistor containing silicon in the channel formation region. Each of the second transistor, the fourth transistor, the fifth transistor, and the sixth transistor is an n-channel type transistor containing a metal oxide in the channel formation region. The metal oxide comprises indium, element M (where element M is one or more selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium), and zinc. The gate of the first transistor is electrically connected to the gate of the second transistor and the gate of the sixth transistor. The gate of the third transistor is electrically connected to the gate of the fourth transistor and the gate of the fifth transistor. Either the source or drain of the first transistor is electrically connected to either the source or drain of the second transistor, either the source or drain of the third transistor, and either the source or drain of the fourth transistor. The source or drain of the second transistor is electrically connected to the source or drain of the fifth transistor. The source or drain of the fourth transistor is electrically connected to the source or drain of the sixth transistor. Each of the first to sixth transistors may operate in the subthreshold region, Semiconductor equipment.

2. It has a first circuit and a first inverter circuit, It has a second circuit and a second inverter circuit, The first circuit comprises a first transistor and a first capacitor, The first transistor is an n-channel type transistor containing a metal oxide in the channel formation region, The metal oxide comprises indium, element M (where element M is one or more selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium), and zinc. The output terminal of the first circuit is electrically connected to the input terminal of the first inverter circuit. The source or drain of the first transistor is electrically connected to the first terminal of the first capacitor and to the output terminal of the first circuit. The transistor included in the first inverter circuit includes cases where it operates in the subthreshold region. The second circuit comprises a second transistor and a second capacitor, The second transistor is an n-channel type transistor containing the metal oxide in the channel formation region, The output terminal of the first inverter circuit is electrically connected to the input terminal of the second circuit. The output terminal of the second circuit is electrically connected to the input terminal of the second inverter circuit. The output terminal of the second inverter circuit is electrically connected to the input terminal of the first circuit. The source or drain of the first transistor, the other of which is electrically connected to the input terminal of the first circuit, Either the source or drain of the second transistor is electrically connected to the first terminal of the second capacitor and to the output terminal of the second circuit. The source or drain of the second transistor, the other of which is electrically connected to the input terminal of the second circuit, The transistor included in the second inverter circuit includes cases where it operates in the subthreshold region. Semiconductor equipment.

3. It has a first circuit and a first inverter circuit, The first circuit comprises a first transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a first capacitor. Each of the first transistor, the fourth transistor, and the sixth transistor is an n-channel type transistor containing a metal oxide in the channel formation region. The metal oxide comprises indium, element M (where element M is one or more selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium), and zinc. The third transistor and the fifth transistor are each p-channel type transistors containing silicon in the channel formation region. The output terminal of the first circuit is electrically connected to the input terminal of the first inverter circuit. The source or drain of the first transistor is electrically connected to the first terminal of the first capacitor and to the gate of the fourth transistor. Either the source or drain of the third transistor is electrically connected to either the source or drain of the fourth transistor, the gate of the fifth transistor, and the gate of the sixth transistor. The source or drain of the fifth transistor is electrically connected to the source or drain of the sixth transistor and to the output terminal of the first circuit. Each of the transistors included in the first inverter circuit, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor, includes cases where they operate in the subthreshold region. Semiconductor equipment.

4. In claim 3, It has a second circuit and a second inverter circuit, The second circuit comprises a second transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, and a second capacitor. Each of the second transistor, the eighth transistor, and the tenth transistor is an n-channel type transistor containing the metal oxide in the channel formation region. Each of the seventh transistor and the ninth transistor is a p-channel type transistor containing silicon in the channel formation region. The output terminal of the first inverter circuit is electrically connected to the input terminal of the second circuit. The output terminal of the second circuit is electrically connected to the input terminal of the second inverter circuit. The output terminal of the second inverter circuit is electrically connected to the input terminal of the first circuit. The source or drain of the first transistor, the other of which is electrically connected to the input terminal of the first circuit, Either the source or drain of the second transistor is electrically connected to the first terminal of the second capacitor and to the gate of the eighth transistor. The source or drain of the seventh transistor is electrically connected to the source or drain of the eighth transistor, the gate of the ninth transistor, and the gate of the tenth transistor. The source or drain of the ninth transistor is electrically connected to the source or drain of the tenth transistor and to the output terminal of the first circuit. Each of the transistors included in the second inverter circuit, the seventh transistor, the eighth transistor, the ninth transistor, and the tenth transistor, including when operating in the subthreshold region, Semiconductor equipment.

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