A high throughput, low interrupt generic micro-coded architecture for ultra high speed communication protocols

Abstract

A Host Controller (HC) system for a generic Ultra High Speed Serial Communication Bus (UHSSCB) to transfer data between the host and the device by employing an instruction based architecture. The new system uses any descriptors or any data structures that are present in the memory and convert them into smaller instructions which provide the control as well as data flow for that transaction. The new technique helps in two ways. First, using the instruction based approach we can divide the big data chunks into smaller manageable entities that can utilize smaller memory blocks for the movement of data thus saving the memory. As a secondary benefit, the smaller blocks may help in reducing the overall power dissipation as memory is the main source of power dissipation due to continuous updates of the data in the memory requiring clock all the time. Second, the new architecture is scalable for implementing any high speed communication bus that is driven through data structures or descriptors based on memory. It is scalable because we can translate any data structures or descriptors into instructions and can use the same building blocks with minor or no changes for implementing those data structures or descriptors belonging to many different protocols like USB3.0 or PCIe 3.0. Fig. 3