Method and apparatus for evaluating clock tree, device and storage medium

Abstract

Embodiments of the present disclosure provide a method and apparatus for evaluating a clock tree, a device and a storage medium. The method comprises: on the basis of a set of structural parameters for a plurality of portions of a clock tree, automatically determining a candidate clock tree structure for the clock tree, wherein each structural parameter in the set of structural parameters is used for defining a structure of one of the plurality of portions; obtaining circuit configuration information associated with the candidate clock tree structure, wherein the circuit configuration information indicates a connection relationship between circuit units in the candidate clock tree structure; and based at least on the circuit configuration information, determining the clock performance of the candidate clock tree structure. Therefore, automatic evaluation and verification of a clock tree design can be realized.

Description

Method, apparatus, device and storage medium for evaluating clock tree

[0001] The present application claims priority to the Chinese patent application No. 202310362046.7, filed on April 6, 2023, entitled “Method, apparatus, device and storage medium for evaluating clock tree”, the whole content of which is incorporated herein by reference. TECHNICAL FIELD

[0002] Example embodiments of the present disclosure generally relate to the field of integrated circuits, and in particular, to a method, apparatus, device and computer readable storage medium for evaluating clock tree. BACKGROUND

[0003] A clock tree is an architecture of clock distribution network, which is used to deliver clock signals to sequential elements. The process of generating a clock tree according to the constraint requirements of a clock network is called clock tree synthesis (CTS). Clock tree synthesis is a very important part of the back-end design process of digital circuits. How to reduce clock skew, reduce on-chip variation (OCV) and improve driving strength are the goals of clock tree synthesis.

[0004] SUMMARY

[0005] In a first aspect of the present disclosure, a method for evaluating a clock tree is provided. The method comprises: automatically determining a candidate clock tree structure for the clock tree based on a set of structure parameters for a plurality of parts of the clock tree, each structure parameter of the set of structure parameters being used to define a structure of one part of the plurality of parts; obtaining circuit configuration information associated with the candidate clock tree structure, the circuit configuration information indicating a connection relationship of circuit cells in the candidate clock tree structure; and determining a clock performance of the candidate clock tree structure based at least on the circuit configuration information.

[0006] In a second aspect of the present disclosure, an apparatus for evaluating a clock tree is provided. The apparatus comprises: a clock tree structure determining module configured to automatically determine a candidate clock tree structure for the clock tree based on a set of structure parameters for a plurality of parts of the clock tree, each structure parameter of the set of structure parameters being used to define a structure of one part of the plurality of parts; a circuit configuration information obtaining module configured to obtain circuit configuration information associated with the candidate clock tree structure, the circuit configuration information indicating a connection relationship of circuit cells in the candidate clock tree structure; and a clock performance determining module configured to determine a clock performance of the candidate clock tree structure based at least on the circuit configuration information.

[0007] In a third aspect of the disclosure, an electronic device is provided. The device includes at least one processing unit; and at least one memory coupled to the at least one processing unit and storing instructions for execution by the at least one processing unit. The instructions, when executed by the at least one processing unit, cause the device to perform the method of the first aspect.

[0008] In a fourth aspect of the disclosure, a computer-readable storage medium is provided. The computer-readable storage medium has stored thereon a computer program, which is executable by a processor to implement the method of the first aspect.

[0009] It should be understood that the content described in this section is not intended to limit the key features or important features of the embodiments of the disclosure, nor is it used to limit the scope of the disclosure. Other features of the disclosure will become apparent through the following description. BRIEF DESCRIPTION OF DRAWINGS

[0010] The above and other features, advantages, and aspects of embodiments of the present disclosure will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings in which:

[0011] FIG. 1 shows a schematic diagram of an example environment in which embodiments of the present disclosure can be implemented;

[0012] FIG. 2 shows a schematic diagram of one example of a clock tree according to some embodiments of the present disclosure;

[0013] FIG. 3 shows a flowchart of an example process of clock tree design according to some embodiments of the present disclosure;

[0014] FIG. 4 shows a flowchart of an example process of clock tree evaluation according to some embodiments of the present disclosure;

[0015] FIG. 5 shows a flowchart of a method for evaluating a clock tree according to some embodiments of the present disclosure;

[0016] FIG. 6 shows a block diagram of an apparatus for evaluating a clock tree according to some embodiments of the present disclosure; and

[0017] FIG. 7 shows a block diagram of a device capable of implementing embodiments of the present disclosure. DETAILED DESCRIPTION

[0018] It can be understood that, before using the technical solutions disclosed in the embodiments of the present disclosure, the type of personal information involved in the present disclosure, the scope of use, the scenario of use, etc. should be informed to the user and the authorization of the user should be obtained in a proper manner according to relevant laws and regulations.

[0019] For example, in response to receiving an active request of a user, a prompt information is sent to the user to explicitly prompt the user that the operation requested to be performed by the user will need to acquire and use personal information of the user. Thus, the user can autonomously select whether to provide the personal information to the software or hardware, such as an electronic device, an application program, a server or a storage medium, performing the operation of the technical solution of the present disclosure according to the prompt information.

[0020] As an optional but non-limiting implementation manner, in response to receiving an active request of a user, the manner of sending a prompt information to the user may, for example, be a pop-up window manner, in which the prompt information can be presented in a text manner. In addition, the pop-up window can also carry a selection control for the user to select "agree" or "disagree" to provide the personal information to the electronic device.

[0021] It can be understood that the above notification and acquisition of user authorization process is only illustrative, and does not limit the implementation manner of the present disclosure, and other manners meeting the relevant laws and regulations can also be applied to the implementation manner of the present disclosure.

[0022] It can be understood that the data involved in the technical solution (including but not limited to the data itself, acquisition or use of the data) should comply with the requirements of the relevant laws and regulations and the relevant provisions.

[0023] The term "in response to" used herein indicates a state in which a corresponding event occurs or a condition is met. It will be understood that the execution time of the subsequent action performed in response to the event or condition is not necessarily strongly associated with the time when the event occurs or the condition is established. For example, in some cases, the subsequent action can be performed immediately when the event occurs or the condition is established; while in other cases, the subsequent action can be performed after a period of time after the event occurs or the condition is established.

[0024] Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although certain embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms, and should not be interpreted as being limited to the embodiments set forth herein, but rather, these embodiments are provided to more thoroughly and completely understand the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are only for exemplary purposes, and are not intended to limit the scope of protection of the present disclosure.

[0025] It should be noted that the titles of any section / subsection provided herein are not limiting. Various embodiments are described throughout this document, and any type of embodiment can be included under any section / subsection. Furthermore, embodiments described in any section / subsection can be combined with any other embodiment described in the same section / subsection and / or in a different section / subsection in any manner.

[0026] In the description of embodiments of the disclosure, the term "includes" and its conjugates are to be construed as open-ended, i.e., "includes but is not limited to". The term "based on" is to be construed as "based at least in part on". The term "one embodiment" or "an embodiment" is to be construed as "at least one embodiment". The term "some embodiments" is to be construed as "at least some embodiments". The terms "a or an", "an", and "the" are to be construed to cover both singular as well as plural referents. Other explicit and implicit definitions can also be included below.

[0027] As used herein, the term "clock tree structure" or similar terms refer to a specific structure of an instantiated clock network.

[0028] In an integrated circuit (e.g., a chip), clock performance of a clock tree is crucial to the operation of various components in the integrated circuit. Thus, in the design of an integrated circuit, it is desirable to design a clock tree structure, or clock tree instance, with excellent clock performance. A clock tree has different structure parameters, and different values of the same structure parameter can cause a relatively large difference in clock performance. In the process of clock tree design or clock tree instantiation, it would be beneficial to understand the impact of changes in structure parameters on clock performance.

[0029] From the whole flow implementation of the design to the verification (also known as evaluation) of the clock tree, higher requirements are placed on the designer's experience in clock tree structure design. The design and simulation tools involved in the whole flow are more, and the automatic implementation of the flow is more complex.

[0030] To this end, embodiments of the disclosure propose a scheme for evaluating a clock tree. According to various embodiments of the disclosure, based on a set of structure parameters for a plurality of parts of a clock tree, a candidate clock tree structure for the clock tree is automatically determined, each structure parameter of the set of structure parameters being used to define a structure of one of the plurality of parts. Circuit configuration information associated with the candidate clock tree structure is obtained, the circuit configuration information indicating a connection relationship of circuit cells in the candidate clock tree structure. Clock performance of the candidate clock tree structure is determined based at least on the circuit configuration information. In this way, the automation of clock tree design, evaluation or verification can be realized from the structure parameters of the clock tree. In this way, by changing the values of the structure parameters, the impact of different structure parameters on clock performance can be quickly and comprehensively understood. This facilitates the realization of excellent clock tree design and optimization process.

[0031] Example embodiments of the disclosure are described below with reference to the accompanying drawings.

[0032] Example environment and example clock tree

[0033] FIG. 1 illustrates a schematic diagram of an example environment 100 in which embodiments of the present disclosure can be implemented. In the environment 100, an electronic device 120 obtains a set of structure parameters 110 for a plurality of portions of a clock tree. Each structure parameter in the set of structure parameters 110 is used to define a structure of one of the plurality of portions. In the set of structure parameters 110, each structure parameter can have one or more parameter values.

[0034] In some embodiments, the parameter values of at least some of the structure parameters in the set of structure parameters 110 can be automatically generated by the electronic device 110. Alternatively or additionally, in some embodiments, the parameter values of one or more of the structure parameters in the set of structure parameters 110 can be specified or customized by a user (e.g., a designer). For example, the electronic device 120 can provide a user interface for receiving user’s customization of one or more of the structure parameters in the set of structure parameters 110.

[0035] The electronic device 120 automatically completes the design and simulation verification of the clock tree based on the combination of the structure parameters in the set of structure parameters 110. Further, the electronic device 120 outputs an evaluation result 130 of the clock tree. The evaluation result can include the clock performance of each clock tree instance designed, such as the delay on one or more clock propagation paths, clock skew, etc.

[0036] In some embodiments, the flow of simulation verification can be automatically iterated for different clock tree structures (also referred to as clock tree instances). For example, in a case where a plurality of combinations of the structure parameters can be determined based on the set of structure parameters 110, each combination can define a clock tree structure. In turn, the simulation verification can be performed for each clock tree structure.

[0037] It should be understood that the structure and function of the environment 100 are described for illustrative purposes only, and do not imply any limitation on the scope of the present disclosure.

[0038] The electronic device 120 can design and simulate any appropriate type of clock tree. In some embodiments, the clock tree can include a clock mesh. For better understanding of embodiments of the present disclosure, one type of clock tree is described below as an example with reference to FIG. 2.

[0039] FIG. 2 shows a schematic diagram of an example clock tree 200, according to some embodiments of the present disclosure. The clock tree 200 includes a clock source 210, a global tree 220, a mesh driver stage 230, a clock mesh 240, and a local tree 280. The local tree 280 can further include a tap driver stage 250, a gating unit 260, and a timing unit 270. The clock tree 200 is used to provide clock signals to the timing units 270 (e.g., registers or memories) and to minimize the difference of the time signals delivered to the timing units 270. The timing units 270 can be regarded as units using clock signals in an integrated circuit, and 0 can also be referred to as a load.

[0040] The clock source 210 is used to generate clock signals, which includes elements capable of actively sending out clock signals (e.g., an active crystal oscillator or a passive crystal oscillator). Since different timing units 270 have different requirements for clock frequencies, the clock source 210 can also include elements for multiplying clock signals (e.g., a phase-locked loop) or elements for dividing clock signals (e.g., a frequency divider). In some embodiments, the clock source 210 can be a clock input port for introducing clock signals from a top chip.

[0041] The global tree 220 is used to deliver clock signals sent out by the clock source 210 with a small clock skew. The global tree 220 includes a plurality of drivers (e.g., buffers or inverters). These drivers can be laid out in a tree structure (e.g., a binary tree or an H-tree), a fishbone structure, or other structures.

[0042] The mesh driver stage 230 is used to drive the clock mesh 240. The mesh driver stage 230 includes a plurality of drivers (e.g., buffers or inverters).

[0043] The clock mesh 240 is used to deliver clock signals to the timing units 270. The clock mesh 240 is a mesh structure formed by shorting some clock signal nodes together, which can reduce the difference of the clock signals delivered to the timing units 270. The metal lines constituting the mesh structure are connected by vias at intersections.

[0044] The tap driver stage 250 is used to couple the clock mesh 240 to the timing units 270. The coupling can be direct coupling or coupling through a tree structure.

[0045] The gating unit 260 is used to turn on and off the clock signals of the timing units 270. Cutting off the clock signals of the timing units 270 when they are not working helps to reduce the dynamic power consumption of the chip.

[0046] The global tree 220 is a common part of the clock path, which can distribute clock signals to the entire clock region, thereby solving the problem of large fan-out and large load of the clock network. The local tree 280 is a non-common part of the clock path, with a small interconnection range.

[0047] The example clock tree 200 described with reference to FIG. 2 is a structurally multi-source clock tree, which reduces on-chip variation (OCV) impact and improves clock tree performance compared to conventional clock trees. For this type of clock tree, the user has strong freedom in design. For example, the global tree, clock mesh, mesh driver stage, tap driver stage, etc. can be customized by the user. However, the local tree is based on register transfer level (RTL), and thus the instantiation of the clock tree is relatively limited. The local tree can be integrated and split by clock logic units in the clock tree synthesis stage without changing the number of logic stages and clock structure.

[0048] In the following, this type of clock tree is mainly described as an example, but it should be understood that this is only exemplary and is not intended to limit the solutions of the present disclosure. Embodiments of the present disclosure are applicable to any appropriate type of clock tree.

[0049] Clock tree design

[0050] In the design stage of the clock tree, the electronic device 120 automatically determines a candidate clock tree structure for the clock tree based on a set of structure parameters for a plurality of parts of the clock tree. The set of structure parameters includes a plurality of structure parameters for defining the plurality of parts of the clock tree. For example, the plurality of parts can be the global tree 220, the mesh driver stage 230, the clock mesh 240 and the tap driver stage 250 described above with reference to FIG. 2. The structure parameters can include, but are not limited to, the number of buffer units in the respective parts, the location in the integrated circuit. For the clock mesh, the structure parameters can include parameters of the pattern of the clock mesh, such as will be described below.

[0051] In some embodiments, at least one structure parameter in the set of structure parameters can be automatically set by the electronic device 120. For example, for a certain structure parameter, the electronic device 120 can automatically select one or more parameter values from a set of candidate parameter values to implement the setting for the structure parameter. For another example, the electronic device 120 can perform interval sampling within a possible value range of the parameter value, thereby determining a plurality of parameter values, and using the parameter values to set the structure parameter.

[0052] Alternatively or additionally, in some embodiments, at least one structure parameter in the set of structure parameters can be customized by the user. Specifically, the electronic device 120 can provide a user interface for structure configuration, and receive at least one parameter in the set of structure parameters via the user interface. The parameter customized by the user can correspond to at least one part of the clock tree. In particular, in this way, customization of the corresponding unit can be implemented.

[0053] In some embodiments, the structure of one or more of the clock grid 240, the grid drive stage 230, and the tap drive stage 250 can be customized by a user. For example, the electronic device 120 can provide a user interface for the grid drive stage 230. Accordingly, the user can specify, via the interface, the number and location distribution of the individual buffer units in the grid drive stage 230, etc. Alternatively or additionally, the electronic device 230 can provide a user interface for the tap drive stage 250. Accordingly, the user can specify, via the interface, the number and location distribution of the buffer units in the tap drive stage 250, etc. Alternatively or additionally, a user interface can be provided for the grid drive stage 230. Accordingly, the user can specify, via the interface, the pattern of the clock grid 240.

[0054] FIG. 3 illustrates a flowchart of an example process 300 of clock tree design, according to some embodiments of the present disclosure. The process 300 is described with the clock tree 200 shown in FIG. 2 as an example. The concepts of clock tree design described with reference to FIG. 3 are also applicable to other types of clock trees.

[0055] At block 310, the electronic device 120 obtains a database. In the database, all the placement operations are completed, including the placement and addition of the required elements. For example, the clock units and the logic units have been placed, the preliminary physical units and power supply schemes have been added, etc.

[0056] The clock units include the clock source 210 and the stages of drivers. The clock source 210 can be referred to as a root node. The timing units 270 can be referred to as sink nodes. The clock signal travels from the clock source 210 through a series of distribution nodes to the timing units 270. The physical units include units without logic functions, such as units for noise reduction. At block 310, the electronic device 120 is ready for the basic conditions of normal clock tree synthesis.

[0057] At block 320, the electronic device 120 performs tap drive stage customization. Specifically, the user’s specification of one or more structural parameter values of the tap drive stage 250 can be received. For example, the user can reasonably select the number and location of the tap drivers (e.g., buffer units) according to the distribution of the sink nodes. The electronic device 120 receives, through the user interface, the structural parameters of the tap drive stage 250, such as the number and location of the buffer units in the tap drive stage 250. For example, the user can be provided with an interface for defining the structure of the tap drive stage, and then the processing is automatically performed according to the user’s input. Alternatively or additionally, in some embodiments, the electronic device 120 can set a given number of buffer units at the corresponding locations based on an average allocation mode. In some embodiments, both user customization and automatic allocation modes can be supported, or one of the modes can be selected or enabled by the user.

[0058] At block 330, the electronic device 120 performs clock mesh customization. Specifically, the electronic device 120 can receive user's specification of one or more values of structural parameters of the clock mesh 240. For example, the user can design the clock mesh 240 according to the specific parameters and analysis of the results, in combination with consideration of resources. The electronic device 120 receives, through a user interface, the structural parameters of the clock mesh 240, such as routing width, routing pitch, pattern pitch, offset, and the like. The routing width refers to the width of the metal lines constituting the mesh structure. The routing pitch refers to the distance between the metal lines constituting the mesh structure. The pattern pitch refers to the distance between different patterns in the mesh. The offset refers to the movement of the mesh relative to a reference position. The user can customize the optimized design according to the specific parameters and analysis of the results, in combination with consideration of resources and the like.

[0059] At block 340, the electronic device 120 performs grid driver level customization. Specifically, the electronic device 120 can receive user's specification of one or more values of structural parameters of the grid driver level 230. For example, the user can design the grid driver level 230 according to the required driving capability and the structure of the clock mesh 240, such as the number and location of buffer units. The electronic device 120 receives, through a user interface, the structural parameters of the grid driver level 230, such as the number and location of buffer units in the grid driver level 230. In some embodiments, the electronic device 120 receives parasitic electrical parameters in the clock mesh 240, such as parasitic capacitance and resistance of the routing, for correcting on-chip errors. The number and location of buffer units can be reasonably designed in combination with the parasitic electrical parameters (e.g., parasitic capacitance and resistance) and simulation results.

[0060] At block 350, the electronic device 120 designs the global tree 220. For example, the user can specify the network structure of the global tree 220, such as an H-tree or a traditional clock tree synthesis, while ensuring that the grid driver level 230 can be driven. The electronic device 120 can insert buffers and route clock signals based on the network structure to generate the global tree 220. Additionally or alternatively, the electronic device 120 can add ground lines for shielding interference to prevent parasitic interference of other signal lines on the network structure. For example, the ground lines can be added according to non-default rules to ensure clock tree performance.

[0061] At block 360, the electronic device 120 performs wire connection of the clock mesh 240. For example, the electronic device 120 connects the input and output of the clock mesh 240 in proximity. Specifically, the output end of the clock mesh 240 is connected to the tap driver level 250, and the input end of the clock mesh 240 is connected to the grid driver level 230. Further, the global tree 220 and the local tree 280 upstream and downstream of the clock mesh 240 can be combined and connected.

[0062] At block 370, the electronic device 120 performs structural generation on the partial tree 280. For example, the electronic device 120 can integrate or split the gating cells 260 to connect to the buffer cells in the tap driver stage 250. Further, the electronic device 120 can perform clock tree synthesis based thereon. Alternatively, the processing can also be customized by the user according to the specific clock tree structure.

[0063] In summary, the electronic device 120 can receive user’s free customization on multiple parts of the clock tree, and automatically generate the clock tree structure based on the user customized set of structure parameters. For example, by design aspect optimization, it is possible to help the user to quickly implement parameter customized clock grid pattern (e.g., width, pitch, etc.), grid driver (e.g., position, number, etc.), tap driver (e.g., position, number, etc.) to design different clock tree structures, so as to optimize the clock tree performance parameters.

[0064] In the example process described above with reference to FIG. 3, the interface for defining the structure parameters is provided for the user’s customized requirements. In this way, it is possible to automatically run according to the user defined structure parameters. This can advantageously avoid human interference.

[0065] Clock tree evaluation

[0066] When evaluating the clock performance of the clock tree, it is necessary to extract parasitic parameters for different clock tree structures, especially the structures containing clock grid, for simulation of the clock tree structure. The traditional static timing analysis tool cannot directly perform static timing analysis on the clock tree containing clock grid, and therefore some embodiments of the present disclosure provide a solution to this defect.

[0067] The electronic device 120 first automatically generates the clock tree structure based on the set of structure parameters 110, such as described with reference to FIG. 3. Then, the electronic device 120 generates circuit configuration information associated with the clock tree structure. Such circuit configuration information indicates the connection relationship of the circuit cells in the clock tree structure. Then, the electronic device 120 simulates and optimizes the clock tree structure based on the circuit configuration information. Finally, the evaluation result 130 of the clock performance for the clock tree structure is output.

[0068] FIG. 4 shows a flowchart of an example process 400 of clock tree evaluation according to some embodiments of the present disclosure. The process 400 is described with the clock tree 200 shown in FIG. 2 as an example, but this is only exemplary. The concept of clock tree verification described with reference to FIG. 4 is also applicable to other types of clock trees.

[0069] At block 410, the electronic device 120 extracts parasitic electrical parameters of the clock tree 200. Because the clock mesh 240 has multiple driving sources, the electronic device 120 extracts parasitic electrical parameters (e.g., parasitic resistance, parasitic capacitance, etc.) of the entire clock network. For example, after the clock tree 200 is designed, the electronic device 120 derives an exchange format file and a netlist of the design. The exchange format file contains location distribution and routing information of each part of the clock tree. The electronic device 120 extracts the parasitic electrical parameters from the exchange format file and outputs a parasitic electrical parameter file. In some embodiments, the electronic device 120 only extracts the parasitic electrical parameters of the clock mesh 240 to reduce computation and improve evaluation efficiency.

[0070] At block 420, the electronic device 120 performs static timing analysis on the clock tree 200. The static timing analysis can obtain electrical configuration information indicating connection relationships of circuit units in the designed clock tree structure. As an example, if the subsequent simulation verification uses SPICE simulation, an input for the SPICE simulation flow can be generated. For example, the static timing analysis flow can be implemented or embedded into an input generation system of the SPICE simulation environment.

[0071] At block 430, the electronic device 120 performs simulation verification on the clock tree 200. For example, the electronic device 120 implements simulation verification on the clock tree 200 based at least on the parasitic electrical parameters and the electrical configuration information. The input of the simulation verification can also include simulation modes, etc., depending on the specific simulation environment used.

[0072] Through the simulation, an evaluation result of the clock performance of the clock tree structure can be obtained. The evaluation result can include path delay, clock propagation latency, clock skew, clock transition, clock uncertainty, clock level, etc.

[0073] In some embodiments, the clock tree design, parasitic electrical parameter extraction, static timing analysis, and simulation verification flow can be implemented automatically, which not only solves the problem of complex cooperation of multiple tools in the traditional design-to-verification flow, but also solves the problem that the traditional static timing analysis tool cannot perform static analysis on the clock tree containing the clock mesh.

[0074] Blocks 410, 420, and 430 in process 400 can be performed for each clock tree structure (also referred to as a candidate clock tree structure) obtained or designed in process 300, so as to obtain the clock performance of each clock tree structure. For example, automatic iteration of the above flow can be performed for different user-customized structures. In this automatic iteration, no manual intervention is needed.

[0075] In some embodiments, the electronic device 120 determines a plurality of clock tree structures based on a plurality of combinations of structure parameters, respectively. For example, the electronic device 120 receives parameter values input by a user regarding the routing positions and routing widths of the clock grid 240, and parameter values regarding the numbers of the grid driver stage 230 and the tap driver stage 250. The electronic device 120 combines these parameters, determines a plurality of clock tree structures, respectively, and outputs evaluation results for each clock tree structure. For example, for each clock tree structure, the blocks 410, 420, and 430 are performed.

[0076] In some embodiments, at block 440, the electronic device 120 can further analyze and optimize the simulation results of the clock tree structures. As mentioned above, a plurality of different clock tree structures can be obtained by customizing different parameters, and simulation results for each clock tree structure (or each set of structure parameters) can be obtained after blocks 410-430 are performed automatically. By analyzing and comparing these simulation results, optimized structure parameters can be obtained.

[0077] In some embodiments, the electronic device 120 can present an interface of the evaluation results 130 or provide a user interface outputting the evaluation results 130 to a user. The evaluation results 130 include clock performances determined for the plurality of clock tree structures, respectively.

[0078] Tables 1-4 show evaluation results of clock tree structures according to some embodiments of the present disclosure. In this example, the set of structure parameters can include the routing pitch and routing width of the clock grid 240, and the number of buffer units in the tap driver stage 250 and the number of buffer units in the grid driver stage 230. The electronic device 120 generates a plurality of clock tree structures and their evaluation results 130 based on combinations of these structure parameters. The evaluation results 130 include the longest path delay and the shortest path delay from the clock source 210 to the timing unit 270. The difference between the longest path delay and the shortest path delay is the clock skew. According to the clock domain and the path relationship, the clock skew can be divided into global skew and local skew. The global skew refers to the maximum skew of any two path delays in the same clock domain. The local skew refers to the maximum skew of any two path delays with a logical relationship in the same clock domain. The evaluation results of Tables 1-4 are compared by taking the global skew as an example.

[0079] Table 1 shows the influence of the change of the routing width of the clock grid 240 on the global skew when the routing pitch of the clock grid 240, the number of buffer units in the tap driver stage 250, and the number of buffer units in the grid driver stage 230 remain unchanged. Each row represents a clock tree structure. As can be seen, the narrower the routing width, the smaller the global skew.

[0080] Table 1 shows the evaluation results of the clock tree structures based on the first set of structure parameter combinations

[0081] Table 2 differs from Table 1 in that the number of buffer units in the grid driver stage 230 is adjusted from 20 to 30. Comparing Table 2 and Table 1, it can be seen that the more the number of grid driver stages 230, the smaller the global skew.

[0082] Table 2 evaluation results of clock tree structures based on a second set of structural parameter combinations

[0083] Table 3 differs from Table 1 in that the routing pitch of the clock grid 240 is adjusted from 229.824 pm to 114.912 pm. Comparing Table 3 and Table 1, it can be seen that the larger the routing pitch, the smaller the global skew.

[0084] Table 3 evaluation results of clock tree structures based on a third set of structural parameter combinations

[0085] Table 4 differs from Table 3 in that the number of buffer units in the tap driver stage 230 is adjusted from 20 to 40. Comparing Table 4 and Table 3, it can be seen that the fewer the number of tap driver stages 230, the smaller the global skew.

[0086] Table 4 evaluation results of clock tree structures based on a fourth set of structural parameter combinations

[0087] It should be appreciated that the data listed in Tables 1-4 are merely exemplary and are not intended to limit the scope of the present disclosure.

[0088] In summary, according to various embodiments of the present disclosure, the electronic device 120 can implement customization of multiple parts of a clock tree based on a set of structural parameters 110 input by a user, and automatically generate multiple clock tree structures without human intervention. The electronic device 120 can also perform clock performance evaluation on the multiple clock tree structures and output evaluation results 130. During the evaluation process, the electronic device 120 automatically performs simulation optimization, solving the problem that traditional static timing analysis tools cannot handle multi-driver structures of clock grids. Further, the electronic device 120 implements full-flow automation of user customization design, parasitic electrical parameter extraction, static timing analysis, simulation verification, and evaluation result display, providing an excellent design optimization flow for back-end clock tree design.

[0089] In other words, the processes 300 and 400 described above with reference to FIGS. 3 and 4 can be implemented automatically. In this way, full-flow automation solutions from design to verification and even to optimization are implemented for clock trees.

[0090] Example process

[0091] FIG. 5 shows a flowchart of a method 500 for evaluating a clock tree, according to some embodiments of the present disclosure. The method 500 can be implemented at the electronic device 120. The method 500 is described below with reference to FIG. 1.

[0092] At block 510, the electronic device 120 automatically determines a candidate clock tree structure for the clock tree based on a set of structure parameters for a plurality of portions of the clock tree, each structure parameter of the set of structure parameters being used to define a structure of one portion of the plurality of portions. At block 520, circuit configuration information associated with the candidate clock tree structure is obtained, the circuit configuration information indicating a connection relationship of circuit cells in the candidate clock tree structure. At block 530, clock performance of the candidate clock tree structure is determined based at least on the circuit configuration information.

[0093] In some embodiments, to determine the candidate clock tree structure, the electronic device 120, in response to at least one structure parameter of the set of structure parameters having different parameter values, determines a plurality of structure parameter combinations, each structure parameter combination including a set of parameter values for defining the plurality of portions; determines a plurality of clock tree structures for the clock tree based on the plurality of structure parameter combinations, respectively; and sets the plurality of clock tree structures as the candidate clock tree structure, respectively.

[0094] In some embodiments, the electronic device 120 presents the clock performance determined for the plurality of clock tree structures, respectively.

[0095] In some embodiments, to determine the plurality of clock tree structures, respectively, the electronic device 120, for a given structure parameter combination of the plurality of structure parameter combinations, determines respective structures of the plurality of portions; and determines a clock tree structure of the plurality of clock tree structures corresponding to the given structure parameter combination based on the respective structures of the plurality of portions and a relative relationship between the plurality of portions.

[0096] In some embodiments, the electronic device 120, for at least one portion of the plurality of portions, provides a user interface for structure configuration; and receives at least one parameter of the set of structure parameters via the user interface, the at least one parameter corresponding to the at least one portion, respectively.

[0097] In some embodiments, the at least one portion includes at least one of: a clock mesh for delivering a clock signal to a timing cell, a mesh driver stage for driving the clock mesh, or a tap driver stage for coupling the clock mesh to the timing cell.

[0098] In some embodiments, the plurality of portions includes a clock mesh for delivering a clock signal to a timing cell, and to determine the clock performance, the electronic device 120 is further based on a parasitic electrical parameter in the candidate clock tree structure.

[0099] Example apparatus and devices

[0100] FIG. 6 illustrates a schematic structural block diagram of an apparatus 600 for evaluating a clock tree, according to certain embodiments of the present disclosure. The apparatus 600 can be implemented as or included in the electronic device 120. Various modules / components in the apparatus 600 can be implemented by hardware, software, firmware, or any combination thereof.

[0101] As shown, the apparatus 600 includes a clock tree structure determination module 610 configured to automatically determine a candidate clock tree structure for the clock tree based on a set of structure parameters for a plurality of portions of the clock tree, each structure parameter of the set of structure parameters being used to define a structure of one of the plurality of portions. The apparatus 600 further includes a circuit configuration information obtaining module 620 configured to obtain circuit configuration information associated with the candidate clock tree structure, the circuit configuration information being indicative of connection relationships of circuit cells in the candidate clock tree structure. The apparatus 600 further includes a clock performance determination module 630 configured to determine a clock performance of the candidate clock tree structure based at least on the circuit configuration information.

[0102] In some embodiments, the clock tree structure determination module is configured to: in response to at least one structure parameter of the set of structure parameters having a different parameter value, determine a plurality of structure parameter combinations, each structure parameter combination including a set of parameter values used to define the plurality of portions; determine a plurality of clock tree structures for the clock tree based on the plurality of structure parameter combinations, respectively; and set the plurality of clock tree structures as the candidate clock tree structure, respectively.

[0103] In some embodiments, the apparatus 600 further includes a clock performance presentation module configured to present the clock performance determined for the plurality of clock tree structures, respectively.

[0104] In some embodiments, the clock tree structure determination module is further configured to: for a given structure parameter combination of the plurality of structure parameter combinations, determine respective structures of the plurality of portions; and determine a clock tree structure of the plurality of clock tree structures corresponding to the given structure parameter combination based on the respective structures of the plurality of portions and relative relationships among the plurality of portions.

[0105] In some embodiments, the apparatus 600 further includes a user interface providing module configured to provide a user interface for structure configuration for at least one portion of the plurality of portions, and a parameter set receiving module configured to receive at least one parameter of the set of structure parameters via the user interface, the at least one parameter corresponding to the at least one portion, respectively.

[0106] In some embodiments, the at least one portion includes at least one of: a clock grid for delivering a clock signal to a timing cell, a grid driving stage for driving the clock grid, or a tap driving stage for coupling the clock grid to the timing cell.

[0107] In some embodiments, the plurality of portions includes a clock mesh for passing a clock signal to the timing unit, and wherein the clock performance determination module is further configured to determine clock performance based on parasitic electrical parameters in the candidate clock tree structure.

[0108] FIG. 7 illustrates a block diagram of an electronic device 700 in which one or more embodiments of the disclosure can be implemented. It should be understood that the electronic device 700 illustrated in FIG. 7 is merely an example and should not be construed to limit the functionality and scope of the embodiments described herein. The electronic device 700 illustrated in FIG. 7 can be used to implement the electronic device 120 of FIG. 1.

[0109] As illustrated in FIG. 7, the electronic device 700 is in the form of a general electronic device. Components of the electronic device 700 can include, but are not limited to, one or more processors or processing units 710, a memory 720, a storage device 730, one or more communication units 740, one or more input devices 750, and one or more output devices 760. The processing unit 710 can be a real or virtual processor and is capable of executing various processing according to programs stored in the memory 720. In a multi-processor system, multiple processing units execute computer-executable instructions in parallel to improve parallel processing capabilities of the electronic device 700.

[0110] The electronic device 700 typically includes a number of computer storage media. Such media can be any available media that is accessible by the electronic device 700 and includes both volatile and non-volatile media, removable and non-removable media. The memory 720 can be a volatile memory (e.g., registers, cache, random access memory (RAM)), a non-volatile memory (e.g., read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory), or some combination thereof. The storage device 730 can be a removable or non-removable media and can include machine-readable media such as a flash drive, a magnetic disk drive, or any other media that can be used to store information and / or data (e.g., training data for training) and that can be accessed by the electronic device 700.

[0111] The electronic device 700 can further include additional detachable / non-detachable, volatile / non-volatile storage media. Although not shown in FIG. 7, a disk drive for reading from or writing to a detachable, non-volatile magnetic disk (e.g., a "floppy disk"), and an optical disk drive for reading from or writing to a detachable, non-volatile optical disk (e.g., a CD-ROM) can be provided. In these cases, each drive can be connected to the bus (not shown) by one or more data media interfaces. The memory 720 can include a computer program product 725 having one or more program modules configured to carry out the various methods or acts of the various embodiments of the present disclosure.

[0112] The communication unit 740 enables communication with other electronic devices over communication media. Additionally, the functionality of the components of the electronic device 700 can be implemented in a single computing cluster or a plurality of computer machines capable of communicating over a communication connection. As such, the electronic device 700 can operate in a networked environment using logical connections to one or more other servers, network personal computers (PCs), or another network nodes in the networking environment.

[0113] The input device 750 can be one or more input devices, such as a mouse, a keyboard, a trackball, etc. The output device 760 can be one or more output devices, such as a display, a speaker, a printer, etc. The electronic device 700 can also communicate with one or more external devices (not shown) such as a storage device, a display device, etc., one or more devices that enable a user to interact with the electronic device 700, or any devices (e.g., a network card, a modem, etc.) that enable the electronic device 700 to communicate with one or more other electronic devices, as needed, through the communication unit 740. Such communication can be carried out via an input / output (I / O) interface (not shown).

[0114] According to an example implementation of the present disclosure, there is provided a computer-readable storage medium having computer-executable instructions stored thereon, where the computer-executable instructions are executed by a processor to implement the method described above. According to an example implementation of the present disclosure, there is also provided a computer program product tangibly stored on a non-transitory computer-readable medium and including computer-executable instructions, where the computer-executable instructions are executed by a processor to implement the method described above.

[0115] Various aspects of the disclosure are now described with reference to the drawings. In general, the drawings described below are diagrammatic and schematic representations of actual or conceptual structures and processes, and are not limiting of the scope of the present disclosure. In the drawings, the size and relative positioning of components can be exaggerated for clarity and / or descriptive purposes. Also, the drawings represent examples of apparatuses and / or methods in accordance with the present disclosure. In some instances, various aspects of the disclosure can be shown in a diagram, or by a series of diagrams, and can include a set of one or more apparatuses or a set of steps performed by one or more apparatuses. Each diagram can represent one or more processes, methods, or apparatuses depending upon the particular point of view of the diagram in question. Thus, diagrams in and of themselves can not encompass the entire scope of the present disclosure. Various examples of the present disclosure are described in terms of diagrams that will be understood by persons of skill in the art and related communications and / or computer applications as provided by the claims.

[0116] The computer readable program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide processes for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0117] The computer readable program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide processes for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0118] The computer readable program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide processes for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0119] implementations of the present disclosure have been described above, the description is illustrative only and not restrictive ones, and is not limited to the disclosed implementations. Numerous modifications and variations will become apparent to those skilled in the art in light of the above teachings. The terminology used is for the purpose of describing the various implementations only and is not intended to limit the scope of the present disclosure. It is to be understood that the use of the singular herein, such as the use of "the item" to describe the singular instance of the item and possibly other items, is only for convenience and that "the item" is intended to cover one or more instances of the item.

Claims

1.A method for evaluating a clock tree, comprising: determining, automatically, a candidate clock tree structure for the clock tree based on a set of structure parameters for a plurality of portions of the clock tree, each structure parameter of the set of structure parameters being used to define a structure of one of the plurality of portions; obtaining circuit configuration information associated with the candidate clock tree structure, the circuit configuration information indicating a connection relationship of circuit cells in the candidate clock tree structure; and determining, based at least on the circuit configuration information, a clock performance of the candidate clock tree structure. 2.The method of claim 1, wherein determining the candidate clock tree structure comprises: in response to at least one structure parameter in the set of structure parameters having different parameter values, determining a plurality of structure parameter combinations, each structure parameter combination including a set of parameter values used to define the plurality of portions; determining, based on the plurality of structure parameter combinations, a plurality of clock tree structures for the clock tree respectively; and setting the plurality of clock tree structures as the candidate clock tree structure respectively. 3.The method of claim 2, further comprising: presenting the clock performance determined for the plurality of clock tree structures respectively. 4.The method of claim 2, wherein determining the plurality of clock tree structures respectively comprises: for a given structure parameter combination in the plurality of structure parameter combinations, determining respective structures of the plurality of portions; and based on the respective structures of the plurality of portions and a relative relationship among the plurality of portions, determining a clock tree structure in the plurality of clock tree structures corresponding to the given structure parameter combination. 5.The method of claim 1, further comprising: providing, for at least one portion in the plurality of portions, a user interface for structure configuration; and receiving, via the user interface, at least one parameter in the set of structure parameters, the at least one parameter corresponding to the at least one portion respectively. 6.The method of claim 5, wherein the at least one portion comprises at least one of: a clock grid for delivering a clock signal to a timing cell, a grid driving stage for driving the clock grid, or a tap driving stage for coupling the clock grid to the timing cell. 7.The method of claim 1, wherein the plurality of portions comprises a clock grid for delivering a clock signal to a timing cell, and wherein determining the clock performance is further based on a parasitic electrical parameter in the candidate clock tree structure. 8.An apparatus for evaluating a clock tree, comprising: a clock tree structure determining module configured to determine, automatically, a candidate clock tree structure for the clock tree based on a set of structure parameters for a plurality of portions of the clock tree, each structure parameter of the set of structure parameters being used to define a structure of one of the plurality of portions; a circuit configuration information obtaining module configured to obtain circuit configuration information associated with the candidate clock tree structure, the circuit configuration information indicating a connection relationship of circuit cells in the candidate clock tree structure; and a clock performance determining module configured to determine, based at least on the circuit configuration information, a clock performance of the candidate clock tree structure. ​ ​ ​ ​ ​ a clock performance determination module configured to determine a clock performance of the candidate clock tree structure based at least on the circuit configuration information. 9.An electronic device comprising: at least one processing unit; and at least one memory coupled to the at least one processing unit and storing instructions for execution by the at least one processing unit, the instructions when executed by the at least one processing unit cause the electronic device to perform the method according to any one of claims 1 to 7. 10.A computer readable storage medium having stored thereon a computer program executable by a processor to implement the method according to any one of claims 1 to 7.

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