Silicon carbide wafer with low lattice distortion, and crystal

Abstract

The present application belongs to the technical field of production and processing of silicon carbides. Disclosed are a silicon carbide wafer with low lattice distortion, and a crystal. The silicon carbide wafer has a diameter of 150mm or more, and the silicon carbide wafer comprises a first main surface and a second main surface, wherein at any horizontal plane parallel to the first main surface and / or the second main surface, the radial comprehensive stress of the wafer is -30 MPa to 30 MPa, and the radial comprehensive stress is a stress value measured in a region that vertically extends from the first main surface or the second main surface into the wafer up to 1%-33% of the thickness of the wafer. The stress distribution of the silicon carbide wafer is uniform, and thus when the silicon carbide wafer is used as a substrate or a seed crystal, the residual stress in epitaxial wafers and crystals can be reduced, the genetic characteristics are optimized, and the yield is improved, thereby obtaining high-quality epitaxial wafers or crystals.

Description

Silicon carbide wafer and crystal with low lattice distortion This application claims the priority of the Chinese patent application filed with the China Patent Office on July 7, 2023, with application number 202310833964.3 and invention name “A Silicon Carbide Wafer and Crystal with Low Lattice Distortion”, the entire contents of which are incorporated by reference into this application. Technical Field The present application relates to the technical field of silicon carbide production and processing, and in particular to a silicon carbide wafer and crystal with low lattice distortion. Background Art During the growth of silicon carbide crystals, various defects such as polycrystalline, polymorphic, micropipes, and dislocations are easily introduced into the crystals due to the imbalance of Si / C ratio, introduction of impurities, and temperature gradient changes. Defects will cause lattice distortion, and more seriously, the crystal form will change, such as the generation of 4H, 6H, 3C, 15R and other polymorphic symbiosis. Lattice distortion releases stress by generating defects, that is, introducing internal stress into silicon carbide. The existence of this internal stress will reduce the quality of silicon carbide crystals and wafers, reduce the yield rate of products, and thus limit the scope of use of wafers. On the other hand, during the processing of silicon carbide wafers, most of them are cut from crystal rods by mechanical processing, such as laser cutting, wire cutting, etc., and then surface treated by mechanical processing such as grinding and polishing. Therefore, during the wafer processing, mechanical stress will cause microcracks on the surface, thereby introducing a damage layer, that is, introducing surface stress in the silicon carbide wafer. Therefore, the thermal stress of crystal growth in a single silicon carbide wafer and the residual stress caused by defects in the body are mixed with the surface stress introduced during the processing of the silicon carbide wafer. The above stresses will affect the subsequent processing and use of the silicon carbide wafer. When it is used as a seed crystal or substrate to grow crystals or epitaxial layers, the stress of the silicon carbide wafer will be inherited to the crystal or epitaxial layer, thereby reducing the quality of downstream products. Summary of the invention In order to solve the above problems, a silicon carbide wafer and crystal with low lattice distortion are provided. The radial comprehensive stress of the silicon carbide wafer is -30 to 30 MPa, and the stress distribution of the wafer is uniform. Using it as a substrate for the growth of an epitaxial layer can reduce the lattice mismatch between the wafer and the epitaxial layer, reduce the lattice distortion, thereby reducing the stress of the epitaxial wafer and improving the quality of the epitaxial wafer. When the epitaxial wafer is used as a seed crystal, the genetic characteristics can be optimized, the quality of the crystal can be improved, and the residual stress in the crystal can be reduced to obtain a high-quality crystal. According to one aspect of the present application, there is provided a silicon carbide wafer with low lattice distortion, the diameter of the silicon carbide wafer being greater than 150 mm, and the silicon carbide wafer comprising a first main surface and a second main surface; At any horizontal plane parallel to the first main surface and / or the second main surface, the radial comprehensive stress of the wafer is -30 to 30 MPa, and the radial comprehensive stress is the stress value detected in the area extending vertically from the first main surface or the second main surface into the wafer to 1% to 33% of the wafer thickness. The radial comprehensive stress is the sum of the radial internal stress and the radial surface stress of the wafer, which can reflect the complete stress information of the wafer. The wafer can be used as a wafer for epitaxial layer growth or a seed crystal for crystal growth to improve the quality of the epitaxial layer or crystal. Optionally, the diameter of the silicon carbide wafer is greater than 200 mm. Since the wafer is subjected to tensile and compressive stresses, the interplanar spacing d undergoes corresponding expansion and contraction changes. Therefore, when using Raman to test stress, the Raman peak intensity will move to low frequency or high frequency. When the wafer is subjected to tensile stress, the Raman peak shifts to low frequency, and the obtained stress value is positive. When the wafer is subjected to compressive stress, the Raman peak shifts to high frequency, and the obtained stress value is negative. Therefore, the positive and negative before the stress value in this application represent the force direction inside the wafer, and the absolute value of the value represents the magnitude of the stress. For example, when the radial comprehensive stress of the first wafer is -20MPa, and the radial comprehensive stress of the second wafer is 10MPa, the first wafer is subjected to compressive stress, the second wafer is subjected to tensile stress, and the radial comprehensive stress of the second wafer is less than the radial comprehensive stress of the second wafer. The radial comprehensive stress of the wafer includes surface stress, which varies with different processing techniques such as cutting, grinding and polishing during the wafer processing. The finer the wafer processing, the closer the surface stress of the wafer is to 0MPa, and thus the smaller the radial comprehensive stress of the wafer. Optionally, the radial comprehensive stress of the wafer is -15 to 20 MPa, Optionally, the wafer has a central area and an annular area surrounding the central area, the width of the annular area extending inward from the edge of the wafer is 5 to 30 mm, and the radial comprehensive stress of the annular area is greater than the radial comprehensive stress of the central area; Optionally, at any horizontal plane parallel to the first main surface and / or the second main surface, the radial comprehensive stress in the central area is -15-5 MPa, and the radial comprehensive stress in the annular area is 5.2-20 MPa. Optionally, at any horizontal plane parallel to the first main surface and / or the second main surface, the radial comprehensive stress in the central area is -14.5-5 MPa. According to the radial comprehensive stress values ​​of the above-mentioned central area and annular area, it can be known that there are compressive stress and tensile stress in the central area, and the annular area is mainly tensile stress. The closer the radial comprehensive stress of the central area is to the radial comprehensive stress of the annular area, the more uniform the radial comprehensive stress distribution of the wafer is, and it can be regarded as a body with uniform stress distribution. Optionally, at any horizontal plane parallel to the first main surface and / or the second main surface, S1 represents the average absolute value of the radial comprehensive stress of the central area, S2 represents the average absolute value of the radial comprehensive stress of the annular area, and 1.159≤S2 / S1≤4.984. The ratio of S2 / S1 represents the difference between the radial comprehensive stress of the annular area and the central area. From this ratio, it can be seen that the radial comprehensive stress of the annular area is greater than the radial comprehensive stress of the central area, and the closer this ratio is to 1, It is proved that the smaller the difference between the annular area and the central area, the more uniform the comprehensive stress distribution of the wafer in the radial direction. The radial comprehensive stress in the annular area is greater than that in the central area. The smaller the width of the annular area extending inward from the edge of the wafer, the larger the area of ​​the central area, and the smaller the radial comprehensive stress of the wafer. If the radial comprehensive stress in the annular area is too large, in actual use, part of the crystal in the annular area can be removed, and only the crystal in the central area can be retained, so as to obtain a higher quality wafer. Optionally, at any horizontal plane parallel to the first main surface and / or the second main surface, Smax1 is recorded as the maximum value of the radial comprehensive stress in the central area, Smin1 is recorded as the minimum value of the radial comprehensive stress in the central area, △S1=Smax1-Smin1, Smax2 is recorded as the maximum value of the radial comprehensive stress in the annular area, Smin2 is recorded as the minimum value of the radial comprehensive stress in the annular area, △S2=Smax2-Smin2, △S1<△S2. Since the radial comprehensive stress in the central area is -15-5MPa, and the radial comprehensive stress in the annular area is 5.2-20MPa, the above-mentioned maximum radial comprehensive stress refers to the actual value of the radial comprehensive stress, distinguishing between compressive stress and tensile stress. For example, at any horizontal plane parallel to the first main surface and / or the second main surface, the radial comprehensive stress in the central area is -10-2MPa, then the maximum value of the radial comprehensive stress is 2MPa, and the minimum value of the radial comprehensive stress is -10MPa, and △S1 is 12MPa. △S1 and △S2 represent the degree of change between the radial crystal plane spacing of the wafer at the microscopic level. The smaller the above-mentioned △S1 and △S2 are, the smaller the change in the radial crystal plane spacing is. Optionally, 0MPa≤△S1≤10MPa, 0MPa≤△S2≤12MPa. Optionally, 0.4MPa≤△S1≤9.7MPa, 1.2MPa≤△S2≤11.8MPa. Optionally, an axial test is performed by extending vertically into the wafer from any point on the first main surface, and the axial comprehensive stress in the central area is -5-5MPa, and the axial comprehensive stress in the annular area is -10-10MPa. The axial comprehensive stress is the stress value detected in the area extending vertically from the first main surface or the second main surface into the wafer to 1%-33% of the wafer thickness. Optionally, an axial test is performed vertically extending into the wafer from any point on the first main surface, and Smax3 is recorded as the maximum value of the axial comprehensive stress in the central area, Smin3 is recorded as the minimum value of the axial comprehensive stress in the central area, △S3=Smax3-Smin3, Smax4 is recorded as the maximum value of the axial comprehensive stress in the annular area, Smin4 is recorded as the minimum value of the axial comprehensive stress in the annular area, △S4=Smax4-Smin4, △S3<△S4. The axial comprehensive stress is the sum of the axial internal stress and the axial surface stress of the wafer. The axial comprehensive stress and radial comprehensive stress in the present application are stress values ​​detected in an area extending vertically from the first main surface or the second main surface into the wafer to 1%-33% of the wafer thickness. The specific range of this area depends on the processing state of the wafer. In actual tests, when the Raman laser is simultaneously located in the surface damage layer, damage stress extension layer and intermediate layer of the wafer, the value measured is the comprehensive stress value. The meanings of the above maximum and minimum axial comprehensive stress are the same as those of the maximum and minimum radial comprehensive stress. Compressive stress and tensile stress are distinguished in the axial direction. For example, on any axis, the axial comprehensive stress in the central area is -5-1MPa, then the maximum axial comprehensive stress is 1MPa, the minimum axial comprehensive stress is -5MPa, and △S3 is 6MPa. The △S3 and △S4 represent the degree of change in the axial inter-crystalline spacing of the wafer at the microscopic level. The smaller the △S3 and △S4 are, the smaller the change in the axial inter-crystalline spacing of the wafer is. Optionally, 0MPa≤△S3≤7MPa, 0MPa≤△S4≤10MPa. Optionally, 0MPa≤△S4≤9.9MPa. Optionally, the curvature of the wafer is -100 μm to 100 μm. Optionally, the curvature of the wafer is -50 μm to 50 μm, Optionally, the curvature of the wafer is -20 μm to 20 μm, Optionally, the curvature of the wafer is -10 μm to 10 μm. Optionally, the first main surface and / or the second main surface has an off-angle of 4° or less relative to the {0001} plane; Optionally, the crystal type of the wafer is one of 2H-SiC, 4H-SiC, 6H-SiC, 3C-SiC, and 15R-SiC. Optionally, the crystal form of the wafer is 4H-SiC. Optionally, the wafer is a semi-insulating wafer or a conductive wafer. Optionally, the local thickness deviation of the central area is 0.1-2 μm, and the local thickness deviation of the annular area is 0.1-2 μm. Optionally, the local thickness deviation of the central area is 0.1-1.3 μm, and the local thickness deviation of the annular area is 0.3-2 μm. Optionally, the comprehensive stress is a value measured by the following steps: (1) Calculate the peak position shift and stress conversion coefficient; (2) Raman is used to test the wafer, where the Raman spot is located in the surface layer and the middle layer of the wafer at the same time, wherein the surface layer is a region extending inward from the surface of the wafer to no more than 30% of the wafer thickness, and a peak value and a peak offset are obtained. The comprehensive stress of the wafer is calculated based on the peak offset and the peak offset and stress conversion coefficient in step (1), and the radial comprehensive stress of the wafer is calculated to be -30 to 30 MPa; Optionally, before step (2), the step of using Raman to perform axial testing on the wafer is also included to determine the depth of the wafer surface layer, wherein the surface layer includes a surface damage layer and a damage stress extension layer, and the Raman spot is simultaneously located in the surface damage layer, the damage stress extension layer and the intermediate layer. Optionally, with the wafer surface as the zero point, the test range of the axial test is from -150 μm to -30 μm inside the wafer to above the wafer surface. Optionally, in the Raman test of step (2), the center point of the Raman spot is located at the junction or inside of the damage stress extension layer, and the junction of the damage stress extension layer includes the junction between the damage stress extension layer and the surface damage layer or the intermediate layer; or the center point of the Raman spot is located inside the damage stress extension layer. Optionally, the center point of the Raman laser spot is located at the junction of the damaged stress extension layer and the inside of the wafer. Optionally, the calculation steps of the peak position offset and the stress conversion coefficient are: Test and calculate the interplane spacing dx and interplane spacing difference △d at different positions of the wafer, and use Hooke's law or stress-strain formula to calculate the stress values ​​at different positions; The peak position value of the wafer is tested by Raman, and the peak position offset at different positions is calculated. The ratio of the peak position offset to the stress value is the peak position offset and stress conversion coefficient. Optionally, the wafer is tested using any one or more of an XRD diffractometer, a synchrotron radiation tester, a white light tester, a neutron diffractometer, a scanning electron microscope, and a transmission electron microscope to obtain the interplanar spacing dx at different positions of the wafer, and calculate the interplanar spacing difference Δd. Optionally, before step (2), the step of performing a curvature test on the surface of the wafer is also included. According to the curvature of the wafer, in step (2), an equidistant focusing Raman test is performed on the surface and interior of the wafer. The equidistant focusing test is to control the distance between the Raman laser spot and the substrate surface at each test point to be equal, and the peak position value and peak position offset are obtained after fitting. After the test in step (2), the peak position value is first obtained by fitting, and this peak position value is compared and calculated with the standard peak to obtain the peak position offset. Optionally, the fitting uses functions including Gaussian, Lorentz, GaussLor, AGauss, Aloren and AgaussLor. According to another aspect of the present application, there is provided a silicon carbide crystal with low lattice distortion, wherein the thickness of the crystal is not less than 1 mm, and the diameter of the crystal is not less than 150 mm; The crystal includes an upper surface and a lower surface, and the crystal has a peripheral region and a middle region that penetrate the upper surface and the lower surface. The width of the peripheral region extending inward from the edge of the crystal is 5 to 30 mm. At any horizontal plane from the upper surface to the lower surface, the stress in the peripheral region is greater than the stress in the middle region. Optionally, the diameter of the crystal is greater than 200 mm. Optionally, at any horizontal plane from the upper surface to the lower surface, the radial stress in the peripheral area is 5.2-20 MPa, and the radial stress in the middle area is -15-5 MPa. Optionally, at any horizontal plane from the upper surface to the lower surface, the radial stress in the peripheral area is 5.2-19.6 MPa, and the radial stress in the middle area is -14.7-5 MPa. Optionally, an axial test is performed extending downward from any point on the upper surface of the crystal, and the axial stress in the peripheral area is -10-10 MPa, and the axial stress in the middle area is -5-5 MPa. Optionally, an axial test is performed extending downward from any point on the upper surface of the crystal, and the axial stress in the peripheral area is -9.3-9.1 MPa, and the axial stress in the middle area is -4.3-4.9 MPa. Optionally, at any plane parallel to the upper surface and / or lower surface, S3 represents the maximum absolute value of radial stress in the middle region, S4 represents the maximum absolute value of radial stress in the peripheral region, and -8MPa≤S4-S3≤10MPa. Optionally, -7.5MPa≤S4-S3≤9.9MPa; Optionally, at any plane parallel to the upper surface and / or lower surface, Smax5 is recorded as the maximum radial stress in the middle region, Smin5 represents the minimum radial stress in the middle region, △S5=Smax5-Smin5, Smax6 is recorded as the maximum radial stress in the peripheral region, Smin6 is recorded as the minimum radial stress in the peripheral region, △S6=Smax6-Smin6, △S5<△S6. The above-mentioned maximum radial stress value refers to the actual value of the radial stress, which distinguishes between compressive stress and tensile stress. For example, at any horizontal plane parallel to the upper surface and / or lower surface, the radial stress in the middle area is -8-2MPa, then the maximum value of the radial stress is 2MPa, and the minimum value of the radial stress is -8MPa. △S5 is 10MPa. △S5 and △S6 represent the degree of change in the radial interplanar spacing of the crystal at the microscopic level. The smaller the above-mentioned △S5 and △S6 are, the smaller the change in the radial interplanar spacing of the crystal is. Optionally, 0MPa≤△S5≤8MPa, 0MPa≤△S6≤10MPa. Optionally, 0MPa≤△S5≤7.7MPa, 0MPa≤△S6≤9.8MPa. Optionally, an axial test is performed vertically extending into the crystal from any point on the upper surface, S5 represents the maximum absolute value of the axial stress in the middle region, S6 represents the maximum absolute value of the axial stress in the peripheral region, -5MPa≤S6-S5≤5MPa; the difference represents the difference between the peripheral region and the middle region, and the smaller the difference is, the more uniform the distribution of the crystal in the radial direction is. Optionally, -4.2MPa≤S6-S5≤4.7MPa. Optionally, an axial test is performed by extending vertically from any point on the upper surface into the crystal, Smax7 is recorded as the maximum axial stress in the middle region, Smin7 is recorded as the minimum axial stress in the middle region, △S7=Smax7-Smin7, Smax8 is recorded as the maximum axial stress in the peripheral region, Smin8 is recorded as the minimum axial stress in the peripheral region, △S8=Smax8-Smin8, △S7<△S8; Optionally, 0MPa≤△S7≤7MPa, 0MPa≤△S8≤10MPa. Optionally, 0.2MPa≤△S7≤7MPa, 0.3MPa≤△S8≤9.2MPa. The above-mentioned maximum axial stress and minimum axial stress have the same meanings as the maximum radial stress and minimum radial stress. Compressive stress and tensile stress are distinguished in the axial direction. For example, on any axis, the axial comprehensive stress in the central area is -5-1MPa, then the maximum axial comprehensive stress is 1MPa, and the minimum radial comprehensive stress is -5MPa. △S7 is 6MPa. △S7 and △S8 represent the degree of change in the axial interplanar spacing of the crystal at the microscopic level. The smaller the above-mentioned △S7 and △S8 are, the smaller the change in the axial interplanar spacing of the crystal is. Optionally, the width of the annular area extending inward from the edge of the wafer is 5 to 15 mm. The above stress values ​​include absolute stress and relative stress. Absolute stress can reflect the difference between the substrate and the perfect SiC crystal without defects, and is used to determine the stress level of the SiC substrate. However, since it is difficult to achieve a perfect SiC substrate with current technology, the relative stress distribution within the substrate surface can be determined by relative stress. For example, when the absolute stress of the substrate is large and the relative stress is small, it means that there are more in-plane defects, but the stress distribution is uniform, the crystal quality is poor, and the uniformity quality in each area of ​​the substrate is poor; if the absolute stress is small and the relative stress is large, the overall substrate quality is good, but there are abnormal quality deviations in some areas. The reference value of absolute stress in this application is the reference stress calculated based on the standard Raman peak position obtained from the perfect lattice parameters of SiC, which is marked as 0; the relative stress is to take a reference value on the entire test plane, and the value of each test point is related to the reference value to obtain the relative stress value of the test point. The reference value includes but is not limited to the median of all stress values ​​on the entire test plane, Any of the results calculated by the mean, mode, or other statistical functions. According to another aspect of the present application, a method for preparing a silicon carbide single crystal is provided, comprising the following steps: (1) Adding silicon carbide powder into a graphite crucible; (2) The furnace body is vacuumed to below 10-6 mbar, and then high-purity inert gas is introduced to 300-500 mbar. This process is repeated 2-3 times, and finally the furnace body is vacuumed to below 10-6 mbar; (3) introducing high-purity inert gas into the furnace body, raising the pressure to 10-100 mbar within 1-3 hours, and continuously introducing high-purity inert gas and maintaining the pressure constant; (4) Crystal growth stage: While maintaining the pressure unchanged, the temperature inside the furnace is raised to the single crystal growth temperature of 2200K-2800K within 3-5 hours, and the growth time is 30-150 hours; (5) After the single crystal growth is completed, open the furnace body and take out the graphite crucible to obtain the silicon carbide single crystal. Optionally, the graphite crucible is coated with a TaC coating, the TaC coating is deposited on the surface of the graphite substrate, and through-type through holes are evenly distributed in the TaC coating, and the density of the through-type through holes is 160-310 / mm2. The TaC coating contains through-holes, which can improve the transmission rate of the silicon carbide raw material atmosphere while improving the uniformity of the temperature field during crystal growth, thereby increasing the growth rate of the crystal and reducing the internal stress of the crystal, obtaining a high-quality silicon carbide crystal with uniform stress distribution. Optionally, the diameter of the through-type through hole is 2-7 μm. Optionally, the diameter of the through-type through hole is 2.3-6.1 μm. This aperture can not only improve the transmission rate of the silicon carbide raw material atmosphere without reducing the protection performance of the graphite substrate, but also avoid the edge stress of the crystal caused by the thermal expansion and compression of the graphite substrate in the thermal field, thereby further reducing the stress in the crystal. Optionally, the thickness of the TaC coating is 30-400 μm, the TaC grains in the TaC coating are arranged in a stacking staggered manner, and the size of the TaC grains is 15-50 μm.

[0200] The growth direction of the TaC grains can improve the temperature resistance and thermal chemical corrosion resistance of the TaC coating, thereby reducing the interference of the graphite substrate on the crystal growth environment and improving the stability of the crystal environment. The beneficial effects of this application include but are not limited to: 1. The radial comprehensive stress of silicon carbide wafer is -30~30Mpa, and the radial comprehensive stress is evenly distributed. It can be used as a substrate for making epitaxial wafers or as a seed crystal for growing crystals. It can optimize genetic characteristics and reduce the stress introduced by genetics, thereby improving the quality of epitaxial wafers or crystals and obtaining high-quality and low-stress epitaxial wafers or crystals. 2. According to the stress values ​​of the wafer in the center area and the annular area, it can be seen that there are compressive stress and tensile stress in the center area, and the annular area is mainly tensile stress. The closer the radial comprehensive stress in the center area is to the radial comprehensive stress in the annular area, the more uniform the radial comprehensive stress distribution of the wafer is. 3. The axial comprehensive stress of the wafer of the present application is less than the radial comprehensive stress, which proves that the axial variability of the wafer is small. According to the above analysis of the comprehensive stresses in the radial and axial directions of the wafer, it can be known that the microscopic crystal plane spacing of the wafer changes, which plays a certain feedback role, so as to adjust the parameters of each process of crystal growth, thereby preparing high-quality wafers. 4. The present application utilizes a TaC coating with through-type through holes formed on the surface of the crucible, which can ensure the transmission of the raw material atmosphere during crystal growth while improving the uniformity of the temperature field, thereby reducing the internal stress in the silicon carbide wafer and avoiding the edge stress of the crystal caused by thermal expansion and compression of the graphite substrate in the thermal field, thereby reducing the stress in the annular area of ​​the wafer. 5. According to the method for preparing silicon carbide single crystals of the present application, the temperature gradient during growth of the silicon carbide single crystal and the uniformity of the temperature in the crucible can be controlled, thereby reducing the residual thermal stress inside the crystal. Moreover, through the quantitative testing method of the present application, the detected comprehensive stress also includes the stress in the wafer due to lattice distortion that has not yet been released through defects, thereby improving the accuracy of internal stress detection. BRIEF DESCRIPTION OF THE DRAWINGS In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings required for use in the embodiments or the prior art descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative labor. In the drawings: FIG1 is a flow chart showing the calculation of the peak position shift and the stress conversion coefficient involved in Example 1 of the present application. FIG. 2 is a diagram showing the axial stress distribution of a silicon carbide wafer subjected to a Raman axial test according to Example 3 of the present application. FIG3 is a schematic diagram of the Raman equidistant focusing test of the comprehensive stress of the substrate involved in Example 4 of the present application. FIG. 4 is a morphology characterization diagram of the TaC coating in crucible 1# involved in Example 5 of the present application. DETAILED DESCRIPTION The embodiments of the present application provide a silicon carbide wafer and a crystal with low lattice distortion. In order to enable those skilled in the art to better understand the technical solutions in the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments of the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of this application. The present application is described in detail below with reference to embodiments, but the present application is not limited to these embodiments. Unless otherwise specified, the raw materials in the examples of this application were purchased through commercial channels. The principle of using Raman to test the stress of the substrate in the following embodiments is as follows: the Raman spectrometer passes a monochromatic laser of a certain wavelength through a series of optical paths and then converges the laser through an objective lens to irradiate the substrate surface, and the laser photons interact with the substrate lattice to cause photon scattering. The occurrence of Raman scattering is related to the lattice vibration of the substrate itself. When there is residual stress in the sample, the tensile and compressive stresses will cause the atomic bond length to be elongated or shortened accordingly, thereby causing the atomic vibration frequency to decrease or increase, which is reflected in the Raman spectrum as the characteristic peak of the substrate moves to a low frequency or a high frequency, that is, a peak position offset occurs. Example 1 Quantitative Testing Method for Wafer Stress (1) Calculation of peak position shift and stress conversion coefficient Referring to Figure 1, first use a single crystal XRD diffractometer to test the silicon carbide wafer and analyze the wafer according to the reciprocal lattice space, calculate the parameters of the standard 4H-silicon carbide wafer and compare them with the standard parameters. Then, according to the Bragg diffraction equation: 2dsinθ=nλ, where d is the crystal plane spacing, θ is the diffraction half angle, n is the diffraction order, and λ is the wavelength, test the θ and d of different wafers, and it can be seen that the tensile and compressive stress inside the crystal causes the crystal plane spacing d to undergo corresponding extension and contraction changes. According to different crystal plane spacings d0 and dx, dx is divided into d1 and d2, where d0 is the theoretical crystal plane spacing, d1 is the crystal plane spacing after tensile stress, and d1 is greater than d0, and d2 is the crystal plane spacing after compressive stress, and d2 is less than d0. The crystal plane spacing difference △d at different positions is calculated, △d=d1-d0 or △d=d0-d2. The actual peak position of the wafer is obtained according to the Raman test, and the peak position offset △v at different test points is calculated compared with the standard peak position; the stress value σ of the silicon carbide wafer at different test points is calculated in combination with Hooke's law or stress-strain formula, and the ratio of the peak position offset to the stress value at different test points is the peak position offset and stress conversion coefficient μ, which ranges from -125 to -2500. The calculation formula of Hooke's law is σ / S=E×(△d / d0), where S is the area affected by σ, which is a fixed value. When Hooke's law is applicable to microscopic calculations, S is the microscopic area, which can be calculated as unit 1. E is the Young's modulus of the wafer, which is a fixed parameter of the wafer. △d is the difference in crystal plane spacing at different positions, d0 is the theoretical crystal plane spacing, and σ is the stress value that needs to be calculated. The calculation formula for stress and strain is σ=E×△d, where E is the Young's modulus of the wafer, which is a fixed parameter of the wafer, △d is the difference in crystal plane spacing at different positions, and σ is the stress value that needs to be calculated. (2) Quantitative test method for wafer stress First, set the Raman test points. You can perform single-point testing or Mapping scanning of the entire wafer. Therefore, single-point testing is a sporadic coordinate point setting, and Mapping scanning is 10x10~50x50 and more points. You can choose the appropriate test method according to the properties of the wafer to determine the Raman test coordinate diagram of the silicon carbide wafer. The test results are then output, including but not limited to editable peak position, peak intensity data and Mapping. The output data is then subjected to peak position fitting, where fitting functions include but are not limited to Gaussian, Lorentz, GaussLor, AGauss, Aloren and AGaussLor, to obtain precise peak position values ​​and peak position offsets, with the peak position accurate to more than one decimal place. Finally, according to the peak shift and stress conversion coefficient μ calculated in (1) and the peak shift △v obtained in the Raman test, the stress value of silicon carbide is calculated as follows: σ(MPa)=μ×△v(cm -1 ), and finally obtain the stress test image of the wafer. Example 2 Wafer Surface Curvature Test Since SiC is subjected to a lot of external mechanical stress during the process of preparing wafers from crystals through a series of processes, it is difficult to ensure that the surface is completely level, that is, there is a certain degree of curvature. In order to eliminate the influence of substrate surface curvature on substrate surface stress and internal stress test, it is necessary to first test the curvature of the substrate. According to the curvature, the substrate comprehensive stress selects the equally spaced focusing test. After the curvature test, the tester needs to be calibrated using single crystal silicon. First, a Z-axis mapping test is performed on the single crystal Si to confirm that it is a Gaussian distribution. The surface of the single crystal Si wafer is taken as the zero point, and an axial mapping test is performed from -100μm inside the single crystal Si wafer to +20μm above the single crystal Si wafer to analyze the change in Raman signal intensity. The single crystal Si wafer is a non-transparent material, so its peak intensity presents a Gaussian distribution, with the surface zero point position as the symmetry axis; then a surface focusing single point test is performed on the single crystal Si, and the single crystal Si Raman peak position is made to 520.70cm through the correction instrument. -1 , at this time, it means that the instrument optical path has been calibrated. The 4H-SiC wafer was tested in the Z direction using a calibrated tester. The Raman laser was emitted from -100μm inside the 4H-SiC wafer to +20μm above the 4H-SiC wafer. The 4H-SiC wafer and other silicon carbides are transparent materials, so the Raman laser can penetrate into the silicon carbide wafer, and the feedback signal gradually weakens as the Raman laser penetration depth increases. Other silicon carbides include semi-insulating, conductive, and 3C, 4H, 15R, 6H and other silicon carbide wafers. Therefore, the Raman peak intensity of the silicon carbide wafer gradually decreases as the Raman laser penetrates deeper into the silicon carbide wafer. The Raman device’s autofocus function can automatically find the strongest peak of the test signal on the wafer surface, so that the curvature of the wafer surface can be measured with the help of this function. The specific method is as follows: S1: First, ensure that the test platform is level, select a fixed origin (0,0) on the test platform, and mark the point as the three-dimensional coordinate (0,0,0); S2: Raise the objective lens to a height that does not touch the wafer according to the wafer thickness, and automatically focus on any point on the wafer surface where the test signal is the strongest. Mark this position as (a, b, c), then adjust the Raman laser downward by a distance of H and focus on the position to (a, b, cH); S3: Adjust the Raman laser test position to (0,0,cH) for an equal focal plane test, that is, the center points of the laser spots are located in the same horizontal plane, and a two-dimensional peak intensity scan of the wafer surface is obtained. According to the peak intensity distribution of the silicon carbide wafer, the distance between the focal plane of the Raman laser and the surface of the silicon carbide wafer can be obtained, so as to obtain the in-plane curvature of the wafer and obtain the in-plane curvature distribution map of the wafer. Example 3 Axial test distinguishes wafer surface stress from internal stress Since the wafer is affected by the temperature field and the introduction of packaging during the crystal growth process, thermal stress and residual stress exist inside the crystal, and the crystal is obtained after a series of cutting, grinding and polishing. The processing process of the crystal to form the wafer will cause surface lattice distortion, thereby generating surface stress. In order to further distinguish the surface stress from the internal stress of the wafer, according to the light transmittance characteristics of silicon carbide, the wafer is subjected to axial testing, namely, Z-direction Mapping, with the wafer surface as the zero point. The test range of the axial test is from -150μm to -30μm inside the wafer to above the wafer surface. During the test, the laser spot gradually focuses upward from the wafer body to the damaged stress extension layer, further to the surface damaged layer, and then continues to focus upward into the air to determine the thickness of the wafer surface damaged layer and the damaged stress extension layer. With the wafer surface as the zero point, the axial test range is that the Raman laser spot gradually moves upward from -100μm inside the wafer to 30μm above the wafer surface. Five points of the wafer are tested from top to bottom, left to right, and the five points on the wafer show the same trend, with only differences in the maximum negative stress at the surface damage. Referring to Figure 2, the Raman laser moves from -100μm inside the wafer upward to about -30μm. At this time, the stress extension line fluctuates up and down, indicating that the internal stress is uniform. When the laser spot is focused on the damaged stress extension layer, the stress curve begins to show a downward trend at -30μm, and the downward trend of stress gradually increases. When it approaches the zero point on the wafer surface, it reaches the maximum negative stress value, which is manifested as the stress value of the surface damaged layer. Finally, the laser spot continues to move upward and gradually leaves the wafer surface into the air, and the stress shows a rapid rise to chaotic fluctuations. Therefore, the thickness of the surface damage layer and the damage stress extension layer of the wafer can be determined according to the axial test results of the wafer. In Figure 2, the stress value inside the crystal is roughly the same, which is a stable value. The surface stress area of ​​the crystal can see the stress fluctuation with an obvious downward trend. Therefore, the radial comprehensive stress of the wafer is the area extending vertically from the surface to the inside of the wafer to 1%-33% of the wafer thickness, which can cover the surface stress and internal stress in the wafer. According to the different processing steps of the wafer, the axial test of this embodiment can be used to determine the penetration depth of the Raman laser during the comprehensive stress test to ensure that the measured area is the comprehensive stress, thereby providing a theoretical basis for the subsequent quantitative test of the comprehensive stress of the wafer. Example 4 Quantitative Testing of Wafer Comprehensive Stress According to the axial test of Example 3, the thickness of the surface damage layer and the damage stress extension layer of the wafer are determined. Since the thickness of the wafer surface damage layer may be less than the curvature of the wafer surface, the equal-focusing plane test method may cause the laser spot to fall entirely into the middle layer of the wafer or entirely into the surface damage layer, resulting in errors in the test results of the wafer's comprehensive stress. Therefore, the equal-space focusing test method is mainly used in the quantitative test of the wafer's comprehensive stress, and the laser's focusing plane changes with the change of the substrate plane. The test principle is shown in Figure 3(a) and Figure 3(b). The axial diameter of the Raman laser spot covers the middle layer, damage stress extension layer and surface damage layer of the wafer. Schematic diagram of the damage layer on the wafer surface. Under this test method, the focusing depth (d) of the Raman laser at different test points remains unchanged. First, the penetration depth (Dp) and the spot diameter (D) of the Raman laser are calculated according to the following formula, and a suitable focusing depth (d) is selected. The requirements that need to be met are that the penetration depth (Dp) is greater than the focusing depth (d), and the axial diameter of the Raman laser spot covers the surface damage layers, damage stress extension layers and intermediate layers of the wafer: In the above formula, Dp is the penetration depth of Raman excitation in the sample, α is the absorption coefficient, λ is the laser wavelength, and k is the extinction coefficient. The specific value of the penetration depth (Dp) is calculated according to the above formula, and a suitable focusing depth (d) is selected. The requirement that needs to be met is that the penetration depth (Dp) is greater than the focusing depth (d), and since the test is for internal stress, the focusing depth d needs to be greater than the thickness of the surface damage layer and the damage stress extension layer tested in Example 3. Where λ is the laser wavelength and Na is the numerical aperture of the device. The spot diameter (D) is the short axis diameter of the laser spot. The larger the value, the stronger the peak intensity of Raman at each test position, and the more impurity peaks there are, which affects the detection accuracy of Raman. When λ is determined, if the value of Na is large, the peak intensity is very weak, which will also affect the Raman detection accuracy. Therefore, it is necessary to select appropriate λ and Na to improve the accuracy of the test method. According to the above-calculated and selected penetration depth (d) and spot diameter (D) of the Raman laser, by debugging the parameters of the Raman tester, the laser is focused on the wafer surface using the automatic focusing function, so that the wafer surface damage layer, the damage stress extension layer and the wafer middle layer all fall within the laser spot range, thereby realizing equal-spaced focusing test at different positions of the wafer. This method is not affected by the bending and warping of the wafer surface, so that the obtained Raman peak intensity is always maintained at the axial maximum value of the test point. According to the stress quantitative test method of Example 1, a comprehensive test map of the wafer is obtained. And compared with the wafer internal stress map obtained by the same equal-spaced focusing test, the laser spot in the internal stress test is located in the middle layer of the wafer. According to the test results, it can be proved that the test method of this embodiment can realize the quantitative test of the comprehensive stress of the wafer surface damage stress and the internal residual stress. The comprehensive stress is divided into comprehensive absolute stress and comprehensive relative stress, and 4H-SiC is used as an example: The comprehensive absolute stress is used to determine the simplified wave vector peak position. The measured 4H-SiC peak position is subtracted from the standard peak position, such as FTO (2 / 4). The calculation formula for the comprehensive absolute stress is: σabsolute=μ×(v 实际 -V FTO(2 / 4) ), σ is in MPa, v 实际 and V FTO(2 / 4) The unit is cm-1 , where v 实际 is the actual FTO(2 / 4) peak position at the substrate test point, V FTO(2 / 4) is the standard peak position of FTO (2 / 4) of the substrate; The comprehensive relative stress is calculated by subtracting the measured values ​​of the same simplified wave vector peak position at any two points in the SiC substrate surface, such as the FTO (2 / 4) peak position. The calculation formula for the comprehensive relative stress is: σrelative=μ×(v (x1,y1) -V (x2,y2) ), σ is in MPa, v (x1,y1) and V (x2,y2) The unit is cm -1 , where v (x1,y1) is the actual FTO(2 / 4) peak position at the substrate test point, V (x2,y2) is the actual FTO (2 / 4) peak position of the substrate relative point. The relative stress value of the test point is calculated according to the above calculation formula. If the relative value of σ is positive, it means that the stress of the test point relative to the relative point is tensile stress. If the relative value of σ is negative, it means that the stress of the test point relative to the relative point is compressive stress. Example 5 This embodiment relates to a method for preparing a TaC coating having a through-type through hole, comprising the following steps: (1) preparing a slurry: 25-40 parts of TaC powder, 5-8 parts of Ta2O5, 20-35 parts of a solvent, 15-25 parts of a cosolvent, 1-3 parts of an air entraining agent, 2-5 parts of a thickener, 5-15 parts of a straight-chain saturated aliphatic hydrocarbon and 1-3 parts of a carbon powder are mixed and stirred at 700-800 r / min for 2-3 hours to obtain a slurry containing TaC; (2) Spraying the slurry onto a surface of a graphite substrate, heating to 60-80° C., maintaining for 2-4 hours to burst bubbles, and then drying at 180-220° C. for 8-12 hours; sintering at 700-900 mbar and 500-700° C. for 3-5 hours; then increasing the pressure to 1000-1100 mbar, increasing the temperature to 1600-1800° C., and sintering for 8-10 hours; then adjusting the pressure to 145-155 kPa, increasing the temperature to 2200-2400° C., sintering for 14-16 hours, and finally cooling to room temperature and normal pressure within 15-25 hours to obtain a TaC coating with through-holes. Crucibles 1#-8# and comparative crucibles D1#-D3# were prepared according to the above preparation method, as follows: Crucible 1# (1) preparing a slurry: 32.7 parts of TaC powder, 6 parts of Ta2O5, 25 parts of ethanol, 20 parts of tetrahydrofuran, 1.5 parts of a saponin-type air entraining agent, 3.5 parts of cellulose ether, 10 parts of a straight-chain saturated aliphatic hydrocarbon and 1.3 parts of carbon powder were mixed, and stirred at 700 r / min for 2.5 h to obtain a slurry containing TaC; (2) The slurry of step (1) is electrostatically sprayed onto the surface of the graphite substrate, the temperature is raised to 70°C, maintained for 3 hours to burst the bubbles, dried at 200°C for 10 hours, and then sintered: sintered at 800 mbar and 600°C for 4 hours; then the pressure is raised to 1000 mbar, the temperature is raised to 1700°C, and sintered for 9 hours; then the pressure is adjusted to 150 kPa, the temperature is raised to 2300°C, and sintered for 15 hours, and finally cooled to room temperature and normal pressure within 20 hours to obtain crucible 1#. Crucible 2# (1) preparing slurry: 25 parts of TaC powder, 5 parts of Ta2O5, 20 parts of ethanol, 15 parts of tetrahydrofuran, 1 part of saponin-type air entraining agent, 2 parts of cellulose ether, 5 parts of straight-chain saturated aliphatic hydrocarbon and 1 part of carbon powder were mixed, and stirred at 800 r / min for 2 h to obtain a slurry containing TaC; (2) The slurry of step (1) is electrostatically sprayed onto the surface of the graphite substrate, the temperature is raised to 60°C, maintained for 4 hours to burst the bubbles, dried at 180°C for 12 hours, and then sintered: sintered at 700 mbar and 500°C for 5 hours; then the pressure is increased to 1000 mbar, the temperature is increased to 1600°C, and sintered for 10 hours; then the pressure is adjusted to 145 kPa, the temperature is increased to 2200°C, and sintered for 16 hours, and finally cooled to room temperature and normal pressure within 15 hours to obtain crucible 2#. Crucible 3# (1) preparing a slurry: 40 parts of TaC powder, 8 parts of Ta2O5, 35 parts of ethanol, 25 parts of tetrahydrofuran, 3 parts of saponin-type air entraining agent, 5 parts of cellulose ether, 15 parts of straight-chain saturated aliphatic hydrocarbon and 3 parts of carbon powder were mixed, and stirred at 700 r / min for 3 h to obtain a slurry containing TaC; (2) The slurry of step (1) was electrostatically sprayed onto the surface of the graphite substrate, the temperature was raised to 80°C, maintained for 2 hours to burst the bubbles, dried at 220°C for 8 hours, and then sintered: sintered at 900 mbar and 700°C for 3 hours; then the pressure was raised to 1100 mbar, the temperature was raised to 1800°C, and sintered for 8 hours; then the pressure was adjusted to 155 kPa, the temperature was raised to 2400°C, and sintered for 14 hours, and finally cooled to room temperature and normal pressure within 25 hours to obtain crucible 3#. Crucible 4# The difference between this embodiment and crucible 1# is that in step (1), the raw materials are mixed and stirred at 700 r / min for 5 min, and the other conditions are the same as those of crucible 1#, to obtain TaC coating 4#. Crucible 5# The difference between this embodiment and crucible 1# is that in step (2), the slurry of step (1) is electrostatically sprayed onto the surface of the graphite substrate, the temperature is raised to 200°C, maintained for 13 hours to burst the bubbles and dried, and then sintered. The other conditions are the same as those of crucible 1#, and crucible 5# is obtained. Crucible 6# The difference between this embodiment and crucible 1# is that in step (2), the sintering is as follows: sintering at 400 mbar and 400°C for 4 hours; then the pressure is increased to 1000 mbar, the temperature is increased to 1700°C, and sintering is performed for 9 hours; then the pressure is adjusted to 150 kPa, the temperature is increased to 2300°C, and sintering is performed for 15 hours, and finally the temperature is lowered to room temperature and normal pressure within 20 hours. The remaining conditions are the same as those of crucible 1#, so that crucible 6# is obtained. Crucible 7# The difference between this embodiment and crucible 1# is that in step (2), the sintering is as follows: sintering at 800 mbar and 600°C for 4 hours; then the pressure is increased to 1000 mbar, the temperature is increased to 1200°C, and sintering is performed for 9 hours; then the pressure is adjusted to 150 kPa, the temperature is increased to 2300°C, and sintering is performed for 15 hours, and finally the temperature is lowered to room temperature and normal pressure within 20 hours. The remaining conditions are the same as those of crucible 1#, so that crucible 7# is obtained. Crucible 8# The difference between this embodiment and crucible 1# is that in step (2), the sintering is as follows: sintering at 800 mbar and 600°C for 4 hours; then the pressure is increased to 1000 mbar, the temperature is increased to 1700°C, and sintering is performed for 9 hours; then the pressure is adjusted to 120 kPa, the temperature is increased to 2500°C, and sintering is performed for 15 hours, and finally the temperature is lowered to room temperature and normal pressure within 20 hours. The remaining conditions are the same as those of crucible 1#, so that crucible 8# is obtained. Comparison crucible D1# Compared with crucible 1#, this comparative example adopts CVD method to prepare TaC coating, specifically: The graphite substrate was placed in a chemical vapor deposition furnace and evacuated to below 50 Pa. The temperature was then raised to 1200°C, and a mixed gas consisting of ethane, TaCl5, H2 and carrier gas argon was introduced. The mixed gas maintained a stable flow rate into the deposition furnace, and the furnace pressure was maintained at 5000 Pa. The molar ratio of TaCl5 and ethane gas was first controlled at 1.2:1 to form a transition layer with a thickness of 50 μm; then the molar ratio of TaCl5 and ethane gas was controlled to 3:1 to form a TaC coating with a thickness of 60 μm, and a comparative crucible D1# was obtained. Compare Crucible D2# Compared with crucible 1#, the raw materials in the slurry of step (1) are different: BYK defoamer is used to replace the saponin air-entraining agent, and the other conditions are the same as those of crucible 1#, that is, comparative crucible D2# is prepared. Compare Crucible D3# Compared with crucible 1#, the raw materials in the slurry of step (1) are different: TaCl5 is used instead of Ta2O5, and the other conditions are the same as those of crucible 1#, that is, comparative crucible D3# is prepared. The cross-sectional SEM test and EDS energy spectrum analysis were performed on the crucibles 1#-8# and the comparative crucibles D1#-D3# prepared above. As shown in Figure 4, Figure 4 is a cross-sectional SEM and EDS mapping diagram of the coating demo. The distribution of TaC and the penetration of the holes can be clearly seen in the image, and it was determined to be a Ta-containing coating by EDS. The TaC coating was subjected to XRD testing, and it was found that the TaC grains were oriented and grown along the

[0200] and

[0220] directions. The thickness of the formed TaC coating, the average pore size of the through-type through holes in the TaC coating, the density, and the size of the TaC grains were tested. The test results are shown in Table 1; Table 1 The crucibles 1#-8# and the comparative crucibles D1#-D3# prepared above were subjected to high temperature erosion and thermochemical erosion experiments to simulate the growth environment of the third generation silicon carbide silicon carbide crystal using the PVT method. The crucibles 1#-8# and the comparative crucibles D1#-D3# were kept at 2300°C and eroded in a silicon carbide atmosphere for 100 hours. The test results are shown in Table 2: Table 2 In Table 2, erosion weight loss rate = [(weight before experiment - weight after experiment) / weight before experiment] × 100%. The above high temperature erosion and thermochemical erosion experiments prove that the TaC coating of this embodiment can improve the protection performance of the graphite substrate, extend the tolerance and corrosion resistance of the TaC coating, and thus extend the service life of the crucible. Example 6 This embodiment relates to a method for preparing a silicon carbide single crystal with a diameter of 150 mm, comprising the following steps: (1) Adding silicon carbide powder into a crucible; (2) The furnace body is vacuumed to below 10-6 mbar, and then high-purity inert gas is introduced to 300-500 mbar. This process is repeated 2-3 times, and finally the furnace body is vacuumed to below 10-6 mbar; (3) introducing high-purity inert gas into the furnace body, raising the pressure to 10-100 mbar within 1-3 hours, and continuously introducing high-purity inert gas and maintaining the pressure constant; (4) Crystal growth stage: While maintaining the pressure unchanged, the temperature inside the furnace is raised to the single crystal growth temperature of 2200K-2800K within 3-5 hours, and the growth time is 30-150 hours; (5) After the crystal growth is completed, open the furnace body and take out the graphite crucible to obtain the silicon carbide single crystal. Add equal amounts of silicon carbide powder to crucibles 1#-3# and comparison crucibles D1#-D3# prepared in Example 6, respectively; evacuate the furnace body to below 10-6 mbar, then introduce high-purity inert gas to 300 mbar, repeat this process 3 times, and finally evacuate the furnace body to below 10-6 mbar; introduce high-purity inert gas into the furnace body, increase the pressure to 30 mbar within 1 hour, continue to introduce high-purity inert gas and keep the pressure constant; crystal growth stage: while keeping the pressure constant, increase the temperature in the furnace body to 2300K within 3 hours, the growth time is 5 hours, and then increase the temperature in the furnace body to 2500K within 5 hours, and the growth time is 90 hours; after the single crystal growth is completed, open the furnace body, take out the graphite crucible, and obtain silicon carbide crystals 1#-3# and comparison silicon carbide crystals D1#-D3#, respectively. The test methods of Examples 1-4 are used to perform radial and axial stress tests on silicon carbide single crystals. This stress test is the internal stress of the crystal, and the equidistant focusing mode test of Example 4 can be used. Under the internal stress test, the penetration depth d of the Raman laser passes through the surface damage layer and the stress extension layer, and is located in the middle layer. Since the thickness of the silicon carbide single crystal is relatively thick, the silicon carbide single crystal can be sliced ​​to avoid the surface stress introduced during the slicing process from affecting the radial stress or axial stress of the crystal. Therefore, an internal stress test is performed on each silicon carbide wafer to obtain the difference in axial stress of the silicon carbide single crystal and the difference in radial stress of the silicon carbide single crystal at different axial positions. The test results are shown in Tables 3 and 4 below: Table 3 Table 4 Example 7 This embodiment relates to the preparation of a silicon carbide wafer, comprising the following steps: (1) cutting the silicon carbide single crystal and slicing it at a cutting speed of 0.003 mm / s to obtain a cut wafer; (2) The cut wafers were passed through a main disk with a rotation speed of 70 r / min, using W10 diamond powder and a load of 0.3 kg / cm 2 Grinding to obtain a ground wafer; (3) The ground wafer is passed through a main disk with a rotation speed of 50 r / min, using W0.5 powder size diamond powder and a load of 0.5 kg / cm 2 Mechanical polishing and main disk speed 50r / min, ceramic disk speed 35r / min, chemical mechanical polishing liquid as polishing material, polishing pressure 0.15kg / cm 2 After chemical polishing, a silicon carbide substrate was obtained. The silicon carbide single crystals 1#-3# prepared in Example 8 were cut, ground, mechanically polished and chemically mechanically polished according to the above steps to obtain silicon carbide wafers 1#-3#. The above silicon carbide wafers 1#-3# were tested using the methods of Examples 1-3 and Example 4. The results are shown in Tables 5 and 6. Table 5 Table 6 The stress values ​​in Tables 3-6 all refer to relative stress values. In the present application, the positive and negative values ​​in the stress values ​​represent whether the substrate is subjected to tensile stress or compressive stress at the test point relative to the above-mentioned reference value. In the prior art, when evaluating and describing the final stress state of a substrate, the maximum value minus the minimum value in the above-mentioned stress values ​​is often used to obtain the difference. For example, the axial stress in the 1# annular region of the silicon carbide wafer is -8.6-9.0. When the axial stress in the 1# annular region of the silicon carbide wafer is generally expressed in this field, it can also be described as a stress value of 17.6MPa. The data in the above Tables 3-6 are only for the SiC wafers and SiC crystals prepared by the crucibles 1#-3# prepared in Example 5 and the comparative crucibles D1#-D3#. When the same crystal growth and processing methods as in Examples 6 and 7 are used and crucibles 4#-8# are used to prepare SiC crystals and SiC wafers, and the parameters of the crystals and wafers in Tables 3-6 are characterized by absolute stress, the crystals can meet the requirements that the width of the peripheral region extending inward from the edge of the crystal is 5 to 30 mm; the radial stress of the peripheral region is 5.2-2 0MPa, the radial stress in the middle area is -15-5MPa; the axial stress in the peripheral area is -10-10MPa, and the axial stress in the middle area is -5-5MPa; -8MPa≤S4-S3≤10MPa; △S5<△S6; 0MPa≤△S5≤8MPa, 0MPa≤△S6≤10MPa; -5MPa≤S6-S5≤5MPa; △S7<△S8; 0MPa≤△S7≤7MPa, 0MPa≤△S8≤10MPa. The wafer can meet the requirements of radial comprehensive stress of -30~30MPa; the width of the annular area extending inward from the edge of the wafer is 5~30mm; the radial comprehensive stress in the central area is -15-5MPa, and the radial comprehensive stress in the annular area is 5.2-20MPa; 1.159≤S2 / S1≤4.984; △S1<△S2; 0MPa≤△S1≤10MPa, 0MPa≤△S2≤12MPa; the axial comprehensive stress in the central area is -5-5MPa, and the axial comprehensive stress in the annular area is -10-10MPa; △S3<△S4, 0MPa≤△S3≤7MPa, 0MPa≤△S4≤10MP. Each embodiment in this application is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the device, equipment, and non-volatile computer storage medium embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment. Finally, it should be understood that the above embodiments of the present application are only used to illustrate the technical solutions of the present invention, rather than to limit them. Although the present invention has been described in detail with reference to the above embodiments, a person skilled in the art should understand that the technical solutions described in the above embodiments can still be modified, or some of the technical features can be replaced by equivalents; and these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A silicon carbide wafer with low lattice distortion, wherein: The silicon carbide wafer has a diameter of 150 mm or more, and comprises a first main surface and a second main surface; At any horizontal plane parallel to the first main surface and / or the second main surface, the radial comprehensive stress of the wafer is -30 to 30 MPa, and the radial comprehensive stress is the stress value detected in the area extending vertically from the first main surface or the second main surface into the wafer to 1% to 33% of the wafer thickness.

2. The silicon carbide wafer according to claim 1, wherein: The wafer has a central area and an annular area surrounding the central area. The width of the annular area extending inward from the edge of the wafer is 5 to 30 mm. The radial comprehensive stress of the annular area is greater than the radial comprehensive stress of the central area.

3. The silicon carbide wafer according to claim 2, wherein: At any horizontal plane parallel to the first main surface and / or the second main surface, the radial comprehensive stress in the central area is -15-5 MPa, and the radial comprehensive stress in the annular area is 5.2-20 MPa.

4. The silicon carbide wafer according to claim 2, wherein: At any horizontal plane parallel to the first main surface and / or the second main surface, S1 represents the average absolute value of the radial comprehensive stress in the central area, S2 represents the average absolute value of the radial comprehensive stress in the annular area, and 1.159≤S2 / S1≤4.

984.

5. The silicon carbide wafer according to claim 2, wherein: At any horizontal plane parallel to the first main surface and / or the second main surface, S max1 S is the maximum value of the radial comprehensive stress in the central area. min1 It is recorded as the minimum value of the radial comprehensive stress in the central area, △S1=S max1 -S min1 , S max2 S is the maximum value of the radial comprehensive stress in the annular area. min2 It is recorded as the minimum value of the radial comprehensive stress in the annular area, △S2=S max2 -S min2 , △S1<△S2.

6. The silicon carbide wafer according to claim 5, wherein: 0MPa≤△S1≤10MPa, 0MPa≤△S2≤12MPa.

7. The silicon carbide wafer according to claim 2, wherein: An axial test is performed by extending vertically into the wafer from any point on the first main surface. The axial comprehensive stress in the central area is -5-5MPa, and the axial comprehensive stress in the annular area is -10-10MPa. The axial comprehensive stress is the stress value detected in the area extending vertically from the first main surface or the second main surface into the wafer to 1%-33% of the wafer thickness.

8. The silicon carbide wafer according to claim 2, wherein: An axial test is performed by extending vertically into the wafer from any point on the first main surface, S max3 It is recorded as the maximum axial comprehensive stress in the central area, S min3 It is recorded as the minimum value of the axial comprehensive stress in the central area, △S3=S max3 -S min3 , S max4 It is recorded as the maximum value of the axial comprehensive stress in the annular area, S min4 It is recorded as the minimum value of the axial comprehensive stress in the annular area, △S4=S max4 -S min4 , △S3<△S4.

9. The silicon carbide wafer according to claim 8, wherein: 0MPa≤△S3≤7MPa, 0MPa≤△S4≤10MPa.

10. The silicon carbide wafer according to any one of claims 1 to 9, wherein: The comprehensive stress is a value measured by the following steps: (1) Calculate the peak position shift and stress conversion coefficient; (2) Raman is used to test the wafer, and the Raman spot is located in the surface layer and the middle layer of the wafer at the same time, wherein the surface layer is a region extending inward from the surface of the wafer to no more than 30% of the wafer thickness, and a peak value and a peak offset are obtained. The comprehensive stress of the wafer is calculated based on the peak offset and the peak offset and stress conversion coefficient in step (1), and the radial comprehensive stress of the wafer is calculated to be -30 to 30 MPa.

11. The silicon carbide wafer according to claim 10, wherein: Before step (2), the method also includes the step of using Raman to perform axial testing on the wafer to determine the depth of the wafer surface layer, wherein the surface layer includes a surface damage layer and a damage stress extension layer, and the Raman spot is simultaneously located in the surface damage layer, the damage stress extension layer and the intermediate layer.

12. A silicon carbide crystal with low lattice distortion, wherein: The thickness of the silicon carbide crystal is not less than 1 mm, and the diameter of the silicon carbide crystal is not less than 150 mm; The silicon carbide crystal includes an upper surface and a lower surface, and has a peripheral region and a middle region that penetrate the upper surface and the lower surface. The width of the peripheral region extending inward from the edge of the crystal is 5 to 30 mm. At any horizontal plane from the upper surface to the lower surface, the stress in the peripheral region is greater than the stress in the middle region.

13. The silicon carbide crystal according to claim 12, wherein: At any horizontal plane from the upper surface to the lower surface, the radial stress in the peripheral area is 5.2-20 MPa, and the radial stress in the middle area is -15-5 MPa; and / or An axial test was performed extending downward from any point on the upper surface of the crystal. The axial stress in the peripheral area was -10-10 MPa, and the axial stress in the middle area was -5-5 MPa.

14. The silicon carbide crystal according to claim 12, wherein: At any plane parallel to the upper surface and / or lower surface, S3 is recorded as the maximum absolute value of radial stress in the middle area, S4 is recorded as the maximum absolute value of radial stress in the peripheral area, and -8MPa≤S4-S3≤10MPa.

15. The silicon carbide crystal according to claim 14, wherein At any plane parallel to the upper surface and / or lower surface, S max5 It is recorded as the maximum radial stress in the middle area, S min5 represents the minimum radial stress in the middle region, △S5=S max5 -S min5 , S max6 It is recorded as the maximum radial stress in the peripheral area, S min6 It is recorded as the minimum radial stress in the peripheral area, △S6 = S max6 -S min6 , △S5<△S6.

16. The silicon carbide crystal according to claim 15, wherein 0MPa≤△S5≤8MPa, 0MPa≤△S6≤10MPa.

17. The silicon carbide crystal according to claim 13, wherein: An axial test is performed by extending vertically into the crystal from any point on the upper surface, where S5 represents the maximum absolute value of the axial stress in the middle region, and S6 represents the maximum absolute value of the axial stress in the peripheral region, and -5MPa≤S6-S5≤5MPa.

18. The silicon carbide crystal according to claim 17, wherein: The axial test is carried out vertically from any point on the upper surface into the crystal, S max7 It is recorded as the maximum axial stress in the middle area, S min7 It is recorded as the minimum axial stress in the middle area, △S7=S max7 -S min7 , S max8 It is recorded as the maximum axial stress in the peripheral area, S min8 It is recorded as the minimum axial stress in the peripheral area, △S8=S max8 -S min8 , △S7<△S8.

19. The silicon carbide crystal according to claim 18, wherein 0MPa≤△S7≤7MPa, 0MPa≤△S8≤10MPa.

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