Optical detection device and electronic apparatus

Abstract

The present invention provides improvement with a transfer capability of a signal charge. A light detection device is provided with: a semiconductor layer that has a first surface part and a second surface part positioned on the opposite side from each other; a photoelectric conversion part that is provided in the semiconductor layer and subjects light incident from the second surface part side of the semiconductor layer to photoelectric conversion; a charge holding part that is provided in the semiconductor layer and holds a signal charge obtained through photoelectric conversion in the photoelectric conversion part; and a transfer transistor that has a gate electrode and transfers the signal charge obtained through photoelectric conversion in the photoelectric conversion part to the charge holding part. The gate electrode includes a first electrode portion extending from the first surface part side to the second surface part side of the semiconductor layer, and a second electrode portion provided on the first electrode portion away from the first surface part of the semiconductor layer, and having an outer shape in planar view which is expanded beyond the first electrode portion.

Description

Photodetector and electronic equipment

[0001] The present technology (technology according to the present disclosure) relates to a photodetector and an electronic device, and in particular to a technology that is effective when applied to a photodetector having a transfer transistor and an electronic device including the same.

[0002] Photodetection devices such as distance measuring devices and solid-state imaging devices include a transfer transistor that transfers signal charges photoelectrically converted in a photoelectric conversion unit to a charge storage unit. Patent Document 1 discloses a transfer transistor with a vertical structure in which a gate electrode extends in the thickness direction of a semiconductor layer.

[0003] Japanese Patent Application Laid-Open No. 2005-223084

[0004] In recent years, the market demand for high-resolution image sensors has led to the development of image sensors with reduced pixel sizes. However, to reduce pixel size, it is necessary to miniaturize the transfer transistor, which narrows the gate electrode extending in the thickness direction of the semiconductor layer. As the gate electrode narrows, the surface area of ​​the gate electrode adjacent to (facing) the semiconductor layer via the gate insulating film decreases, reducing the potential modulation capability and the signal charge transfer capability of the transfer transistor, which transfers signal charges photoelectrically converted in the photoelectric conversion unit to the charge storage unit.

[0005] Vertical transfer transistors are considered to be more advantageous for transferring signal charges than horizontal transfer transistors, but a decrease in signal charge transfer capacity affects the image quality characteristics of the image sensor, so there was room for improvement.

[0006] The purpose of this technology is to improve the transfer capability of signal charges.

[0007] (1) A photodetector according to an aspect of the present technology includes: a semiconductor layer having a first surface portion and a second surface portion located opposite to each other; a photoelectric conversion portion provided in the semiconductor layer and performing photoelectric conversion on light incident from the second surface portion side of the semiconductor layer; a charge holding portion provided in the semiconductor layer and holding signal charges photoelectrically converted by the photoelectric conversion portion; and a transfer transistor having a gate electrode and transferring the signal charges photoelectrically converted by the photoelectric conversion portion to the charge holding portion. The gate electrode includes a first electrode portion extending from the first surface portion side of the semiconductor layer toward the second surface portion side, and a second electrode portion provided on the first electrode portion at a distance from the first surface portion of the semiconductor layer and having an outer shape larger than that of the first electrode portion in a plan view.

[0008] (2) An electronic device according to another aspect of the present technology includes the above-mentioned photodetector; an optical lens that focuses image light from a subject on an imaging surface of the detection device; and a signal processing circuit that performs signal processing on a signal output from the photodetector.

[0009] 9A is a chip layout diagram schematically showing a configuration example of a solid-state imaging device according to a first embodiment of the present technology. FIG. 10A is a block diagram schematically showing a configuration example of a solid-state imaging device according to a first embodiment of the present technology. FIG. 10B is an equivalent circuit diagram showing a configuration example of a pixel and a pixel circuit according to a first embodiment of the present technology. FIG. 10C is a plan view schematically showing a configuration example of a pixel block included in the pixel array section of FIG. 1. FIG. 10D is an enlarged plan view of one pixel included in the pixel block of FIG. 4. FIG. 5 is a longitudinal sectional view schematically showing a longitudinal sectional structure taken along the a5-a5 cutting line of FIG. 5. FIG. 6 is a plan view schematically showing a planar shape of a second electrode portion of the gate electrode shown in FIG. 6. FIG. 7 is a diagram showing an example of potential in the charge transfer path of FIG. 6. FIG. 7A is a longitudinal sectional view schematically showing a longitudinal sectional structure of a photoelectric conversion region according to a conventional reference example. FIG. 7B is a diagram showing an example of potential in the charge transfer path of FIG. 9A. FIG. 9C is a longitudinal sectional view schematically showing a process of a method for manufacturing a solid-state imaging device according to a first embodiment of the present technology. FIG. 9A is a longitudinal sectional view schematically showing a process subsequent to the process of FIG. 10A. FIG. 9B is a longitudinal sectional view schematically showing a process subsequent to the process of FIG. 10C. 10B is a longitudinal cross-sectional view schematically showing a step subsequent to the step of FIG. 10D. FIG. 10C is a longitudinal cross-sectional view schematically showing a step subsequent to the step of FIG. 10E. FIG. 10D is a longitudinal cross-sectional view schematically showing a step subsequent to the step of FIG. 10F. FIG. 11C is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure of a photoelectric conversion region that is a modified example 1-1 of the first embodiment of the present technology. FIG. 11D is a plan view schematically showing a planar shape of a second electrode portion included in the gate electrode of the transfer transistor of FIG. 11A. FIG. 11A is a plan view schematically showing another planar shape of the second electrode portion included in the gate electrode of the transfer transistor of FIG. 11A. FIG. 11C is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure of a photoelectric conversion region that is a modified example 1-2 of the first embodiment of the present technology. FIG. 12A is a plan view schematically showing a planar shape of a second electrode portion included in the gate electrode of the transfer transistor of FIG. 12A. FIG. 12A is a plan view schematically showing another planar shape of the second electrode portion included in the gate electrode of the transfer transistor of FIG. 12A. FIG. 12C is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure of a photoelectric conversion region that is a modified example 1-3 of the first embodiment of the present technology. FIG. 10 is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure of a photoelectric conversion region which is a modified example 1-4 of the first embodiment of the present technology.17A . FIG. 17B is a plan view schematically showing the planar shape of a second electrode portion included in the gate electrode of the transfer transistor of FIG. 14A . FIG. 17C is a plan view schematically showing another planar shape of the second electrode portion included in the gate electrode of the transfer transistor of FIG. 14A . FIG. 17D is a longitudinal sectional view schematically showing a longitudinal sectional structure of a photoelectric conversion region which is Modification 1-5 of the first embodiment of the present technology. FIG. 17E is a longitudinal sectional view schematically showing a longitudinal sectional structure of a photoelectric conversion region which is Modification 1-6 of the first embodiment of the present technology. FIG. 17F is a longitudinal sectional view schematically showing a configuration example of a solid-state imaging device according to a second embodiment of the present technology. FIG. 17G is a plan view schematically showing the planar shape of a barrier layer included in the photoelectric conversion region of FIG. 17A . FIG. 17H is a longitudinal sectional view schematically showing a configuration example of a solid-state imaging device according to a third embodiment of the present technology. FIG. 17I is a longitudinal sectional view schematically showing a configuration example of a solid-state imaging device according to a fourth embodiment of the present technology. FIG. 17I is a longitudinal sectional view schematically showing a configuration example of a solid-state imaging device according to a fifth embodiment of the present technology. FIG. 17I is a longitudinal sectional view schematically showing a configuration example of a solid-state imaging device according to a sixth embodiment of the present technology. FIG. 17I is a plan view schematically showing a configuration example of a pixel of a solid-state imaging device according to a seventh embodiment of the present technology. 30A is a plan view schematically showing the planar shape of a second electrode portion included in the gate electrode of the transfer transistor of FIG. 22A. FIG. 31B is a longitudinal cross-sectional view schematically showing a configuration example of a solid-state imaging device according to an eighth embodiment of the present technology. FIG. 31C is a plan view schematically showing a configuration example of a pixel in a solid-state imaging device according to a ninth embodiment of the present technology. FIG. 31D is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure along the a24-a24 cutting line of FIG. 24. FIG. 31E is a perspective view schematically showing a schematic configuration of a gate electrode of a transfer transistor which is a modified example 9-1 of the ninth embodiment of the present technology. FIG. 31F is a perspective view schematically showing a gate electrode of a transfer transistor which is a modified example 9-2 of the ninth embodiment of the present technology. FIG. 31F is a plan view schematically showing a configuration example of a pixel in a solid-state imaging device according to a tenth embodiment of the present technology. FIG. 31C is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure along the a29-a29 cutting line of FIG. 29. FIG. 31D is a plan view schematically showing a schematic configuration of the gate electrode of the transfer transistor shown in FIG. 29. FIG. 31E is a plan view with the head of the gate electrode shown in FIG. 31B omitted. FIG. 31F is a diagram showing an example of potential in the charge transfer path of FIG. 30. FIG. 10 is a longitudinal sectional view schematically showing a longitudinal sectional structure of a photoelectric conversion region as a conventional reference example.33A . FIG. 33B is a diagram showing an example of potential in the charge transfer path of FIG. 33A . FIG. 33C is a plan view schematically showing a gate electrode of a transfer transistor which is a modified example 10-1 of the tenth embodiment of the present technology. FIG. 33D is a plan view schematically showing a gate electrode of a transfer transistor which is a modified example 10-2 of the tenth embodiment of the present technology. FIG. 33E is a plan view schematically showing a gate electrode of a transfer transistor which is a modified example 10-3 of the tenth embodiment of the present technology. FIG. 33F is a plan view schematically showing a gate electrode of a transfer transistor which is a modified example 10-4 of the tenth embodiment of the present technology. FIG. 33G is a plan view schematically showing a gate electrode of a transfer transistor which is a modified example 10-5 of the tenth embodiment of the present technology. FIG. 33H is a plan view schematically showing a gate electrode of a transfer transistor which is a modified example 10-6 of the tenth embodiment of the present technology. FIG. 33I is a block diagram showing an example of a configuration of an electronic device according to an eleventh embodiment of the present technology. FIG. 33I is a block diagram showing an example of a configuration of an electronic device according to a twelfth embodiment of the present technology. FIG. 33J is a block diagram showing an example of a schematic configuration of a vehicle control system according to a thirteenth embodiment of the present technology. FIG. 33J is an explanatory diagram showing an example of installation positions of an outside-vehicle information detection unit and an imaging unit. Fig. 20 is a diagram showing an example of a schematic configuration of an endoscopic surgery system according to a fourteenth embodiment of the present technology. Fig. 21 is a block diagram showing an example of a functional configuration of a camera head and a CCU. Fig. 22 is an exploded perspective view schematically showing an example of a configuration of a solid-state imaging device according to a fifteenth embodiment of the present technology. Fig. 23 is an equivalent circuit diagram showing an example of a configuration of a pixel and a pixel circuit according to the fifteenth embodiment of the present technology.

[0010] Hereinafter, embodiments of the present technology will be described in detail with reference to the drawings. Note that in the drawings referred to in the following description, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each layer, etc. may differ from the actual ones. Therefore, specific thicknesses and dimensions should be determined with reference to the following description.

[0011] Furthermore, it goes without saying that the dimensional relationships and ratios may differ between the drawings. Furthermore, the effects described in this specification are merely examples and are not intended to be limiting, and other effects may also be present.

[0012] Furthermore, the following embodiments exemplify devices and methods for embodying the technical idea of ​​the present technology, and do not limit the configuration to the following. In other words, the technical idea of ​​the present technology can be modified in various ways within the technical scope described in the claims.

[0013] Furthermore, the definitions of directions such as up and down in the following description are merely for the sake of convenience and do not limit the technical concept of the present technology. For example, if an object is rotated 90 degrees and observed, up and down are converted to left and right and read as such, and if an object is rotated 180 degrees and observed, up and down are obviously read as reversed.

[0014] In the following embodiments, among the three directions orthogonal to each other in space, a first direction and a second direction orthogonal to each other in the same plane are referred to as the X direction and the Y direction, respectively, and a third direction orthogonal to each of the first direction and the second direction is referred to as the Z direction. In the following embodiments, the thickness direction of a semiconductor layer 21 (described later) will be described as the Z direction. In the following embodiments, the Z direction will be described as "one direction" of the present technology.

[0015] In the following embodiments, the thickness of the semiconductor layer 21 refers to the distance between a first surface S1 and a second surface S2 that are located on opposite sides in the Z direction, and the thickness direction of the semiconductor layer 21 refers to the direction representing the thickness of the semiconductor layer 21. In the following embodiments, a planar view refers to the semiconductor layer 21 viewed from the Z direction (one direction). A cross-sectional view refers to the cross section along the Z direction (one direction) viewed from a direction perpendicular to the Z direction.

[0016] First Embodiment In this first embodiment, an example in which the present technology is applied to a solid-state imaging device that is a back-illuminated CMOS (Complementary Metal Oxide Semiconductor) image sensor as a photodetector will be described.

[0017] <Overall Configuration of Solid-State Imaging Device> First, the overall configuration of the solid-state imaging device 1A will be described. As shown in Fig. 1 , the solid-state imaging device 1A according to the first embodiment of the present technology is mainly composed of a semiconductor chip 2 having a rectangular two-dimensional planar shape when viewed in a plane. That is, the solid-state imaging device 1A is mounted on the semiconductor chip 2, and the semiconductor chip 2 can be considered as the solid-state imaging device 1A. As shown in Fig. 42 , this solid-state imaging device 1A (201) captures image light (incident light 206) from a subject via an optical lens 202, converts the amount of incident light 206 formed on the imaging surface into an electrical signal on a pixel-by-pixel basis, and outputs the electrical signal as a pixel signal.

[0018] As shown in FIG. 1, a semiconductor chip 2 on which a solid-state imaging device 1A is mounted includes, in a two-dimensional plane including an X direction and a Y direction which are orthogonal to each other, a rectangular pixel array section 2A provided in the center, and a peripheral section 2B provided outside the pixel array section 2A so as to surround the pixel array section 2A.

[0019] Here, the semiconductor chips 2 are formed in the manufacturing process by dicing a semiconductor wafer including a semiconductor layer 21 (described later) into chip formation regions. Therefore, the configuration of the solid-state imaging device 1A described below is generally the same in the wafer state before the semiconductor wafer is diced. Therefore, the present technology can be applied to both the semiconductor chip state and the semiconductor wafer state.

[0020] The pixel array unit 2A shown in Fig. 1 is, for example, a light receiving surface that receives light collected by an optical lens (optical system) 202 shown in Fig. 42. The pixel array unit 2A has a plurality of pixels 3 (sensor pixels) arranged in a matrix on a two-dimensional plane including the X direction and the Y direction. In other words, the pixels 3 are repeatedly arranged in each of the X direction and the Y direction that are orthogonal to each other within the two-dimensional plane.

[0021] 1, a plurality of bonding pads 14 are arranged in the peripheral portion 2B. Each of the plurality of bonding pads 14 is arranged, for example, along each of the four sides in a two-dimensional plane of the semiconductor chip 2. Each of the plurality of bonding pads 14 functions as an input / output terminal that electrically connects the semiconductor chip 2 to an external device.

[0022] <Logic Circuit> The semiconductor chip 2 includes a logic circuit 13 shown in Fig. 2. As shown in Fig. 2, the logic circuit 13 includes a vertical drive circuit 4, a column signal processing circuit 5, a horizontal drive circuit 6, an output circuit 7, and a control circuit 8. The logic circuit 13 is configured of a CMOS (Complementary MOS) circuit having, as field effect transistors, for example, n-channel conductivity type MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) and p-channel conductivity type MOSFETs.

[0023] The vertical drive circuit 4 shown in Fig. 2 is configured with, for example, a shift register. The vertical drive circuit 4 sequentially selects desired pixel drive lines 10, supplies pulses to the selected pixel drive lines 10 for driving the pixels 3, and drives each pixel 3 row by row. That is, the vertical drive circuit 4 sequentially selects and scans each pixel 3 in the pixel array section 2A row by row in the vertical direction, and supplies pixel signals from the pixels 3 based on signal charges generated by the photoelectric conversion section 25 (see Fig. 3) of each pixel 3 in accordance with the amount of received light to the column signal processing circuit 5 via the vertical signal line 11.

[0024] The column signal processing circuits 5 are arranged, for example, for each column of pixels 3, and perform signal processing such as noise removal for each pixel column on signals output from one row of pixels 3. For example, the column signal processing circuits 5 perform signal processing such as CDS (Correlated Double Sampling) and AD (Analog-Digital) conversion to remove fixed pattern noise specific to each pixel.

[0025] 2 is configured by, for example, a shift register. The horizontal drive circuit 6 sequentially outputs horizontal scanning pulses to the column signal processing circuits 5, thereby selecting each of the column signal processing circuits 5 in turn and causing each column signal processing circuit 5 to output a pixel signal that has undergone signal processing to a horizontal signal line 12.

[0026] 2 performs signal processing on pixel signals sequentially supplied from each of the column signal processing circuits 5 via the horizontal signal line 12, and outputs the processed signals. The signal processing may include, for example, buffering, black level adjustment, column variation correction, various types of digital signal processing, etc.

[0027] 2 generates clock signals and control signals that serve as references for the operations of the vertical drive circuit 4, column signal processing circuit 5, horizontal drive circuit 6, etc., based on the vertical synchronization signal, horizontal synchronization signal, and master clock signal. Then, the control circuit 8 outputs the generated clock signals and control signals to the vertical drive circuit 4, column signal processing circuit 5, horizontal drive circuit 6, etc.

[0028] <Pixel Block> The semiconductor chip 2 includes a pixel block 15 and a pixel circuit (readout circuit) 16 shown in FIG.

[0029] 3 and 4, the pixel block 15 includes a plurality of pixels 3. The pixel block 15 of the first embodiment includes, for example, a 2x2 arrangement of four pixels 3 (3a, 3b, 3c, 3d) arranged two by two adjacent to each other in each of the X and Y directions in a plan view, although this is not limited thereto. Although FIGS. 3 and 4 mainly illustrate one pixel block 15, the pixel blocks 15 are repeatedly arranged in each of the X and Y directions to form the pixel array unit 2A shown in FIG. 1.

[0030] As shown in FIG. 3 , the four pixels 3 a, 3 b, 3 c, and 3 d included in one pixel block 15 each have common components. Specifically, each of the four pixels 3 a, 3 b, 3 c, and 3 d included in one pixel block 15 includes a photoelectric conversion unit 25, a floating diffusion region FD serving as a charge storage unit for storing (accumulating) signal charges photoelectrically converted by the photoelectric conversion unit 25, and a transfer transistor TR for transferring the signal charges photoelectrically converted by the photoelectric conversion unit 25 to the floating diffusion region FD. Each of the four pixels 3 a, 3 b, 3 c, and 3 d included in one pixel block 15 also includes a photoelectric conversion region (photoelectric conversion cell) 22 of a semiconductor layer 21 shown in FIG. 6 . The photoelectric conversion unit 25, the floating diffusion region FD, and the transfer transistor TR are each provided in the photoelectric conversion region 22, as shown in FIG. 6 .

[0031] 3 is configured by, for example, a pn junction photodiode (PD) and generates a signal charge according to the amount of light received. The photoelectric conversion unit 25 also temporarily holds (accumulates) the generated signal charge.

[0032] The photoelectric conversion unit 25 has a cathode side electrically connected to the source region of the transfer transistor TR, and an anode side electrically connected to a reference potential line (for example, ground).

[0033] 3 transfers the signal charges photoelectrically converted by the photoelectric conversion unit 25 to the floating diffusion region FD. The source region of the transfer transistor TR is electrically connected to the cathode side of the photoelectric conversion unit 25, and the drain region is electrically connected to the floating diffusion region FD. The gate electrode of the transfer transistor TR is electrically connected to a transfer transistor drive line of the pixel drive lines 10 shown in FIG.

[0034] (Floating Diffusion Region) The floating diffusion region FD shown in FIG. 3A temporarily accumulates and holds the signal charges transferred from the photoelectric conversion unit 25 via the transfer transistor TR.

[0035] 3, the input side of the pixel circuit 16 is electrically connected to the floating diffusion region FD. The pixel circuit 16 of the first embodiment is provided, for example, for each pixel block 15, and is shared by four pixels 3 (3a, 3b, 3c, 3d) included in one pixel block 15.

[0036] In the first embodiment, as an example, a circuit configuration is used in which one pixel circuit 16 is assigned to one pixel block 15, each unit of which includes four pixels 3, but the present invention is not limited to this first embodiment. For example, a circuit configuration may be used in which one pixel circuit 16 is assigned to one pixel block 15, each unit of which includes two or more pixels 3, or a circuit configuration may be used in which one pixel circuit 16 is assigned to multiple pixel blocks 15, each unit of which includes multiple pixels 3. A circuit configuration in which one pixel circuit 16 is assigned to one pixel 3 may also be used.

[0037] 3 has an input stage electrically connected to the floating diffusion region FD of each of the four pixels 3 (3a, 3b, 3c, and 3d) included in one pixel block 15. The pixel circuit 16 reads out the signal charges held in the floating diffusion region FD of each of the four pixels 3 (3a, 3b, 3c, and 3d) and outputs a pixel signal based on the read signal charges. In other words, the pixel circuit 16 converts the signal charges photoelectrically converted by the photoelectric conversion unit 25 (photodiode PD) into a pixel signal based on the signal charges and outputs the pixel signal.

[0038] 3, the pixel circuit 16 includes a plurality of pixel transistors Q. The pixel circuit 16 of the first embodiment includes, but is not limited to, an amplification transistor AMP, a selection transistor SEL, a reset transistor RST, and a switching transistor FDG as the pixel transistors Q. These pixel transistors Q (AMP, SEL, RST, FDG) and the transfer transistor TR are insulated gate field effect transistors, and the gate insulating film is made of, for example, silicon oxide (SiO ２These transistors are configured with MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) made of a silicon nitride (Si) film. ３ N ４ Alternatively, a metal insulator semiconductor field effect transistor (MISFET) made of a laminated film of a silicon nitride film, a silicon oxide film, or the like may be used.

[0039] Of the pixel transistors Q (AMP, SEL, RST, FDG) included in the pixel circuit 16, the selection transistor SEL, the reset transistor RST, and the switching transistor FDG mainly function as switching elements, and the remaining amplification transistor AMP mainly functions as an amplification element.

[0040] 3, the source region of the amplifier transistor AMP is electrically connected to the drain region of the select transistor SEL, and the drain region is electrically connected to the power supply line Vdd and the drain region of the reset transistor RST. The gate electrode of the amplifier transistor AMP is electrically connected to the floating diffusion region FD of each of the four pixels 3 (3a, 3b, 3c, and 3d) and the source region of the switching transistor FDG.

[0041] 3, the source region of the select transistor SEL is electrically connected to the vertical signal line 11 (VSL), the drain region is electrically connected to the source region of the amplification transistor AMP, and the gate electrode of the select transistor SEL is electrically connected to the select transistor drive line of the pixel drive lines 10 shown in FIG.

[0042] 3, the source region of the reset transistor RST is electrically connected to the drain of the switching transistor FDG, and the drain region is electrically connected to the power supply line Vdd and the drain region of the amplification transistor AMP. The gate electrode of the reset transistor RST is electrically connected to the reset transistor drive line of the pixel drive line 10 shown in FIG.

[0043] 3, the switching transistor FDG has a source region electrically connected to the gate electrode of the amplification transistor AMP and the floating diffusion region FD of each of the four pixels 3 (3 a, 3 b, 3 c, 3 d), and a drain region electrically connected to the source region of the reset transistor RST. The gate electrode of the switching transistor FDG is electrically connected to a switching transistor drive line among the pixel drive lines 10 shown in FIG.

[0044] The selection transistor SEL and the switching transistor FDG may be omitted as necessary.

[0045] When the selection transistor SEL is omitted, the source region of the amplification transistor AMP is electrically connected to the vertical signal line 11 (VSL). When the switching transistor FDG is omitted, the source region of the reset transistor RST is electrically connected to the gate electrode and floating diffusion region FD of the amplification transistor AMP.

[0046] When the transfer transistor TR shown in FIG. 3 is turned on, it transfers the signal charge generated in the photoelectric conversion unit 25 (photodiode PD) to the floating diffusion region FD.

[0047] When the reset transistor RST shown in FIG. 3 is turned on, it resets the potential (signal charge) of the floating diffusion region FD to the potential of the power supply line Vdd.

[0048] The selection transistor SEL shown in FIG. 3 controls the output timing of the pixel signal from the pixel circuit 16 .

[0049] 3 generates a pixel signal having a voltage corresponding to the level of the signal charge held in the floating diffusion region FD. The amplifier transistor AMP constitutes a source-follower amplifier and outputs a pixel signal having a voltage corresponding to the level of the signal charge generated in the photoelectric conversion unit 25 (photodiode PD). When the selection transistor SEL is turned on, the amplifier transistor AMP amplifies the potential of the floating diffusion region FD and outputs a voltage corresponding to the potential to the column signal processing circuit 5 via the vertical signal line 11 (VSL).

[0050] The switching transistor FDG shown in FIG. 3 controls charge retention by the floating diffusion region FD, and adjusts the multiplication factor of the voltage according to the potential amplified by the amplifier transistor AMP.

[0051] The switching transistor FDG is used to switch the conversion efficiency. Generally, pixel signals are small when shooting in dark locations. Based on Q = CV, when performing charge-to-voltage conversion, if the FD capacitance C (floating diffusion capacitance C) of the floating diffusion region FD is large, the voltage V converted to a voltage by the amplifier transistor AMP will be small. On the other hand, in bright locations, pixel signals are large, so if the FD capacitance C of the floating diffusion region FD is not large, the floating diffusion region FD cannot fully absorb the charge of the photoelectric conversion unit 25 (photodiode PD). Furthermore, the FD capacitance C of the floating diffusion region FD must be large so that the voltage V converted to a voltage by the amplifier transistor AMP does not become too large (in other words, to reduce it). Based on these considerations, when the switching transistor FDG is turned on, the gate capacitance of the switching transistor FDG increases, thereby increasing the overall FD capacitance C. On the other hand, when the switching transistor FDG is turned off, the overall FD capacitance C decreases. In this way, by switching the switching transistor FDG on and off, the FD capacitance C can be made variable, and the conversion efficiency can be changed.

[0052] During operation of the solid-state imaging device 1A according to the first embodiment, signal charges generated in the photoelectric conversion unit 25 of the pixel 3 are held (accumulated) in the floating diffusion region FD via the transfer transistor TR of the pixel 3. The signal charges held in the floating diffusion region FD are then read out by the pixel circuit 16 and applied to the gate electrode of the amplifier transistor AMP of the pixel circuit 16. A horizontal line selection control signal is applied to the gate electrode of the select transistor SEL of the pixel circuit 16 from the vertical shift register. By setting the selection control signal to a high (H) level, the select transistor SEL becomes conductive, and a current corresponding to the potential of the floating diffusion region FD, amplified by the amplifier transistor AMP, flows through the vertical signal line 11. Furthermore, by setting the reset control signal applied to the gate electrode of the reset transistor RST of the pixel circuit 16 to a high (H) level, the reset transistor RST becomes conductive, resetting the signal charges accumulated in the floating diffusion region FD.

[0053] 3 are mounted on a semiconductor layer 21 (see FIG. 6 ) described later. Although not limited thereto, the pixel transistors Q (AMP, SEL, RST, FDG) included in the pixel circuit 16 shown in FIG. 3 are also mounted on the semiconductor layer 21, for example.

[0054] <<Specific Configuration of Solid-State Imaging Device>> Next, a specific configuration of the semiconductor chip 2 (solid-state imaging device 1A) will be described with reference to Figs. 4 to 7. To make the drawings easier to understand, the multilayer wiring layer, which will be described later, is omitted from Figs. 4 to 7. Also, while Fig. 1 illustrates the light incident surface side of the semiconductor chip 2, Fig. 4 is a plan view of the semiconductor chip 2 as viewed from the opposite side to the light incident surface side (the multilayer wiring layer side).

[0055] As shown in Figure 6, the semiconductor chip 2 comprises a semiconductor layer 21 having a first surface portion S1 and a second surface portion S2 located opposite each other in the thickness direction (Z direction) as one direction, an inter-pixel isolation region 31 provided in the semiconductor layer 21 and serving as an isolation region extending in the thickness direction (Z direction) of the semiconductor layer 21, and a photoelectric conversion region 22 provided in the semiconductor layer 21 and partitioned by the inter-pixel isolation region 31, and including the first surface portion S1 and the second surface portion S2 of the semiconductor layer 21.

[0056] Although not shown, the semiconductor chip 2 further includes a multi-layer wiring layer provided on the first surface S1 side of the semiconductor layer 21.

[0057] In addition, the semiconductor chip 2 further includes a planarization film 61, an optical filter 63, and a microlens (on-chip lens) 64 provided in this order from the second surface S2 side of the semiconductor layer 21.

[0058] Here, the first surface S1 of the semiconductor layer 21 is sometimes referred to as a main surface or an element forming surface, and the second surface S2 is sometimes referred to as a back surface. The solid-state imaging device 1A according to the first embodiment photoelectrically converts incident light incident from the second surface S2 side of the semiconductor layer 21 by a photoelectric conversion unit 25 (photodiode PD) provided in the photoelectric conversion region 22 of the semiconductor layer 21. Therefore, in the first embodiment, the second surface S2 of the semiconductor layer 21 is sometimes referred to as a light incident surface.

[0059] 4, four pixels 3 (3a, 3b, 3c, 3d) included in one pixel block 15 are arranged two by two in each of the X and Y directions in a plan view, forming a 2 x 2 layout. That is, in the pixel array section 2A shown in FIG. 1, pixel blocks 15, each consisting of four pixels 3 (3a, 3b, 3c, 3d) as one unit, are repeatedly arranged in each of the X and Y directions.

[0060] <Planarization film, optical filter, and microlens> The planarization film 61 shown in FIG. 6 is provided on the second surface S2 side of the semiconductor layer 21 so as to cover the second surface S2 of the semiconductor layer 21, and planarizes the second surface S2 side of the semiconductor layer 21.

[0061] 6 is provided for each pixel 3. The optical filter 63 separates the color of the incident light that is incident from the light incident surface side (second surface portion S2 side) of the semiconductor chip 2. The microlens 64 condenses the irradiated light and allows the condensed light to be efficiently incident on the pixel 3.

[0062] 6 , the semiconductor layer 21 includes an inter-pixel isolation region 31 extending in the thickness direction (Z direction) of the semiconductor layer 21, and a photoelectric conversion region 22 partitioned by the inter-pixel isolation region 31. The photoelectric conversion region 22 is provided for each pixel 3. The semiconductor layer 21 may be a Si substrate, a SiGe substrate, an InGaAs substrate, or the like. In the first embodiment, a p-type semiconductor substrate made of single crystal silicon, for example, is used as the semiconductor layer 21, although the present invention is not limited thereto.

[0063] 4 , the inter-pixel isolation region 31 includes a first extending portion 31x extending in the X direction in a plan view and a second extending portion 31y extending in the Y direction. The inter-pixel isolation region 31 further includes an intersection portion (point of intersection) 31xy where the first extending portion 31x and the second extending portion 31y intersect with each other on the same plane. In this first embodiment, the first extending portion 31x and the second extending portion 31y are, for example, perpendicular to each other.

[0064] The first extending portions 31x are repeatedly arranged at predetermined intervals in the Y direction, and the second extending portions 31y are repeatedly arranged at predetermined intervals in the X direction. That is, the inter-pixel isolation region 31 has a grid-like planar pattern in plan view.

[0065] 4 and 5 , the inter-pixel isolation region 31 corresponding to one photoelectric conversion region 22 has a rectangular annular planar pattern (ring-shaped planar pattern) in a plan view, and surrounds the periphery of one photoelectric conversion region 22 (see FIG. 5 ). The inter-pixel isolation region 31 corresponding to one pixel block 15 has a composite planar pattern having a cross-shaped planar pattern in which a first extension portion 31 x and a second extension portion 31 y are arranged orthogonal to each other within the rectangular annular planar pattern (see FIG. 4 ).

[0066] 4, in the inter-pixel isolation region 31 corresponding to one pixel block 15, an intersection (intersection) 31xy between the first extending portion 31x and the second extending portion 31y is located in the center of the pixel block 15. The photoelectric conversion regions 22 of the four pixels 3 (3a, 3b, 3c, 3d) are arranged in a matrix so as to surround this intersection 31xy.

[0067] (Vertical cross-sectional shape) As shown in Figure 6, the inter-pixel isolation region 31 extends in the thickness direction (Z direction) in the direction in which the first surface portion S1 side and the second surface portion S2 side of the semiconductor layer 21 are separated from each other, and electrically and optically isolates two photoelectric conversion regions 22 that are adjacent to each other in a planar view.

[0068] Although not limited to this, the inter-pixel isolation region 31 is configured as an engraved isolation type (trench isolation type) including, for example, an engraved portion 32 extending in the thickness direction (Z direction) of the semiconductor layer 21 and an isolation insulating film 34 provided in this engraved portion 32. Furthermore, although not limited to this, the inter-pixel isolation region 31 overlaps with an inter-element isolation region 41 provided on the first surface S1 side of the semiconductor layer 21, and extends from the bottom of this inter-element isolation region 41 to the second surface S2 of the semiconductor layer 21.

[0069] 4 , the photoelectric conversion region 22 is surrounded by the inter-pixel isolation region 31 in a plan view (when the semiconductor layer 21 is viewed from the thickness direction of the semiconductor layer 21), and has a rectangular planar shape. Specifically, the photoelectric conversion region 22 is surrounded in the inter-pixel isolation region 31 by two first extending portions 31x that extend in the X direction and are spaced apart in the Y direction, and two second extending portions 31y that extend in the Y direction and are spaced apart in the X direction. The photoelectric conversion region 22 is partitioned by the inter-pixel isolation region 31 including these first extending portions 31x and second extending portions 31y, and is separated from other adjacent photoelectric conversion regions 22.

[0070] As shown in Figure 6, the photoelectric conversion region 22 has a p-type well region 23 consisting of a p-type semiconductor region provided in the semiconductor layer 21 across the first surface portion S1 and the second surface portion S2 of the semiconductor layer 21, an n-type semiconductor region 24 provided in the p-type well region 23 at a distance from the first surface portion S1 of the semiconductor layer 21, and a photoelectric conversion unit 25 including the p-type well region 23 and the n-type semiconductor region 24 and provided in the semiconductor layer 21 at a distance from the first surface portion S1 of the semiconductor layer 21.

[0071] The photoelectric conversion region 22 further includes an n-type floating diffusion region FD that is provided on the first surface S1 side of the semiconductor layer 21 and overlaps with the n-type semiconductor region 24 in a planar view, and serves as a charge holding section that holds signal charges photoelectrically converted by the photoelectric conversion section 25, and a transfer transistor TR that is provided on the first surface S1 side of the semiconductor layer 21 and overlaps with the n-type semiconductor region 24 in a planar view, and transfers the signal charges photoelectrically converted by the photoelectric conversion section 25 to the n-type floating diffusion region FD.

[0072] In addition, the photoelectric conversion region 22 further has an inter-element isolation region 41 provided on the first surface S1 side of the semiconductor layer 21, element formation regions 43a and 43b partitioned by this inter-element isolation region 41, and a power supply region 43z partitioned by this inter-element isolation region 41.

[0073] Furthermore, the photoelectric conversion region 22 further includes a pixel transistor Q included in the pixel circuit 16 of Fig. 3. In this first embodiment, although not limited thereto, for example, as shown in Fig. 4, among four pixels 3 (3a, 3b, 3c, 3d) included in one pixel block 15, the photoelectric conversion region 22 of pixel 3a further includes an amplification transistor AMP as the pixel transistor Q, the photoelectric conversion region 22 of pixel 3b further includes a selection transistor SEL as the pixel transistor Q, the photoelectric conversion region 22 of pixel 3c further includes a switching transistor FDG as the pixel transistor Q, and the photoelectric conversion region 22 of pixel 3d further includes a reset transistor RST as the pixel transistor Q.

[0074] 5 and 6 , the inter-element isolation region 41 is provided in a surface layer portion on the first surface portion S1 side of the semiconductor layer 21. The inter-element isolation region 41 overlaps with the inter-pixel isolation region 31 in a plan view and is integrated with the inter-pixel isolation region 31.

[0075] Although not limited thereto, the inter-element isolation region 41 has, for example, an STI (Shallow Trench Isolation) structure in which an isolation insulating film 41b is selectively embedded in a shallow groove 41a recessed from the first surface S1 toward the second surface S2 of the semiconductor layer 21. As shown in FIG. 4 , the inter-element isolation region 41 is provided across adjacent photoelectric conversion regions 22 with the inter-pixel isolation region 31 interposed therebetween in a plan view.

[0076] 6, the p-type well region 23 is provided over a wide area across the first surface portion S1 side and the second surface portion S2 side of the semiconductor layer 21 in each photoelectric conversion region 22. The p-type well region 23 is in contact with the inter-pixel isolation region 31 along the thickness direction (Z direction) of the semiconductor layer 21.

[0077] 6 , the n-type semiconductor region 24 is provided in the p-type well region 23 in each photoelectric conversion region 22. That is, six sides of the n-type semiconductor region 24, including the top surface, bottom surface, and four side surfaces, are surrounded by the p-type well region 23. The n-type semiconductor region 24 is separated from the first surface S1 and second surface S2 of the semiconductor layer 21 and the inter-pixel isolation region 31.

[0078] 6 includes a p-type well region 23 and an n-type semiconductor region 24 in each photoelectric conversion region 22. The photoelectric conversion unit 25 is configured as a p-n junction photodiode (PD) including a p-n junction between the p-type well region 23 and the n-type semiconductor region 24.

[0079] The photoelectric conversion unit 25 photoelectrically converts light incident on the n-type semiconductor region 24 from the second surface S2 side of the semiconductor layer 21 into signal charges in the n-type semiconductor region 24, and temporarily holds (accumulates) the photoelectrically converted signal charges at the pn junction between the p-type well region 23 and the n-type semiconductor region 24. The photoelectric conversion unit 25 is provided in the semiconductor layer 21 at a distance from the first surface S1 of the semiconductor layer 21.

[0080] 6 , the n-type floating diffusion region FD is provided in the p-type well region 23 on the first surface portion S1 side of the semiconductor layer 21. The n-type floating diffusion region FD overlaps with the photoelectric conversion section 25 (n-type semiconductor region 24) in a plan view, and is spaced apart from the photoelectric conversion section 25 (n-type semiconductor region 24) in the thickness direction (Z direction) of the semiconductor layer 21. In other words, the p-type well region 23 is provided between the n-type floating diffusion region FD and the n-type semiconductor region 24.

[0081] The n-type floating diffusion region FD is separated from a gate electrode 54 of the transfer transistor TR (described later) via an n-type semiconductor region 56t provided in the p-type well region 23 on the first surface S1 side of the semiconductor layer 21. The n-type floating diffusion region FD is composed of an n-type semiconductor region having a higher impurity concentration than the n-type semiconductor region 56t.

[0082] The n-type semiconductor region 56t overlaps the n-type semiconductor region 24 in a plan view, and is spaced apart from the n-type semiconductor region 24 in the thickness direction (Z direction) of the semiconductor layer 21. In other words, the p-type well region 23 is provided between the n-type semiconductor region 56t and the n-type semiconductor region 24.

[0083] Here, in this first embodiment, the n-type floating diffusion region FD and the n-type semiconductor region 56t are described separately, but the n-type floating diffusion region FD may be configured to include the n-type semiconductor region 56t.

[0084] 4 to 6 , the element formation region 43 a, the element formation region 43 b, and the power supply region 43 z are each provided for each photoelectric conversion region 22. Each of the element formation regions 43 a, 43 b, and the power supply region 43 z is surrounded by an inter-element isolation region 41 on the first surface S1 side of the semiconductor layer 21, and has an island shape that is individually isolated.

[0085] In the element formation region 43a, a p-type well region 23, an n-type semiconductor region 56t, an n-type floating diffusion region FD, and a transfer transistor TR are provided.

[0086] On the other hand, a pixel transistor Q is provided in the element formation region 43b. In the first embodiment, as shown in FIG. 4 , an amplifier transistor AMP, for example, is provided as the pixel transistor Q in the element formation region 43a of the photoelectric conversion region 22 of pixel 3a. A select transistor SEL, for example, is provided as the pixel transistor Q in the element formation region 43b of the photoelectric conversion region 22 of pixel 3b. A switching transistor FDG, for example, is provided as the pixel transistor Q in the element formation region 43b of the photoelectric conversion region 22 of pixel 3c. A reset transistor RST, for example, is provided as the pixel transistor Q in the element formation region 43b of the photoelectric conversion region 22 of pixel 3d. That is, the pixel transistor Q included in the pixel circuit 16 is provided on the first surface S1 side of the semiconductor layer 21.

[0087] 6, the amplifier transistor AMP has a gate electrode 55 provided so as to overlap the element formation region 43b of the photoelectric conversion region 22 in a plan view, and a gate insulating film 52 provided between the gate electrode 55 and the element formation region 43b. The amplifier transistor AMP also has a pair of main electrode regions 56a and 56b provided in the element formation region 43b on both sides of the gate electrode 55 in the gate length direction and functioning as a source region and a drain region, and a channel formation portion provided between the pair of main electrode regions 56a and 56b.

[0088] Each of the pair of main electrode regions 56a and 56b is formed, for example, by an n-type semiconductor region provided in the p-type well region 23 of the element formation region 43b. The channel formation portion is formed, for example, by the p-type well region 23 provided in the element formation region 43b. The gate insulating film 52 is formed, for example, by a silicon oxide film. The gate electrode 55 is formed, for example, by a polycrystalline silicon film doped with impurities that reduce resistance.

[0089] In addition, as the pixel transistors Q included in the pixel circuit 16, the selection transistor SEL, the switching transistor FDG, and the reset transistor RST other than the amplification transistor AMP also have the same configuration as the amplification transistor AMP, so a description of these pixel transistors Q (SEL, FDG, RST) will be omitted.

[0090] 4 and 5 , a p-type power supply contact region WC is provided in the power supply region 43z. Although not shown in detail, this p-type power supply contact region WC is provided in the p-type well region 23 on the first surface S1 side of the semiconductor layer 21, and is electrically connected to this p-type well region 23. The p-type power supply contact region WC is made of a p-type semiconductor region having a higher impurity concentration than the p-type well region 23.

[0091] A first reference potential (Vss potential) of, for example, 0 V is applied to the p-type power supply contact region WC as a reference potential within the semiconductor chip 2 (within the solid-state imaging device 1A) during operation, and the potential is fixed to this first reference potential during operation.

[0092] (Transfer Transistor) As shown in FIG. 6 , the transfer transistor TR is provided on the first surface S1 side of the semiconductor layer 21 (the first surface S1 side of the photoelectric conversion region 22). The transfer transistor TR has a gate electrode 54 provided on the first surface S1 side of the photoelectric conversion region 22 (semiconductor layer 21) across the inside and outside of the semiconductor layer 21, and a gate insulating film 52 provided between the gate electrode 54 and the semiconductor layer 21. The transfer transistor TR also has an n-type semiconductor region 24 functioning as a source region, an n-type semiconductor region 56t and an n-type floating diffusion region FD functioning as drain regions, and a p-type well region 23 functioning as a channel formation region. This transfer transistor RT is configured as a vertical type.

[0093] 5 and 6 , the gate electrode 54 of the transfer transistor TR is provided at a position overlapping the n-type semiconductor region 24 in a plan view. The gate electrode 54 has a head 54a provided outside the first surface portion S1 of the semiconductor layer 21 with the gate insulating film 52 interposed therebetween, and a body 54b integrated with the head 54a and provided adjacent to the semiconductor layer 21 in the gate trench portion 51 of the semiconductor layer 21 with the gate insulating film 52 interposed therebetween.

[0094] As shown in FIGS. 6 and 7, the body portion 54b is a first electrode portion 54b extending from the first surface portion S1 side of the semiconductor layer 21 toward the second surface portion S2 side. １ and the first electrode portion 54b is spaced apart from the first surface portion S1 of the semiconductor layer 21. １ and the outer shape in plan view is the first electrode portion 54b １ The second electrode portion 54b is expanded ２ The second electrode portion 54b has a stepped shape including the ２ is the first electrode portion 54b in a plan view of the semiconductor layer 21 viewed from the thickness direction (Z direction) of the semiconductor layer 21. １ The first electrode portion 54b is two-dimensionally expanded. １ The outer size of the first electrode portion 54b in plan view is smaller than that of the head portion 54a. １It has a larger configuration than

[0095] As shown in FIG. 6, the gate trench 51 includes a first recessed portion 51b extending from the first surface S1 side of the semiconductor layer 21 toward the second surface S2 side. １ The first recessed portion 51b １ and the first dug portion 51b １ the first recessed portion 51b protruding from the second surface S2 of the semiconductor layer 21 and having an outer shape in plan view of the first recessed portion 51b １ The second dug portion 51b is wider than the ２ and,

[0096] As shown in FIG. 6, the first electrode portion 54b of the gate electrode 54 １ The first recessed portion 51b of the gate groove portion 51 is １ The second electrode portion 54b of the gate electrode 54 is provided ２ The second recessed portion 51b of the gate groove portion 51 is ２ It is set up in.

[0097] As shown in FIGS. 6 and 7, the first electrode portion 54b of the gate electrode 54 １ Although not limited to this, the second electrode portion 54b of the gate electrode is formed in a cylindrical shape, for example. ２ Although not limited thereto, the first electrode portion 54b of the gate electrode 54 has, for example, a circular planar shape in plan view and an elliptical cross-sectional shape along the thickness direction of the semiconductor layer 21. １ and the second electrode portion 54b ２ are provided at positions overlapping the photoelectric conversion portion 25, that is, the n-type semiconductor region 24 in plan view.

[0098] Here, "the outer shape in plan view is the first electrode portion 54b １ The second electrode portion 54b is expanded more than the ２ In other words, the second electrode portion 54b ２ is the first electrode portion 54b １ The second electrode portion 54b is thicker than the first electrode portion 54b. ２ The outline of the first electrode portion 54b in plan view is １ The second electrode portion 54b is located outside the outline of the second electrode portion 54b.２ The area of ​​the cross section perpendicular to the thickness direction (Z direction) of the semiconductor layer 21 is the same as that of the first electrode portion 54b. １ That is, the body portion 54b of the gate electrode 54 is thicker on the photoelectric conversion portion 25 side than on the first surface portion S1 side of the semiconductor layer 21.

[0099] As shown in FIG. 6, the second electrode portion 54b of the gate electrode 54 ２ Although not limited thereto, for example, the second electrode portion 54b of the gate electrode 54 is located closer to the photoelectric conversion unit 25 than the element isolation region 41 in the thickness direction (Z direction) of the semiconductor layer 21. ２ is spaced apart from each of the element isolation region 41 and the photoelectric conversion portion 25 (n-type semiconductor region 24) in the thickness direction (Z direction) of the semiconductor layer 21.

[0100] 10A to 10G , a method for manufacturing the solid-state imaging device 1A according to the first embodiment of the present technology will be described. In this first embodiment, the description will be focused on the manufacture of the gate electrode 54 of the transfer transistor TR, which is included in the method for manufacturing the solid-state imaging device 1A.

[0101] 10A , a photoelectric conversion region 22, a p-type well region 23, a photoelectric conversion unit 25 including an n-type semiconductor region 24, an inter-pixel isolation region 31, an inter-element isolation region 41, element formation regions 43a and 43b, a power supply region 43z, and the like are formed in a semiconductor layer 21. Each of the element formation regions 43a and 43b and the power supply region 43z can be formed in an island shape by forming a shallow groove portion 41a in the semiconductor layer 21, then forming an isolation insulating film so as to fill the shallow groove portion 41a, and then selectively removing the isolation insulating film other than the shallow groove portion 41a so that the isolation insulating film remains in the shallow groove portion 41a.

[0102] Next, the semiconductor layer 21 in the element forming region 43a is selectively etched to form a first recessed portion 51b on the first surface portion S1 side of the semiconductor layer 21, the first recessed portion 51b extending from the first surface portion S1 to the second surface portion S2 side, as shown in FIG. 10B. １ The first dug portion 51b is formed. １can be formed by selectively etching the first surface portion S1 of the semiconductor layer 21 using, for example, well-known photolithography and anisotropic dry etching techniques.

[0103] 10C, an etching mask M1 is formed on the first surface S1 side of the semiconductor layer 21. The etching mask M1 is formed on the first surface S1 side of the semiconductor layer 21 and the first carved portion 51b. １ a mask portion M1a covering the side surface of the semiconductor layer 21 in the recessed portion 51b; a first recessed portion 51b surrounded by the mask portion M1a and defined as a first recessed portion 51b in a plan view; １ The opening M1b overlaps the first dug portion 51b. １ The etching mask M1 is formed to have a width narrower than that of the semiconductor layer 21. The etching mask M1 is formed of a material that has an etching ratio with respect to the semiconductor layer 21.

[0104] Next, the first surface S1 side of the semiconductor layer 21 and the first recessed portion 51b １ With the side surface of the semiconductor layer 21 in the etching mask M1 covered with the mask portion M1a of the etching mask M1, the semiconductor layer 21 exposed from the opening M1b of the etching mask M1 is selectively etched using, for example, an isotropic etching technique, to form a first carved portion 51b as shown in FIG. 10D. １ and the width of the first dug portion 51b １ a second excavated portion (expanded excavated portion) 51b wider than the width of the first excavated portion ２ In this process, the second dug portion 51b ２ 10D, the second carved portion 51b has an elliptical cross section along the thickness direction (Z direction) of the semiconductor layer 21. ２ 7, the planar shape of the second electrode portion 54b ２ In this process, the first dug portion 51b is formed in a circular shape similar to that of the first dug portion 51b. １ and second recessed portion 51b ２ A gate trench 51 including the

[0105] Next, after selectively removing the etching mask M1, the first and second dug portions 51b are formed as shown in FIG. 10E. １ , 51b ２ A gate insulating film 52 is formed on the inner walls (inner walls of the gate trench 51) of each of the element formation regions 43a and 43b of the photoelectric conversion region 22, and also on the upper surface (first surface S1 of the semiconductor layer 21) of each of the element formation regions 43a and 43b of the photoelectric conversion region 22. The gate insulating film 52 may be, for example, a silicon oxide film. The silicon oxide film can be formed by thermal oxidation or deposition, but in this first embodiment, a silicon oxide film formed by thermal oxidation is used as the gate insulating film 52. The thermal oxidation method can form a silicon oxide film with better film quality than the deposition method.

[0106] Next, as shown in FIG. 10F, a gate electrode film 53 is formed. The gate electrode film 53 is formed in the first and second recessed portions 51b. １ , 51b ２ The gate electrode film 53 is formed on the first surface S1 side of the semiconductor layer 21 so as to fill the interior of each of the gate electrodes 53. The gate electrode film 53 can be formed by, for example, a polycrystalline silicon film that can be formed by a CVD method and into which an impurity that reduces the resistance value is introduced during or after the film formation.

[0107] 10G, the gate electrode film 53 is patterned to form a gate electrode 54 in the element formation region 43a of the photoelectric conversion region 22, and a gate electrode 55 in the element formation region 43b. In this process, the gate electrode 54 is formed in a vertical shape including a head 54a provided outside the first surface S1 of the semiconductor layer 21 with the gate insulating film 52 interposed therebetween, and a body 54b integrated with the head 54a and provided adjacent to the semiconductor layer 21 in the gate trench 51 of the semiconductor layer 21 with the gate insulating film 52 interposed therebetween. The body 54b has a first electrode portion 54b extending from the first surface S1 side of the semiconductor layer 21 toward the second surface S2 side. １ and the first electrode portion 54b is spaced apart from the first surface portion S1 of the semiconductor layer 21. １ and the outer shape in plan view is the first electrode portion 54b １ The second electrode portion 54b is expanded more than the ２The second electrode portion 54b is formed in a stepped shape including the ２ is the first electrode portion 54b １ the tip end side (the end portion side on the second surface side of the semiconductor layer) of the first electrode portion 54b １ It is formed by being integrated with

[0108] Next, after forming the gate electrodes 54 and 55 shown in FIG. 10G, an n-type semiconductor region 56t and an n-type floating diffusion region FD are formed in the element formation region 43a of the photoelectric conversion region 22, a pair of main electrode regions 56a and 56b are formed in the element formation region 43b of the photoelectric conversion region 22, and a p-type power supply contact region WC is formed in the power supply region 43z.

[0109] By this process, a transfer transistor TR is formed in the element formation region 43 a of the photoelectric conversion region 22, the transfer transistor TR mainly including the p-type well region 23 as a channel formation portion, the n-type semiconductor region 24 as a source region, the gate insulating film 52, the gate electrode 54, the n-type semiconductor region 56 t as a drain region, and the n-type floating diffusion region FD. Also, by this process, a pixel transistor Q (AMP, SEL, RST, FDG) is formed in the element formation region 43 b of the photoelectric conversion region 22, the pixel transistor Q including the p-type well region 23 as a channel formation region, the gate insulating film 52, the gate electrode 55, and a pair of main electrode regions 56 a and 56 b that function as a source region and a drain region.

[0110] <<Main Effects of the First Embodiment>> Next, the main effects of the first embodiment will be described with reference to a conventional reference example shown in Figs. 9A and 9B. Fig. 8 shows the signal charge transfer path R １ 9A is a longitudinal sectional view showing a schematic longitudinal sectional structure of a photoelectric conversion region according to a conventional reference example; ２ 9A is a diagram showing an example of the potential at 54z. In FIG. 9A, the same reference numerals as in FIG. 6 are used for the components other than the gate electrode 54z.

[0111] As shown in FIG. 9A, the gate electrode 54z of the transfer transistor TR, which is a conventional reference example, has a head 54z provided on the outer side of the first surface S1 of the semiconductor layer 21 with a gate insulating film 52 interposed therebetween. １ And this head 54z １ and a body portion 54z formed adjacent to the semiconductor layer 21 in the gate trench portion 51 of the semiconductor layer 21 with the gate insulating film 52 interposed therebetween. ２ and a body portion 54z. ２ basically extends linearly in the thickness direction (Z direction) of the semiconductor layer 21, and the head 54z in plan view １ The outer dimensions of the side and this head 54z １ The outer dimensions of the tip end on the opposite side are generally the same as those of the columnar shape.

[0112] 6 and 7, the gate electrode 54 of the transfer transistor TR according to the first embodiment has a head 54a provided outside the first surface S1 of the semiconductor layer 21 with the gate insulating film 52 interposed therebetween, and a body 54b integrated with the head 54a and provided adjacent to the semiconductor layer 21 in the gate trench 51 of the semiconductor layer 21 with the gate insulating film 52 interposed therebetween. The body 54b has a first electrode portion 54b extending from the first surface S1 side of the semiconductor layer 21 toward the second surface S2 side. １ and the first electrode portion 54b is spaced apart from the first surface portion S1 of the semiconductor layer 21. １ and the outer size in plan view is １ The second electrode portion 54b is expanded ２ 9A, the transfer transistor TR of the first embodiment has a surface area of ​​the body portion 54b adjacent to the semiconductor layer 21 via the gate insulating film 52, which is larger than the surface area of ​​the second electrode portion 54b. ２ This can improve the signal charge transfer capability of the transfer transistor TR that transfers the signal charge photoelectrically converted in the photoelectric conversion unit 25 to the floating diffusion region FD.

[0113] In the case of the conventional transfer transistor TR shown in FIG. 9A, the body 54z of the gate electrode 54z has been reduced in size as the transistor is miniaturized.２ When the gate insulating film 52 is thinned, the body portion 54z adjacent to the semiconductor layer 21 is ２ The surface area of ​​the photoelectric conversion portion 25 is reduced, the potential modulation capability is reduced, and the signal charge transfer capability of the transfer transistor TR that transfers the signal charge photoelectrically converted in the photoelectric conversion portion 25 to the floating diffusion region FD is reduced.

[0114] In contrast, in the case of the transfer transistor TR according to the first embodiment, as the transistor is miniaturized, the first electrode portion 54b of the body 54b of the gate electrode 54 １ Even if the diameter of the second electrode portion 54b is reduced, ２ By the expansion of the gate insulating film 52, the trunk portion 54z adjacent to the semiconductor layer 21 is formed. ２ This allows for a larger surface area and suppresses a decrease in the potential modulation capability.

[0115] Therefore, according to the solid-state imaging device 1A according to the first embodiment, it is possible to miniaturize the pixels 3 while suppressing a decrease in the signal charge transfer capability of the transfer transistor TR.

[0116] As shown in FIG. 9B, in the case of the conventional transfer transistor TR, the body portion 54z adjacent to the semiconductor layer 21 via the gate insulating film 52 ２ Since the surface area of ​​the charge transfer channel R2 is small and the modulation power is low, a potential barrier is easily formed in the charge transfer channel R2.

[0117] In contrast, as shown in FIG. 8, in the case of the transfer transistor TR according to the first embodiment, the surface area of ​​the body portion 54b adjacent to the semiconductor layer 21 via the gate insulating film 52 is large and the modulation power is high, so that no barrier exists in the potential of the signal charge transfer path R1, and the potential is smoother compared to FIG. 9B.

[0118] As can be seen from FIGS. 8 and 9B, the potential of the first embodiment shown in FIG. 8 is smoother than the conventional potential shown in FIG. 9B, and it is clear that application of this technology is useful.

[0119] 8 and 9B are data when the transfer transistor TR is in the "ON" state. The potential shown in FIG. 8 and the potential shown in FIG. 9B are data when the first electrode portion 54b of the body portion 54b shown in FIG. １ 9A (outer size in plan view) and the body portion 54z shown in FIG. ２ This is the case where the thickness (external size in plan view) of the wiring is the same as the design value.

[0120] <<Modification of First Embodiment>> Next, a modification of the gate electrode 54 of the transfer transistor TR will be described.

[0121] <Modification 1-1> Fig. 11A is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure of a photoelectric conversion region which is Modification 1-1 of the first embodiment of the present technology. Fig. 11B is a plan view schematically showing a planar shape of a second electrode portion included in a gate electrode of a transfer transistor of Fig. 11A. Fig. 11C is a plan view schematically showing another planar shape of the second electrode portion included in the gate electrode of Fig. 11A.

[0122] In the first embodiment described above, the gate electrode 54 is configured as follows: as shown in FIGS. 6 and 7, the first electrode portion 54b of the body portion 54b １ The second electrode portion 54b of the body portion 54b is formed in a cylindrical shape. ２ The first electrode portion 54b has a circular planar shape and an elliptical cross-sectional shape. １ and the second electrode portion 54b ２ The shape of the first embodiment is not limited to that of the first embodiment.

[0123] For example, as a modified example 1-1, as shown in FIGS. 11A and 11B, the first electrode portion 54b １ The second electrode portion 54b may be configured in a prismatic shape. ２ may be configured in a rectangular parallelepiped shape.

[0124] Rectangular second electrode portion 54b ２ is the second recessed portion 51b ２ The rectangular parallelepiped second dug portion 51b can be formed by processing the second dug portion 51b into a rectangular parallelepiped shape. ２can be easily formed by using a semiconductor layer 21 having a (111) crystal plane of single crystal silicon, and etching the semiconductor layer 21 by, for example, an anisotropic wet etching technique under etching conditions that are in line with the (111) crystal plane of the single crystal silicon in the second recess formation step of FIG. 10D , which is included in the manufacturing process of the solid-state imaging device 1A.

[0125] In addition, the second electrode portion 54b ２ The planar shape of the second electrode portion 54b can be controlled by rotating the orientation of the semiconductor layer 21 in a plan view. ２ 11C shows a case where the sides of the planar shape of the second electrode portion 54b are formed along the X direction and the Y direction. ２ 11B shows a case where the sides of the planar shape of the second electrode portion 54b are inclined with respect to the X and Y directions. ２ is the second electrode portion 54b shown in FIG. ２ The orientation in plan view is shifted by 45°.

[0126] In this modified example 1-1, the same effect as in the first embodiment can be obtained. ２ Therefore, for the same pixel size (planar size of the photoelectric conversion region 22), the second electrode portion 54b ２ The volume of the photoelectric conversion portion 25 (n-type semiconductor region 24) can be increased in a state where it is spaced apart from the surface of the photoelectric conversion portion 25, and the saturated charge amount Qs can be increased.

[0127] <Modification 1-2> Fig. 12A is a longitudinal sectional view schematically showing a longitudinal sectional structure of a photoelectric conversion region according to Modification 1-2 of the first embodiment of the present technology. Fig. 12B is a plan view schematically showing a planar shape of a second electrode portion included in a gate electrode of a transfer transistor according to Fig. 12A. Fig. 12C is a plan view schematically showing another planar shape of the second electrode portion included in a gate electrode of a transfer transistor according to Fig. 12A.

[0128] As shown in FIGS. 12A and 12B, in this modification 1-2, the first electrode portion 54b is formed in the body portion 54b of the gate electrode 54.１ The second electrode portion 54b is formed in a rectangular column shape. ２ It is configured in an octahedral shape.

[0129] Octahedral-shaped second electrode portion 54b ２ is the second recessed portion 51b ２ The second recessed portion 51b having an octahedral shape can be formed by processing the recessed portion 51b into an octahedral shape. ２ can be easily formed by using a semiconductor layer 21 having a (100) crystal plane of single crystal silicon, and etching the semiconductor layer 21 by, for example, an anisotropic wet etching technique under etching conditions that are in line with the (100) crystal plane of the single crystal silicon in the second recess formation step of FIG. 10D , which is included in the manufacturing process of the solid-state imaging device 1A.

[0130] The octahedral second electrode portion 54b ２ In this case, the planar shape can be controlled by rotating the orientation of the semiconductor layer 21 in a plan view. ２ 12C shows a case where the sides of the planar shape of the second electrode portion 54b are formed along the X and Y directions. ２ 12B shows a case where the sides of the planar shape of the second electrode portion 54b are formed so as to be inclined with respect to the X and Y directions. ２ is the second electrode portion 54b shown in FIG. ２ The orientation in plan view is shifted by 45°.

[0131] As shown in FIG. 12A, the octahedral second electrode portion 54b ２ is an inclined surface (slope portion) SS that intersects with the thickness direction (Z direction) of the semiconductor layer 21 and extends obliquely from the n-type semiconductor region 24 side of the photoelectric conversion unit 25 toward the floating diffusion region FD. １ It has.

[0132] In this modified example 1-2, the same effect as in the first embodiment can be obtained. ２ is the inclined surface SS １, the signal charges can be transferred to the floating diffusion region FD more efficiently than in the first embodiment.

[0133] In this modified example 1-2, the second electrode portion 54b ２ The second electrode portion 54b is provided in the n-type semiconductor region 24. ２ may be spaced apart from the n-type semiconductor region 24. In this case, however, the volume of the photoelectric conversion portion 25 (n-type semiconductor region 24) decreases.

[0134] <Modification 1-3> FIG. 13 is a longitudinal sectional view schematically showing a longitudinal sectional structure of a photoelectric conversion region that is Modification 1-3 of the first embodiment of the present technology.

[0135] As shown in FIG. 13, this modification 1-3 has an octahedral second electrode portion 54b ２ In this modified example 1-3, the second electrode portion 54b is in contact with the element isolation region 41 on the side opposite to the floating diffusion region FD in plan view. ２ is the inclined surface SS １ It has.

[0136] In this modified example 1-3, the same effects as those in the first embodiment can be obtained. ２ is the inclined surface SS １ , the signal charges can be transferred to the floating diffusion region FD more efficiently than in the first embodiment.

[0137] <Modification 1-4> Fig. 14A is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure of a photoelectric conversion region according to Modification 1-4 of the first embodiment of the present technology. Fig. 14B is a plan view schematically showing a planar shape of a second electrode portion included in a gate electrode of a transfer transistor shown in Fig. 14A. Fig. 14C is a plan view schematically showing another planar shape of the second electrode portion included in a gate electrode of a transfer transistor shown in Fig. 14A.

[0138] As shown in FIGS. 14A and 14B, this modification 1-4 has a first electrode portion 54b １ The second electrode portion 54b is formed in a rectangular column shape. ２In plan view, the first electrode portion 54b １ In the case of this modification 1-4, the second electrode portion 54b is extended to the side opposite to the floating diffusion region FD side. ２ It is preferable to extend

[0139] The second electrode portion 54b of this modified example 1-4 ２ In this case, the second dug portion 51b is formed in the same manner as in the above-described modified example 1-1. ２ The second electrode portion 54b of this modified example 1-4 can be easily formed by processing the ２ 14B, the planar shape of the second electrode portion 54b having a square planar shape can be controlled by rotating the orientation of the semiconductor layer 21 in a planar view. ２ 14C illustrates a second electrode portion 54b having a triangular planar shape. ２ is shown as an example.

[0140] In this modification 1-4, the same effect as in the first embodiment can be obtained. In addition, in the case of this modification 1-4, the second electrode portion 54b is formed toward the saddle point of the potential in the photoelectric conversion unit 25 (PD). ２ By expanding the area of ​​the floating diffusion region FD, the signal charges can be transferred to the floating diffusion region FD more efficiently than in the first embodiment.

[0141] <Modifications 1-5 and 1-6> In the first embodiment described above, the gate electrode 54 having the head portion 54a and the body portion 54b has been described, but the present technology is not limited to the gate electrode 54 of the first embodiment described above.

[0142] For example, as a modified example 1-5, as shown in FIG. 15, the head portion 54a shown in FIG. 6 is omitted, and the first electrode portion 54b １ The gate electrode 54 of this modification 1-5 also has a first electrode portion 54b extending from the first surface portion S1 side of the semiconductor layer 21 toward the second surface portion S2 side. １ and the first electrode portion 54b is spaced apart from the first surface portion S1 of the semiconductor layer 21. ２ and the outer shape in plan view is the first electrode portion 54b１ The second electrode portion 54b is expanded ２ The configuration includes the following.

[0143] As a modified example 1-6, as shown in FIG. 16, the head portion 54a shown in FIG. 6 is omitted, and the first electrode portion 54b is １ may be provided in the semiconductor layer 21. In the gate electrode 54 of this modified example 1-6, the first electrode portion 54b extending from the first surface portion S1 side of the semiconductor layer 21 toward the second surface portion S2 side １ and the first electrode portion 54b is spaced apart from the first surface portion S1 of the semiconductor layer 21. ２ and the outer shape in plan view is the first electrode portion 54b １ The second electrode portion 54b is expanded ２ The configuration includes the following.

[0144] [Second Embodiment] In this second embodiment, an example of a photoelectric conversion region including a barrier layer will be described. Fig. 17A is a longitudinal sectional view schematically showing an example of a configuration of a solid-state imaging device according to a second embodiment of the present technology. Fig. 17B is a plan view schematically showing the planar shape of a barrier layer included in the photoelectric conversion region of Fig. 17A.

[0145] As shown in Figures 17A and 17B, the solid-state imaging device 1B of the second embodiment of the present technology is basically configured in the same manner as the solid-state imaging device 1A of the first embodiment described above, with the following differences in configuration.

[0146] 17A and 17B , the solid-state imaging device 1B according to the second embodiment of the present technology further includes a barrier layer 65 that is provided between the n-type semiconductor region 24 included in the photoelectric conversion unit 25 and the first surface S1 of the semiconductor layer 21 in a region other than the region facing the floating diffusion region FD when the semiconductor layer 21 is viewed in a plan view from the thickness direction (Z direction) of the semiconductor layer 21, and that suppresses movement of signal charges photoelectrically converted by the photoelectric conversion unit 25 toward the first surface S1. The other configurations are generally similar to those of the first embodiment described above.

[0147] In the first embodiment, although not limited thereto, for example, the barrier layer 65 is provided so as to overlap with each of the inter-element isolation region 41, the element formation region 43b, and the power supply region 43z in a region other than the region facing the floating diffusion region FD in a planar view, but not to overlap with the element formation region 43a. Furthermore, the barrier layer 65 is provided so as to be spaced apart from the inter-pixel isolation region 31 in a region other than the region facing the floating diffusion region FD in a planar view. The barrier layer 65 is formed of, for example, a p-type semiconductor region having a higher impurity concentration than the p-type well region 23.

[0148] As shown in Figure 17A, the barrier layer 65 is provided at a distance from each of the main electrode regions 56a, 56b of the pixel transistor Q and the n-type semiconductor region 24 of the photoelectric conversion section 25 in the thickness direction (Z direction) of the semiconductor layer 21.

[0149] The solid-state imaging device 1B according to the second embodiment also provides the same effects as the solid-state imaging device 1A according to the first embodiment. Furthermore, in the region where the barrier layer 65 is provided, the signal charges photoelectrically converted in the photoelectric conversion unit 25 can be suppressed from moving toward the first surface S1 of the semiconductor layer 21. This makes it possible to transfer the signal charges to the floating diffusion region FD more efficiently than in the first embodiment.

[0150] In this second embodiment, the barrier layer 65 is provided at a position where the inter-element isolation region 41 and the barrier layer 65 are adjacent to each other in the thickness direction (Z direction) of the semiconductor layer 21, but the barrier layer 65 may also be provided closer to the second surface portion S2 of the semiconductor layer 21 than the inter-element isolation region 41.

[0151] 11A, a barrier layer 65 is applied to the above-described modified example 1-1 shown in Fig. 11A. Fig. 18 is a longitudinal sectional view schematically showing a longitudinal sectional structure of a photoelectric conversion region of a solid-state imaging device according to a third embodiment of the present technology.

[0152] A solid-state imaging device 1C according to the third embodiment of the present technology has basically the same configuration as that of the above-described modified example 1-1, and further includes a barrier layer 65 in addition to the configuration of the above-described modified example 1-1.

[0153] As in the second embodiment described above, the barrier layer 65 of this third embodiment is provided between the n-type semiconductor region 24 included in the photoelectric conversion section 25 and the first surface portion S1 of the semiconductor layer 21 in an area other than the area facing the floating diffusion region FD when the semiconductor layer 21 is viewed in a plane from the thickness direction (Z direction) of the semiconductor layer 21, and suppresses the movement of signal charges photoelectrically converted by the photoelectric conversion section 25 toward the first surface portion S1.

[0154] The solid-state imaging device 1C according to the third embodiment also provides the same effects as those of the second embodiment described above.

[0155] [Fourth Embodiment] In this fourth embodiment, a barrier layer 65 is applied to the above-described modified example 1-2 shown in Fig. 12A. Fig. 19 is a longitudinal sectional view schematically showing a longitudinal sectional structure of a photoelectric conversion region of a solid-state imaging device according to a fourth embodiment of the present technology. A solid-state imaging device 1D according to the fourth embodiment of the present technology basically has the same configuration as the above-described modified example 1-2 shown in Fig. 12A, and further includes a barrier layer 65 in addition to the configuration of the above-described modified example 1-2.

[0156] As in the second embodiment described above, the barrier layer 65 of this fourth embodiment is provided between the n-type semiconductor region 24 of the photoelectric conversion section 25 and the first surface S1 of the semiconductor layer 21 in an area other than the area facing the floating diffusion region FD when the semiconductor layer 21 is viewed in a plane from the thickness direction (Z direction) of the semiconductor layer 21, and suppresses the movement of signal charges photoelectrically converted by the photoelectric conversion section 25 toward the first surface S1.

[0157] The solid-state imaging device 1D according to the fourth embodiment also provides the same effects as those of the second embodiment.

[0158] Fifth Embodiment In this sixth embodiment, a barrier layer 65 is applied to the above-described modified example 1-3 shown in Fig. 13. Fig. 20 is a longitudinal sectional view schematically showing a longitudinal sectional structure of a photoelectric conversion region of a solid-state imaging device according to a fifth embodiment of the present technology. A solid-state imaging device 1E according to the fifth embodiment of the present technology basically has the same configuration as the above-described modified example 1-3 shown in Fig. 13, and further includes a barrier layer 65 in addition to the configuration of the above-described modified example 1-3.

[0159] As in the second embodiment described above, the barrier layer 65 of this fifth embodiment is provided between the n-type semiconductor region 24 included in the photoelectric conversion section 25 and the first surface portion S1 of the semiconductor layer 21 in an area other than the area facing the floating diffusion region FD when the semiconductor layer 21 is viewed in a plane from the thickness direction (Z direction) of the semiconductor layer 21, and suppresses the movement of signal charges photoelectrically converted by the photoelectric conversion section 25 toward the first surface portion S1.

[0160] The solid-state imaging device 1E according to the fifth embodiment also provides the same effects as those of the second embodiment described above.

[0161] Sixth Embodiment In this sixth embodiment, a barrier layer 65 is applied to the above-described modified example 1-4 shown in FIG. 14A. FIG. 21 is a longitudinal sectional view schematically showing a longitudinal sectional structure of a photoelectric conversion region of a solid-state imaging device according to a sixth embodiment of the present technology. A solid-state imaging device 1F according to the sixth embodiment of the present technology basically has the same configuration as the above-described modified example 1-4 shown in FIG. 14A, and further includes a barrier layer 65 in addition to the configuration of the above-described modified example 1-4.

[0162] As in the second embodiment described above, the barrier layer 65 of this sixth embodiment is provided between the n-type semiconductor region 24 included in the photoelectric conversion section 25 and the first surface portion S1 of the semiconductor layer 21 in an area other than the area facing the floating diffusion region FD when the semiconductor layer 21 is viewed in a plane from the thickness direction (Z direction) of the semiconductor layer 21, and suppresses the movement of signal charges photoelectrically converted by the photoelectric conversion section 25 toward the first surface portion S1.

[0163] The solid-state imaging device 1F according to the sixth embodiment also provides the same effects as those of the second embodiment described above.

[0164] 22A is a plan view schematically illustrating a configuration example of a pixel of a solid-state imaging device according to a seventh embodiment of the present technology, and FIG. 22B is a plan view schematically illustrating a planar shape of a second electrode portion included in a gate electrode of a transfer transistor of FIG.

[0165] A solid-state imaging device 1G according to the seventh embodiment of the present technology has basically the same configuration as the solid-state imaging device 1A according to the first embodiment described above, but the configuration of the pixels 3 is different.

[0166] That is, as shown in FIG. 5, the pixel 3 of the first embodiment described above has a configuration in which one photoelectric conversion section 25 (PD) is provided in one photoelectric conversion region 22 .

[0167] 22A and 22B is configured as a phase difference pixel that detects a phase difference between two photoelectric conversion units 25 provided in one photoelectric conversion region 22. The present technology can also be applied to a solid-state imaging device 1G that includes such a phase difference pixel.

[0168] 22A and 22B , the photoelectric conversion region 22 of the seventh embodiment includes a transfer transistor TR for each photoelectric conversion unit 25. That is, the photoelectric conversion region 22 of the seventh embodiment includes two transfer transistors TR corresponding to two photoelectric conversion units 25.

[0169] The body portion 54b of the gate electrode 54 included in the transfer transistor TR of the seventh embodiment has a first electrode portion 54b extending from the first surface portion S1 side of the semiconductor layer 21 toward the second surface portion S2 side, similar to the gate electrode 54 of the first embodiment described above. １ and the first electrode portion 54b is spaced apart from the first surface portion S1 of the semiconductor layer 21. １ and the outer shape in plan view is the first electrode portion 54b １ The second electrode portion 54b is expanded more than the ２ and a stepped shape including the above.

[0170] The solid-state imaging device 1G according to the seventh embodiment also provides the same effects as the solid-state imaging device 1A according to the first embodiment described above.

[0171] [Eighth Embodiment] In this eighth embodiment, an example in which the present technology is applied to a two-stage stacked solid-state imaging device in which two semiconductor layers are stacked in two stages will be described, as a stacked-type photodetector device in which semiconductor layers are stacked in multiple stages. Fig. 23 is a longitudinal sectional view schematically showing an example of a configuration of a solid-state imaging device according to the eighth embodiment of the present technology.

[0172] As shown in Fig. 23 , a solid-state imaging device 1H according to an eighth embodiment of the present technology has basically the same configuration as the solid-state imaging device 1A according to the first embodiment described above, but differs in the following configuration. That is, as shown in Fig. 23 , the solid-state imaging device 1H according to the eighth embodiment further includes a semiconductor layer 81 provided on the first surface portion S1 side of the semiconductor layer 21 with an insulating layer 71 interposed therebetween, and an insulating layer 91 provided on the side of the semiconductor layer 81 opposite the insulating layer 71 side. In addition, in the solid-state imaging device 1H according to the eighth embodiment, a pixel transistor Q included in the pixel circuit 16 (see Fig. 3 ) is provided in the semiconductor layer 81. In Fig. 23 , an amplification transistor AMP is illustrated as an example of the pixel transistor Q.

[0173] In the eighth embodiment, the semiconductor layer 21 corresponds to a specific example of a "first semiconductor layer" in the present technology, and the semiconductor layer 81 corresponds to a specific example of a "second semiconductor layer" in the present technology.

[0174] Furthermore, as shown in FIG. 23, the solid-state imaging device 1H according to the eighth embodiment further includes a conductive path 95 that electrically connects the floating diffusion region FD provided in the semiconductor layer 21 and the amplification transistor AMP provided in the semiconductor layer 81.

[0175] The conductive path 95 includes a through contact electrode 92 that extends from the insulating layer 91 to the floating diffusion region FD in the stacking direction (Z direction) of the semiconductor layer 21 and the semiconductor layer 81 and is connected to the floating diffusion region FD, a contact electrode 93 that is embedded in the insulating layer 91 and is connected to the gate electrode 55 of the amplification transistor AMP, and a wiring 94 that is provided on the side of the insulating layer 91 opposite the semiconductor layer 81 side and is electrically and mechanically connected to each of the through contact electrode 92 and the contact electrode 93.

[0176] The wiring 94 may be formed of, for example, a metal film such as aluminum (Al) or copper (Cu), or an alloy film mainly containing Al or Cu. The insulating layer 91 may be formed of, for example, a silicon oxide film. The insulating layer 71 includes, for example, two insulating films 72 and 75. These insulating films 72 and 75 may be formed of, for example, silicon oxide films. The semiconductor layer 81 may be formed of, for example, a Si substrate, a SiGe substrate, or an InGaAs substrate. In the eighth embodiment, the semiconductor layer 21 is formed of, for example, a p-type semiconductor substrate made of single crystal silicon, although this is not limited thereto. The through contact electrode 92 is electrically isolated from the semiconductor layer 81. The through contact electrode 92 and the contact electrode 93 may be formed of, for example, a high-melting-point metal film such as titanium (Ti) or tungsten (W).

[0177] The solid-state imaging device 1H according to the eighth embodiment also provides the same effects as those of the solid-state imaging device 1A according to the first embodiment described above. That is, the present technology can also be applied to a two-stage stacked solid-state imaging device 1H in which two semiconductor layers 21 and 81 are stacked in two stages.

[0178] Although not shown, the present technology can also be applied to a multi-layer stacked solid-state imaging device in which three or more semiconductor layers are stacked in multiple stages.

[0179] Ninth Embodiment In this ninth embodiment, a photoelectric conversion region 22 having a flat isolation structure will be described. Fig. 24 is a plan view schematically showing a configuration example of a pixel in a solid-state imaging device according to a ninth embodiment of the present technology. Fig. 25 is a longitudinal sectional view schematically showing a longitudinal sectional structure taken along the a24-a24 cutting line in Fig. 24. Fig. 26 is a perspective view schematically showing a schematic configuration of a gate electrode included in the transfer transistor in Fig. 24.

[0180] As shown in Figures 24 and 25, the solid-state imaging device 1I of the ninth embodiment of the present technology is basically configured in the same manner as the solid-state imaging device 1A of the first embodiment described above, and differs mainly in the configuration of the inter-pixel isolation region 31 and the photoelectric conversion region 22, and the arrangement of the pixel transistors Q.

[0181] As shown in Figure 25, the inter-pixel isolation region 31 of this ninth embodiment extends from the second surface portion S2 side of the semiconductor layer 21 toward the first surface portion S1 side, and terminates halfway through the semiconductor layer 21, away from the first surface portion S1.

[0182] 25, the photoelectric conversion region 22 of the ninth embodiment is selectively partitioned by the inter-pixel isolation region 31 on the second surface portion S2 side of the semiconductor layer 21, but is not partitioned by the inter-pixel isolation region 31 on the first surface portion S1 side of the semiconductor layer 21. The photoelectric conversion region 22 of the ninth embodiment does not include the inter-element isolation region 41 of the STI structure shown in FIG. 6 of the first embodiment.

[0183] 24, of the pixel transistors Q (AMP, SEL, RST, FDG) included in the pixel circuit 16 (see FIG. 3), the amplification transistor AMP, the selection transistor SEL, and the reset transistor RST are each arranged on the boundary line of the pixel 3 so as to surround the photoelectric conversion region 22 in a plan view. The remaining switching transistor FDG, together with the transfer transistor TR, is provided in the center of the photoelectric conversion region 22 away from the boundary line of the pixel 3 in a plan view.

[0184] 24 and 25 , the pixel transistors Q (AMP, SEL, RST, FDG) included in the pixel circuit 16 are provided in the surface layer portion of the first surface portion S1 of the photoelectric conversion region 22, as in the first embodiment described above. Each of the main electrode regions 56 a and 56 b of these pixel transistors Q is provided in a p-type well region 23, and adjacent pixel transistors Q are insulated and isolated by this p-type well region 23. That is, the photoelectric conversion region 22 of this ninth embodiment has a flat isolation structure in which adjacent pixel transistors Q are isolated by a p-type semiconductor region.

[0185] As shown in FIG. 24, the amplifier transistor AMP and the select transistor SEL share one main electrode region 56a of the pair of main electrode regions 56a and 56b of the amplifier transistor AMP and the other main electrode region 56b of the pair of main electrode regions 56a and 56b of the select transistor SEL, and are connected in series.

[0186] 24 and 25, the n-type floating diffusion region FD in the ninth embodiment also serves as one of the pair of main electrode regions 56a and 56b of the switching transistor FDG, 56. In the ninth embodiment, the n-type semiconductor region 56t shown in FIG.

[0187] As shown in FIG. 25, the transfer transistor TR of the ninth embodiment has basically the same configuration as the transfer transistor TR shown in FIGS. 11A to 11C of the above-described modified example 1-1, except for the configuration of the gate electrode 54.

[0188] That is, as shown in FIGS. 24 to 26, the gate electrode 54 of the transfer transistor TR of the ninth embodiment has a first electrode portion 54b of a body portion 54b. １ The second electrode portion 54b of the body 54b is formed in a rectangular column shape. ２ The gate electrode 54 has a body 54b that extends across the n-type well region 23 and the n-type semiconductor region 24 in the thickness direction (Z direction) of the photoelectric conversion region 22. ２ is provided in the n-type semiconductor region 24. Therefore, in the gate electrode 54 of the transfer transistor TR of the ninth embodiment, the first electrode portion 54b extending from the first surface portion S1 side of the semiconductor layer 21 toward the second surface portion S2 side is also provided. １ and the first electrode portion 54b is spaced apart from the first surface portion S1 of the semiconductor layer 21. ２ and the outer shape in plan view is the first electrode portion 54b １ The second electrode portion 54b is expanded ２ Includes:

[0189] The head 54a included in the gate electrode 54 of the transfer transistor TR of the ninth embodiment is configured, for example, in the shape of a rectangular parallelepiped having a longitudinal direction. １ The second electrode portion 54b of the body 54b is formed in a cylindrical shape. ２ The plane shape is rectangular.

[0190] The solid-state imaging device 1I according to the ninth embodiment also provides the same effects as the solid-state imaging device 1A according to the first embodiment described above.

[0191] 25 illustrates the light-shielding film 62. The light-shielding film 62 has a grid-like planar pattern in plan view so as to separate the adjacent pixels 3. ３ " denotes a signal charge transfer path in the photoelectric conversion region 22.

[0192] <Modification of Ninth Embodiment> Next, a modification of the gate electrode 54 of the transfer transistor TR will be described.

[0193] 27 is a perspective view schematically illustrating a gate electrode of a transfer transistor according to Modification 9-1 of the ninth embodiment of the present disclosure. As shown in FIG. 27, Modification 9-1 has a first electrode portion 54b １ Of the two surface portions located opposite to each other in the extension direction (Z direction) of the solid-state imaging device 11, the surface portion opposite to the head portion 54a has a convex shape. In this modification 9-1, the same effects as those of the solid-state imaging device 1I of the ninth embodiment described above can be obtained.

[0194] <Modification 9-2> FIG. 28 is a perspective view schematically showing a gate electrode of a transfer transistor according to Modification 9-2 of the ninth embodiment of the present technology.

[0195] As shown in FIG. 28, this modification 9-2 has a first electrode portion 54b １ The second electrode portion 54b is located midway in the extension direction of the ２ and the first electrode portion 54b １ In the extension direction (Z direction) of the second electrode portion 54b ２ The first electrode portions 54b are provided on the two opposite surfaces of the１ The second electrode portion 54b ２ The surface portion on the opposite side to the head portion 54a has a convex shape. In this modified example 9-2, the same effects as those of the solid-state imaging device 1I of the ninth embodiment described above can be obtained.

[0196] [Tenth embodiment] Fig. 29 is a plan view schematically showing a configuration example of a pixel in a solid-state imaging device according to a tenth embodiment of the present technology. Fig. 30 is a longitudinal sectional view schematically showing a longitudinal sectional structure taken along the a29-a29 cutting line in Fig. 29. Fig. 31A is a plan view schematically showing a schematic configuration of a gate electrode of a transfer transistor shown in Fig. 29. Fig. 31B is a plan view in which the top of the gate electrode shown in Fig. 31A is omitted. Fig. 32 is a plan view of a signal charge transfer path R in Fig. 30. ３ 1 is a diagram illustrating an example of a potential in FIG.

[0197] A solid-state imaging device 10J according to the tenth embodiment of the present technology has basically the same configuration as the solid-state imaging device 1I according to the ninth embodiment described above, but differs in the configuration of the gate electrode 54 of the transfer transistor TR.

[0198] That is, as shown in FIGS. 29 and 30, the gate electrode 54 of the transfer transistor TR according to the tenth embodiment has the structure of the gate electrode 54 shown in FIGS. 24 and 25 of the ninth embodiment, and in addition, a charge passage portion 66 through which signal charges pass from the second surface portion S2 side of the semiconductor layer 21 to the n-type floating diffusion region FD side is formed in the second electrode portion 54b. ２ We are preparing for this.

[0199] As shown in FIGS. 29 to 31B, the charge passage portion 66 of the tenth embodiment has a second electrode portion 54b in the thickness direction (Z direction) of the semiconductor layer 21. ２ and a second electrode portion 54b ２ The through-hole 67 is formed at a distance from the edge of the first electrode portion 54b in a plan view. １ The gate electrode 11 is provided on the floating diffusion region FD side of the gate electrode 11 and has an elongated hole shape extending along the X direction in a plan view.

[0200] The gate electrode 54 of the transfer transistor TR according to the tenth embodiment has a charge passage 66 (through hole 67) through which signal charges pass from the second surface S2 side of the semiconductor layer 21 to the n-type floating diffusion region FD side, and the second electrode portion 54b ２ Therefore, the signal charges photoelectrically converted in the n-type semiconductor region 24 of the photoelectric conversion unit 25 move to the n-type floating diffusion region FD through the charge passage portion 66 of the gate electrode 54. Therefore, according to the solid-state imaging device 1J according to the tenth embodiment, the signal charge transfer capability for transferring the signal charges photoelectrically converted in the photoelectric conversion unit 25 to the floating diffusion region FD can be further improved compared to the modification 1-1 shown in FIG. 11A described above.

[0201] 33A is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure of a photoelectric conversion region according to a conventional reference example. ４ 33A is a diagram showing an example of the potential at 54z. In addition, in Fig. 33A, the same reference numerals as in Fig. 30 are used for the components other than the gate electrode 54z.

[0202] As shown in FIG. 33A, in the case of the gate electrode 54z of the conventional transfer transistor TR, the body portion 54z adjacent to the semiconductor layer 21 via the gate insulating film 52 ２ Therefore, as shown in FIG. 33B, the surface area of ​​the body 54z is small and the modulation power is low. ２ (the second surface S2 side of the semiconductor layer 21) from the tip of the signal charge transfer path R ４ This can easily create barriers to the potential of the project.

[0203] 30, in the case of the transfer transistor TR according to the tenth embodiment, the surface area of ​​the body portion 54b adjacent to the semiconductor layer 21 via the gate insulating film 52 is large, and the modulation power is high. Therefore, as shown in FIG. ３ There is no barrier in the potential, and the potential is smoother compared to FIG. 33B.

[0204] As can be seen from FIGS. 32 and 33B, the potential of the tenth embodiment shown in FIG. 32 is smoother than the conventional potential shown in FIG. 33B, and it is clear that application of this technology is useful.

[0205] 32 and 33B are data when the transfer transistor TR is in the "ON" state. The potential shown in FIG. 32 and the potential shown in FIG. 33B are data when the first electrode portion 54b of the body portion 54b shown in FIG. １ The thickness (external size in a plan view) of the body 54z shown in FIG. ２ This is the case where the thickness (external size in plan view) of the wiring is the same as the design value.

[0206] <<Modification of Tenth Embodiment>> Next, a modification of the gate electrode 54 of the transfer transistor TR will be described.

[0207] <Modification 10-1> FIG. 34 is a plan view schematically showing a gate electrode of a transfer transistor according to Modification 10-1 of the tenth embodiment of the present technology.

[0208] As shown in FIG. 34, in this modification 10-1, two through holes 67 are formed as charge passages 66 in the second electrode portion 54b of the body 54b of the gate electrode 54. ２ The two through holes 67 extend in the X direction in a plan view and are connected to the first electrode portion 54b. １ The first electrode portions 54b are spaced apart from each other in the Y direction. １ The second electrode portion 54b has a cylindrical shape. ２ The first electrode portion 54b has a rectangular planar shape. １ is the second electrode portion 54b in plan view. ２ In this modification 10-1, the same effects as those of the solid-state imaging device 1J according to the tenth embodiment can be obtained.

[0209] In the case of this modified example 10-5, at least one of the two through holes 67 is located in the first electrode portion 54b in plan view. １ It is preferable to provide the transistor on the floating diffusion region FD side.

[0210] <Modification 10-2> FIG. 35 is a plan view schematically showing a gate electrode of a transfer transistor according to Modification 10-2 of the tenth embodiment of the present technology.

[0211] As shown in FIG. 35, in this modification 10-2, two through holes 67 are formed as charge passages 66 in the second electrode portion 54b of the body 54b of the gate electrode 54. ２ The two through holes 67 extend in the Y direction in a plan view and are connected to the first electrode portion 54b. １ The first electrode portions 54b are spaced apart from each other in the X direction. １ The second electrode portion 54b has a cylindrical shape. ２ The first electrode portion 54b1 has a rectangular planar shape. ２ It is connected to the center of the

[0212] This modification 10-2 also provides the same effects as the solid-state imaging device 1J according to the above-described tenth embodiment.

[0213] <Modification 10-3> FIG. 36 is a plan view schematically showing a gate electrode of a transfer transistor according to Modification 10-3 of the tenth embodiment of the present technology.

[0214] As shown in FIG. 34, in this modification 10-1, two slits 68 are formed as charge passages 66 between the second electrode portion 54b of the body 54b of the gate electrode 54. ２ Each of the two slits 68 is formed in the second electrode portion 54b in a plan view. ２ The two slits 68 extend inward (inward) from the edge of the second electrode portion 54b with a predetermined width. ２ and extends in the Y direction from the edge of the first electrode portion 54b. １ The first electrode portions 54b are spaced apart from each other in the Y direction. １ The second electrode portion 54b has a cylindrical shape. ２ The first electrode portion 54b has a rectangular planar shape. １ is the second electrode portion 54b in plan view. ２ It is connected to the center of the

[0215] This modification 10-3 also provides the same effects as the solid-state imaging device 1J according to the above-described tenth embodiment.

[0216] <Modification 10-4> FIG. 37 is a plan view schematically showing a gate electrode of a transfer transistor according to Modification 10-4 of the tenth embodiment of the present technology.

[0217] As shown in FIG. 37, in this modification 10-4, one slit 68 is provided as a charge passage 66 between the second electrode portion 54b of the body 54b of the gate electrode 54. ２ The first electrode portion 54b is configured to be １ The second electrode portion 54b has a cylindrical shape. ２ The first electrode portion 54b has a rectangular planar shape. １ is the second electrode portion 54b in plan view. ２ The slit 68 is connected to a position that is off the center of the second electrode portion 54b in the Y direction. ２ From the edge of the first electrode portion 54b １ In the case of this modified example 10-4, the slit 68 extends toward the first electrode portion 54b in a plan view. １ It is preferable to provide the transistor on the floating diffusion region FD side.

[0218] This modification 10-4 also provides the same effects as the solid-state imaging device 1J according to the above-described tenth embodiment.

[0219] <Modification 10-5> FIG. 38 is a plan view schematically showing a gate electrode of a transfer transistor according to Modification 10-5 of the tenth embodiment of the present technology.

[0220] As shown in FIG. 38, in this modification 10-5, one through-hole 67 is formed as a charge passage 66 in the second electrode portion 54b of the body 54b of the gate electrode 54. ２ The first electrode portion 54b is configured to be １ The second electrode portion 54b has a cylindrical shape. ２ The first electrode portion 54b has a circular planar shape. １ is the second electrode portion 54b in plan view. ２The through-hole 67 extends in the X direction and is connected to the center of the first electrode portion 54b in the Y direction. １ and the second electrode portion 54b ２ In the case of this modified example 10-5, the through-hole 67 is provided between the edge of the first electrode portion 54b in plan view. １ It is preferable to provide the transistor on the floating diffusion region FD side.

[0221] This modification 10-5 also provides the same effects as the solid-state imaging device 1J according to the above-described tenth embodiment.

[0222] <Modification 10-6> FIG. 39 is a plan view schematically showing a gate electrode of a transfer transistor according to Modification 10-6 of the tenth embodiment of the present technology.

[0223] As shown in FIG. 39, in this modification 10-6, one through-hole 67 is formed as a charge passage 66 in the second electrode portion 54b of the body 54b of the gate electrode 54. ２ The first electrode portion 54b is configured to be １ The second electrode portion 54b has a cylindrical shape. ２ The through-hole 67 has a circular planar shape. ２ The first electrode portion 54b is provided at the center of the first electrode portion 54b. １ The two first electrode portions 54b are provided. １ is the second electrode portion 54b ２ In this modified example 10-6, the first electrode portion, the through-hole, and the first electrode portion are arranged in this order in the X direction.

[0224] This modification 10-6 also provides the same effects as the solid-state imaging device 1J according to the above-described tenth embodiment.

[0225] <Modification 10-7> FIG. 40 is a plan view schematically showing a gate electrode of a transfer transistor according to Modification 10-7 of the tenth embodiment of the present technology.

[0226] As shown in FIG. 40, in this modification 10-7, one through-hole 67 is formed as a charge passage 66 in the second electrode portion 54b of the body 54b of the gate electrode 54.２ The first electrode portion 54b is configured to be １ The second electrode portion 54b has a rectangular column shape. ２ The through-hole 67 has a rectangular planar shape. ２ The first electrode portion 54b is provided at the center of the first electrode portion 54b. １ The two first electrode portions 54b are provided. １ is the second electrode portion 54b ２ The second electrode portion 54b is located at a position away from the center of the ２ In this modified example 10-7, the first electrode portion 54b is connected to the first electrode portion 54b in the X direction. １ , the through-hole 67 and the first electrode portion 54b １ are arranged in this order.

[0227] This modification 10-7 also provides the same effects as the solid-state imaging device 1J according to the above-described tenth embodiment.

[0228] Eleventh Embodiment Application Example to Electronic Devices The present technology (technology according to the present disclosure) can be applied to various electronic devices, such as imaging devices such as digital still cameras and digital video cameras, mobile phones with imaging functions, and other devices with imaging functions. Fig. 41 is a block diagram showing a configuration example of an imaging device installed in an electronic device.

[0229] As shown in FIG. 41, electronic device 101 includes an optical system 102, a photodetector 103, and a DSP (Digital Signal Processor) 104, and is configured by connecting DSP 104, a display device 105, an operation system 106, a memory 108, a recording device 109, and a power supply system 110 via a bus 107, and is capable of capturing still images and moving images.

[0230] The optical system 102 is configured to have one or more lenses, and guides image light (incident light) from a subject to the photodetector 103 , forming an image on the light-receiving surface (sensor portion) of the photodetector 103 .

[0231] The solid-state imaging devices 1A to 1J having any of the configuration examples described above, and a solid-state imaging device 1K described below, are used as the photodetector 103. Electrons are accumulated in the photodetector 103 for a certain period of time in accordance with an image formed on the light-receiving surface via the optical system 102. A signal corresponding to the electrons accumulated in the photodetector 103 is then supplied to the DSP 104.

[0232] The DSP 104 performs various signal processing on the signal from the photodetector 103 to acquire an image, and temporarily stores the image data in the memory 108. The image data stored in the memory 108 is recorded in the recording device 109 or supplied to the display device 105 to display the image. In addition, the operation system 106 accepts various operations by the user and supplies operation signals to each block of the electronic device 101, and the power supply system 110 supplies the power necessary to drive each block of the electronic device 101.

[0233] With this configuration, the signal charge transfer capability of the transfer transistor TR in the photodetector 103 is improved, and therefore the image quality performance of the electronic device 101 of the eleventh embodiment can be improved.

[0234] Twelfth Embodiment Application Examples to Electronic Devices The present technology (technology related to the present disclosure) can be applied to various electronic devices, such as imaging devices such as digital still cameras and digital video cameras, mobile phones with imaging functions, or other devices with imaging functions.

[0235] FIG. 42 is a diagram showing a schematic configuration of an electronic device (for example, a camera) according to an eleventh embodiment of the present technology.

[0236] 42, the electronic device 200 includes a solid-state imaging device 201, an optical lens 202, a shutter device 203, a drive circuit 204, and a signal processing circuit 205. The electronic device 200 illustrates an embodiment in which the solid-state imaging devices 1A to 1J according to the first to tenth embodiments and the fifteenth embodiment of the present technology are used as the solid-state imaging device 201 in an electronic device (for example, a camera).

[0237] The optical lens 202 focuses image light (incident light 206) from the subject on the imaging surface of the solid-state imaging device 201. This causes signal charges to accumulate in the solid-state imaging device 201 for a certain period of time. The shutter device 203 controls the light irradiation period and light blocking period for the solid-state imaging device 201. The drive circuit 204 supplies drive signals that control the transfer operation of the solid-state imaging device 201 and the shutter operation of the shutter device 203. The drive signals (timing signals) supplied from the drive circuit 204 cause charge transfer in the solid-state imaging device 201. The signal processing circuit 205 performs various signal processing on signals (pixel signals (image signals)) output from the solid-state imaging device 201. The processed video signals are stored in a storage medium such as a memory or output to a monitor.

[0238] With this configuration, the signal charge transfer capability of the transfer transistor TR in the solid-state imaging device 201 is improved, and therefore the image quality performance of the electronic device 200 of the twelfth embodiment can be improved.

[0239] The electronic device 200 to which the solid-state imaging device of the above-described embodiment can be applied is not limited to a camera, but can also be applied to other electronic devices. For example, the solid-state imaging device may be applied to an imaging device such as a camera module for a mobile device such as a mobile phone or a tablet terminal.

[0240] Furthermore, the present technology can be applied to not only the solid-state imaging device as the image sensor described above, but also to photodetection devices in general, including distance measurement sensors called ToF (Time of Flight) sensors that measure distance. A distance measurement sensor emits light toward an object, detects the light reflected from the surface of the object, and calculates the distance to the object based on the time of flight between when the light is emitted and when the reflected light is received. The pixel transistor described above can also be used in this distance measurement sensor.

[0241] Thirteenth Embodiment Application Example to a Moving Body The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of moving body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0242] FIG. 43 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology of the present disclosure can be applied.

[0243] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 12, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (interface) 12053.

[0244] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0245] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0246] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.

[0247] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0248] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0249] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the distance between vehicles, maintaining vehicle speed, vehicle collision warning, vehicle lane departure warning, etc.

[0250] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0251] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.

[0252] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying the passengers of the vehicle or the outside of the vehicle of information. In the example of Fig. 43, the output devices are exemplified by an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0253] Fig. 44 is a diagram showing an example of the installation position of the image capturing unit 12031. In Fig. 44, the vehicle 12100 has image capturing units 12101, 12102, 12103, 12104, and 12105 as the image capturing unit 12031.

[0254] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The forward images acquired by the imaging units 12101 and 12105 are mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0255] 44 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.

[0256] At least one of the image capturing units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image capturing units 12101 to 12104 may be a stereo camera made up of multiple image capturing elements, or may be an image capturing element having pixels for phase difference detection.

[0257] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100), thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of autonomous driving, which runs autonomously without relying on driver operation.

[0258] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines a collision risk that indicates the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0259] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian is present in the images captured by the image capturing units 12101 to 12104. Such pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104 as infrared cameras and performing pattern matching on a series of feature points that indicate the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0260] The foregoing has described an example of a vehicle control system to which the technology according to the present disclosure can be applied. The technology according to the present disclosure can be applied to, for example, the above-described multiple electronic control units and imaging unit 12031 among the above-described configurations. Specifically, the solid-state imaging devices according to the first to tenth embodiments and the solid-state imaging device according to the fifteenth embodiment described below can be applied to the above-described multiple electronic control units and imaging unit 12031. By applying the technology according to the present disclosure to the electronic control unit and imaging unit 12031, the signal charge transfer capability of the transfer transistor TR can be improved, thereby improving the reliability of the electronic control unit and imaging unit 12031.

[0261] Fourteenth Embodiment Application Example to an Endoscopic Surgery System The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be applied to an endoscopic surgery system.

[0262] FIG. 45 is a diagram showing an example of a schematic configuration of an endoscopic surgery system to which the technology according to the present disclosure (the present technology) can be applied.

[0263] Figure 45 shows an operator (doctor) 11131 performing surgery on a patient 11132 on a patient bed 11133 using an endoscopic surgery system 11000. As shown in the figure, the endoscopic surgery system 11000 is composed of an endoscope 11100, other surgical tools 11110 such as an insufflation tube 11111 and an energy treatment tool 11112, a support arm device 11120 that supports the endoscope 11100, and a cart 11200 on which various devices for endoscopic surgery are mounted.

[0264] The endoscope 11100 is composed of a lens barrel 11101, a region of a predetermined length from the tip of which is inserted into a body cavity of a patient 11132, and a camera head 11102 connected to the base end of the lens barrel 11101. In the example shown, the endoscope 11100 is configured as a so-called rigid scope having a rigid lens barrel 11101, but the endoscope 11100 may also be configured as a so-called flexible scope having a flexible lens barrel.

[0265] An opening into which an objective lens is fitted is provided at the tip of the lens barrel 11101. A light source device 11203 is connected to the endoscope 11100, and light generated by the light source device 11203 is guided to the tip of the lens barrel by a light guide extending inside the lens barrel 11101, and is irradiated via the objective lens toward an object to be observed inside the body cavity of the patient 11132. The endoscope 11100 may be a direct-viewing endoscope, an oblique-viewing endoscope, or a side-viewing endoscope.

[0266] An optical system and an image sensor are provided inside the camera head 11102, and light reflected from an object to be observed (observation light) is collected by the optical system onto the image sensor. The observation light is photoelectrically converted by the image sensor to generate an electrical signal corresponding to the observation light, i.e., an image signal corresponding to the observed image. The image signal is sent to a camera control unit (CCU) 11201 as RAW data.

[0267] The CCU 11201 is configured with a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), etc., and comprehensively controls the operations of the endoscope 11100 and the display device 11202. Furthermore, the CCU 11201 receives an image signal from the camera head 11102 and performs various types of image processing on the image signal, such as development processing (demosaic processing), to display an image based on the image signal.

[0268] Under the control of the CCU 11201, the display device 11202 displays an image based on an image signal that has been subjected to image processing by the CCU 11201.

[0269] The light source device 11203 is composed of a light source such as an LED (Light Emitting Diode), and supplies irradiation light to the endoscope 11100 when photographing the surgical area, etc.

[0270] The input device 11204 is an input interface for the endoscopic surgery system 11000. A user can input various information and instructions to the endoscopic surgery system 11000 via the input device 11204. For example, the user inputs an instruction to change the imaging conditions (type of irradiation light, magnification, focal length, etc.) of the endoscope 11100.

[0271] The treatment tool control device 11205 controls the driving of the energy treatment tool 11112 for cauterizing tissue, incising, sealing blood vessels, etc. The insufflation device 11206 inflates the body cavity of the patient 11132 through the insufflation tube 11111 in order to ensure a clear field of view for the endoscope 11100 and a working space for the surgeon. The recorder 11207 is a device capable of recording various types of information related to the surgery. The printer 11208 is a device capable of printing various types of information related to the surgery in various formats such as text, images, or graphs.

[0272] The light source device 11203, which supplies illumination light to the endoscope 11100 when photographing the surgical site, can be configured from a white light source, such as an LED, a laser light source, or a combination of these. When the white light source is configured from a combination of RGB laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high precision, allowing the light source device 11203 to adjust the white balance of the captured image. In this case, it is also possible to time-share images corresponding to each RGB by irradiating the object of observation with laser light from each RGB laser light source and controlling the drive of the image sensor of the camera head 11102 in synchronization with the irradiation timing. According to this method, color images can be obtained without providing a color filter to the image sensor.

[0273] Furthermore, the light source device 11203 may be controlled to change the intensity of light it outputs at predetermined time intervals. By controlling the driving of the image sensor of the camera head 11102 in synchronization with the timing of the change in light intensity to acquire images in a time-division manner and combining the images, it is possible to generate an image with a high dynamic range that is free from so-called blocked-up shadows and blown-out highlights.

[0274] The light source device 11203 may also be configured to supply light in a predetermined wavelength band corresponding to special light observation. Special light observation, for example, utilizes the wavelength dependence of light absorption in body tissues to irradiate light with a narrower band than the light irradiated during normal observation (i.e., white light), thereby capturing high-contrast images of specific tissues, such as blood vessels on the surface of mucous membranes, known as narrow-band imaging. Alternatively, special light observation may involve fluorescence observation, in which images are obtained using fluorescence generated by irradiating excitation light. Fluorescence observation may involve irradiating excitation light onto body tissues and observing the fluorescence from the tissue (autofluorescence observation), or by locally injecting a reagent such as indocyanine green (ICG) into the body tissue and irradiating the tissue with excitation light corresponding to the fluorescent wavelength of the reagent to obtain a fluorescent image. The light source device 11203 may be configured to supply narrow-band light and / or excitation light corresponding to such special light observation.

[0275] FIG. 46 is a block diagram showing an example of the functional configuration of the camera head 11102 and the CCU 11201 shown in FIG.

[0276] The camera head 11102 has a lens unit 11401, an imaging unit 11402, a drive unit 11403, a communication unit 11404, and a camera head control unit 11405. The CCU 11201 has a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera head 11102 and the CCU 11201 are connected to each other via a transmission cable 11400 so that they can communicate with each other.

[0277] The lens unit 11401 is an optical system provided at the connection portion with the lens barrel 11101. Observation light taken in from the tip of the lens barrel 11101 is guided to the camera head 11102 and enters the lens unit 11401. The lens unit 11401 is composed of a combination of multiple lenses including a zoom lens and a focus lens.

[0278] The imaging unit 11402 is composed of an imaging element. The imaging element constituting the imaging unit 11402 may be a single (so-called single-chip type) or multiple (so-called multi-chip type). When the imaging unit 11402 is composed of a multi-chip type, for example, each imaging element may generate an image signal corresponding to each of RGB, and a color image may be obtained by combining these signals. Alternatively, the imaging unit 11402 may be configured to have a pair of imaging elements for acquiring image signals for the right eye and the left eye corresponding to 3D (dimensional) display. The 3D display allows the surgeon 11131 to more accurately grasp the depth of the biological tissue at the surgical site. Note that when the imaging unit 11402 is composed of a multi-chip type, multiple lens units 11401 may be provided corresponding to each imaging element.

[0279] Furthermore, the imaging unit 11402 does not necessarily have to be provided in the camera head 11102. For example, the imaging unit 11402 may be provided inside the lens barrel 11101, immediately after the objective lens.

[0280] The driving unit 11403 is configured by an actuator, and moves the zoom lens and focus lens of the lens unit 11401 by a predetermined distance along the optical axis under the control of the camera head control unit 11405. This allows the magnification and focus of the image captured by the imaging unit 11402 to be adjusted appropriately.

[0281] The communication unit 11404 is configured by a communication device for transmitting and receiving various types of information to and from the CCU 11201. The communication unit 11404 transmits the image signal obtained from the imaging unit 11402 to the CCU 11201 via the transmission cable 11400 as RAW data.

[0282] Furthermore, the communication unit 11404 receives a control signal for controlling the driving of the camera head 11102 from the CCU 11201 and supplies the control signal to the camera head control unit 11405. The control signal includes information on the imaging conditions, such as information specifying the frame rate of the captured image, information specifying the exposure value at the time of imaging, and / or information specifying the magnification and focus of the captured image.

[0283] The image capturing conditions such as the frame rate, exposure value, magnification, and focus may be appropriately specified by the user, or may be automatically set by the control unit 11413 of the CCU 11201 based on the acquired image signal. In the latter case, the endoscope 11100 is equipped with a so-called AE (Auto Exposure) function, AF (Auto Focus) function, and AWB (Auto White Balance) function.

[0284] The camera head control unit 11405 controls the driving of the camera head 11102 based on a control signal received from the CCU 11201 via the communication unit 11404 .

[0285] The communication unit 11411 is configured by a communication device for transmitting and receiving various information to and from the camera head 11102. The communication unit 11411 receives an image signal transmitted from the camera head 11102 via the transmission cable 11400.

[0286] Furthermore, the communication unit 11411 transmits to the camera head 11102 a control signal for controlling the driving of the camera head 11102. The image signal and the control signal can be transmitted by electrical communication, optical communication, or the like.

[0287] The image processing unit 11412 performs various image processing operations on the image signal, which is RAW data transmitted from the camera head 11102 .

[0288] The control unit 11413 performs various controls related to the imaging of the surgical site, etc. by the endoscope 11100 and the display of the captured image obtained by imaging the surgical site, etc. For example, the control unit 11413 generates a control signal for controlling the driving of the camera head 11102.

[0289] Furthermore, the control unit 11413 displays the captured image showing the surgical site, etc., on the display device 11202 based on the image signal subjected to image processing by the image processing unit 11412. At this time, the control unit 11413 may recognize various objects in the captured image using various image recognition technologies. For example, the control unit 11413 can recognize surgical tools such as forceps, specific biological parts, bleeding, mist generated when using the energy treatment tool 11112, etc., by detecting the shape and color of the edges of objects included in the captured image. When displaying the captured image on the display device 11202, the control unit 11413 may use the recognition results to superimpose various surgical support information on the image of the surgical site. By superimposing the surgical support information and presenting it to the surgeon 11131, the burden on the surgeon 11131 can be reduced and the surgeon 11131 can proceed with the surgery reliably.

[0290] The transmission cable 11400 connecting the camera head 11102 and the CCU 11201 is an electrical signal cable for electrical signal communication, an optical fiber for optical communication, or a composite cable of these.

[0291] In the illustrated example, communication is performed wired using a transmission cable 11400, but communication between the camera head 11102 and the CCU 11201 may also be performed wirelessly.

[0292] The foregoing has described an example of an endoscopic surgery system to which the technology according to the present disclosure can be applied. Of the above-described configurations, the technology according to the present disclosure can be applied to, for example, the CCU 11201 and the imaging unit 11402 of the camera head 11102. Specifically, the solid-state imaging devices according to the first to tenth embodiments described above and the solid-state imaging device according to the fifteenth embodiment described below can be applied to the CCU 11201 and the imaging unit 10402. By applying the technology according to the present disclosure to the CCU 11201 and the imaging unit 10402, the reliability of the CCU 11201 and the imaging unit 10402 can be improved.

[0293] Although an endoscopic surgery system has been described as an example here, the technology disclosed herein may also be applied to other systems, such as a microsurgery system.

[0294] Fifteenth Embodiment In this fifteenth embodiment, an example in which the present technology is applied to a three-layer stacked solid-state imaging device in which three substrates including semiconductor layers are stacked in three layers will be described as a stacked-type photodetector in which semiconductor layers are stacked in multiple layers. FIG. 47 is an exploded perspective view schematically showing a configuration example of a solid-state imaging device according to a fifteenth embodiment of the present technology. FIG. 48 is an equivalent circuit diagram showing a configuration example of pixels and pixel circuits in a solid-state imaging device according to the fifteenth embodiment of the present technology. As shown in FIG. 47 , a solid-state imaging device 1K according to the fifteenth embodiment of the present technology includes three substrates (a first substrate (first substrate) 310, a second substrate (second substrate) 320, and a third substrate (third substrate) 330). This solid-state imaging device 1K has a three-dimensional structure in which three substrates (the first substrate 310, the second substrate 320, and the third substrate 330) are stacked. The first base 310, the second base 320, and the third base 330 are stacked in this order.

[0295] The first base 310 has a semiconductor layer 311 including a plurality of sensor pixels 312 that perform photoelectric conversion. The semiconductor layer 311 corresponds to a specific example of a "first semiconductor layer" of the present technology (technology related to the present disclosure). The plurality of sensor pixels 312 are arranged in a matrix within a pixel region 313 of the first base 310. The second base 320 has a semiconductor layer 321 including pixel circuits (readout circuits) 322 for every four sensor pixels 312, the pixel circuits outputting pixel signals based on charges output from the sensor pixels 312. The semiconductor layer 321 corresponds to a specific example of a "second semiconductor layer" of the present technology. The second base 320 has a plurality of pixel drive lines 323 extending in the row direction and a plurality of vertical signal lines 324 extending in the column direction. The third base 330 has a semiconductor layer 331 including a logic circuit 332 that processes pixel signals. The logic circuit 332 includes, for example, a vertical drive circuit 333, a column signal processing circuit 334, a horizontal drive circuit 335, and a system control circuit 336. The logic circuit 332 (specifically, the horizontal drive circuit) outputs an output voltage Vout for each sensor pixel 312 to the outside. In the logic circuit 332, for example, a low-resistance region made of silicide formed using a salicide (self-aligned silicide) process such as CoSi2 or NiSi may be formed on the surface of the impurity diffusion region in contact with the source electrode and the drain electrode.

[0296] The vertical drive circuit 333, for example, sequentially selects a plurality of sensor pixels 312 row by row. The column signal processing circuit 334, for example, performs correlated double sampling (CDS) processing on pixel signals output from each sensor pixel 312 in the row selected by the vertical drive circuit 333. The column signal processing circuit 334 extracts the signal level of the pixel signal by performing CDS processing, for example, and stores pixel data corresponding to the amount of light received by each sensor pixel 312. The horizontal drive circuit 335, for example, sequentially outputs the pixel data stored in the column signal processing circuit 334 to the outside. The system control circuit 336, for example, controls the driving of each block (the vertical drive circuit 333, the column signal processing circuit 334, and the horizontal drive circuit 335) in the logic circuit 332. FIG. 48 illustrates an example of a sensor pixel 312 and a pixel circuit 322. 48 , a case will be described in which four sensor pixels 312 share one pixel circuit 322. Here, “sharing” means that the outputs of the four sensor pixels 312 are input to a common pixel circuit 322.

[0297] The sensor pixels 312 have common components. In Fig. 48, in order to distinguish the components of the sensor pixels 312 from one another, an identification number (1, 2, 3, 4) is added to the end of the reference numeral of the component of each sensor pixel 312. Hereinafter, when it is necessary to distinguish the components of each sensor pixel 312 from one another, an identification number is added to the end of the reference numeral of the component of each sensor pixel 312. However, when it is not necessary to distinguish the components of each sensor pixel 312 from one another, the identification number at the end of the reference numeral of the component of each sensor pixel 312 is omitted.

[0298] Each sensor pixel 312 includes, for example, a photodiode PD, a transfer transistor TR electrically connected to the photodiode PD, and a floating diffusion region (FD) serving as a charge storage unit that temporarily stores signal charge output from the photodiode PD via the transfer transistor TR. The photodiode PD corresponds to a specific example of the photoelectric conversion unit 25 shown in the first to eleventh embodiments. The photodiode PD performs photoelectric conversion to generate charge corresponding to the amount of received light. The cathode of the photodiode PD is electrically connected to the source of the transfer transistor TR, and the anode of the photodiode PD is electrically connected to a reference potential line (e.g., ground). The drain of the transfer transistor TR is electrically connected to the floating diffusion region FD, and the gate of the transfer transistor TR is electrically connected to a pixel drive line 323. As in the first embodiment, the logic circuit 322 is configured, for example, with a complementary metal-oxide semiconductor (CMOS) circuit.

[0299] The floating diffusion regions FD of the sensor pixels 312 that share one pixel circuit 322 are electrically connected to each other and to the input terminal of the common pixel circuit 322. The pixel circuit 322 includes, for example, a reset transistor RST, a selection transistor SEL, and an amplification transistor AMP. Note that the selection transistor SEL may be omitted if necessary. The source of the reset transistor RST (the input terminal of the pixel circuit 322) is electrically connected to the floating diffusion region FD, and the drain of the reset transistor RST is electrically connected to the power supply line VDD and the drain of the amplification transistor AMP. The gate of the reset transistor RST is electrically connected to a pixel drive line 323 (see FIG. 47). The source of the amplification transistor AMP is electrically connected to the drain of the selection transistor SEL, and the gate of the amplification transistor AMP is electrically connected to the source of the reset transistor RST. The source of the selection transistor SEL (the output terminal of the pixel circuit 322) is electrically connected to a vertical signal line 324, and the gate of the selection transistor SEL is electrically connected to the pixel drive line 323 (see FIG. 47).

[0300] When the transfer transistor TR is turned on, it transfers the charge of the photodiode PD to the floating diffusion region FD. The reset transistor RST resets the potential of the floating diffusion region FD to a predetermined potential. When the reset transistor RST is turned on, it resets the potential of the floating diffusion region FD to the potential of the power supply line VDD. The selection transistor SEL controls the output timing of the pixel signal from the pixel circuit 322. The amplification transistor AMP generates a pixel signal with a voltage corresponding to the level of the charge stored in the floating diffusion region FD. The amplification transistor AMP forms a source follower amplifier and outputs a pixel signal with a voltage corresponding to the level of the charge generated in the photodiode PD. When the selection transistor SEL is turned on, the amplification transistor AMP amplifies the potential of the floating diffusion FD and outputs a voltage corresponding to the amplified potential to the column signal processing circuit 334 via the vertical signal line 324. The reset transistor RST, the amplification transistor AMP, and the selection transistor SEL are, for example, CMOS transistors.

[0301] 23 of the above-mentioned eighth embodiment, in this fifteenth embodiment as well, the floating diffusion region FD provided in the semiconductor layer 311 of the first base 310 and the gate electrode of the amplification transistor AMP provided in the semiconductor layer 321 of the second base 320 different from the first base 310 are electrically connected via a conductive path 95. The transfer transistor TR of this fifteenth embodiment can be any of the transfer transistors TR described in the above-mentioned embodiments (first to seventh embodiments, ninth to tenth embodiments) and their modified examples.

[0302] Therefore, the solid-state imaging device 1K according to the fifteenth embodiment also provides the same effects as those of the above-described embodiments and their modified examples. That is, the present technology can also be applied to a solid-state imaging device 1K having a three-dimensional structure in which three bases (a first base 310, a second base 320, and a third base 330) are stacked.

[0303] The present technology may be configured as follows: (1) A photodetector including: a semiconductor layer having a first surface portion and a second surface portion located opposite to each other in one direction; a photoelectric conversion portion provided in the semiconductor layer at a distance from the first surface portion of the semiconductor layer and performing photoelectric conversion on light incident from the second surface portion of the semiconductor layer; a charge holding portion provided in the semiconductor layer and holding signal charges photoelectrically converted by the photoelectric conversion portion; and a transfer transistor having a gate electrode and transferring the signal charges photoelectrically converted by the photoelectric conversion portion to the charge holding portion, wherein the gate electrode includes a first electrode portion extending from the first surface portion side of the semiconductor layer toward the second surface portion side, and a second electrode portion provided on the first electrode portion at a distance from the first surface portion of the semiconductor layer and having an outer shape larger than that of the first electrode portion in a plan view. (2) The photodetector according to (1), wherein the second electrode portion extends two-dimensionally when the semiconductor layer is viewed from the one direction. (3) The photodetector according to (1) or (2), wherein the second electrode portion has an elliptical cross section along the one direction. (4) The photodetector according to (1) or (2), wherein the second electrode portion has a rectangular parallelepiped shape. (5) The photodetector according to (1) or (2), wherein the second electrode portion has an octahedral shape. (6) The photodetector according to (1) or (2), wherein the second electrode portion extends to a side opposite to the charge holding portion side of the first electrode portion when the semiconductor layer is viewed from the one direction. (7) The photodetector according to (1) or (2), wherein the second electrode portion includes a slope portion that intersects the one direction and extends obliquely from the photoelectric conversion portion side toward the charge holding portion side. (8) A photodetector device according to any one of (1) to (7) above, further comprising: an element formation region separated by an inter-element isolation region and provided on the first surface side of the semiconductor layer, overlapping the charge retention portion when the semiconductor layer is viewed from the one direction; and a pixel transistor provided in the element formation region, wherein the second electrode portion is located on the second surface side of the semiconductor layer relative to the inter-element isolation region in the one direction.(9) The photodetector according to any one of (1) to (8), further comprising: a barrier layer provided between the photoelectric conversion section and the first surface portion of the semiconductor layer in a region other than a region facing the charge retention section when the semiconductor layer is viewed from the one direction, the barrier layer suppressing migration of signal charges photoelectrically converted in the photoelectric conversion section toward the first surface portion. (10) The photodetector according to (9), further comprising: a well region of a first conductivity type provided between the first surface portion of the semiconductor layer and the photoelectric conversion section, the barrier layer being a semiconductor region of a first conductivity type having a higher impurity concentration than the well region of the first conductivity type. (11) The photodetector according to any one of (1) to (10), further comprising: a gate electrode further including a charge passage portion through which signal charges pass from the photoelectric conversion section side of the second electrode portion to the charge retention section side. (12) The photodetector according to (11), wherein the charge passage portion is a slit extending inward from an edge of the second electrode portion with a predetermined width, or a through-hole spaced from the edge of the second electrode portion. (13) The photodetector according to (11) or (12), wherein the charge passage portion is provided at a position offset from a center of the second electrode portion when the semiconductor layer is viewed from the one direction. (14) The photodetector according to (11) or (12), wherein the charge passage portion is provided at a center of the second electrode portion when the semiconductor layer is viewed from the one direction. (15) The photodetector according to any one of (1) to (14), further comprising a pixel circuit that reads out signal charges held in the charge holding portion and outputs a pixel signal based on the read signal charges, and a pixel transistor included in the pixel circuit is provided on the first surface side of the semiconductor layer in the photoelectric conversion region. (16) The photodetector according to any one of (1) to (15), further comprising: a first semiconductor layer as the semiconductor layer; a second semiconductor layer provided so as to overlap the semiconductor layer in the one direction; and a pixel circuit that reads out the signal charges held in the charge holding portion and outputs a pixel signal based on the read signal charges, wherein a pixel transistor included in the pixel circuit is provided in the second semiconductor layer.(17) An electronic device comprising: a photodetector; an optical lens that focuses image light from a subject on an imaging surface of the photodetector; and a signal processing circuit that performs signal processing on a signal output from the photodetector, wherein the photodetector comprises: a semiconductor layer having a first surface portion and a second surface portion located opposite each other in one direction; a photoelectric conversion portion that is provided in the semiconductor layer and spaced apart from the first surface portion of the semiconductor layer, and performs photoelectric conversion on light incident from the second surface portion side of the semiconductor layer; a charge holding portion that is provided in the semiconductor layer and holds signal charges photoelectrically converted by the photoelectric conversion portion; and a transfer transistor that has a gate electrode and transfers the signal charges photoelectrically converted by the photoelectric conversion portion to the charge holding portion, wherein the gate electrode includes a first electrode portion that extends from the first surface portion side of the semiconductor layer toward the second surface portion side, and a second electrode portion that is provided in the first electrode portion and spaced apart from the first surface portion of the semiconductor layer, and has an outer shape that is larger than that of the first electrode portion in a planar view.

[0304] The scope of the present technology is not limited to the exemplary embodiments shown and described, but includes all embodiments that achieve equivalent effects to those intended by the present technology. Furthermore, the scope of the present technology is not limited to the combination of the features of the invention defined by the claims, but may be defined by any desired combination of specific features among all the respective disclosed features.

[0305] DESCRIPTION OF SYMBOLS 1A...Solid-state imaging device 2...Semiconductor chip 2A...Pixel array section 2B...Peripheral section 3...Pixel 4...Vertical drive circuit 5...Column signal processing circuit 6...Horizontal drive circuit 7...Output circuit 8...Control circuit 10...Pixel drive line 11...Vertical signal line 12...Horizontal signal line 13...Logic circuit 14...Bonding pad 15...Pixel block 16...Pixel circuit (readout circuit) 21...Semiconductor layer (first semiconductor layer) 22...Photoelectric conversion region 23...P-type well region (p-type semiconductor region) 24...N-type semiconductor region 25...Photoelectric conversion section (PD) 31...Inter-pixel isolation region 32...Dug portion 34...Isolation insulating film 41...Inter-element isolation region (field isolation region) 41a...Shallow groove portion 41b...Isolation insulating film 43a, 43b...Element formation region 43z...Power supply region 51...Gate trench portion 51b １ ...First dug portion 51b ２ ...second recessed portion 52...gate insulating film 53...gate electrode film 54...gate electrode 54a...head portion 54b...body portion 54b １ ...first electrode portion 54b ２ ...second electrode portion 55a...gate electrode 56a １ , 56a ２: ...Main electrode region 56t...n-type semiconductor region 61...planarization film 63...optical filter 64...microlens 65...barrier layer 66...charge passage portion 67...through hole 68...slit 81...semiconductor layer (second semiconductor layer) 200...electronic device 201...solid-state imaging device 202...optical lens (optical system) 203...shutter device 204...drive circuit 205...signal processing circuit 301...solid-state imaging device 310...first base 311...semiconductor layer (first semiconductor layer) 312...sensor pixel 313...pixel region 320...second base 321...semiconductor layer (second semiconductor layer) 322...pixel circuit (readout circuit) 323...pixel drive line 324...vertical drive line 330...third base 331...semiconductor layer 332...logic circuit 333...vertical drive circuit 334...Column signal processing circuit 335...Horizontal drive circuit 336...System control circuit AMP...Amplifying transistor FD...n-type floating diffusion region FDG...Switching transistor Q...Pixel transistor R1, R2, R3, R4...Signal charge transfer path RST...Reset transistor SEL...Selection transistor S1...First surface portion S2...Second surface portion TR...Transfer transistor WC...Power supply contact region

Claims

1. A photodetector comprising: a semiconductor layer having a first surface portion and a second surface portion located opposite each other in one direction; a photoelectric conversion portion provided in the semiconductor layer spaced apart from the first surface portion of the semiconductor layer and performing photoelectric conversion on light incident from the second surface portion side of the semiconductor layer; a charge holding portion provided in the semiconductor layer and holding signal charges photoelectrically converted by the photoelectric conversion portion; and a transfer transistor having a gate electrode and transferring the signal charges photoelectrically converted by the photoelectric conversion portion to the charge holding portion, wherein the gate electrode includes a first electrode portion extending from the first surface portion side of the semiconductor layer toward the second surface portion side, and a second electrode portion provided on the first electrode portion spaced apart from the first surface portion of the semiconductor layer and having an outer shape larger than that of the first electrode portion in a planar view.

2. The photodetector device according to claim 1, wherein the second electrode portion extends two-dimensionally when the semiconductor layer is viewed from the one direction.

3. The light detection device according to claim 1, wherein the second electrode portion has an elliptical cross section along the one direction.

4. The photodetector device according to claim 1, wherein said second electrode portion is shaped like a rectangular parallelepiped.

5. The photodetector device of claim 1, wherein said second electrode portion is octahedral in shape.

6. The photodetector according to claim 1, wherein the second electrode portion extends on a side opposite to the charge retaining portion side of the first electrode portion when the semiconductor layer is viewed from the one direction.

7. The photodetector according to claim 1, wherein the second electrode portion includes an inclined surface portion that intersects the one direction and extends obliquely from the photoelectric conversion portion side toward the charge storage portion side.

8. The photodetector device of claim 1, further comprising: an element formation region partitioned by an element isolation region on the first surface side of the semiconductor layer, overlapping with the charge retention portion when the semiconductor layer is viewed from said one direction; and a pixel transistor provided in the element formation region, wherein the second electrode portion is located on the second surface side of the semiconductor layer relative to the element isolation region in said one direction.

9. The photodetection device described in claim 1, further comprising a barrier layer provided between the photoelectric conversion section and the first surface portion of the semiconductor layer in an area other than the area facing the charge retention section when the semiconductor layer is viewed from the one direction, and which suppresses the movement of signal charges photoelectrically converted by the photoelectric conversion section toward the first surface portion.

10. The photodetection device according to claim 9, further comprising a well region of a first conductivity type provided between the first surface portion of the semiconductor layer and the photoelectric conversion portion, and the barrier layer is a semiconductor region of a first conductivity type having a higher impurity concentration than the well region of the first conductivity type.

11. The photodetector according to claim 1, wherein the gate electrode further includes a charge passage portion through which signal charges pass from the photoelectric conversion portion side of the second electrode portion to the charge retention portion side.

12. The photodetector according to claim 11, wherein the charge passage portion is a slit extending inward from the edge of the second electrode portion with a predetermined width, or a through hole spaced apart from the edge of the second electrode portion.

13. The photodetector according to claim 11, wherein, when the semiconductor layer is viewed from the one direction, the charge passage portion is provided at a position offset from the center of the second electrode portion.

14. The photodetector according to claim 11, wherein, when the semiconductor layer is viewed from the one direction, the charge passage portion is provided in the center of the second electrode portion.

15. The photodetection device according to claim 1, further comprising a pixel circuit that reads out the signal charge held in the charge holding portion and outputs a pixel signal based on the read-out signal charge, wherein a pixel transistor included in the pixel circuit is provided on the first surface side of the semiconductor layer in the photoelectric conversion region.

16. The photodetection device according to claim 1, further comprising: a first semiconductor layer, a second semiconductor layer provided so as to overlap the semiconductor layer in the one direction; and a pixel circuit that reads out the signal charge held in the charge holding portion and outputs a pixel signal based on the read-out signal charge, wherein a pixel transistor included in the pixel circuit is provided in the second semiconductor layer.

17. An electronic device comprising: a photodetector; an optical lens that focuses image light from a subject on an imaging surface of the photodetector; and a signal processing circuit that processes a signal output from the photodetector, wherein the photodetector comprises: a semiconductor layer having a first surface and a second surface located opposite each other in one direction; a photoelectric conversion unit that is provided in the semiconductor layer and spaced apart from the first surface of the semiconductor layer, and performs photoelectric conversion on light incident from the second surface side of the semiconductor layer; a charge holding unit that is provided in the semiconductor layer and holds signal charges photoelectrically converted by the photoelectric conversion unit; and a transfer transistor having a gate electrode and transferring the signal charges photoelectrically converted by the photoelectric conversion unit to the charge holding unit, wherein the gate electrode includes a first electrode portion extending from the first surface side of the semiconductor layer toward the second surface side, and a second electrode portion that is provided on the first electrode portion and spaced apart from the first surface of the semiconductor layer, and has an outer shape larger than that of the first electrode portion in a planar view.

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