Transimpedance amplifier and optical receiver

Abstract

The present invention relates to the technical field of optical communications. Disclosed are a transimpedance amplifier and an optical receiver. The transimpedance amplifier comprises: a pre-amplifier, which pre-amplifier comprises a first single-sided pre-amplification circuit and a second single-sided pre-amplification circuit, which are symmetrically arranged, wherein the first single-sided pre-amplification circuit and the second single-sided pre-amplification circuit each comprise a common-emitter common-base circuit, a direct-current bias circuit and an emitter follower circuit. An input end of the common-emitter common-base circuit serves as an input end of the pre-amplifier and is connected to an optical detector; the direct-current bias circuit is connected to the common-emitter common-base circuit; the emitter follower circuit is connected to the common-emitter common-base circuit; and an output end of the emitter follower circuit serves as an output end of the pre-amplifier and is connected to a next-stage circuit of the pre-amplifier. The present invention can achieve low noise, high bandwidth and large gain.

Description

A transimpedance amplifier and an optical receiver Technical Field

[0001] The present invention relates to the technical field of optical communications, and in particular to a transimpedance amplifier and an optical receiver. Background Art

[0002] As the cornerstone of modern communications, fiber-optic communication plays a vital role in modern society. As a crucial component of existing fiber-optic communication transmission systems, optical receivers primarily convert weak optical signals transmitted through optical fibers into electrical signals, amplifying and equalizing them. The output characteristics of optical receivers comprehensively reflect the performance of the entire fiber-optic communication system. The transimpedance amplifier (TIA), the core electronic chip in an optical receiver, converts the weak current signal generated by the photodetector into a voltage signal and amplifies it for processing by subsequent signal processing circuits. The performance of the TIA directly affects the performance of the entire optical receiver. Its bandwidth determines the bandwidth of the entire receiver, while its gain and noise characteristics determine the sensitivity of the optical receiver.

[0003] In the prior art, a conventional transimpedance amplifier uses a preamplifier composed of a common base amplifier and an emitter follower, and its three technical indicators of noise, bandwidth, and gain are mutually restricted.

[0004] However, high-performance transimpedance amplifiers require low noise, high bandwidth, and large gain. How to resolve the constraints and contradictions between these indicators is a severe challenge for high-performance transimpedance amplifiers.

[0005] Furthermore, due to differences in transmission distance, the magnitude of the current signal converted from the light received by the photodetector also varies. Therefore, a transimpedance amplifier (TIA) must possess a wide dynamic gain range to meet application requirements. Currently, TIAs primarily utilize equalizer circuits to increase gain and expand bandwidth, while also enabling gain adjustment. However, existing equalizer circuits, when implementing gain adjustment with a wide dynamic range, can cause the DC operating point voltage of the output node to vary significantly, leading to large variations in the input DC operating point voltage of the next-stage circuit, thus degrading the performance of the entire TIA.

[0006] Summary of the Invention

[0007] The embodiments of the present invention provide a transimpedance amplifier and an optical receiver to solve the technical problem in the related art that the existing transimpedance amplifier is difficult to achieve low noise, high bandwidth and large gain.

[0008] In a first aspect, a transimpedance amplifier is provided, comprising:

[0009] A preamplifier, the preamplifier comprising a first unilateral preamplifier circuit and a second unilateral preamplifier circuit that are symmetrically arranged, the first unilateral preamplifier circuit and the second unilateral preamplifier circuit each comprising:

[0010] a common emitter common base circuit, the input end of which is connected to a photodetector as the input end of the preamplifier;

[0011] a DC bias circuit connected to the cascode circuit, the DC bias circuit being configured to provide a DC bias voltage for the cascode circuit;

[0012] An emitter follower circuit is connected to the common-emitter common-base circuit, and an output end of the emitter follower circuit serves as an output end of the preamplifier and is connected to a subsequent stage circuit of the preamplifier.

[0013] In some embodiments, the common emitter common base circuit includes a load resistor, a feedback resistor, a first inductor, a first transistor, and a fourth transistor;

[0014] The DC bias circuit includes a first resistor, a second resistor, a first capacitor and a third transistor;

[0015] The first end of the first inductor is connected to a photodetector as an input end of the preamplifier, and the second end of the first inductor is connected to the base of the first transistor;

[0016] The first end of the load resistor is connected to a power supply, the second end of the load resistor is connected to the collector of the fourth transistor and the emitter follower circuit, the emitter of the fourth transistor is connected to the collector of the first transistor, and the emitter of the first transistor is grounded;

[0017] A first end of the first resistor is connected to a power supply, a second end of the first resistor is connected to the collector and base of the third transistor, a first end of the second resistor is connected to the second end of the first resistor, a second end of the second resistor is connected to the base of the fourth transistor and the first end of the first capacitor, and a second end of the first capacitor is grounded;

[0018] A first end of the feedback resistor is connected to a first end of the first inductor, and a second end of the feedback resistor is connected to the emitter follower circuit.

[0019] In some embodiments, the emitter follower circuit includes:

[0020] A first emitter follower unit, comprising a second transistor and a first current source;

[0021] a second emitter follower unit comprising a fifth transistor and a second current source, wherein the second emitter follower unit is a mirror image of the first emitter follower unit;

[0022] The collector of the second transistor is connected to a power supply, the base of the second transistor is connected to the collector of the fourth transistor and the base of the fifth transistor, the emitter of the second transistor is connected to the first end of the first current source, and the second end of the first current source is grounded;

[0023] The collector of the fifth transistor is connected to the power supply, the emitter of the fifth transistor is connected to the first end of the second current source, the second end of the second current source is grounded, and the emitter of the fifth transistor serves as the output end of the preamplifier and is connected to the subsequent stage circuit of the preamplifier.

[0024] In some embodiments, the second transistor is the same as the fifth transistor, and the first current source is the same as the second current source.

[0025] In some embodiments, the transimpedance amplifier further comprises:

[0026] A variable gain amplifier, wherein the differential input end of the variable gain amplifier is connected to the output end of the first unilateral preamplifier circuit and the output end of the second unilateral preamplifier circuit, and the variable gain amplifier is used to amplify the voltage signal output by the preamplifier and output it to the subsequent stage circuit of the variable gain amplifier.

[0027] In some embodiments, the variable gain amplifier includes a first unilateral variable gain amplifier circuit and a second unilateral variable gain amplifier circuit that are symmetrically arranged, and a negative feedback circuit;

[0028] The first unilateral variable gain amplifier circuit and the second unilateral variable gain amplifier circuit both include: a fourth resistor, a fifth resistor, a sixth resistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, a third current source, and a fourth current source;

[0029] The negative feedback circuit includes an operational amplifier, a first MOS tube, a third capacitor and two seventh resistors;

[0030] The base of the sixth transistor serves as the input terminal of the first unilateral variable gain amplifier circuit or the second unilateral variable gain amplifier circuit, and is connected to the output terminal of the first unilateral preamplifier circuit or the output terminal of the second unilateral preamplifier circuit; the emitter of the sixth transistor is connected to the first terminal of the third current source, and the second terminal of the third current source is grounded;

[0031] A first end of the fourth resistor is connected to a power supply, a second end of the fourth resistor is connected to the collector of the seventh transistor, a base of the seventh transistor is connected to a first control voltage, and an emitter of the seventh transistor is connected to the collector of the sixth transistor;

[0032] A first end of the fifth resistor is connected to the drain of the first MOS transistor, a second end of the fifth resistor is connected to the collector of the eighth transistor, a base of the eighth transistor is connected to a first control voltage, and an emitter of the eighth transistor is connected to the collector of the sixth transistor;

[0033] A first end of the sixth resistor is connected to a power supply, a second end of the sixth resistor is connected to the collector of the ninth transistor, a base of the ninth transistor is connected to the collector of the seventh transistor, an emitter of the ninth transistor is connected to the collector and base of the tenth transistor, an emitter of the tenth transistor is connected to a first end of the fourth current source, a second end of the fourth current source is grounded, and an emitter of the tenth transistor serves as an output end of the first unilateral variable gain amplifier circuit or the second unilateral variable gain amplifier circuit;

[0034] Two ends of the two seventh resistors connected in series are respectively connected to the collector of the seventh transistor of the first unilateral variable gain amplifier circuit and the collector of the seventh transistor of the second unilateral variable gain amplifier circuit. A common end of the two seventh resistors connected in series is connected to the first end of the third capacitor and the non-inverting input end of the operational amplifier. The second end of the third capacitor is grounded. The inverting input end of the operational amplifier is connected to a reference voltage. The output end of the operational amplifier is connected to the gate of the first MOS transistor. The source of the first MOS transistor is connected to a power supply.

[0035] In some embodiments, the transimpedance amplifier further comprises:

[0036] A fixed gain amplifier, wherein a differential input terminal of the fixed gain amplifier is correspondingly connected to the output terminal of the first unilateral variable gain amplifier circuit and the output terminal of the second unilateral variable gain amplifier circuit.

[0037] In some embodiments, the transimpedance amplifier further comprises:

[0038] An output buffer circuit, wherein the differential input end of the output buffer circuit is connected to the differential output end of the fixed gain amplifier, and the differential output end of the output buffer circuit serves as the differential output end of the transimpedance amplifier.

[0039] In some embodiments, the transimpedance amplifier further comprises:

[0040] a gain control circuit connected to the variable gain amplifier and the output buffer circuit;

[0041] A DC offset voltage elimination circuit, wherein the differential input end of the DC offset voltage elimination circuit is connected to the differential output end of the output buffer circuit, and the differential output end of the DC offset voltage elimination circuit is connected to the differential input end of the variable gain amplifier.

[0042] In a second aspect, an optical receiver is provided, comprising the aforementioned transimpedance amplifier.

[0043] The beneficial effects brought about by the technical solution provided by the present invention include:

[0044] Embodiments of the present invention provide a transimpedance amplifier and an optical receiver. The transimpedance amplifier's preamplifier utilizes a common-emitter common-base architecture, resulting in improved open-loop gain. Due to the greater open-loop gain, the feedback resistor can be appropriately increased, thereby increasing the preamplifier's gain and reducing its noise while maintaining the preamplifier's bandwidth. The transimpedance amplifier of the present invention achieves low noise, high bandwidth, and high gain, resulting in superior performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0046] FIG1 is a schematic diagram of a transimpedance amplifier according to an embodiment of the present invention;

[0047] FIG2 is a circuit diagram of a preamplifier of a transimpedance amplifier provided by an embodiment of the present invention;

[0048] FIG3 is a circuit structure diagram of a variable gain amplifier of a transimpedance amplifier provided by an embodiment of the present invention;

[0049] FIG4 is a schematic diagram of an S-parameter simulation of a transimpedance amplifier provided by an embodiment of the present invention;

[0050] FIG5 is a schematic diagram of an eye diagram simulation of a transimpedance amplifier provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0051] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.

[0052] The embodiment of the present invention provides a transimpedance amplifier, which can solve the technical problem that existing transimpedance amplifiers are difficult to achieve low noise, high bandwidth and large gain.

[0053] As shown in Figures 1 and 2, an embodiment of the present invention provides a transimpedance amplifier, including a preamplifier, wherein the preamplifier includes a first unilateral preamplifier circuit and a second unilateral preamplifier circuit, both of which include a common-emitter common-base circuit, a DC bias circuit, and an emitter-follower circuit.

[0054] The input end of the cascode circuit is connected to a photodetector as the input end of the preamplifier. The DC bias circuit is connected to the cascode circuit and is used to provide a DC bias voltage for the cascode circuit. The emitter follower circuit is connected to the cascode circuit, and the output end of the emitter follower circuit serves as the output end of the preamplifier and is connected to the subsequent stage of the preamplifier.

[0055] Specifically, referring to FIG2 , the common emitter common base circuit includes a load resistor R L , feedback resistor R f , a first inductor L1, a first transistor Q1 and a fourth transistor Q4.

[0056] The DC bias circuit includes a first resistor R1, a second resistor R2, a first capacitor C1 and a third transistor Q3.

[0057] The first end of the first inductor L1 is connected to a photodetector PD as an input end of the preamplifier, and the second end of the first inductor L1 is connected to the base of the first transistor Q1.

[0058] A first end of the load resistor RL is connected to a power supply, a second end of the load resistor RL is connected to the collector of the fourth transistor Q4 and the emitter follower circuit, an emitter of the fourth transistor Q4 is connected to the collector of the first transistor Q1, and an emitter of the first transistor Q1 is grounded.

[0059] A first end of the first resistor R1 is connected to a power supply, a second end of the first resistor R1 is connected to the collector and base of the third transistor Q3, a first end of the second resistor R2 is connected to the second end of the first resistor R1, a second end of the second resistor R2 is connected to the base of the fourth transistor Q4 and the first end of the first capacitor C1, and a second end of the first capacitor C1 is grounded.

[0060] A first end of the feedback resistor Rf is connected to a first end of the first inductor L1 , and a second end of the feedback resistor Rf is connected to the emitter follower circuit.

[0061] Specifically, the transfer function of the preamplifier is: Therefore, the gain of the preamplifier is Z f Modulo, that is: Among them, R f is the feedback resistor of the preamplifier; A is the open-loop gain of the preamplifier, A=g m1 g m4 RL, R L is the load resistance, g m1 、g m4 are the transconductances of the first transistor Q1 and the fourth transistor Q4, respectively, both of which are integers greater than 1; C total is the equivalent capacitance of the input terminal. It can be seen that increasing the feedback resistor R f This can increase the gain of the preamplifier.

[0062] The 3dB bandwidth of the preamplifier is: It can be seen that in order to increase the 3dB bandwidth of the preamplifier, it is necessary to increase A or reduce C. total , or reduce R f .

[0063] The equivalent input current noise of the preamplifier is:

[0064] Where k is the Boltzmann constant, T is the thermodynamic temperature, and γ is the channel noise coefficient. It can be seen that increasing the feedback resistor R f This can reduce the noise of the preamplifier.

[0065] In summary, the preamplifier of the transimpedance amplifier in the embodiment of the present invention adopts a common emitter common base structure composed of the first transistor Q1 and the fourth transistor Q4. Compared with the traditional common base preamplifier, its open loop gain A=g m1 g m4 R L , the open-loop gain is improved. Due to the larger open-loop gain A, R can be appropriately increased. fThe value of is set, thereby ensuring the bandwidth of the preamplifier while also improving the gain of the preamplifier and reducing the noise of the preamplifier. That is, the transimpedance amplifier in the embodiment of the present invention achieves low noise, high bandwidth, and high gain, and has better performance.

[0066] In addition, the equivalent capacitance at the input C pd is the parasitic capacitance of the photodetector PD, C in is the input equivalent capacitance (C in is the parasitic capacitance of the preamplifier input node to ground). When the first inductor L1 is not provided between the base of the first transistor Q1 and the photodetector PD, α in the above formula is 1; when the first inductor L1 is provided between the base of the first transistor Q1 and the photodetector PD, α is s 2 L1C in +1<-1. After the first inductor L1 is added, the equivalent capacitance of the input terminal is smaller than the equivalent capacitance of the input terminal without the first inductor L1, thereby further improving the 3dB bandwidth of the preamplifier.

[0067] As an optional implementation, in one embodiment of the invention, referring to FIG. 1 and FIG. 2 , the emitter follower circuit includes: a first emitter follower unit and a second emitter follower unit.

[0068] The first emitter follower unit includes a second transistor Q2 and a first current source I1 , the second emitter follower unit includes a fifth transistor Q5 and a second current source I2 , and the second emitter follower unit is a mirror image of the first emitter follower unit.

[0069] The collector of the second transistor Q2 is connected to the power supply, the base of the second transistor Q2 is connected to the collector of the fourth transistor Q4 and the base of the fifth transistor Q5, the emitter of the second transistor Q2 is connected to the first end of the first current source I1, and the second end of the first current source I1 is grounded.

[0070] The collector of the fifth transistor Q5 is connected to the power supply, the emitter of the fifth transistor Q5 is connected to the first end of the second current source I2, the second end of the second current source I2 is grounded, and the emitter of the fifth transistor Q5 serves as the output end of the preamplifier and is connected to the subsequent stage circuit of the preamplifier.

[0071] In order to ensure the critical damping response of the preamplifier, the open-loop bandwidth of the preamplifier must usually be more than twice its 3dB bandwidth. The open-loop bandwidth of the preamplifier is proportional to the load resistance R L The product of the output node capacitance of the preamplifier is inversely proportional to the load resistance R of the common emitter and common base. LThe smaller the product of the output node capacitance of the preamplifier, the better. The embodiment of the present invention adds a second emitter follower unit consisting of a fifth transistor Q5 and a second current source I2 on the basis of a traditional preamplifier. The second emitter follower unit is a mirror image of the first emitter follower unit, effectively isolating the preamplifier from the subsequent circuit, reducing the influence of the subsequent circuit on the output node capacitance of the preamplifier. When the subsequent circuit remains unchanged, the output node capacitance of the preamplifier is smaller, and thus the load resistance R L has a higher upper limit. Therefore, for the same C total 、R f , the preamplifier load resistor R L With a higher ceiling, the preamplifier has a higher 3dB bandwidth and optimal response.

[0072] Furthermore, the second transistor Q2 is the same as the fifth transistor Q5 , and the first current source I1 is the same as the second current source I2 , so that the first emitter follower unit and the second emitter follower unit are completely mirror images.

[0073] As an optional implementation, in one embodiment of the invention, as shown in Figure 1, the transimpedance amplifier also includes: a variable gain amplifier, the differential input end of the variable gain amplifier is connected to the output end of the first unilateral preamplifier circuit and the output end of the second unilateral preamplifier circuit, and the variable gain amplifier is used to amplify the voltage signal output by the preamplifier and output it to the subsequent stage circuit of the variable gain amplifier.

[0074] Specifically, referring to FIG3 , the variable gain amplifier includes a first unilateral variable gain amplifier circuit and a second unilateral variable gain amplifier circuit and a negative feedback circuit that are symmetrically arranged;

[0075] The first unilateral variable gain amplifier circuit and the second unilateral variable gain amplifier circuit each include: a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a sixth transistor Q6, a seventh transistor Q7, an eighth transistor Q8, a ninth transistor Q9, a tenth transistor Q10, a third current source I3, and a fourth current source I4. Optionally, the first to tenth transistors Q1 to Q10 are NPN transistors.

[0076] The negative feedback circuit includes an operational amplifier AMP, a first MOS transistor M1, a third capacitor C3, and two seventh resistors R7. Optionally, the first MOS transistor M1 is a PMOS transistor.

[0077] The base of the sixth transistor Q6 serves as the input end of the first unilateral variable gain amplifier circuit or the second unilateral variable gain amplifier circuit, and is connected to the output end of the first unilateral preamplifier circuit or the output end of the second unilateral preamplifier circuit. The emitter of the sixth transistor Q6 is connected to the first end of the third current source I3, and the second end of the third current source I3 is grounded.

[0078] A first end of the fourth resistor R4 is connected to a power supply, a second end of the fourth resistor R4 is connected to the collector of the seventh transistor Q7, a base of the seventh transistor Q7 is connected to a first control voltage, and an emitter of the seventh transistor Q7 is connected to the collector of the sixth transistor Q6;

[0079] A first end of the fifth resistor R5 is connected to the drain of the first MOS transistor M1, a second end of the fifth resistor R5 is connected to the collector of the eighth transistor Q8, a base of the eighth transistor Q8 is connected to the first control voltage, and an emitter of the eighth transistor Q8 is connected to the collector of the sixth transistor Q6;

[0080] A first end of the sixth resistor R6 is connected to a power supply, a second end of the sixth resistor R6 is connected to the collector of the ninth transistor Q9, a base of the ninth transistor Q9 is connected to the collector of the seventh transistor Q7, an emitter of the ninth transistor Q9 is connected to the collector and base of the tenth transistor Q10, an emitter of the tenth transistor Q10 is connected to a first end of the fourth current source I4, a second end of the fourth current source I4 is grounded, and the emitter of the tenth transistor Q10 serves as an output end of the first unilateral variable gain amplifier circuit or the second unilateral variable gain amplifier circuit.

[0081] Two ends of the two seventh resistors R7 connected in series are respectively connected to the collector of the seventh transistor Q7 of the first unilateral variable gain amplifier circuit and the collector of the seventh transistor Q7 of the second unilateral variable gain amplifier circuit. A common end of the two seventh resistors R7 connected in series is connected to the first end of the third capacitor C3 and the non-inverting input end of the operational amplifier AMP. The second end of the third capacitor C3 is grounded. The inverting input end of the operational amplifier AMP is connected to a reference voltage. The output end of the operational amplifier AMP is connected to the gate of the first PMOS transistor M1. The source of the first PMOS transistor M1 is connected to a power supply.

[0082] Typically, the variable gain amplifier also includes a third resistor R3 and a second capacitor C2, and the two ends of the third resistor R3 and the second capacitor C2 in parallel are respectively connected to the first end of the third current source I3 of the first unilateral variable gain amplifier circuit and the first end of the third current source I3 of the second unilateral variable gain amplifier circuit.

[0083] As shown in FIG3 , the sixth transistor Q6, the seventh transistor Q7, the eighth transistor Q8, the third current source I3, the fourth resistor R4, and the fifth resistor R5 form two common-emitter-common-base circuits. The sixth transistor Q6 is an input transistor, and the seventh transistor Q7 and the eighth transistor Q8 are common-base transistors, respectively forming two common-emitter-common-base circuits with the sixth transistor Q6. The fourth resistor R4 and the fifth resistor R5 serve as load resistors for the seventh transistor Q7 and the eighth transistor Q8, respectively. By adjusting the first control voltage at the base of the seventh transistor Q7 and the second control voltage at the base of the eighth transistor Q8, the current flowing through the two common-emitter-common-base circuits of the seventh transistor Q7 and the eighth transistor Q8 can be changed, thereby achieving gain adjustment of the variable gain amplifier.

[0084] Following the output node A of the common-emitter-common-base circuit formed by the sixth and seventh transistors Q6 and Q7 of the variable gain amplifier is an emitter follower circuit consisting of a ninth transistor Q9, a tenth transistor Q10, a fourth current source I4, and a sixth resistor R6, which is used to improve the variable gain amplifier's load capacity. The ninth transistor Q9 serves as the input of the emitter follower circuit. The diode-connected tenth transistor Q10 regulates the voltage at the output node of the emitter follower circuit to ensure that the input transistor of the subsequent stage connected thereto is at the optimal operating point. The sixth resistor R6 consumes a certain amount of power supply voltage margin while also improving the reliability of the tenth transistor Q10.

[0085] The variable gain amplifier can change the magnitude of the current flowing through the branch of the seventh transistor Q7 and the eighth transistor Q8 by changing the voltage values ​​of the first control voltage Vctrl1 and the second control voltage Vctrl2. For example, when the voltage of Vctrl1 is increased, the current flowing through the branch of the seventh transistor Q7 increases, and the gain of the signal passing through the common-emitter-common-base amplifier branch formed by the sixth transistor Q6 and the seventh transistor Q7 also increases. When the voltage of Vctrl1 is reduced, the current flowing through the branch of the seventh transistor Q7 decreases, and the gain of the signal passing through the common-emitter-common-base amplifier branch formed by the sixth transistor Q6 and the seventh transistor Q7 also decreases.

[0086] The DC common-mode point voltage of the output node A of the common-emitter-common-base structure formed by the sixth transistor Q6 and the seventh transistor Q7 in the variable gain amplifier is extracted through two seventh resistors R7 and a third capacitor C3, and is connected to the positive electrode of the non-inverting input terminal of the operational amplifier AMP. The single-ended output of the operational amplifier AMP is connected to the gate of the first MOS transistor M1 to form a negative feedback loop. During the gain adjustment process of the variable gain amplifier, the current flowing through the seventh transistor Q7 will change, and the voltage drop across the fourth resistor R4 will also change, thereby causing the voltage of the output node A to change. When the current flowing through the seventh transistor Q7 increases, the voltage drop across the fourth resistor R4 increases, and the voltage at the output node A decreases. The operational amplifier AMP in the negative feedback loop The voltage of the output node B decreases, thereby increasing the voltage of the drain point P of the first MOS transistor M1. In this way, the voltage of the output node A will be pulled up, so that the voltage of the output node A of the common emitter and common base formed by the sixth transistor Q6 and the seventh transistor Q7 remains unchanged during the gain adjustment process of the variable gain amplifier. In this way, the voltage of the output nodes OutP and OutN of the emitter follower of the variable gain amplifier will also remain unchanged, so that the voltage of the input node of the subsequent stage circuit connected to the output nodes OutP and OutN of the emitter follower of the variable gain amplifier remains unchanged, thereby ensuring that the input tube of the subsequent stage circuit is at the optimal DC operating point, thereby improving the performance of the entire transimpedance amplifier.

[0087] As an optional implementation, in one embodiment of the invention, as shown in FIG1 , the transimpedance amplifier further includes a fixed-gain amplifier, wherein the differential input of the fixed-gain amplifier is connected to the output of the first unilateral variable-gain amplifier circuit and the output of the second unilateral variable-gain amplifier circuit. The fixed-gain amplifier is configured to further amplify the output signal of the variable-gain amplifier, thereby increasing the gain and achieving bandwidth expansion.

[0088] As an optional implementation, in one embodiment of the invention, as shown in FIG1 , the transimpedance amplifier further includes an output buffer circuit, wherein the differential input of the output buffer circuit is connected to the differential output of the fixed-gain amplifier, and the differential output of the output buffer circuit serves as the differential output of the transimpedance amplifier. The output buffer circuit is configured to achieve 50 ohm impedance matching and improve the load capacity of the entire transimpedance amplifier.

[0089] As an optional implementation, in one embodiment of the invention, as shown in FIG1 , the transimpedance amplifier further includes a gain control circuit connected to the variable gain amplifier and the output buffer circuit. The gain control circuit is configured to adjust Vctrl1 and Vctrl2 in the variable gain circuit to achieve gain control. Simultaneously, the gain control circuit detects the magnitude of the output signal from the output buffer circuit and dynamically adjusts Vctrl1 and Vctrl2 in the variable gain circuit to achieve automatic gain control.

[0090] As an optional implementation, in one embodiment of the invention, as shown in FIG1 , the transimpedance amplifier further includes a DC offset voltage cancellation circuit, wherein the differential input of the DC offset voltage cancellation circuit is connected to the differential output of the output buffer circuit, and the differential output of the DC offset voltage cancellation circuit is connected to the differential input of the variable gain amplifier. The DC offset voltage cancellation circuit is configured to detect the DC voltage at the operating point of the differential end of the variable gain amplifier, the fixed gain amplifier, and the output buffer circuit, and to cancel the offset voltage at the operating point of the differential end of the variable gain amplifier, the fixed gain amplifier, and the output buffer circuit through a negative feedback mechanism, thereby improving the performance of the entire transimpedance amplifier.

[0091] Figure 4 shows the S-parameter simulation results of the transimpedance amplifier provided in an embodiment of the present invention. The transimpedance amplifier in an embodiment of the present invention achieves a 3dB bandwidth of more than 53GHz and has a transimpedance gain of more than 75dB. Figure 5 shows the eye diagram simulation results of the transimpedance amplifier provided in an embodiment of the present invention. The transimpedance amplifier in an embodiment of the present invention can meet the transmission rate requirement of 64Gb / s and has a leading advantage in high-speed performance.

[0092] An embodiment of the present invention further provides an optical receiver, comprising the aforementioned transimpedance amplifier.

[0093] In the description of the present invention, it should be noted that the orientation or positional relationship indicated by the terms "upper" and "lower" is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention. Unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be internal communication between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to the specific circumstances.

[0094] It should be noted that, in the present invention, relational terms such as "first" and "second" are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply the existence of any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprising a ..." does not exclude the presence of other identical elements in the process, method, article or device comprising the element.

[0095] The foregoing description is intended only to provide specific embodiments of the present invention, which will enable those skilled in the art to understand and implement the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not intended to be limited to the embodiments shown herein, but is to be construed in the widest possible manner consistent with the principles and novel features of the present invention.

Claims

1. A transimpedance amplifier, characterized in that: include: A preamplifier, the preamplifier comprising a first single-sided preamplifier circuit and a second single-sided preamplifier circuit which are symmetrically arranged, the first single-sided preamplifier circuit and the second single-sided preamplifier circuit both comprising: A common emitter common base circuit, whose input terminal is connected to a photodetector as the input terminal of the preamplifier; A DC bias circuit connected to the common emitter common base circuit, the DC bias circuit being used to provide a DC bias voltage for the common emitter common base circuit; An emitter follower circuit is connected to the common emitter common base circuit, and the output end of the emitter follower circuit is connected to the subsequent stage circuit of the preamplifier as the output end of the preamplifier.

2. The transimpedance amplifier according to claim 1, characterized in that: The common emitter common base circuit comprises a load resistor, a feedback resistor, a first inductor, a first transistor and a fourth transistor; The DC bias circuit includes a first resistor, a second resistor, a first capacitor and a third transistor; The first end of the first inductor is connected to a photodetector as an input end of the preamplifier, and the second end of the first inductor is connected to the base of the first transistor; The first end of the load resistor is connected to a power supply, the second end of the load resistor is connected to the collector of the fourth transistor and the emitter follower circuit, the emitter of the fourth transistor is connected to the collector of the first transistor, and the emitter of the first transistor is grounded; A first end of the first resistor is connected to a power supply, a second end of the first resistor is connected to a collector and a base of the third transistor, a first end of the second resistor is connected to a second end of the first resistor, a second end of the second resistor is connected to a base of the fourth transistor and a first end of the first capacitor, and a second end of the first capacitor is grounded; The first end of the feedback resistor is connected to the first end of the first inductor, and the second end of the feedback resistor is connected to the emitter follower circuit.

3. The transimpedance amplifier according to claim 2, characterized in that: The emitter follower circuit comprises: A first emitter follower unit, which includes a second transistor and a first current source; A second emitter follower unit, comprising a fifth transistor and a second current source, wherein the second emitter follower unit is a mirror image of the first emitter follower unit; The collector of the second transistor is connected to a power supply, the base of the second transistor is connected to the collector of the fourth transistor and the base of the fifth transistor, the emitter of the second transistor is connected to the first end of the first current source, and the second end of the first current source is grounded; The collector of the fifth transistor is connected to the power supply, the emitter of the fifth transistor is connected to the first end of the second current source, the second end of the second current source is grounded, and the emitter of the fifth transistor is connected to the subsequent stage circuit of the preamplifier as the output end of the preamplifier.

4. The transimpedance amplifier according to claim 3, characterized in that: The second transistor is the same as the fifth transistor, and the first current source is the same as the second current source.

5. The transimpedance amplifier according to claim 1, characterized in that: Also includes: A variable gain amplifier, wherein the differential input end of the variable gain amplifier is connected to the output end of the first unilateral preamplifier circuit and the output end of the second unilateral preamplifier circuit, and the variable gain amplifier is used to amplify the voltage signal output by the preamplifier and output it to the subsequent stage circuit of the variable gain amplifier.

6. The transimpedance amplifier according to claim 5, characterized in that: The variable gain amplifier comprises a first unilateral variable gain amplifier circuit and a second unilateral variable gain amplifier circuit and a negative feedback circuit which are symmetrically arranged; The first unilateral variable gain amplifier circuit and the second unilateral variable gain amplifier circuit The circuits all include: a fourth resistor, a fifth resistor, a sixth resistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, a third current source and a fourth current source; The negative feedback circuit includes an operational amplifier, a first MOS tube, a third capacitor and two seventh resistors; The base of the sixth triode is used as the input end of the first unilateral variable gain amplifier circuit or the second unilateral variable gain amplifier circuit, and is connected to the output end of the first unilateral preamplifier circuit or the output end of the second unilateral preamplifier circuit, the emitter of the sixth triode is connected to the first end of the third current source, and the second end of the third current source is grounded; A first end of the fourth resistor is connected to a power supply, a second end of the fourth resistor is connected to a collector of the seventh transistor, a base of the seventh transistor is connected to a first control voltage, and an emitter of the seventh transistor is connected to a collector of the sixth transistor; The first end of the fifth resistor is connected to the drain of the first MOS transistor, the second end of the fifth resistor is connected to the collector of the eighth transistor, the base of the eighth transistor is connected to the first control voltage, and the emitter of the eighth transistor is connected to the collector of the sixth transistor; A first end of the sixth resistor is connected to a power supply, a second end of the sixth resistor is connected to the collector of the ninth triode, a base of the ninth triode is connected to the collector of the seventh triode, an emitter of the ninth triode is connected to the collector and base of the thirteenth triode, an emitter of the thirteenth triode is connected to a first end of the fourth current source, a second end of the fourth current source is grounded, and an emitter of the tenth triode serves as an output end of the first unilateral variable gain amplifier circuit or the second unilateral variable gain amplifier circuit; The two ends of the two seventh resistors connected in series are respectively connected to the collector of the seventh transistor of the first unilateral variable gain amplifier circuit and the collector of the seventh transistor of the second unilateral variable gain amplifier circuit, and the common end of the two seventh resistors connected in series is connected to the collector of the seventh transistor of the first unilateral variable gain amplifier circuit. The first end of the third capacitor is connected to the non-inverting input end of the operational amplifier, the second end of the third capacitor is grounded, the inverting input end of the operational amplifier is connected to a reference voltage, the output end of the operational amplifier is connected to the gate of the first MOS tube, and the source of the first MOS tube is connected to a power supply.

7. The transimpedance amplifier according to claim 5, characterized in that: Also includes: A fixed gain amplifier, wherein a differential input terminal of the fixed gain amplifier is correspondingly connected to an output terminal of the first unilateral variable gain amplifier circuit and an output terminal of the second unilateral variable gain amplifier circuit.

8. The transimpedance amplifier according to claim 7, characterized in that: Also includes: An output buffer circuit, wherein the differential input end of the output buffer circuit is connected to the differential output end of the fixed gain amplifier, and the differential output end of the output buffer circuit serves as the differential output end of the transimpedance amplifier.

9. The transimpedance amplifier according to claim 8, characterized in that: Also includes: a gain control circuit, the gain control circuit being connected to the variable gain amplifier and the output buffer circuit; A DC offset voltage elimination circuit, wherein the differential input end of the DC offset voltage elimination circuit is connected to the differential output end of the output buffer circuit, and the differential output end of the DC offset voltage elimination circuit is connected to the differential input end of the variable gain amplifier.

10. An optical receiver, characterized in that: A transimpedance amplifier comprising any one of claims 1 to 9.

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