Dual trigger voltage droop detection

Abstract

The present techniques relate to droop detection and there is disclosed circuitry for detecting a voltage droop event, the circuitry configured to: receive a clock signal from a clock distribution network; monitor a measurement value associated with a voltage provided to the circuitry by a power delivery network; provide a first droop detection signal to the clock distribution network in response to the measurement value reaching a first threshold value; cause a control entity to take a first mitigation action in response to the first droop detection signal; provide a second droop detection signal to the clock distribution network in response to the measurement value reaching a second threshold value different to the first threshold value; and cause the control entity to take a second mitigation action in response to the second droop detection signal.

Description

Dual Trigger Voltage Droop Detection

[0001] The present techniques relate to droop detection. In particular, the present techniques relate to detection of voltage droop events in an information processing system and triggering of voltage droop mitigation actions.

[0002] Some computer circuits (e.g. a central processor unit (CPU) or graphics processor unit (GPU)) may experience performance issues. For example, a CPU can generate voltage droops due to large changes in current required from a power delivery network (PDN).

[0003] There is a need for mitigation action to address such performance issues.

[0004] The present techniques relate to addressing or mitigating such performance issues, or improving known mitigation techniques.

[0005] According to a first aspect, there is provided circuitry for detecting a voltage droop event, the circuitry configured to: receive a clock signal from a clock distribution network; monitor a measurement value associated with a voltage provided to the circuitry by a power delivery network; provide a first droop detection signal to the clock distribution network in response to the measurement value reaching a first threshold value; cause a control entity to take a first mitigation action in response to the first droop detection signal; provide a second droop detection signal to the clock distribution network in response to the measurement value reaching a second threshold value different to the first threshold value; and cause the control entity to take a second mitigation action in response to the second droop detection signal.

[0006] Furthermore, there may be a third threshold value that is used to reset both the first and the second detection signals.

[0007] The circuitry may comprise the clock distribution network, the power delivery network and / or the control entity.

[0008] The first mitigation action may comprise modifying a frequency of the clock signal by the clock distribution network. The first mitigation action may comprise decreasing the frequency of the clock signal by the clock distribution network. In this way, a time component may be increased. Alternatively or additionally, the first mitigation action may comprise increasing the frequency of the clock signal by the clock distribution network. The increase in frequency may be prior to or following a decrease in frequency.

[0009] The second mitigation action may comprise pausing the clock. Pausing the clock may allow for a performance to be maintained. The second mitigation action may comprise pausing the clock for a predetermined number of clock cycles before restarting the clock. The predetermined number of cycles may be user-settable and / or resettable. The restarting of the clock may also be caused by the voltage rising above a third threshold. If the measurement value still meets the second threshold value following the restarting of the clock, the second mitigation action may be repeated.

[0010] The second threshold value may be lower than the first threshold value. In this way, the first mitigation action may be carried out prior to the second mitigation action. The first droop detection signal may be provided to the clock distribution network in response to the measurement value falling below the first threshold value. Accordingly, the first mitigation action may be triggered following initiation of a voltage droop. The second droop detection signal may be provided to the clock distribution network in response to the measurement value falling below the second threshold value. Accordingly, the second mitigation action may be triggered following continuance of the voltage droop.

[0011] Alternatively, the first threshold value may be lower than the second threshold value. In this alternative arrangement, the first droop detection signal may be provided to the clock distribution network in response to the measurement value exceeding the first threshold value. Furthermore, in this alternative arrangement, the second droop detection signal may be provided to the clock distribution network in response to the measurement value exceeding the second threshold value. Accordingly, with this alternative arrangement, the first and second mitigation actions may be triggered as a measurement value and voltage rises.

[0012] The third threshold value may be higher than the first threshold value and the second threshold value. In this way, the first droop detection signal and the second droop detection signal will have in-built hysteresis.

[0013] Alternatively, the value may be lower than the first threshold value and the second threshold value. In this way, the first droop detection signal and the second droop detection signal will have in-built hysteresis.

[0014] The measurement value may comprise a score. The score may correspond to a count of a number of gate stages traversed in a delay line during a predetermined number of clock cycles. The score may represent the voltage for a given process lot point and given temperature.

[0015] The predetermined number of clock cycles may be one clock cycle. Alternatively, the predetermined number of clock cycles may be more than one clock cycle, such as two, three, four, five, ten or any other number of clock cycles. A lower number of clock cycles, such as one clock cycle, may mean that the first and second mitigation actions may be triggered quickly enough during a voltage droop event to have an impact on the voltage droop event, for example preventing the voltage droop lowering a voltage to a critical level.

[0016] The measurement value may be categorized into at least three zones, preferably four zones. For example, the categories may include a safe zone, a pre-droop detected zone, a droop detected zone, and a sign-off violated zone. The safe zone may include all values above a third threshold value, wherein no imminent voltage droop is expected. The pre-droop detected zone may include all values between the first and third threshold values, wherein an imminent voltage droop may be expected. The droop detected zone may include all valuesbetween the first and second threshold values. The sign-off violated zone may include all values below the second threshold value. When the measurement value registers in the safe zone, the next voltage droop event may be counted as a new voltage droop event. When the measurement value passes from the droop-detected zone into the safe zone, or when the measurement value passes from the sign-off violated zone into the droop detected zone or the pre-droop detected zone, a subsequent dropping of the measurement value may be considered a continuance of a current voltage droop event and not a subsequent voltage droop event.

[0017] The circuitry may be further configured to perform one or more slope checks. The circuitry may comprise appropriate storage to allow for a slope to be calculated. Providing the first droop detection signal to the clock distribution network may be carried out in response to the measurement value reaching a first threshold value and in response to a calculated slope value being above or below a predetermined slope value.

[0018] The first droop detection signal may be provided as a single bit that is used to notify a critical droop event. Remedial action may be required to ensure reliable system functionality in case of a critical droop event. The second droop detection signal may be provided as a single bit that is used to notify violation of a sign-off threshold violation. Violation of the sign- off threshold is considered to be a sign-off event, which is a droop for which the application of the fall-back clock frequency is not sufficient to ensure correct execution of the circuit function. This can be the result of a rare, deep droop event, brown-out from the power-source or the response programmed when the circuit’s nominal operation point already at the lower voltage bound, where droop includes the risk of hold-timing failures as opposed to the set-up timing failures addressed by frequency reduction. The response to a sign-off event is to hold the clock and rely on static data retention in within the circuit until the event has passed. Violation of the sign-off threshold may mean that immediate safety action may be required, such as powering down an associated load.

[0019] The first and / or second droop detection signal may be synchronised with a rising edge of a clock function.

[0020] The second droop detection signal may trigger a warning, alarm and / or notification to be generated or operated. The second droop detection signal may indicate that there is a safety problem and that an associated system must be stopped. For example, if the system includes an automobile, the second droop detection signal may indicate that a voltage has reached an unsafe level and that immediate action, such as stopping the automobile, may be necessary to , for example, ensure required automotive grade safety.

[0021] The circuitry may allow for a test function to be carried out. For example, a forced voltage droop may be applied to the circuitry and the functioning, characteristics and / oroutputs of the circuitry monitored and assessed for compliance with expected functioning, characteristics and / or outputs.

[0022] According to a second aspect, there is provided a method comprising: providing a clock signal from a clock distribution network to circuitry; monitoring a measurement value associated with a voltage provided to the circuitry by a power delivery network; providing a first droop detection signal to the clock distribution network in response to the measurement value reaching a first threshold value; taking a first mitigation action in response to receiving the first droop detection signal; providing a second droop detection signal to the clock distribution network in response to the measurement value reaching a second threshold value different to the first threshold value; and taking a second mitigation action in response to receiving the second droop detection signal. The first mitigation action may comprise modifying a frequency of the clock signal by the clock distribution network. The first mitigation action may comprise decreasing the frequency of the clock signal by the clock distribution network or the first mitigation action may comprise increasing the frequency of the clock signal by the clock distribution network.

[0023] The second mitigation action may comprise pausing the clock, where the second mitigation action may comprise pausing the clock for a predetermined number of clock cycles before restarting the clock.

[0024] The second threshold value may be lower than the first threshold value or, alternatively, the second threshold value may be higher than the first threshold value.

[0025] The first droop detection signal may be provided to the clock distribution network in response to the measurement value falling below the first threshold value. The second droop detection signal may be provided to the clock distribution network in response to the measurement value falling below the second threshold value.

[0026] The first droop detection signal may be a first order droop event, and the first threshold value may be a droop threshold. The second droop detection signal may be a second or higher order droop event, and the second threshold value may be a sign-off threshold.

[0027] In embodiments, the first threshold value may lower than the second threshold value the first droop detection signal may be provided to the clock distribution network in response to the measurement value exceeding the first threshold value; and the second droop detection signal may provided to the clock distribution network in response to the measurement value exceeding the second threshold value.The measurement value may comprise a score, where the score may correspond to a count of a number of gate stages traversed in a delay line during a predetermined number of clock cycles, where the predetermined number of clock cycles may be one clock cycle.

[0028] The method may include functioning steps of any of the components discussed with reference to the first aspect.

[0029] According to a third aspect, there is provided an apparatus comprising: circuitry; a power delivery network configured to provide current to the circuitry; and a clock distribution network configured to provide a clock signal to the circuitry; wherein the circuitry is configured to: receive a clock signal from the clock distribution network; monitor a measurement value associated with a voltage provided to the circuitry by the power delivery network; provide a first droop detection signal to the clock distribution network in response to the measurement value reaching a first threshold value; and provide a second droop detection signal to the clock distribution network in response to the measurement value reaching a second threshold value different to the first threshold value; wherein the apparatus is configured to: take a first mitigation action in response to receiving the first droop detection signal; and take a second mitigation action in response to receiving the second droop detection signal.

[0030] The circuitry may be the circuitry of the first aspect. In this regard, the third aspect may include any or each of the additional optional features discussed with regards to the first aspect.Brief Description of the Drawings

[0031] Embodiments of the present techniques will now be described by way of example only and with reference to the accompanying drawings, in which:

[0032] FIG. 1 illustratively shows a method diagram showing the steps of a method for droop detection;

[0033] FIG. 2 illustratively shows a top-level diagram of an example droop detector;

[0034] FIG. 3 illustratively shows a graph depicting the four zones into which the score may be characterised;

[0035] FIG. 4 illustratively shows a graph depicting the score over time of two example cases;

[0036] FIG. 5 illustratively shows a trigger management flow diagram describing the course of action taken during each clock cycle for managing triggers;

[0037] FIG. 6 illustratively shows a graph depicting resonance against frequency for two example cases;

[0038] FIG. 7 illustratively shows a graph depicting voltage against time for an example case;

[0039] FIG. 8 illustratively shows an example of a delay monitor having a delay line.

[0040] FIG. 9 illustrates a system and a chip-containing product; and

[0041] FIG. 10 illustrates a droop event and a corresponding mitigation action.Detailed Description

[0042] FIG. 1 illustratively shows a method diagram showing the steps of a method 100 for droop detection. In particular, the method 100 is a dual trigger droop detection method. The first step is to provide 110 a clock signal from a clock distribution network to circuitry. In the present embodiments, the clock distribution network interfaces with various circuity to, for example provide one or more clock signals to the various circuitry (e.g. where the clock distribution network comprises a clock tree or edge tree). Furthermore, the clock distribution network is operable to receive one or more signals from the various circuitry and perform one or more actions responsive to the one or more signals as will be apparent from the description herein. The next step is to monitor 120 a measurement value associated with a voltage provided to the circuitry by a power delivery network.

[0043] The next step is to provide 130 a first droop detection signal to the clock distribution network in response to the measurement value reaching a first threshold value. This step may be considered to be the first trigger of the dual trigger method. Following the step of providing 130 a first droop detection signal, the method 100 includes taking 140 a first mitigation action in response to receiving the first droop detection signal.

[0044] The method 100 also includes providing 150 a second droop detection signal to the clock distribution network in response to the measurement value reaching a second threshold value different to the first threshold value. This step may be considered to be the second trigger of the dual trigger method. Following the step of providing 150 a second droop detection signal, the method 100 includes taking 160 a second mitigation action in response to receiving the second droop detection signal.

[0045] FIG. 2 illustratively shows top-level diagram of an example droop detector 200. The droop detector 200 has two major parts: soft IP 210 and hard IP 220. The soft IP 210 is the combination of a Monitor Local Interface 230 and sensor logic 240. The hard IP 220 includes a sensor core 250. The interface between the soft IP 210 and the hard IP 220 is dependent on the implementation of the hard IP 220.

[0046] As shown in FIG. 2, TRIG_DROOP and TRIG_SOFF are direct outputs of the droop detector. TRIG_DROOP is the trigger that triggers providing 130 the first droop detection signal to the clock distribution network as discussed with reference to FIG. 1. TRIG_SOFF is the trigger that triggers providing 150 the second droop detection signal to the clock distribution network as discussed with reference to FIG. 1. The timing of triggering TRIG_DROOP and TRIF_SOFF is discussed with reference to FIG. 4. TRIG_DROOP and TRIG_SOFF are both synchronised with the rising edge of input FUNC_CLK, which is the clock cycle received from the clock distribution network in the first step of the method 100 described with reference to FIG. 1.

[0047] FIG. 3 illustratively shows a graph 300 depicting the four zones into which the score may be characterised, wherein the x-axis indicates time and the y-axis indicates score. Thescore corresponds to a count of a number of gate stages (e.g. fine gate stages) traversed in a delay line during a clock cycle. The score represents the voltage for a given process lot point and given temperature. The four zones are a safe zone 310, a pre-droop detected zone 320, a droop detected zone 330, and a sign-off violated zone 340.

[0048] The safe zone 310 and the pre-droop detected zone 320 are separated by the AVAL_PRE_DROOP threshold 315, which is an example of the third threshold described with reference to the aspects of the present techniques. Accordingly, the safe zone 310 includes all plot points having a score greater than or equal to the value of the AVAL_PRE_DROOP threshold 315.

[0049] The pre-droop detected zone 320 and the droop detected zone 330 are separated by the AVAL_DROOP threshold 325, which is an example of the first threshold described with reference to the aspects of the present techniques. Accordingly, the pre-droop detected zone 320 includes all plot points having a score less than the value of the AVAL_PRE_DROOP threshold 315 but greater than or equal to the value of the AVAL_DROOP threshold 325.

[0050] The droop detected zone 330 and the sign-off violated zone 340 are separated by the AVAL_SIGNOFF threshold 335, which is an example of the second threshold described with reference to the aspects of the present techniques. Accordingly, the droop detected zone 330 includes all plot points having a score less than the value of the AVAL_DROOP threshold 325 but greater than or equal to the value of the AVAL_SIGNOFF threshold 335.

[0051] It follows, therefore, that the sign-off violated zone 340 includes all plot points having a score less than the value of the AVAL_SIGNOFF threshold 335.

[0052] FIG. 4 illustratively shows a graph 400 depicting the score over time of two example cases, a first case 410 (Case-A) and a second case 420 (Case-B). The time axis is quantized in FUNC_CLK cycles, such that each vertical grid line corresponds to a single FUNC_CLK cycle. It can be seen that the score for each case 410, 420 is measured during each FUNC_CLK cycle. The circuitry includes the necessary storage or memory to store the necessary number of scores over time for a voltage droop to be identified. FIG. 4 also depicts the signal waveforms corresponding to TRIG_DROOP and TRIG_SOFF for the first case (Case-A) and second case (Case-B).

[0053] The first case 410 includes a drop in score from the safe zone 310, beyond the AVAL_PRE_DROOP threshold 315, into the pre-droop detected zone 320. The first case 410 subsequently includes a drop in score from the pre-droop detected zone 320, beyond the AVAL_DROOP threshold 325, into the droop detected zone 330. The score passing the AVAL_DROOP threshold 325 triggers the sending of the first droop detection signal discussed herein. The first case 410 subsequently includes a drop in score from the droop detected zone 330, beyond the AVAL_SIGNOFF threshold 335, into the sign-off violated zone 340. The score passing the AVAL_SIGNOFF threshold 335 triggers the sending of the second droopdetection signal discussed herein. The score increases before decreasing again. The passing of the score from the safe zone 310 into the sign-off violated zone 340 occurs twice in the first case 410, such that the first and second droop detection signals are provided twice.

[0054] The second case 410 includes a drop in score from the safe zone 310, beyond the AVAL_PRE_DROOP threshold 315, into the pre-droop detected zone 320. The second case 420 subsequently includes a drop in score from the pre-droop detected zone 320, beyond the AVAL_DROOP threshold 325, into the droop detected zone 330. The score passing the AVAL_DROOP threshold 325 triggers the sending of the first droop detection signal discussed herein. The second case 420 subsequently includes an increase in score into the pre-droop detected zone 320, such that the score does not meet the AVAL_SIGNOFF threshold 335 or enter into the sign-off violated zone 340. Accordingly, there is no sending of the second droop detection signal discussed herein. The score is not shown to reach the safe zone 310 before again decreasing.

[0055] A drop in score into the droop detected zone 330 may be considered to be a first order droop event, which is the highest resonance frequency of the Power Delivery Network (PDN). The circuitry provides protection against a first order droop event by causing action to be taken in response to the first droop detection signal, for example by decreasing the frequency of the clock signal by the clock distribution network. The functionality is not limited to protecting against first order droop events. In other examples the functionality may provide protection against higher order droop events (e.g. 2ndorder droop events, 3rdorder droop events etc.). As an illustrative example, there are chip designs that have high density capacitors (e.g. MIM capacitors) that provide a shallow first order droop event so for such designs the droop events that are mitigated may not be first order droop events.

[0056] A drop in score into the sign-off violated zone 340 may be considered to be a higher order droop event, such as a second or third order droop event. The circuitry provides protection against a higher order droop event by causing action to be taken in response to the second droop detection signal, for example by pausing the clock.

[0057] Furthermore, there may be other thresholds which may result in further mitigation signals. For example, a third threshold value may be higher than the first threshold value and the second threshold value. In this way, the first droop detection signal and the second droop detection signal will have in-built hysteresis.

[0058] Alternatively, the third (or an additional fourth) threshold value may be lower than the first threshold value and the second threshold value. In this way, the first droop detection signal and the second droop detection signal will have in-built hysteresis.

[0059] In an illustrative example, both the first and the second droop detection signals are reset in response to the third (or fourth) thresholds being met.

[0060] It can be seen in FIG. 4 that both the first case 410 and the second case 420 include a drop in score from the safe zone 310, past the AVAL_PRE_DROOP 315 threshold and into the pre-droop detected zone 320, and then past the AVAL_DROOP threshold 325 and into the droop detected zone 330. The first case 410 and the second case 420 both include drops in score, followed by increases in score, then followed by a further drop in score.

[0061] In the first case 410, the increase in score is sufficient to bring the score back above the AVAL_PRE_DROOP threshold 315 and into the safe zone 310. Once the score re-enters the safe zone 310, the voltage droop is considered to have concluded. The subsequent drop in score into the droop detected zone 330 is considered to be a second voltage droop event.

[0062] However, in the second case 420, the increase in score is not sufficient to bring the score back above the AVAL_PRE_DROOP threshold 315 and into the safe zone 310. Accordingly, the subsequent drop in score into the droop detected zone 330 is considered to be a continuation of the first voltage droop event.

[0063] In the first case 410, a droop event counter is incremented to show two droop events. However, in the second case 420, a droop event counter is incremented to show only one droop event.

[0064] Whilst FIG. 4 generally depicts the AVAL_PRE_DROOP 315 being higher than both the AVAL_DROOP threshold 325 and the AVAL_SIGNOFF threshold 335. Such functionality may occur when e.g. voltage and the measurement value have a positive correlation. In alternative embodiments, for example when voltage and the measurement value have a negative correlation (e.g. stage delay), AVAL_PRE_DROOP 315 may be lower than AVAL_DROOP threshold 325 which, in turn, may be lower than the AVAL_SIGNOFF threshold 335.

[0065] FIG. 5 illustratively shows trigger management flow diagram describing the course of action taken during each clock cycle for managing triggers. The flow begins by calculating a score in the respective clock cycle and determining if the score is in the safe zone, the predroop detected zone, the droop detected zone, or the sign-off violated zone. The circuitry includes four registers, namely a TRIG_DROOP register, a TRIG_SOFF register, an int_SKIP_CHECKS_TILL_NEXT_PRE_DROOP register and an int_C LOG KS_TO_D ROOP register.

[0066] If the score is in the safe zone, each of the four registers are reset and the flow ends.

[0067] If the score is in the pre-droop detected zone, a state of the int_CLOCKS_TO_DROOP register is interrogated. If the int_CLOCKS_TO_DROOP register does not meet a O’xF condition, the int_CLOCKS_TO_DROOP register is incremented by 1’b1 and the flow ends. If the int_CLOCKS_TO_DROOP register does meet a OxF condition, the int_SKIP_CHECKS_TILL_NEXT_PRE_DROOP register is set to 1’b1 and the flow ends.

[0068] If the score is in the droop detected zone, the int_SKIP_CHECKS_TILL_NEXT_PRE_DROOP register is interrogated. If the int_SKIP_CHECKS_TILL_NEXT_PRE_DROOP register is set at 1’b1 , the flow ends. If the int_SKIP_CHECKS_TILL_NEXT_PRE_DROOP register is not set at 1’b1 , the level of the int_C LOG KS_TO_D ROOP is compared to the level of AVAL_CLOCKS_TO_DROOP. If int_CLOCKS_TO_DROOP is not less than or equal to AVAL_CLOCKS_TO_DROOP, the int_SKIP_CHECKS_TILL_NEXT_PRE_DROOP register is set to Tb1 and the flow ends. If int_CLOCKS_TO_DROOP is less than or equal to AVAL_CLOCKS_TO_DROOP, the TRIG_DROOP is set to 1’b1 , thereby causing a first mitigation action, and the flow ends.

[0069] If the score is in the sign-off violated zone, TRIG_SOFF and TRIG_DROOP are set to 1’b1 , meaning both the first and second mitigation actions are caused, the monitor trigger command is sent to the MGI, and the flow ends.

[0070] FIG. 6 illustratively shows a graph 600 depicting resonance against frequency for two example cases. The first case 610 includes a first peak 611 , a second peak 612 and a third peak 613. The first peak 611 has a relatively high impedance. The second peak 612 and third peak 613 have a relatively low impedance. Accordingly, the first case 610 may be considered to be a first order voltage droop. Only TRIG_DROOP may be relevant in the first case 610. In the second case 620, the first peak 621 and the second peak 622 have a relatively high impedance. The third peak 623 has a relatively low impedance. Accordingly, the second case 620 may be considered to be a second order voltage droop. Both the TRIG_DROOP and TRIG_SOFF may be relevant in the second case 620.

[0071] FIG. 7 illustratively shows a graph 700 showing a transient voltage plot depicting voltage against time for an example case. In the depicted example case, three voltage droops occur. A first droop 710 brings the voltage below the AVAL_PRE_DROOP threshold but not below the AVAL_DROOP threshold. Therefore, no mitigation action is completed. A second droop 720 does not bring the voltage below the AVAL_PRE_DROOP threshold. Therefore, no mitigation action is completed. A third droop 730 is caused by a 3.5GHz large load step, and the voltage falls below the AVAL_PRE_DROOP threshold and subsequently below the AVAL_DROOP threshold. Accordingly, mitigation action is required. In order to ensure continued performance of the circuit, the clock is paused for 3 cycles before the frequency is set to 3GHz. This mitigation action brings the voltage back above the AVAL_PRE_DROOP threshold and to a safe level. The restarting of the clock causes a step down in voltage, taking the voltage below the AVAL_PRE_DROOP threshold. The circuit is operated under 3GHz for 512 clock cycles before the clock pausing and restarting is repeated four times. Depending on the level of the AVAL_PRE_DROOP threshold, the pausing and restarting may be completed a different number of times. Once the voltage has reached a steady level above the AVAL_PRE_DROOP threshold, the 3.5GHz operation is restarted, and the steadyoperation can be seen in FIG. 7 to re-enter the safe zone above the AVAL_PRE_DROOP threshold.

[0072] It can be seen, therefore, that the mitigation action taken in response to the voltage falling below the AVAL_DROOP threshold has worked to move the voltage back in to the safe zone above the AVAL_PRE_DROOP threshold and away from a safety critical low voltage level.

[0073] An example of a delay monitor 808 having a delay line which may be used in accordance with the present techniques is illustratively shown in FIG. 8.

[0074] The delay monitor 808 comprises a coarse delay line 802, a fine delay line 804 and an encoder 806. The delay monitor optionally comprises a fractional offset 808 between the coarse delay and the fine delay.

[0075] The measurement value or score is provided by the output of the encoder. The measurement value or score corresponds to a count of the number of fine gate stages traversed in the fine delay line 804 during a predetermined number of clock cycles. The output may be measured every output clock cycle of a clock distribution network and averaged over a predetermined number of clock cycles for analysis.

[0076] It will be appreciated that the delay line 804 is only provided as an example of method to provide the measurement value.

[0077] As shown in FIG. 9, one or more packaged chips 400, with the circuitry described above implemented on one chip or distributed over two or more of the chips, are manufactured by a semiconductor chip manufacturer. In some examples, the chip product 400 made by the semiconductor chip manufacturer may be provided as a semiconductor package which comprises a protective casing (e.g. made of metal, plastic, glass or ceramic) containing the semiconductor devices implementing the circuitry described above and connectors, such as lands, balls or pins, for connecting the semiconductor devices to an external environment. Where more than one chip 400 is provided, these could be provided as separate integrated circuits (provided as separate packages), or could be packaged by the semiconductor provider into a multi-chip semiconductor package (e.g. using an interposer, or by using three- dimensional integration to provide a multi-layer chip product comprising two or more vertically stacked integrated circuit layers).

[0078] In some examples, a collection of chiplets (i.e. small modular chips with particular functionality) may itself be referred to as a chip. A chiplet may be packaged individually in a semiconductor package and / or together with other chiplets into a multi-chiplet semiconductor package (e.g. using an interposer, or by using three-dimensional integration to provide a multilayer chiplet product comprising two or more vertically stacked integrated circuit layers).

[0079] The one or more packaged chips 400 are assembled on a board 402 together with at least one system component 404 to provide a system 406. For example, the board maycomprise a printed circuit board. The board substrate may be made of any of a variety of materials, e.g. plastic, glass, ceramic, or a flexible substrate material such as paper, plastic or textile material. The at least one system component 404 comprise one or more external components which are not part of the one or more packaged chip(s) 400. For example, the at least one system component 404 could include, for example, any one or more of the following: another packaged chip (e.g. provided by a different manufacturer or produced on a different process node), an interface module, a resistor, a capacitor, an inductor, a transformer, a diode, a transistor and / or a sensor.

[0080] A chip-containing product 416 is manufactured comprising the system 406 (including the board 402, the one or more chips 400 and the at least one system component 404) and one or more product components 412. The product components 412 comprise one or more further components which are not part of the system 406. As a non-exhaustive list of examples, the one or more product components 412 could include a user input / output device such as a keypad, touch screen, microphone, loudspeaker, display screen, haptic device, etc.; a wireless communication transmitter / receiver; a sensor; an actuator for actuating mechanical motion; a thermal control device; a further packaged chip; an interface module; a resistor; a capacitor; an inductor; a transformer; a diode; and / or a transistor. The system 406 and one or more product components 412 may be assembled on to a further board 414.

[0081] The board 402 or the further board 414 may be provided on or within a device housing or other structural support (e.g. a frame or blade) to provide a product which can be handled by a user and / or is intended for operational use by a person or company.

[0082] The system 406 or the chip-containing product 416 may be at least one of: an enduser product, a machine, a medical device, a computing or telecommunications infrastructure product, or an automation control system. For example, as a non-exhaustive list of examples, the chip-containing product could be any of the following: a telecommunications device, a mobile phone, a tablet, a laptop, a computer, a server (e.g. a rack server or blade server), an infrastructure device, networking equipment, a vehicle or other automotive product, industrial machinery, consumer device, smart card, credit card, smart glasses, avionics device, robotics device, camera, television, smart television, DVD players, set top box, wearable device, domestic appliance, smart meter, medical device, heating / lighting control device, sensor, and / or a control system for controlling public infrastructure equipment such as smart motorway or traffic lights.

[0083] FIG. 10 illustrates a droop event and a corresponding mitigation action. The score during the droop event generally follows that of the first case 410 shown in FIG. 4, passing from the safe zone into the sign-off violated zone, and back into the safe zone. As discussed with reference to FIG. 4, when the score crosses the AVAL_DROOP threshold from the pre-droop detected zone into the droop detected zone, the clock frequency is reduced. Accordingly, the system switches from a fast clock to a slow clock.

[0084] The system continues with the slow clock until the score rises into the safe zone, crossing the AVAL_PRE_DROOP threshold. Once the score re-enters the safe zone, the droop event is considered to be over or concluded, and the frequency is increased back to the original frequency to return the system back to the fast clock. Accordingly, the lower frequency and slow clock arrangement is used only when the score drops into the droop detected zone, until the score re-enters the safe zone.

[0085] As will be appreciated by one skilled in the art, the present technology may be embodied as a method, a circuit or a computer readable medium comprising data and imperatives to cause construction of a circuit. Accordingly, the present techniques may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware. Where the word “component” is used, it will be understood by one of ordinary skill in the art to refer to any portion of any of the above embodiments.

[0086] Concepts described herein may be embodied in computer-readable code for fabrication of an apparatus that embodies the described concepts. For example, the computer-readable code can be used at one or more stages of a semiconductor design and fabrication process, including an electronic design automation (EDA) stage, to fabricate an integrated circuit comprising the apparatus embodying the concepts. The above computer- readable code may additionally or alternatively enable the definition, modelling, simulation, verification and / or testing of an apparatus embodying the concepts described herein.

[0087] For example, the computer-readable code for fabrication of an apparatus embodying the concepts described herein can be embodied in code defining a hardware description language (HDL) representation of the concepts. For example, the code may define a register- transfer-level (RTL) abstraction of one or more logic circuits for defining an apparatus embodying the concepts. The code may define a HDL representation of the one or more logic circuits embodying the apparatus in Verilog, SystemVerilog, Chisel, or VHDL (Very High- Speed Integrated Circuit Hardware Description Language) as well as intermediate representations such as FIRRTL. Computer-readable code may provide definitions embodying the concept using system-level modelling languages such as SystemC and SystemVerilog or other behavioural representations of the concepts that can be interpreted by a computer to enable simulation, functional and / or formal verification, and testing of the concepts.

[0088] Additionally or alternatively, the computer-readable code may define a low-level description of integrated circuit components that embody concepts described herein, such as one or more netlists or integrated circuit layout definitions, including representations such asGDSII. The one or more netlists or other computer-readable representation of integrated circuit components may be generated by applying one or more logic synthesis processes to an RTL representation to generate definitions for use in fabrication of an apparatus embodying the present techniques. Alternatively or additionally, the one or more logic synthesis processes can generate from the computer-readable code a bitstream to be loaded into a field programmable gate array (FPGA) to configure the FPGA to embody the described concepts. The FPGA may be deployed for the purposes of verification and test of the concepts prior to fabrication in an integrated circuit or the FPGA may be deployed in a product directly.

[0089] The computer-readable code may comprise a mix of code representations for fabrication of an apparatus, for example including a mix of one or more of an RTL representation, a netlist representation, or another computer-readable definition to be used in a semiconductor design and fabrication process to fabricate an apparatus embodying the present techniques. Alternatively or additionally, the concept may be defined in a combination of a computer-readable definition to be used in a semiconductor design and fabrication process to fabricate an apparatus and computer-readable code defining instructions which are to be executed by the defined apparatus once fabricated.

[0090] Such computer-readable code can be disposed in any known transitory computer- readable medium (such as wired or wireless transmission of code over a network) or non- transitory computer-readable medium such as semiconductor, magnetic disk, or optical disc. An integrated circuit fabricated using the computer-readable code may comprise components such as one or more of a central processing unit, graphics processing unit, neural processing unit, digital signal processor or other components that individually or collectively embody the concept.

[0091] In the present application, the words “configured to...” are used to mean that an element of an apparatus has a configuration able to carry out the defined operation. In this context, a “configuration” means an arrangement or manner of interconnection of hardware or software. For example, the apparatus may have dedicated hardware which provides the defined operation, or a processor or other processing device may be programmed to perform the function. “Configured to” does not imply that the apparatus element needs to be changed in any way in order to provide the defined operation.

[0092] In the present application, lists of features preceded with the phrase “at least one of” mean that any one or more of those features can be provided either individually or in combination. For example, “at least one of: [A], [B] and [C]” encompasses any of the following options: A alone (without B or C), B alone (without A or C), C alone (without A or B), A and B in combination (without C), A and C in combination (without B), B and C in combination (without A), or A, B and C in combination.

[0093] Although illustrative embodiments of the present techniques have been described in detail herein with reference to the accompanying drawings, it is to be understood that the present techniques are not limited to those precise embodiments, and that various changes and modifications can be effected therein by one skilled in the art without departing from the scope of the present techniques as defined by the appended claims.

Claims

Claims1. Circuitry for detecting a voltage droop event, the circuitry configured to: receive a clock signal from a clock distribution network; monitor a measurement value associated with a voltage provided to the circuitry by a power delivery network; provide a first droop detection signal to the clock distribution network in response to the measurement value reaching a first threshold value; cause a control entity to take a first mitigation action in response to the first droop detection signal; provide a second droop detection signal to the clock distribution network in response to the measurement value reaching a second threshold value different to the first threshold value; and cause the control entity to take a second mitigation action in response to the second droop detection signal.

2. The circuitry of claim 1, wherein the first mitigation action comprises modifying a frequency of the clock signal by the clock distribution network.

3. The circuitry of claim 2, wherein the first mitigation action comprises decreasing the frequency of the clock signal by the clock distribution network.

4. The circuitry of claim 2 or 3, wherein the first mitigation action comprises increasing the frequency of the clock signal by the clock distribution network.

5. The circuitry of any preceding claim, wherein the second mitigation action comprises pausing the clock.

6. The circuitry of claim 5, wherein the second mitigation action comprises pausing the clock for a predetermined number of clock cycles before restarting the clock.

7. The circuitry of any preceding claim, wherein the second threshold value is lower than the first threshold value or wherein the second threshold value is higher than the first threshold value.

8. The circuitry of any preceding claim, wherein the first droop detection signal is provided to the clock distribution network in response to the measurement value falling below the first threshold value.

9. The circuitry of any preceding claim, wherein the second droop detection signal is provided to the clock distribution network in response to the measurement value falling below the second threshold value.

10. The circuitry of any of claims 1 to 6, wherein: the first threshold value is lower than the second threshold value; the first droop detection signal is provided to the clock distribution network in response to the measurement value exceeding the first threshold value; and the second droop detection signal is provided to the clock distribution network in response to the measurement value exceeding the second threshold value.

11. The circuitry of any preceding claim, wherein the measurement value comprises a score, the score corresponding to a count of a number of gate stages traversed in a delay line during a predetermined number of clock cycles.

12. The circuitry of claim 11 , wherein the predetermined number of clock cycles is one clock cycle.13 The circuitry of any preceding claim, where the circuitry is to reset both the first and the second detection signals responsive to the measurement value meeting a third threshold value.

14. A method comprising: providing a clock signal from a clock distribution network to circuitry; monitoring a measurement value associated with a voltage provided to the circuitry by a power delivery network; providing a first droop detection signal to the clock distribution network in response to the measurement value reaching a first threshold value; taking a first mitigation action in response to receiving the first droop detection signal; providing a second droop detection signal to the clock distribution network in response to the measurement value reaching a second threshold value different to the first threshold value; andtaking a second mitigation action in response to receiving the second droop detection signal.

15. The method of claim 14, wherein the first mitigation action comprises modifying a frequency of the clock signal by the clock distribution network.

16. The method of claim 15, wherein the first mitigation action comprises decreasing the frequency of the clock signal by the clock distribution network.

17. The method of claim 15 or 16, wherein the first mitigation action comprises increasing the frequency of the clock signal by the clock distribution network.

18. The method of any of claims 14 to 17, wherein the second mitigation action comprises pausing the clock.

19. The method of claim 18, wherein the second mitigation action comprises pausing the clock for a predetermined number of clock cycles before restarting the clock.

20. The method of any of claims 14 to 19, wherein the first droop detection signal is provided to the clock distribution network in response to the measurement value falling below the first threshold value.

21. The method of any of claims 14 to 20, wherein the second droop detection signal is provided to the clock distribution network in response to the measurement value falling below the second threshold value.

22. An apparatus comprising: circuitry; a power delivery network configured to provide current to the circuitry; and a clock distribution network configured to provide a clock signal to the circuitry; wherein the circuitry is configured to: receive a clock signal from the clock distribution network; monitor a measurement value associated with a voltage provided to the circuitry by the power delivery network; provide a first droop detection signal to the clock distribution network in response to the measurement value reaching a first threshold value; andprovide a second droop detection signal to the clock distribution network in response to the measurement value reaching a second threshold value different to the first threshold value; wherein the apparatus is configured to: take a first mitigation action in response to receiving the first droop detection signal; and take a second mitigation action in response to receiving the second droop detection signal.

23. A system comprising: the circuitry of any of claims 1 to 13, implemented in at least one packaged chip; at least one system component; and a board, wherein the at least one packaged chip and the at least one system component are assembled on the board.

24. A chip-containing product comprising the system of claim 23 assembled on a further board with at least one other product component.

25. A non-transitory computer-readable medium to store computer-readable code for fabrication of the circuitry for detecting a voltage droop event of any of claims 1-13.

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