Reception circuit, semiconductor integrated circuit, and transmission / reception system

Abstract

This reception circuit includes a clock generation circuit that generates a reception clock signal, and a plurality of data reception circuits that respectively receive separate data signals on the basis of the reception clock signal. The clock generation circuit includes: a variable delay circuit for generating a delay reference clock signal by delaying, by a delay amount corresponding to a delay control signal, a reference clock signal received by a clock reception circuit; a delay synchronization circuit for sequentially delaying the delay reference clock signal to generate a plurality of internal clock signals; and a selector circuit for selecting one of the plurality of internal clock signals on the basis of a phase selection signal and outputting the selected one as a reception clock signal. Thus, it is possible to generate a clock signal capable of receiving a plurality of data signals at an appropriate timing while suppressing an increase in power consumption.

Description

Receiving circuit, semiconductor integrated circuit, and transmitting / receiving system

[0001] The present invention relates to a receiving circuit, a semiconductor integrated circuit, and a transmitting / receiving system.

[0002] A phase adjustment circuit is known in which an input signal is supplied to a phase shift circuit and a variable delay circuit connected in series, the phase of the delayed input signal and a reference signal is detected by a phase detection circuit, and the detection result is fed back to the phase shift circuit and the variable delay circuit to adjust the phase.

[0003] A known synchronous circuit supplies a clock signal to two phase shift circuits, each connected in series with a fine shift circuit for finely adjusting the phase and a coarse shift circuit for coarsely adjusting the phase, and a control circuit selects one of the phase shift circuits to adjust the phase of the clock signal. The control circuit operates the fine shift circuit of the selected phase shift circuit to adjust the phase, operates the fine shift circuit and the coarse shift circuit of the unselected phase shift circuit, and switches the selected phase shift circuit when the delay amount of the fine shift circuit reaches a threshold.

[0004] A delay-locked loop (DLL) circuit is known, which has a phase interpolator and a variable delay circuit connected in series, and outputs an output clock signal from the variable delay circuit that has the same phase as an input clock signal supplied to the phase interpolator. This type of DLL circuit generates an output clock signal without operating the phase interpolator until the DLL is locked, and then operates the phase interpolator after the DLL is locked, thereby generating an output clock signal with reduced jitter.

[0005] Japanese Patent Application Publication No. 2004 / 0130366 Japanese Patent Application Publication No. 2008 / 0252346

[0006] Incidentally, a receiving circuit having a plurality of data receiving circuits, each of which receives a plurality of data signals transmitted together with a clock signal via a transmission line, can receive the correct data signals by correcting the phase shift of the plurality of data signals or the clock signal that occurs in the transmission line, etc. For example, each of the plurality of data receiving circuits may be provided with a phase shift circuit that corrects the phase of the clock signal to an appropriate phase.

[0007] However, if a phase shift circuit is provided for each of multiple data receiving circuits, the number of phase shift circuits increases as the number of received data signals increases, resulting in increased power consumption by the receiving circuits. Also, while it is conceivable to provide a common phase shift circuit for multiple data receiving circuits and adjust the phase of the clock signal to match one of the multiple data signals, no consideration has been given to which data signal the phase of the clock signal should be adjusted to match.

[0008] The present invention has been made in view of the above points, and has as its object to generate a clock signal that can receive a plurality of data signals at appropriate timing while suppressing an increase in power consumption.

[0009] In one aspect of the present invention, a receiving circuit has a clock generation circuit that generates a received clock signal and a plurality of data receiving circuits that each receive a separate data signal based on the received clock signal, and the clock generation circuit has a clock receiving circuit that receives a reference clock signal, a variable delay circuit that delays the reference clock signal received by the clock receiving circuit by a delay amount corresponding to a delay control signal to generate a delayed reference clock signal, a delay synchronization circuit that sequentially delays the delayed reference clock signal to generate a plurality of internal clock signals, and a selector circuit that selects one of the plurality of internal clock signals based on a phase selection signal and outputs it as the received clock signal.

[0010] According to the disclosed technology, it is possible to generate a clock signal that allows a plurality of data signals to be received at appropriate timing while suppressing an increase in power consumption.

[0011] 1 is a block diagram illustrating a problem of a receiving circuit that receives a plurality of data signals together with a clock signal in a system that transmits and receives data signals. FIG. 2 is a block diagram illustrating an example of a system that transmits and receives data signals in an embodiment. FIG. 3 is a block diagram illustrating an example of a clock receiver, a variable delay circuit, and a DLL circuit of FIG. 2. FIG. 4 is a circuit diagram illustrating an example of a variable delay circuit of FIG. 2. FIG. 5 is a timing diagram illustrating an example of a clock signal generated by the DLL circuit of FIG. 3. FIG. 6 is an explanatory diagram illustrating an example of an operation for finely adjusting the phase of a clock signal using the variable delay circuit of FIG. 4. FIG. 7 is a flow chart illustrating an example of a calibration operation of the receiving circuit of FIG. 2. FIG. 8 is a flow chart illustrating an example of an operation of step S200 of FIG. 9. FIG. 10 is a flow chart illustrating ...

[0012] Hereinafter, embodiments will be described with reference to the drawings. In the following, a symbol indicating a signal is also used to indicate a signal line, a signal terminal, or a signal node. A symbol indicating a voltage is also used to indicate a voltage line, a voltage terminal, or a voltage node to which a voltage is supplied. When signal lines are complementary signal lines, a single signal line indicates the complementary signal line.

[0013] 1 is a block diagram illustrating a receiver circuit for receiving multiple data signals together with a clock signal in a data signal transmission / reception system. The system 100 shown in FIG. 1 includes a root die 200 and an endpoint die 300 interconnected via a transmission path 110.

[0014] The root die 200 includes a phase-locked loop (PLL) circuit 210, a clock driver 220, and multiple data transmission circuits 230. Each data transmission circuit 230 includes a serializer (SER) 231 and a data driver 232. The endpoint die 300 includes a receiving circuit 310 and user logic 340. The receiving circuit 310 includes a clock receiver 320 and multiple data receiving circuits 330. Each data receiving circuit 330 includes a data receiver 331, a slicer 332, a deserializer (DES) 333, and a phase shift circuit 334.

[0015] In the root die 200, a PLL circuit 210 generates a transmit clock signal TCLK based on an input clock signal (not shown), the transmit clock signal TCLK being in phase with the input clock signal. A clock driver 220 transmits the transmit clock signal TCLK to a clock receiver 320 of the endpoint die 300 via a transmission path 110. In each data transmission circuit 230, a serializer 231 converts an n-bit parallel data signal DT into a serial signal in synchronization with the transmit clock signal TCLK and outputs the serial signal to a data driver 232. The data driver 232 transmits the data signal received from the serializer 231 to a corresponding data reception circuit 330 of the endpoint die 300 via the transmission path 110.

[0016] In the endpoint die 300, the clock receiver 320 receives the transmit clock signal TCLK from the root die 200 via the transmission path 110 and outputs the receive clock signal RCLK to the phase shift circuit 334 of each data receiving circuit 330. In each data receiving circuit 330, the phase shift circuit 334 includes an analog circuit such as an operational amplifier, and shifts the phase of the receive clock signal RCLK based on a set shift amount and outputs the shifted signal to the slicer 332.

[0017] For example, before receiving a data signal to be processed by the user logic 340 from the root die 200, the endpoint die 300 performs calibration to determine the amount of phase shift of the receive clock signal RCLK for each data receiving circuit 330. For example, for each data receiving circuit 330, the endpoint die 300 determines the amount of shift to set the phase of the receive clock signal RCLK to the center of the transition edges on both sides of each test data signal transmitted from the corresponding data transmitting circuit 230.

[0018] The data receiver 331 receives a serial data signal transmitted from the corresponding data transmission circuit 230 in the route die 200 and outputs the received data signal to the slicer 332. The slicer 332 acquires the data signal in synchronization with the phase-shifted reception clock signal RCLK received from the phase shift circuit 334 and outputs the acquired data signal to the deserializer 333. The deserializer 333 converts the serial data signal received from the slicer 332 into an n-bit parallel data signal and outputs it to the user logic 340. The deserializer 333 is an example of a serial-to-parallel conversion circuit that converts multiple serial data signals received sequentially via the transmission path 110 into parallel data signals.

[0019] The user logic 340 processes the n-bit data signals received from each of the multiple data receiving circuits 330. For example, the user logic 340 may include a processor, a memory, or a logic circuit.

[0020] 1 has a phase shift circuit 334 including an analog circuit such as an operational amplifier for each data receiving circuit 330, and therefore consumes more power than when there is no phase shift circuit 334. Furthermore, the more lanes there are in the transmission path 110 that transmits data signals, the more phase shift circuits 334 are mounted on the endpoint die 300, which increases the power consumption of the endpoint die 300.

[0021] 2 shows an example of a system for transmitting and receiving data signals according to an embodiment. Elements similar to those shown in FIG. 1 are designated by the same reference numerals, and detailed descriptions thereof will be omitted. The system 100A shown in FIG. 2 includes a root die 200A and an endpoint die 300A interconnected via a transmission path 110 including multiple lanes.

[0022] The root die 200A and the endpoint die 300A may be semiconductor integrated circuits such as a system on chip (SoC) or a field-programmable gate array (FPGA). For example, the system 100A may adopt Bunch of Wires (BoW), which is a die-to-die (D2D) interconnect standard.

[0023] The root die 200A includes a PLL circuit 210, a clock driver 220, and a plurality of data transmission circuits 230A. Each data transmission circuit 230A includes a data generation circuit (DTGEN) 233, a selection circuit (SEL) 234, a serializer (SER) 231, and a data driver 232.

[0024] The endpoint die 300A includes a receiving circuit 310A and user logic 340. The receiving circuit 310A includes a clock receiver 320, a variable delay circuit 350, a DLL circuit 360, a phase adjustment sequencer 370, a phase selector 380, and multiple data receiving circuits 330A. Each data receiving circuit 330A includes a data receiver 331, a slicer 332, and a deserializer (DES) 333. The user logic 340 is an example of a processing circuit that processes multiple data signals received by the receiving circuit 310A. Note that the user logic 340 may be provided outside the endpoint die 300A.

[0025] The clock receiver 320, variable delay circuit 350, DLL circuit 360, and phase selector 380 are an example of a clock generation circuit that generates output clock signals OCLK and OCLKX. The clock receiver 320 is an example of a clock reception circuit that receives the transmission clock signal TCLK. The DLL circuit 360 is an example of a delay locked loop circuit. The phase selector 380 is an example of a selector circuit.

[0026] In the root die 200A, the clock driver 220 of each data transmission circuit 230 transmits a transmission clock signal TCLK to the clock receiver 320 of the endpoint die 300A via the transmission path 110. Within the root die 200A, a calibration signal CALB indicating a calibration mode is generated based on an instruction from the endpoint die 300A. When the calibration signal CALB indicates a calibration mode, the data generation circuit 233 generates a test data signal TDT and outputs it to the selection circuit 234. The calibration signal CALB is generated during the calibration mode in which the endpoint die 300A searches for an appropriate timing phase of the clock signal that enables the endpoint die 300A to correctly acquire a data signal.

[0027] The calibration signal CALB may be sequentially supplied to any of the multiple data transmission circuits 230A. In this case, one of the data transmission circuits 230A generates the test data signal TDT and transmits it to the endpoint die 300A. Alternatively, the calibration signal CALB may be commonly supplied to the multiple data transmission circuits 230A. In this case, all of the data transmission circuits 230A simultaneously generate the test data signal TDT and transmit it to the endpoint die 300A.

[0028] When the calibration signal CALB does not indicate the calibration mode, i.e., when the system is operating, the selection circuit 234 selects the n-bit data signal DT and outputs it to the serializer 231. When the calibration signal CALB indicates the calibration mode, i.e., when the system is in calibration mode, the selection circuit 234 selects the n-bit test data signal TDT and outputs it to the serializer 231.

[0029] The serializer 231 converts an n-bit data signal DT or test data signal TDT into a serial signal in synchronization with the transmission clock signal TCLK, and transmits the converted serial data signal to the corresponding data receiving circuit 330A via the data driver 232. For example, the multiple data transmitting circuits 230A convert separate data signals DT, which are multiple data signals independent of one another, into serial signals using the serializer 231 and transmit the serial signals to the transmission path 110. In other words, separate data signals DT, which are independent of one another, are transmitted to multiple lanes in the transmission path 110 connected to the multiple data transmitting circuits 230A.

[0030] In the endpoint die 300A, the clock receiver 320 receives the transmit clock signal TCLK from the root die 200A via the transmission path 110 and outputs the receive clock signal RCLK to the variable delay circuit 350. The variable delay circuit 350 adjusts (delays) the phase of the receive clock signal RCLK in accordance with the delay code DCODE and outputs the adjusted phase as the clock signal DCLK to the DLL circuit 360. The DLL circuit 360 generates clock signals P0, P45, P90, P135, M180, M225, M270, and M315, which have phase differences of 0°, 45°, 90°, 135°, 180°, 225°, 270°, and 315° from the clock signal received from the variable delay circuit 350, and outputs the signals to the phase selector 380. Clock signals P0, P45, P90, P135, M180, M225, M270, and M315 are examples of internal clock signals. An example of the DLL circuit 360 is shown in FIG.

[0031] The phase adjustment sequencer 370 operates during a calibration mode and monitors the test data signals TDT output from the multiple data receiving circuits 330A. The calibration mode is an example of a test mode. The phase adjustment sequencer 370 then generates a phase selection signal PSEL and a delay code DCODE for generating appropriate output clock signals OCLK and OCLKX for all of the data receiving circuits 330A, and outputs these signals to the phase selector 380 and the variable delay circuit 350, respectively. The phase adjustment sequencer 370 is an example of a phase adjustment control circuit.

[0032] This allows each data receiving circuit 330A to receive the data signal at the appropriate timing after transitioning from the calibration mode to the system operation mode in which the data signal DT is received. Examples of the operation of determining the output clock signals OCLK, OCLKX of the appropriate phase using the phase adjustment sequencer 370 are shown in Figures 7 to 12. The output clock signals OCLK, OCLKX are examples of receive clock signals that are received in common by all of the data receiving circuits 330A.

[0033] The phase selector 380 selects one of the clock signals P0, P45, P90, and P135 in response to the phase selection signal PSEL output from the phase adjustment sequencer 370, and outputs the selected signal as the output clock signal OCLK. The phase selector 380 also selects one of the clock signals M180, M225, M270, and M315 in response to the phase selection signal PSEL, and outputs the selected signal as the output clock signal OCLKX. The waveforms of the clock signals P0, P45, P90, P135, M180, M225, M270, and M315 are shown in FIG. 5.

[0034] Each data receiving circuit 330A has a configuration in which the phase shifter 324 is removed from each data receiving circuit 330 in FIG. 1 . The data receiver 331 receives a data signal transmitted from the corresponding data transmitting circuit 230 in the route die 200A and outputs the received data signal to the slicer 332. For example, the data signals output from the data receiver 331 to the slicer 332 are separate data signals for each of the multiple lanes of the transmission path 110, and are independent of each other. The slicer 332 acquires the data signal received from the data receiver 331 in synchronization with the output clock signal OCLK or the output clock signal OCLKX, and outputs the acquired data signal to the deserializer 333.

[0035] The deserializer 333 converts the serial data signal from the slicer 332 into an n-bit parallel data signal and outputs it to the user logic 340. For example, the multiple data receiving circuits 330A receive separate data signals that are independent of each other from the data transmitting circuit 230A connected via the transmission path 110, and convert the received data signals into parallel data signals.

[0036] 3 shows an example of the clock receiver 320, variable delay circuit 350, and DLL circuit 360 of FIG. 2. The clock receiver 320 includes a buffer 321 and resistors R1 and R2. The variable delay circuit 350 includes a delay buffer 351 and a voltage digital-to-analog conversion circuit (VDAC) 352. The DLL circuit 360 includes five buffers 361 connected in series, five level shifters (LSFTs) 362, a phase frequency comparator (PFD) 363, a charge pump (Cpump) 364, and a low-pass filter (LPF) 365.

[0037] The buffer 361 is an example of a delay buffer, and the plurality of buffers 361 connected in series is an example of a delay buffer string. The phase frequency comparator 363, the charge pump 364, and the low-pass filter 365 are an example of a delay adjustment circuit that adjusts the delay amount of the plurality of buffers 361 in accordance with the phase difference between the clock signals P0 and M360 so that the phase difference between the clock signals P0 and M360 is equal to one cycle of the clock signal DCLK.

[0038] The buffer 321 of the clock receiver 320 is, for example, a current mode logic (CML) buffer. The buffer 321 receives differential transmit clock signals TCLK and / TCLK via capacitors C1 and C2 and outputs differential receive clock signals RCLK and / RCLK to the variable delay circuit 350. The receive clock signals RCLK and / RCLK are an example of a reference clock signal. The clock receiver 320 determines a differential common voltage by connecting each of its differential inputs to outputs of opposite polarity via resistors R1 and R2.

[0039] 2. The delay buffer 351 delays the differential reception clock signals RCLK and / RCLK received from the clock receiver 320 in accordance with the voltage VP from the VDAC 352, and outputs the delayed signals as differential clock signals DCLK and / DLCK to the first-stage buffer 361 of the DLL circuit 360.

[0040] Each buffer 361 of the DLL circuit 360 is, for example, a CML buffer. Each buffer 361 outputs a differential clock signal delayed according to the voltage generated by the low-pass filter 365 to a subsequent buffer 361 and level shifter 362. Each level shifter 362 is provided corresponding to each buffer 361, and converts the voltage level of the differential clock signal output from the corresponding buffer 361 to a CMOS level.

[0041] Each level shifter 362 outputs a differential clock signal with converted voltage level as clock signal P0 / M180, P45 / M225, P90 / M270, P135 / M315, or P180 / M360. The clock signals P0 / M180, P45 / M225, P90 / M270, and P135 / M315 are output to a phase selector 380, and the clock signal P180 / M360 is output to a phase frequency comparator 363.

[0042] The phase frequency comparator 363 generates a control signal (e.g., a pulse signal) that controls the charge pump 364 in accordance with the phase difference between the clock signal P01 and the clock signal M360. The charge pump Cpump outputs a current in accordance with the control signal from the phase frequency comparator 363 to the low-pass filter 365. The low-pass filter 365 generates a voltage in accordance with the current from the charge pump Cpump and outputs the generated voltage to the control terminal of each buffer 361.

[0043] The DLL circuit 360 adjusts the delay amount of each buffer 361 so that the phase difference between the clock signals P0 and M360 becomes zero using a phase frequency comparator 363, a charge pump Cpump, and a low-pass filter 365. Then, clock signals P0, P45, P90, P135, M180, M225, M270, and M315, each shifted in phase by 45 degrees, are generated.

[0044] The phase selector 380 selects one of the pairs of clock signals P0 / M180, P45 / M225, P90 / M270, and P135 / M315 according to the logical value of the 2-bit phase selection signal PSEL, for example, and outputs it as output clock signals OCLK and OCLKX.

[0045] 3 shows an example in which a differential clock signal is used, but a single-phase clock signal may also be used. Also, in FIG. 2, a differential data signal or a single-phase data signal may be transmitted from the data transmitting circuit 230A to the data receiving circuit 330A.

[0046] 4 shows an example of the variable delay circuit 350 of FIG. 2. The VDAC 352 has variable resistors VR1 and VR2 connected in series via a node VP between a power supply line VDDA and a ground line GND. The resistance values ​​of the variable resistors VR1 and VR2 change depending on the value of the delay code DCODE. The VDAC 352 outputs a voltage VP corresponding to the value of the delay code DCODE. For example, the voltage VP decreases as the value of the delay code DCODE increases, and increases as the value of the delay code DCODE decreases. When the delay code DCODE has n bits, the VDAC 352 can output 2 n different voltages VP. The VDAC 352 is an example of a voltage generation circuit that generates a voltage corresponding to the value of the delay code DCODE.

[0047] The delay buffer 351 includes variable resistors VR3 and VR4, transistors T1 and T2, and a current source CS1. For example, the variable resistors VR3 and VR4 are pre-trimmed to predetermined resistance values. For example, the transistors T1 and T2 are n-channel MOS (Metal Oxide Semiconductor) transistors. The gate of the transistor T1 is connected to an input terminal IN+ that receives the receive clock signal RCLK. The gate of the transistor T2 is connected to an input terminal IN- that receives the receive clock signal / RCLK.

[0048] The variable resistor VR3 and the transistor T1 are connected in series between the power supply line VDDA and the node ND1 via the output terminal OUT-, which outputs the clock signal / DCLK. The variable resistor VR4 and the transistor T2 are connected in series between the power supply line VDDA and the node ND1 via the output terminal OUT+, which outputs the clock signal DCLK. The current source CS1 is connected between the node ND1 and the ground line GND, and passes a current according to the voltage VP. For example, the current source CS1 decreases the amount of current as the voltage VP becomes relatively lower, and increases the amount of current as the voltage VP becomes relatively lower.

[0049] For example, the delay buffer 351 increases the delay difference between the differential receive clock signals RCLK, / RCLK received at the differential input terminals IN+, IN− and the differential clock signals DCLK, / DCLK output from the differential output terminals OUT+, OUT− as the voltage VP becomes relatively lower. Also, the delay buffer 351 decreases the delay difference between the receive clock signals RCLK, / RCLK and the clock signals DCLK, / DCLK as the voltage VP becomes relatively higher. That is, the delay buffer 351 increases the delay amount when the value of the delay code DCODE is large, and decreases the delay amount when the value of the delay code DCODE is small. When the delay code DCODE has n bits, the delay buffer 351 can set 2 n different delay amounts.

[0050] 5 shows an example of clock signals generated by the DLL circuit 360 of Fig. 3. As described above, the DLL circuit 360 generates clock signals P0, P45, P90, P135, M180, M225, M270, M315, and M360, each having a phase difference of 45 degrees. The data signals received by the slicer 332 of Fig. 2 are preferably acquired at the center of the reception period of each data signal (the timing at the center of the transition edges on both sides) (ideal edge position).

[0051] 5, the clock signal closest to the ideal edge position of data signal D1 is clock signal P90. The clock signal closest to the ideal edge position of data signal D2 is clock signal M270, which is 180 degrees behind clock signal P90.

[0052] However, since the DLL circuit 360 can only select one of four phases of clock signals for each data signal, it is difficult to generate a clock signal with an ideal edge position using only the DLL circuit 360. Therefore, fine adjustment of the phase of the clock signal is performed using the variable delay circuit 350. As shown in FIG. 5, the receiving circuit 310A (FIG. 2) has a so-called half-rate architecture in which the clock rate is half the data rate.

[0053] Fig. 6 shows an example of the operation of finely adjusting the phase of a clock signal by the variable delay circuit 350 of Fig. 4. In the example shown in Fig. 6, the data signal is assumed to have a 0101 pattern in which logical values ​​0 and 1 appear alternately.

[0054] 2 switches the clock signal selected by the phase selector 380 in the order of clock signals P0, P45, P90, and P135 in the calibration mode, and further switches the delay amount of the variable delay circuit 350 in order by changing the delay code DCODE. Then, the phase adjustment sequencer 370 obtains the logical value of the data signal for each combination of the clock signals P0, P45, P90, and P135 and the delay code DCODE, and searches for the delay code DCODE at which the logical value switches.

[0055] In the clock signal P0, when the delay code DCODE is between "0" and "2", a logical value of "1" is obtained, and when the delay code DCODE is "3" or greater, a logical value of "0" is obtained. That is, the logical value of the delay code DCODE switches between "2" and "3". In the clock signals P45, P90, and P135, a logical value of "0" is obtained for all delay codes DCODE.

[0056] Then, the phase adjustment sequencer 370 outputs to the phase selector 380 a phase selection signal PSEL that causes the phase selector 380 to select a clock signal P90 whose phase is delayed by 90 degrees from the clock signal P0 at which the logical value switches. The phase adjustment sequencer 370 also outputs a delay code DCODE of "2" or "3" at which the logical value switches to the variable delay circuit 350. As a result, during system operation after the calibration mode, the slicer 332 of the data receiving circuit 330A can acquire data signals in synchronization with the clock signal OCLK whose transition edge occurs near the center timing of each data signal and the clock signal OCLKX whose phase is shifted by 180 degrees from the clock signal OCLK.

[0057] 7 to 12 show an example of a calibration operation of the receiving circuit 310A in FIG. 2. The calibration operation is an operation in which the system 100A transitions to a calibration mode and determines the phase of a clock signal that enables all data receiving circuits 330A to properly acquire data signals. During the calibration mode, the endpoint die 300A instructs the root die 200A to generate test data TDT.

[0058] Based on instructions from the endpoint die 300A, the root die 200A causes the data generation circuit (DTGEN) 233 of each data transmission circuit 230A to generate test data TDT, and outputs a calibration signal CALB to the selection circuit 234 to select the test data TDT.

[0059] 7 to 12 may be implemented by hardware that implements the phase adjustment sequencer 370. When the phase adjustment sequencer 370 is implemented by a processor such as a CPU mounted on the endpoint die 300A, the operations shown in Figures 7 to 12 may be implemented by a program executed by the processor. Alternatively, the operations shown in Figures 7 to 12 may be implemented by cooperation between hardware and software that implement the phase adjustment sequencer 370.

[0060] The elements used during calibration mode are described below. Assume that the system 100A has a known number n (an even number) of lanes that transmit serial data signals from the root die 200A to the endpoint die 300A. The number n of lanes is equal to the number of data transmitting circuits 230A and the number of data receiving circuits 330A. Lane #n indicates the number of the selected lane and is also used to refer to the lane itself.

[0061] The phase selection signal PSEL has two bits, and the phase selector 380 can select four pairs of clock signals P0 / M180, P45 / M225, P90 / M270, and P135 / M315 according to the phase selection signal PSEL. Hereinafter, the value of the two bits of the phase selection signal PSEL will be indicated as PSEL<2:1>. PSEL<2> indicates the value of the most significant bit of the phase selection signal PSEL, and PSEL<1> indicates the value of the least significant bit of the phase selection signal PSEL.

[0062] The phase selector 380 selects clock signals P0 / M180 when PSEL<2:1>="00", and selects clock signals P45 / M225 when PSEL<2:1>="01". The phase selector 380 selects clock signals P90 / M270 when PSEL<2:1>="10", and selects clock signals P135 / M315 when PSEL<2:1>="11".

[0063] In the calibration mode, the operation of searching for the phases of the clock signals OCLK and OCLKX with appropriate timing is performed using the clock signals P0, P45, P90, and P135, as described in Fig. 6. Note that the operation of searching for the phases of the clock signals OCLK and OCLKX with appropriate timing may also be performed using the clock signals M180, M225, M270, and M315.

[0064] Below are examples of the various registers mounted on the phase adjustment sequencer 370 that operate during calibration mode. PSEL<2:1>: Holds the value of the phase selection signal PSEL<2:1> when the phase is adjusted for each even number of lanes. Since there is n registers, one for each lane, the value may differ for each lane. sum2P: Used to add the PSEL<2> of all lanes, and its initial value is "0". sum1P: Used to add the PSEL<1> of all lanes, and its initial value is "0". ans2P: Holds the answer to the majority vote for PSEL<2>. ans1P: Holds the answer to the majority vote for PSEL<1>. numL2P: Holds the number of lanes whose PSEL<2> value matches ans2P. numL1P: Holds the number of lanes whose PSEL<1> value matches ans1P. Glb_PSEL<2:1>: Holds the value of PSEL<2:1> to be set for all lanes. That is, it holds the value of PSEL<2:1>, which generates the phase of the clock signals OCLK and OCLKX at the appropriate timing. DCODE<m:1>: Holds the value of the delay code DCODE when the phase is adjusted for each lane. There are m bits, and the value may be different for each lane. sumD: Used to add up each bit of the delay code DCODE<m:1> for all lanes. It is initialized to "1" each time the addition of each bit of DCODE<m:1> is completed. ansD<m:1>: Holds the answer to the majority vote for the delay code DCODE<m:1>. numLD: Holds the number of lanes where the value of the delay code DCODE<m:1> matches ansD<m:1>. mnum: Holds the number of bits (bit position) from the LSB (Least Significant Bit) of the bit to be processed in the delay code DCODE. It is any of "1" to "m", where "m" indicates the MSB (Most Significant Bit). Glb_DCODE<m:1>: Holds the delay code DCODE to be set for all lanes. In other words, it holds the value of DCODE<m:1> that generates the phases of the clock signals OCLK and OCLKX with appropriate timing.

[0065] 7, after transitioning to the calibration mode, in step S102, the phase adjustment sequencer 370 initializes a counter n to "1." Next, in step S104, the phase adjustment sequencer 370 selects lane #n of the transmission path 110. Next, in step S106, the phase adjustment sequencer 370 outputs a phase selection signal PSEL that causes the phase selector 380 to select the clock signal P0.

[0066] Next, in step S108, the phase adjustment sequencer 370 sequentially switches the value of the delay code DCODE to cause the slicer 332 of the data receiving circuit 330A corresponding to lane #n to acquire the test data signal TDT. Next, in step S110, the phase adjustment sequencer 370 determines whether the value of the test data signal TDT acquired by the slicer 332 has transitioned. That is, the phase adjustment sequencer 370 determines whether the logic value of the test data signal TDT acquired with the previous delay code DCODE has changed. If the value of the test data signal TDT has not transitioned, the phase adjustment sequencer 370 performs step S112. If the value of the test data signal TDT has transitioned, the phase adjustment sequencer 370 performs step S114. In step S112, the phase adjustment sequencer 370 increments the phase selection signal PSEL and then performs step S108.

[0067] The phase range of the clock signal OCLK, which changes according to the loop from step S108 to step S112 using a 0101 pattern as the test data signal TDT, is equal to the period of the logic value of each test data signal TDT. Therefore, a transition in the value of the test data signal TDT is detected in any of the loops from step S108 to step S114, which are repeated multiple times.

[0068] In step S114, the phase adjustment sequencer 370 stores the value of the delay code DCODE and the value of the phase selection signal PSEL when it detects a transition in the value of the test data signal TDT in a register or memory as the optimal phase for lane #n, and then performs step S116.

[0069] In step S116, the phase adjustment sequencer 370 determines whether lane #n is the maximum. If lane #n is the maximum, the phase adjustment sequencer 370 performs step S200 of FIG. 8. By performing the process shown in FIG. 7, the phase of the clock signals OCLK and OCLKX is determined so that the slicer 332 of the data receiving circuit 330A corresponding to each lane #n can properly acquire the test data signal TDT at the time of performing step S200. If lane #n is not the maximum, the phase adjustment sequencer 370 performs step S118. In step S118, the phase adjustment sequencer 370 increments "n" and returns to step S104.

[0070] 8, the phase adjustment sequencer 370 determines the optimum phases for all lanes saved in step S114 by majority vote, and sets the value of the phase selection signal PSEL and the value of the delay code DCODE corresponding to the optimum phase determined by the majority vote to Glb_PSEL<2:1> and Glb_DCODE<m:1>, respectively. Examples of the processing in step S200 will be described with reference to FIGS. 9 to 12.

[0071] Next, in step S120, the phase adjustment sequencer 370 overwrites Glb_PSEL<2:1> with the value of PSEL<2:1>, which generates clock signals OCLK, OCLKX that are 90 degrees behind Glb_PSEL<2:1> set by the majority vote process in step S200, and ends the operations in Figures 7 and 8. As a result, in the operation of the system 100A after the calibration mode is performed, the slicers 332 of all of the data receiving circuits 330A can acquire the data signal DT at the appropriate timing by commonly using the clock signals OCLK, OCLKX having the phase determined by the majority vote process.

[0072] 9 to 12 show an example of the operation of step S200 in FIG. 8. First, in step S202, the phase adjustment sequencer 370 initializes counter n to "1." Next, in step S204, the phase adjustment sequencer 370 selects lane #n of the transmission path 110. Next, in step S206, the phase adjustment sequencer 370 adds PSEL<2> of PSEL<2:1> of lane #n saved in step S114 in FIG. 7 to sum2P. A "0" in PSEL<2> indicates that clock signal P00 or P45 was selected as the optimal phase in the processing of FIG. 7, and a "1" in PSEL<2> indicates that clock signal P90 or P135 was selected as the optimal phase in the processing of FIG. 7.

[0073] Next, in step S208, the phase adjustment sequencer 370 determines whether lane #n is the maximum. If lane #n is the maximum, the phase adjustment sequencer 370 performs step S212. At the time of performing step S212, the number of lanes for which clock signal P90 or P135 was selected as the optimal phase in the processing of FIG. 7 is held as sum2P. If lane #n is not the maximum, the phase adjustment sequencer 370 performs step S210. In step S210, the phase adjustment sequencer 370 increments "n" and returns to step S204.

[0074] In step S212, the phase adjustment sequencer 370 compares sum2P with n / 2, which is half the number of lanes. If sum2P is less than half the number n of lanes, the phase adjustment sequencer 370 performs step S214 because the majority of lanes #n have selected clock signal P0 or P45 as the optimal phase. If sum2P is equal to or greater than half the number n of lanes, the phase adjustment sequencer 370 performs step S216 because the majority of lanes #n have selected clock signal P90 or P135 as the optimal phase.

[0075] In step S214, the phase adjustment sequencer 370 sets ans2P, which is the majority answer for PSEL<2>, to "0", indicating that clock signal P0 or P45 is the optimal phase. The phase adjustment sequencer 370 also sets the difference between the number of lanes n and sum2P to numL2P, which is the number of lanes for which the majority answer was "0", and then performs step S218.

[0076] In step S216, the phase adjustment sequencer 370 sets ans2P, which is the answer of the majority vote for PSEL<2>, to "1", indicating that the clock signal P90 or P135 has the optimum phase. The phase adjustment sequencer 370 also sets sum2P to numL2P, which is the number of lanes for which the answer of the majority vote was "1", and executes step S218. In step S218, the phase adjustment sequencer 370 initializes counter n to "1" and selects lane #n.

[0077] 10, the phase adjustment sequencer 370 compares PSEL<2> of lane #n with ans2P, which is the answer to the majority vote obtained in step S214 or step S216. If PSEL<2> is the same as ans2P, the phase adjustment sequencer 370 performs step S222 because the currently selected lane is the lane that is the target of the majority vote for PSEL<1>. If PSEL<2> is different from ans2P, the phase adjustment sequencer 370 performs step S224 without performing step S222 because the currently selected lane is not the lane that is the target of the majority vote for PSEL<1>.

[0078] That is, in the process of majority voting on the lower-order bits of the phase selection signal PSEL, the phase adjustment sequencer 370 excludes values ​​of the phase selection signal PSEL that do not include a logical value that is the answer to the majority vote on the higher-order bits of the phase selection signal PSEL, and accumulates the number of logical values ​​of 1 or 0. This makes it possible to prevent unnecessary addition processes and the like from being performed in the process of searching for an appropriate phase of the clock signals OCLK and OCLKX, and to prevent the search time from becoming long.

[0079] In step S222, the phase adjustment sequencer 370 adds the value of PSEL<1>, which is the lower bit of PSEL<2:1> of the lane #n that is the target of the majority vote, to sum1P, and then performs step S224.

[0080] In step S224, the phase adjustment sequencer 370 determines whether lane #n is the maximum. If lane #n is the maximum, the phase adjustment sequencer 370 performs step S228. If lane #n is not the maximum, the phase adjustment sequencer 370 performs step S226. In step S226, the phase adjustment sequencer 370 increments "n" and returns to step S220.

[0081] In step S228, the phase adjustment sequencer 370 compares sum1P with numL2P / 2. If sum1P is smaller than half of numL2P, which is the number of lanes that match the majority vote result for PSEL<2>, the phase adjustment sequencer 370 performs step S230 because the lanes #n for which the clock signal P0 or P90 was selected as the optimal phase account for a majority of numL2P. If sum1P is equal to or greater than half of numL2P, the phase adjustment sequencer 370 performs step S232 because the lanes #n for which the clock signal P90 or P135 was selected as the optimal phase account for more than numL2P.

[0082] In step S230, the phase adjustment sequencer 370 sets ans1P, which is the answer of the majority vote for PSEL<1>, to "0," indicating that the clock signal P0 or P90 is the optimal phase. The phase adjustment sequencer 370 also sets the difference between numL2P, which is the number of lanes for which the answer of the majority vote for PSEL<2> was "0," and sum1P to numL1P, which is the number of lanes for which the answer of the majority vote for PSEL<2:1> was "0," and then executes step S234. The difference between numL2P and sum1P indicates the number of lanes for which PSEL<1> is "0" in lane #n, which is the target of the majority vote.

[0083] In step S232, the phase adjustment sequencer 370 sets ans1P, which is the answer of the majority vote for PSEL<1>, to "1," indicating that the clock signal P45 or P135 is in the optimal phase. The phase adjustment sequencer 370 also sets sum1P to numL1P, which is the number of lanes for which the answer of the majority vote for PSEL<2:1> was "1," and then executes step S234. sum1P indicates the number of lanes for which PSEL<1> is "1" among lane #n, which is the target of the majority vote.

[0084] In step S234, the phase adjustment sequencer 370 sets Glb_PSEL<2>, which is the value of PSEL<2> to be set for all lanes #n, to ans2P calculated in step S214 or step S216 of Fig. 9. The phase adjustment sequencer 370 also sets Glb_PSEL<1>, which is the value of PSEL<1> to be set for all lanes #n, to ans1P calculated in step S230 or step S232. This makes it possible to determine by majority vote the phase of the clock signal P0, P45, P90, or P135 that has more transitions of the test data signal TDT than the others in all lanes #n.

[0085] Next, in step S236, the phase adjustment sequencer 370 sets the bit position mnum to be processed in the delay code DCODE to be processed to "m", which indicates the position of the most significant bit. The phase adjustment sequencer 370 also sets numLD, which stores the number of lanes whose value of the delay code DCODE<m:1> matches the answer of the majority vote, ansD<m:1>, to numL1P. The processing from step S236 onward is processing for determining the optimum value of the delay code DCODE by majority vote.

[0086] Next, in step S238 of FIG. 11, the phase adjustment sequencer 370 sets the initial value of counter n to "1", selects lane #n, and initializes sumD, which is a variable for adding each bit of the delay code DCODE, to "0".

[0087] Next, in step S240, the phase adjustment sequencer 370 compares PSEL<2> with ans2P and PSEL<1> with ans1P. If PSEL<2> is equal to ans2P and PSEL<1> is equal to ans1P, the phase adjustment sequencer 370 determines that lane #n is the lane to be searched for, and therefore performs step S242. If PSEL<2> is different from ans2P or if PSEL<1> is different from ans1P, the phase adjustment sequencer 370 determines that lane #n is not the lane to be searched for, and therefore performs step S248 without performing steps S242, S244, and S246. This prevents unnecessary additions and other operations from being performed in the process of searching for the appropriate phases of the clock signals OCLK and OCLKX, thereby preventing the search time from becoming longer. As a result, the operating time of the phase adjustment sequencer 370 in calibration mode can be shortened, and power consumption can be reduced.

[0088] In step S242, the phase adjustment sequencer 370 determines whether the bit position mnum to be processed in the delay code DCODE is the most significant bit m, and if it is the most significant bit m, it performs step S246, and if it is not the most significant bit m, it performs step S244. That is, in the loop for each lane #n shown in Figures 11 and 12, step S244 is not performed the first time when the bit position mnum is the most significant bit m, but step S244 is performed from the second time onwards when it is not the most significant bit m.

[0089] In step S244, the phase adjustment sequencer 370 compares DCODE<m:mnum+1> with ansD<m:mnum+1>, which is the answer to the majority vote of the delay code DCODE<m:mnum+1> obtained so far. Note that if the bit position mnum is not the most significant bit m for the second or subsequent time, the process from step S246 onwards has been performed on the most significant bits up to that point, so the value of ansD<m:mnum+1> has already been obtained. If DCODE<m:mnum+1> and ansD<m:mnum+1> are equal, the phase adjustment sequencer 370 performs step S246 to include them in the majority vote process. If DCODE<m:mnum+1> and ansD<m:mnum+1> are different, the phase adjustment sequencer 370 performs step S248 to exclude them from the majority vote process. This prevents unnecessary addition processes and the like from being performed, and prevents the search time from becoming longer. As a result, the operating time of the phase adjustment sequencer 370 in the calibration mode can be shortened, and power consumption can be reduced.

[0090] In step S246, the phase adjustment sequencer 370 adds the DCODE<mnum> of lane #n to sumD. Next, in step S248, the phase adjustment sequencer 370 determines whether lane #n is the maximum. If lane #n is the maximum, the phase adjustment sequencer 370 performs step S252 in FIG. 12 , and if lane #n is not the maximum, the phase adjustment sequencer 370 performs step S250. In step S250, the phase adjustment sequencer 370 increments "n" and returns to step S240.

[0091] 12, the phase adjustment sequencer 370 compares sumD with numLD / 2. If sumD is smaller than half of numLD, which is the number of lanes that match the majority decision result for the delay code DCODE, the phase adjustment sequencer 370 performs step S254 because the majority of lanes #n in the lane #n subject to the majority decision have a delay code DCODE<mnum> of "0." If sumD is equal to or greater than half of numLD, which is the number of lanes that match the majority decision result for the delay code DCODE, the phase adjustment sequencer 370 performs step S256 because the majority of lanes #n in the lane #n subject to the majority decision have a delay code DCODE<mnum> of "1."

[0092] In step S254, the phase adjustment sequencer 370 sets ansD<mnum>, which is the answer of the majority vote at the bit position mnum to be processed, to "0." The phase adjustment sequencer 370 also subtracts sumD from numLD, which is the number of lanes that matches the answer of the majority vote for the delay code DCODE<m:1>, to obtain a new numLD, and then performs step S258. In step S256, the phase adjustment sequencer 370 sets ansD<mnum> to "1," sets numLD to sumD, and then performs step S258.

[0093] In step S258, the phase adjustment sequencer 370 determines whether mnum is "1". That is, the phase adjustment sequencer 370 determines whether the majority vote process has been performed up to the least significant bit of the delay code DCODE. If mnum is "1", the phase adjustment sequencer 370 performs step S260 because the appropriate value of the delay code DCODE has been determined by majority vote. If mnum is not "1", the phase adjustment sequencer 370 performs step S262 because there are bits in the delay code DCODE that have not been subjected to majority vote process.

[0094] In step S260, the phase adjustment sequencer 370 sets Glb_DCODE<m:1>, which is the value of the delay code DCODE<m:1> to be set for all lanes #n, to ansD<m:1>, and ends the operation of step S200 shown in Figures 9 to 12. In step S262, the phase adjustment sequencer 370 decrements mnum, thereby shifting the bit mnum to be processed by majority vote in the delay code DCODE by one bit to the lower side, and returns to step S238 in Figure 11.

[0095] As described above, in this embodiment, the phases of the clock signals OCLK and OCLKX that cause the multiple data receiving circuits 330A to acquire data are set by the variable delay circuit 350 and phase selector 380 that are provided in common outside the multiple data receiving circuits 330A. This makes it possible to reduce power consumption of the receiving circuit 310A compared to when a phase shift circuit or the like that sets the phase of the clock signals OCLK and OCLKX is provided inside each data receiving circuit 330A.

[0096] The phase adjustment sequencer 370 determines the phases of the clock signals OCLK and OCLKX that enable appropriate acquisition of data signals for each data receiving circuit 330A. The phase adjustment sequencer 370 then takes a majority vote on the determined phases to set common clock signals OCLK and OCLKX with appropriate timing for the multiple data receiving circuits 330A. As a result, even when the variable delay circuit 350 and phase selector 380 that set the phases of the clock signals OCLK and OCLKX are provided in common to the multiple data receiving circuits 330A, it is possible to generate clock signals that enable the multiple data receiving circuits 330A to receive data signals at appropriate timing.

[0097] By controlling the variable delay circuit 350 and the phase selector 380 using the phase adjustment sequencer 370 to sequentially shift the phases of the clocks OCLK and OCLKX, it is possible to obtain clock signals OCLK and OCLKX with appropriate timing that allows data signals to be acquired for each data receiving circuit 330A.

[0098] The phase adjustment sequencer 370 sets the value of the delay code DCODE and the value of the phase selection signal PSEL corresponding to the clock signals OCLK and OCLKX with the appropriate timing determined in the calibration mode, respectively, in the variable delay circuit 350 and the phase selector 380. This allows each data receiving circuit 330A to receive a data signal at the appropriate timing after transitioning from the calibration mode to the system operation mode.

[0099] The phase adjustment sequencer 370 accumulates the number of logical 1s or logical 0s in the phase selection signal PSEL in order from the most significant bit, and when repeating the process of determining the logical value of the majority as the answer to the majority vote, in the majority vote on the lower bit side, it excludes values ​​of the phase selection signal PSEL that do not include the logical value that is the answer to the majority vote on the higher bit side and accumulates the number of logical 1s or logical 0s. This makes it possible to prevent unnecessary addition processes and the like from being performed in the process of searching for the appropriate phase of the clock signals OCLK and OCLKX, and to prevent the search time from becoming long.

[0100] The phase adjustment sequencer 370 accumulates the number of logical 1s or logical 0s in the delay code DCODE, starting from the most significant bit, and repeats the process of determining the logical value of the majority as the answer to the majority vote. When the majority vote is performed on the lower-order bits, the phase adjustment sequencer 370 accumulates the number of logical 1s or logical 0s while excluding delay code DCODE values ​​that do not include the logical value that is the answer to the majority vote on the higher-order bits. Furthermore, the phase adjustment sequencer 370 accumulates the number of logical 1s or logical 0s while excluding delay code DCODE values ​​corresponding to the phase selection signal PSEL that do not include the logical value that is the answer to the majority vote of the phase selection signal PSEL that has already been determined. This prevents unnecessary additions and other operations from being performed during the process of searching for the appropriate phase of the clock signals OCLK and OCLKX, thereby preventing the search time from becoming longer. As a result, the operating time of the phase adjustment sequencer 370 in the calibration mode can be shortened, and power consumption can be reduced.

[0101] Although the present invention has been described above based on the embodiments, the present invention is not limited to the requirements shown in the above embodiments. These requirements can be changed without departing from the spirit of the present invention, and can be appropriately determined depending on the application form.

[0102] 100, 100A System 110 Transmission path 200, 200A Route die 210 PLL circuit 220 Clock driver 230, 230A Data transmission circuit 231 Serializer 232 Data driver 233 Data generation circuit (DTGEN) 234 Selection circuit (SEL) 300, 300A Endpoint die 310, 310A Receiving circuit 320 Clock receiver 321 Buffer 330, 330A Data receiving circuit 331 Data receiver 332 Slicer 333 Deserializer (DES) 334 Phase shift circuit 340 User logic 350 Variable delay circuit 351 Delay buffer 352 Voltage digital-to-analog conversion circuit (VDAC) 360 DLL circuit 361 Buffer 362 Level shifter (LSFT) 363 Phase frequency comparator (PFD) 364 Charge pump (Cpump) 365 Low pass filter (LPF) 370 Phase adjustment sequencer 380 Phase selector C1, C2 Capacitor CALB Calibration signal CS1 Current source DCLK, / DCLL Clock signal DCODE Delay code DT Data signal GND Ground line IN+, IN- Input terminal M180, M225, M270, M315 Clock signal ND1 Node OCLK, OCLKX Output clock signal OUT-, OUT+ Output terminal P0, P45, P90, P135 Clock signal PSEL Phase selection signal R1, R2 Resistor RCLK, / RCLK Receive clock signal T1, T2 Transistor TCLK, / TCLK Transmit clock signal TDT Test data signal VDDA Power line VP Voltage VR1, VR2, VR3, VR4 Variable resistors

Claims

1. A receiving circuit having a clock generation circuit that generates a receive clock signal and a plurality of data receiving circuits that each receive a separate data signal based on the receive clock signal, wherein the clock generation circuit has: a clock receiving circuit that receives a reference clock signal; a variable delay circuit that delays the reference clock signal received by the clock receiving circuit by an amount of delay corresponding to a delay control signal to generate a delayed reference clock signal; a delay synchronization circuit that sequentially delays the delayed reference clock signal to generate a plurality of internal clock signals; and a selector circuit that selects one of the plurality of internal clock signals based on a phase selection signal and outputs it as the receive clock signal.

2. The receiving circuit according to claim 1, wherein said receiving clock signal is a common clock signal for said plurality of data receiving circuits.

3. A receiver circuit as claimed in claim 1, further comprising a phase adjustment control circuit for generating said delay control signal and said phase selection signal.

4. The receiving circuit of claim 3, wherein the phase adjustment control circuit controls the variable delay circuit and selector circuit to sequentially shift the phase of the receiving clock signal, determines for each of the plurality of data receiving circuits the phase at which the data signal can be acquired at an appropriate timing, and determines the phase of the receiving clock signal common to the plurality of data receiving circuits by taking a majority vote of the determined plurality of phases.

5. The receiving circuit of claim 3, wherein the value of the phase selection signal and the value of the delay control signal are represented by multiple bits, and the phase adjustment control circuit sequentially changes the value of the delay control signal for each value of the phase selection signal, thereby determining, for each of the multiple data receiving circuits, the phase of the receiving clock signal that enables the data signal to be acquired at the appropriate timing.

6. The receiving circuit of claim 4, wherein the phase adjustment control circuit, in a majority vote for a plurality of the phases, accumulates the number of logical 1s or logical 0s in the phase selection signal, starting from the most significant bit, for each of the plurality of data receiving circuits, and determines the logical value that results in the majority vote as the answer to the majority vote for the phase selection signal by repeating this process.

7. The receiving circuit of claim 4, wherein the phase adjustment control circuit determines, for each of the multiple data receiving circuits, in a majority vote for a plurality of the phases, a value of the answer of the phase selection signal in a majority vote on the lower bits of the phase selection signal, by excluding values ​​of the phase selection signal that do not include a logical value that is the answer of the majority vote on the higher bits of the phase selection signal, and accumulating the number of logical values ​​1 or 0.

8. The receiving circuit of claim 6 or claim 7, wherein the phase adjustment control circuit accumulates the number of logical 1s or logical 0s in the delay control signal, starting from the most significant bit, for each of the multiple data receiving circuits, in the phase indicated by the value of the majority answer of the phase selection signal, and repeats the process of taking the logical value with the majority of the accumulated number as the majority answer, thereby determining the majority answer of the delay control signal.

9. The receiving circuit of claim 6 or 7, wherein the phase adjustment control circuit determines the value of the majority vote answer of the delay control signal for each of the multiple data receiving circuits at the phase indicated by the value of the majority vote answer of the phase selection signal by accumulating the number of logical values ​​1 or 0 in the majority vote on the lower bits of the delay control signal, excluding values ​​of the delay control signal that do not include the logical value that is the majority vote answer on the upper bits of the delay control signal.

10. The receiving circuit of claim 3, wherein the phase adjustment control circuit determines the value of the phase selection signal and the value of the delay control signal that generate the receiving clock signal having a phase determined by majority vote, outputs the determined value of the phase selection signal to the selector circuit, and outputs the determined value of the delay control signal to the variable delay circuit.

11. The receiving circuit of claim 3, wherein said phase adjustment control circuit operates during a test mode and generates said delay control signal and said phase selection signal.

12. The receiving circuit of claim 11, wherein the phase adjustment control circuit controls the variable delay circuit and selector circuit during the test mode to set the phase of the receiving clock signal to a phase determined by majority vote, and in a system operation mode after the test mode, each of the plurality of data receiving circuits acquires a data signal based on the receiving clock signal whose phase has been set by the phase adjustment control circuit.

13. A receiving circuit as claimed in any one of claims 1 to 5, wherein the reference clock signal, the delayed reference clock signal, the internal clock signal and the receiving clock signal are each a differential clock signal, and the delay synchronisation circuit is a differential delay synchronisation circuit which receives a differential signal as an input.

14. The receiving circuit according to any one of claims 1 to 5, wherein the delay synchronization circuit comprises: a delay buffer train including a plurality of delay buffers connected in series, the delay buffer at a first stage receiving the delayed reference clock signal and generating the plurality of internal clock signals having mutually different phases from each of the plurality of delay buffers; and a delay adjustment circuit which adjusts the amount of delay of the plurality of delay buffers based on the phase difference of the internal clock signals output from two of the delay buffers.

15. A receiving circuit as claimed in any one of claims 1 to 5, wherein the variable delay circuit comprises: a voltage generating circuit that generates a voltage according to the value of the delay control signal; and a delay buffer that delays the reference clock signal according to the voltage to generate a delayed reference clock signal, the delay amount being variable according to the voltage.

16. A receiving circuit according to any one of claims 1 to 5, wherein each of said plurality of data receiving circuits has a serial-to-parallel conversion circuit that converts a plurality of serial data signals sequentially received via a transmission line into parallel data signals.

17. The receiving circuit according to any one of claims 1 to 5, wherein the separate data signals received by the multiple data receiving circuits are multiple data signals independent of one another.

18. A semiconductor integrated circuit having a receiving circuit including a clock generating circuit that generates a received clock signal and a plurality of data receiving circuits that each receive a separate data signal based on the received clock signal, and a processing circuit that processes the plurality of data signals received by the receiving circuit, wherein the clock generating circuit has: a clock receiving circuit that receives a reference clock signal; a variable delay circuit that delays the reference clock signal received by the clock receiving circuit by an amount of delay corresponding to a delay control signal to generate a delayed reference clock signal; a delay synchronization circuit that sequentially delays the delayed reference clock signal to generate a plurality of internal clock signals; and a selector circuit that selects one of the plurality of internal clock signals based on a phase selection signal and outputs it as the received clock signal.

19. A transmission / reception system having a transmission circuit including a first clock generation circuit that generates a reference clock signal and a plurality of data transmission circuits that transmit separate data signals based on the reference clock signal; and a reception circuit including a second clock generation circuit that generates a reception clock signal based on the reference clock signal, and a plurality of data reception circuits provided corresponding to the plurality of data transmission circuits and each receiving the separate data signals based on the reception clock signal, wherein each of the plurality of data transmission circuits has: a data generation circuit that generates a test data signal; and a selection circuit that selects either the test data signal or a data signal and outputs it as the separate data, and the second clock generation circuit has: a clock reception circuit that receives the reference clock signal; a variable delay circuit that delays the reference clock signal received by the clock reception circuit by an amount of delay corresponding to a delay control signal to generate a delayed reference clock signal; a delay synchronization circuit that sequentially delays the delayed reference clock signal to generate a plurality of internal clock signals; and a selector circuit that selects one of the plurality of internal clock signals based on a phase selection signal to output it as the reception clock signal.

20. The transmitting / receiving system according to claim 19, wherein the selection circuit selects the test data signal in a test mode, and selects the data signal in a system operation mode after the test mode.

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