High power density power module packaging with low inductance and good current balancing

Abstract

A power module and method for making the same, comprising a substrate, one or more semiconductor devices positioned on the substrate, an auxiliary substrate positioned on the substrate, and a first busbar located on the auxiliary substrate. A second busbar electrically is connected to the substrate such that, in use, a power loop current path extends between the first and second busbars via the substrate and the auxiliary substrate.

Description

[0001] High Power Density Power Module Packaging with Low Inductance and Good Current Balancing

[0002] Field of Disclosure

[0003] The present application relates to high power density power module designs, and in particular but not limited to high power density SiC power module designs.

[0004] Background

[0005] SiC devices have the advantages of high switching speed and high operation temperature. As a result, the development of SiC power modules are in high demand. The requirements for the packaging design for SiC power module generally include low stray inductance and good current balancing performances, to fully make use of the fast switching speed of the SiC devices. Low parasitic inductances and good current balancing increases the overall efficiency of the power module, particularly at faster switching speeds. As such, this is generally desirable in SiC power module technology.

[0006] In power module technologies, power loop parasitic inductance can be induced by long commutation paths (also referred to as (DC) power loops) and asymmetric placements of interconnections, such as busbars, wire bonds and copper tracks. The presence of power loop parasitic inductances can lead to large voltage spikes during turn-off transients of active switches. In some cases, the undesired voltage spikes can potentially exceed the device’s voltage ratings, and therefore impact the safe operation of fast switching devices such as SiC MOSFETs.

[0007] Figure 1 depicts a circuit lay out for a power module 10, comprising a substrate with lower and upper switch circuits 1 , 2, a conductive track 3 for a gate-source loop, busbar or power terminals 4, 5 and 6, a baseplate 7, wire bonds 8 and semiconductor devices 9 such as MOSFETs. The gate terminal of the MOSFETs 9 are wire bonded to conductive track 3. As a result of this design, the power source wire bonds and auxiliary source wire bonds must be extended to reach over and across conductive track 3, increasing the path length for the power source and auxiliary source current flows.

[0008] One method for reducing the power / commutation loop parasitic inductance is to place the DC+ and DC- busbars 4, 5 adjacent to each other, as shown in Figure 1. This partial overlapping of the busbars 4, 5 also increases the mutual coupling of the busbars to therefore reduce the parasitic inductance.

[0009] However, the design of Figure 1 splits the commutation loop into two loops 21 , 22, as shown in Figure 2. In particular, Figure 2 shows how the return path is separated and the currents are diverted (e.g. resulting in a non-linear current flow direction) around the upper switch area on the substrate. The discontinuities introduced by this diversion to the current path may increase stray inductances in the DC power loop. Additionally, narrow paths for the return current of the DC- commutation path may result in further increases in parasitic resistances.

[0010] Additionally, in power module 10 the direction of current flow is the same or approximately the same for the currents flowing through the gate wire bonds, auxiliary source wire bonds and power source wire bonds. This may result in may magnetic coupling between the various currents of power module 10, inducing and increasing parasitic inductances.

[0011] Further example power module designs are described in US10283454 B2 and US10917992 B2.

[0012] The Applicant has therefore recognised a need for improved high power density power module packaging with low parasitic inductance and good current balancing.

[0013] Summary

[0014] Aspects and preferred features are outlined in the accompanying claims.

[0015] The present disclosure provides a cost efficient and easily manufacturable power module arrangement for reducing or minimising the length of a power commutation loop and for reducing the parasitic inductances in the power commutation loop. Implementations according to the present disclosure further facilitate improved current sharing balance between semiconductor devices such as MOSFETs in a switch. The reduction of parasitic inductances and increase in current balancing contribute to higher efficiency of the power module. High efficiency power modules are desirable, as even a small increase in efficiency of the power module can greatly reduce wasted energy and other resources.

[0016] According to a first aspect of the present disclosure, there is provided a power module comprising: a substrate one or more semiconductor devices positioned on the substrate; an auxiliary substrate positioned on the substrate; a first busbar located on the auxiliary substrate; and a second busbar electrically connected to the substrate such that, in use, a power loop current path extends between the first and second busbars via the substrate and the auxiliary substrate.

[0017] The auxiliary substrate, which is mounted to a main substrate of the power module, has the first (e.g. DC-) busbar mounted to it, thereby isolating the voltage polarity of the first busbar from the opposite polarity second (e.g. DC+) voltage of the main substrate on which the auxiliary substrate is mounted. The substrate and auxiliary substrate may be electrically connected, for example via the one or more semiconductor devices, such that a current may flow from the substrate to the auxiliary substrate (e.g. via the one or more semiconductor devices) or vice versa.

[0018] The use of an auxiliary substrate for attaching the first busbar to the power module may facilitate a shortened power loop commutation path, and may further assist in avoiding discontinuities in the power loop commutation path. As such, the auxiliary substrate may assist in reducing parasitic inductances and other stray inductances. For example, the presence of the auxiliary substrate under the first (e.g. DC-) busbar facilitates a current flow beneath the first busbar and through the first busbar, thereby facilitating a smaller commutation loop.

[0019] Each substrate and / or auxiliary substrate may comprise various materials. For example, the substrate I auxiliary substrate may be a DBC (Direct Bonded Copper) or an AMB (Active Metal Brazed) substrate comprising a top copper layer and a bottom copper layer bonded or brazed to a ceramic middle layer. The ceramic material may comprise e.g. Silicon Nitride, Aluminium Nitride, Alumina or any other ceramic insulator. The substrate may instead be an integrated metal substrate (IMS). The IMS may comprise a resin-based material as an insulation layer separating the circuit layer from the baseplate. The substrate may alternatively be an integrated metal baseplate (IMB), for example with a ceramic insulator moulded into aluminium or other metal baseplate with an aluminium or other metal circuit layer bonded to one face of the ceramic middle layer.

[0020] In implementations, the power module comprises a second substrate electrically connected to the substrate, wherein second power bus bar is electrically connected to the second substrate. Optionally, the module may comprise a second auxiliary substrate positioned on and electrically connected to the second substrate, wherein the second busbar is located on the second auxiliary substrate. The substrate may therefore be referred to as a first substrate when a second substrate is provided. One or more second semiconductor devices may be positioned on the second substrate, and the second substrate and the second auxiliary substrate may be electrically connected via the one or more semiconductor devices.

[0021] Alternatively, the power module may comprise only a single (main) substrate. Optionally, a second auxiliary substrate may be positioned on and electrically connected to the substrate, wherein the second busbar is located on the second auxiliary substrate.

[0022] As such, the second busbar and / or any other busbars (e.g. a third or AC busbar) provided may be arranged on a corresponding auxiliary substrate in a similar manner to the first busbar. For example, the module may comprise three busbars corresponding to AC, DC- and DC+ power terminals. The busbars may be arranged symmetrically with e.g. two outer busbars (e.g. AC, DC+) positioned towards an edge of the power module and one central busbar (e.g. DC-) positioned centrally in the power module. Each or any of the busbars may be mounted to an auxiliary substrate rather than directly to its corresponding main (i.e. first or second) substrate.

[0023] The power module may be provided with a busbar designed and shaped to increase the mutual inductance between the first and second busbars. The first or second busbar may be provided with this shape. For example, in implementations the first busbar comprises: first, second and third sections, wherein: the first and third sections are parallel to one another; the second section is between the first section and the third section; and the second section is perpendicular to the first and third sections; and fourth and fifth section perpendicular to the first, second and third sections, wherein: the fourth section is between the first and second sections; and the fifth section is between the second and third sections.

[0024] The first and second busbars may be positioned such that the second section extends from the fourth section towards the second busbar, for example such that the fifth section is separated from the second busbar by 10mm or less, 5mm or less, 2.5mm or less, or 1mm or less.

[0025] The small separation and overlap between at least part of the first busbar and a corresponding at least part of the second busbar may therefore result, in use, in relative high mutual inductances between the busbars. This is turn may facilitate a reduction in power loop stray inductances. Generally speaking, a smaller separation distance may result in further reductions to stray inductances, but at a cost of higher manufacturing costs e.g. as a result of tighter machining tolerances. The preferred separation of the busbars may therefore depend on various factors, including for example the voltage rating of the device and the intended application.

[0026] In implementations, the fifth section and the second busbar may be separated by an isolation layer. The isolation layer may be a thin isolation layer or isolation film, for example with a thickness of less than 1 mm. The isolation layer may comprise any suitable material, such as an electrically insulating material.

[0027] The substrate and / or second substrate may each be a single contiguous or continuous element and extends beneath the auxiliary substrate. For example, the substrate and / or second substrate may each comprise a single conductive (e.g. copper) layer without gaps, voids or other holes that may result in a discontinuity in the power loop current path. This in turn may facilitate a more linear flow of current in the power loop commutation path due to a reduction in discontinuities. This in turn may assist in reducing stray inductances of the commutation path.

[0028] In implementations, the power module comprises a further auxiliary substrate electrically connected to a gate terminal of the one or more semiconductor devices, wherein the further auxiliary substrate is located on the substrate, and wherein the substrate extends beneath of further auxiliary substrate.

[0029] The further auxiliary substrate may provide a current path for the source-gate current loop of the semiconductor devices. One auxiliary substrate may be provided for each source-gate circuit loop, and the power module may therefore be provided with multiple further auxiliary substrates on each of the substrate and / or second substrate. The use of an auxiliary substrate for the source-gate current loops may facilitate a reduction in interference between the power loop currents and the source-gate currents.

[0030] Each auxiliary substrate may be attached to its respective (main) substrate by any suitable means, for example soldering, sintering, transient liquid phase soldering, welding or brazing.

[0031] Optionally, the or each further auxiliary substrate is attached to the respective main substrate such that it is perpendicular to the power loop current path extending, in use, between the first and second busbars. The auxiliary substrates may therefore provide a current path flow in the source-gate circuit loop that is perpendicular to the current flow in the power loop. As such, magnetic field coupling between the gate loop and power loop may be reduced or minimised, thereby reducing coupling of parasitic inductances between the power loop and the gate loop, and thus reducing the current imbalance in the power module.

[0032] In implementations, wherein the one or more semiconductor devices comprise a plurality of semiconductor devices. The semiconductor devices may be arranged geometrically in a line and electrically connected in parallel, and the first busbar may have a width that is equal to or greater than a length of the line such that each semiconductor device is an approximately equal distance from a base of the busbar. The provision of a wide busbar adjacent to all of the paralleled semiconductor devices on the substrate may further enhance the current balancing of the power module. The one or more second semiconductor devices, where provided, may similarly be arranged geometrically in a line and electrically connected in parallel.

[0033] The one or more semiconductor devices may comprise e.g. Si, SiC or GaN based devices, or other semiconductor device types. The one or more semiconductor device may additionally or alternatively be provided in combination with other components, such as a freewheeling or anti-parallel diode, depending on the intended use and functionality of the power module.

[0034] For example, in an implementation the semiconductor devices comprise silicon carbide (SiC) based semiconductor devices, such as SiC MOSFETs. The reduced parasitic and stray inductances provided by power module designs according to this disclosure may be particularly advantageous when used in combination with SiC semiconductor devices, due to the relatively high switching speeds of these technologies.

[0035] Each of the substrate and / or second substrate may be attached to or located on a baseplate, i.e. such that a single baseplate is provided for all substrates.

[0036] In implementations, the power module may be arranged in a half bridge configuration. For example, the power module may comprise a first switch on the substrate and a second switch on the second substrate, such that the high side devices (e.g. MOSFETs) and the DC+ busbar are provided on one substrate, and the low side devices (e.g. MOSFETs), the DC- busbar and the AC busbar are provided on the other substrate(s). The busbars may be positioned symmetrically and / or adjacent to the respective semiconductor devices in the switches.

[0037] Thus, in e.g. half bridge configurations, the auxiliary substrate may be mounted to the main substrate of one of the high or low side switches. The auxiliary substrate being mounted to the switch in this way means that the first busbar (e.g. the DC- or DC+ busbar) can be positioned closer to the opposite polarity switch, whilst still remaining isolated from the opposite polarity switch. This may facilitate a reduction in the DC power circuit path length and therefore reduce the parasitic inductance in the DC power loop

[0038] The power module may comprise a baseplate or a heat sink attached to the substrate and / or second substrate, for example via a thermally conductive material, a thermal interface material and / or an isolation layer or film.

[0039] According to a second aspect of the present disclosure, there is provided method for making a power module, the method comprising: attaching one or more semiconductor devices to a substrate; attaching an auxiliary substrate to the substrate such that the auxiliary substrate is positioned on and electrically connected to the substrate; attaching a first busbar on the auxiliary substrate; and electrically connecting a second busbar to the substrate such that, in use, a power loop current path extends between the first and second busbars via the substrate and the auxiliary substrate.

[0040] Electrically connecting second busbar to the substrate may similarly comprise: providing a second substrate; electrically connecting the second substrate to the substrate; and electrically connecting the second busbar to the second substrate.

[0041] The method may also include various other steps of process, for example additional (e.g. further or second) auxiliary substrates may be attached to the main (i.e. first and second) substrates, providing wire bonding for the power loop and the gate loop current paths, attaching one or more gate resistor(s) for the semiconductor devices and or attaching signal pin(s) to the module.

[0042] The method may comprise attaching the second and / or any further busbars (e.g. an AC busbar) to the substrate(s) in their respective positions. The method may comprise attaching the main (i.e. first and / or second) substrates to a baseplate.

[0043] According to a third aspect of the present disclosure, there is provided a busbar for use in a power module, the busbar comprising: first, second and third sections, wherein: the first and third sections are parallel to one another; the second section is between the first section and the third section; and the second section is perpendicular to the first and third sections; and fourth and fifth section perpendicular to the first, second and third sections, wherein: the fourth section is between the first and second sections; and the fifth section is between the second and third sections.

[0044] The shape of the busbar may, in use, facilitate an increase in the mutual inductance between the busbars by reducing a distance between it and a further busbar. As such, the busbar shape may facilitate a reduction in e.g. power loop stray inductances. For example, in some implementations stray inductance may be reduced to less than 5nH.

[0045] According to a fourth aspect of the present disclosure, there is provided a power module comprising: the busbar of the third aspect connected to a first substrate a second busbar connected to a second substrate, wherein the first and second substrates are spaced apart from one another; and wherein the second section extends from the first substrate to the second substrate. Optionally, the second section extends from the first substrate to the second substrate such that the fifth section is separated from the second busbar by 10mm or less, 5mm or less, 2.5mm or less, or 1 mm or less.

[0046] Brief Description of the Figures

[0047] Some preferred embodiments of the invention will now be described, by way of example only and with reference to the accompanying drawings, in which:

[0048] Figure 1 illustrates an example power module design.

[0049] Figure 2 illustrates a commutation loop for an example power module design.

[0050] Figures 3a and 3b illustrate an example power module design according to an implementation of the present disclosure.

[0051] Figures 4a and 4b illustrate a commutation loop for a power module design according to an implementation of the present disclosure. Figures 5a-d illustrate an example power module design according to an implementation of the present disclosure.

[0052] Figures 6a and 6b illustrate an example power module design according to an implementation of the present disclosure.

[0053] Figure 7 illustrates a commutation loop for a power module design according to an implementation of the present disclosure.

[0054] Figure 8 illustrates an example substrate layout for a power module design according to an implementation of the present disclosure.

[0055] Figure 9a-d illustrate example power module designs for current balancing according to an implementation of the present disclosure.

[0056] Figure 10 illustrates a source-gate current loop in an example power module design according to an implementation of the present disclosure.

[0057] Figure 11 illustrates an example power module design according to an implementation of the present disclosure comprising a cooling module, such as a heatsink or coldplate.

[0058] Figures 12a and b illustrate an example power module design according to an implementation of the present disclosure.

[0059] Figure 13 illustrates an example manufacturing process for a power module design according to an implementation of the present disclosure.

[0060] Detailed Description of the Preferred Embodiments

[0061] Figures 3a and 3b depict top and side views of an example power module 30 according to an implementation of the present disclosure. The power module is arranged in a half-bridge configuration, and comprises lower and upper switch substrates 10, 11 , upper and lower auxiliary switch substrates 12, 13, busbar or power terminals 14, 15 and 16, a baseplate 20 and semiconductor devices 19, such as SiC MOSFETs provided on each of the lower and upper switch substrates 10, 11. Figures 4a and 4b show an example commutation path 40 in the power loop of the power module 30. The commutation path 40 in the power loop is routed around a pad 17 on the main (lower switch) substrate 22. The pad 17 comprises an isolated copper region, to which the (DC-) busbar 15 is attached. Pad 17 is in turn electrically connected to substrate 11 via wire bonds 18. Pad 17 is provided in a same substrate layer as substrate 11 , and isolated from it by a gap or isolation region. As a result, pad 17 may be positioned in a gap or hole within substrate 11.

[0062] The DC- busbar 15 is configured with a shape that allows at least part of busbar 15 to be located in close proximity (e.g. with a small separation such as 10mm or less, for example 2.5mm) to the DC+ busbar 14, which itself is attached to the lower switch substrate 10. The close proximity of the busbars 14, 15 facilitates an increase in mutual coupling and a decrease in parasitic inductances. Optionally, an isolation layer may be provided between the busbars 14, 15, such that the busbars 14, 15 are separated by the isolation layer. The isolation layer may be a thin isolation layer, e.g. with a thickness of 1mm or less.

[0063] The DC- busbar 15 may be attached to the pad 17 via various means, for example but not limited to soldering, sintering, transient liquid phase soldering, welding or brazing.

[0064] However, the layout of power module 30, and in particular the use of pad 17, splits the commutation path in the power loop, causing the currents to pass to either side of pad 17 towards the devices 19 in the next switch along the current path. The wire bonds 18 from the devices 19 direct the current back to pad 17, and therefore to the busbar 15 bonded to pad 17. The need for current to flow around pad 17 results in discontinuities in the otherwise largely geometrically linear flow path of the current, which may increase parasitic inductances.

[0065] Figures 5a and 5b depict top and side views of a further example power module 50 according to an implementation of the present disclosure. Figures 5c and 5d meanwhile, respectively depict enhanced views of regions A and B of power module 50. Several features of power module 50 correspond to those of power module 30, and like reference numerals are provided.

[0066] Relative to power module 30, power module 50 does not comprise an isolated pad 17. Instead, in power module 50 the DC- busbar is attached to an auxiliary substrate 52. The DC- busbar may again be attached to the auxiliary substrate 52 via any suitable means, such as soldering, sintering, transient liquid phase soldering, welding or brazing. The DC- busbar 15 is therefore mounted on the auxiliary substrate 52 and completes the DC power current path loop.

[0067] Auxiliary substrate 52 is itself attached to the (main) substrate 11 by soldering, sintering, transient liquid phase soldering, welding, brazing or any other suitable means. Figures 6a depicts a further side view of power module 50, while Figure 6b depicts an enhanced view of region C showing a busbar 15. The shape of DC- busbar 15 facilitates electro-mechanical connections from the circuit inside the module to the external connection.

[0068] To facilitate this, busbar 15 comprises several sections, for example first 60, second 64 and third 68 sections parallel or approximately parallel to the substrate 11 , and fourth 62 and fifth 66 sections perpendicular or approximately perpendicular to the substrate 11. A first section 60 may be approximately parallel to the substrate 11 for connecting busbar 15 to the auxiliary substrate 52. A fourth section 62 may be approximately perpendicular to the substrate 11. A second section 64 may be approximately parallel to the substrate 11 between the auxiliary substrate 52 and the (DC+) busbar 14, to for reducing a distance between the DC- and DC+ busbars. The third section 62 of busbar 15 may be of sufficient height to raise the second section 64 of busbar 15 above the other components (e.g. wire bonds, sensors, etc.) of the power module 50.

[0069] The busbar 15 further comprises a fifth section 66 approximately perpendicular to the substrate 11. The fifth section 66 is positioned proximate (e.g. separated 10mm or less) to a corresponding section of busbar 14, to increase a mutual coupling of the busbars to therefore reduce the parasitic inductance. Finally, the third section 68 may be approximately parallel to the substrate 11 for facilitating a connection to external devices.

[0070] Figure 7 depicts part of a commutation path 70 in the power loop of the power module 50. Relative to the power module 30 depicted in e.g. Figure 3a, there is no break or gap in the structure of substrate 11 of power module 50. As a result, the current path may pass under or beneath the auxiliary substrate 52 to form an approximately geometrically linear current path (e.g. without or with minimal discontinuities) through substrate 11. Auxiliary substrate 52 may in turn receive a current from wire bonds 18 connected to semiconductor devices 19, and provide the current to the attached busbar. The auxiliary substrate 52 therefore facilitates a shorter commutation loop and reduced power loop inductances relative to the layout of power module 30. It will be understood that this benefit is applicable to busbars of any shape, and is not limited solely to power modules comprising a busbar with a shape corresponding to busbar 15.

[0071] Figure 8 depicts a top view of the (main) upper and lower switch substrates 10, 11 for use in power module 50. As depicted in Figure 8, the auxiliary substrates 12, 13 and 52 facilitates the use of single, contiguous conductive regions across the entirety of the substrate layer. This in turn reserves large conductive (e.g. copper) area on the main substrates 10, 11 for the DC power loop current path, without introducing any discontinuities in the current path flow due to e.g. gaps or holes in the substrate. This in turn helps to reduce or minimise small stray inductances that may result from these discontinuities in the current path, as current may flow uninterrupted in the main substrates 10, 11 due to the current in the return path being routed through the auxiliary substrate.

[0072] Figure 9a depicts current balancing in a power module according to the present disclosure. As depicted by current flows 90, 92, the central position of the middle power busbar may assist in maintaining a balanced current flow through the module.

[0073] Optionally, and as depicted in Figure 9b, the busbar 15 may be approximately the same width as the adjacent row of paralleled semiconductor power devices 19, to thereby further reduce stray inductance in the DC power loop. The use of wide busbars further assist in providing good current balancing across the power module. As further shown in Figure 9c, busbars 14 and 16 may also be wide busbars, for example with approximately the same width as the busbar 15.

[0074] Figure 9d depicts current balancing in an example power module with wide busbars 14, 15, 16. As shown by current flows 94, 96, the current balancing of the module may be further enhanced through the provision of the wide busbars relative to the example current flows 90, 92 depicted in Figure 9a.

[0075] Figure 10 depicts the gate-source current loop 100, which flows through auxiliary substrates 12, 13. The auxiliary substrates 12, 13 help to direct the gate-source current loop perpendicular to the direction of the DC power loop current, thereby reducing or minimising parasitic inductances. Additionally, the use of auxiliary substrates 12, 13 facilitates a more linear flow of current in the DC power loop by reducing or preventing discontinuities in the current path through substrates 10, 11.

[0076] As depicted in Figure 11 , a power module according to the present disclosure may be mounted or otherwise connected to a heatsink 22 or other cooling module, for example using a thermal interface material 21 or any other suitable means known to the skilled person. Insulating films may also be provided, for enhanced electrical isolation and thermal conductivity between the power module and the heatsink 22. The power module packaging may therefore comprise e.g. a forced air cooling heat sink or a water cooling heat sink. It will be understood that the implementations described above are provided merely as illustrative examples, and that the present disclosure is applicable for use in conjunction with e.g. different circuit layouts and / or different circuit topologies. It may be used in power module designs which use Si, SiC or GaN, or other semiconductor device types. It may be used where the semiconductor device is used in combination with a freewheeling or anti-parallel diode is used in the power module. Any other busbar (e.g. DC+, AC) in the module or all busbars in the module may additionally or alternatively be mounted to auxiliary substrates, to facilitate current commutation in the power loop, or in the gate-source loop, without obstacles or discontinuities which affect the direct flow of current in the commutation loop. The DC- busbar shape may similarly be additionally or alternatively applied to the DC+ or the AC busbars.

[0077] Similarly, the substrate may comprise various materials. For example, the substrate may comprise a copper bonded ceramic substrate. The ceramic material may be e.g. Silicon Nitride, Aluminium Nitride, Alumina or any other ceramic insulator. The substrate may instead be an integrated metal substrate (IMS). The IMS may comprise a resin based material as an insulation layer separating the circuit layer from the baseplate. The substrate may alternatively be an integrated metal baseplate (IMB), for example with a ceramic moulded into aluminium or other metal.

[0078] While each implementation described above is depicted with a specifically shaped busbar 15, it will be further understood that the shape of busbar 15 or any other busbar is not an essential feature to some implementations of the present disclosure. For example, any known busbar shape may be used in conjunction with e.g. auxiliary substrates or wide busbars as described above.

[0079] One such example power module 120 is depicted in Figures 12a and b. The structure of power module 120 generally corresponds to that of power module 30 and like reference numerals are provided. In place of busbar 15, a central (e.g. DC-) busbar 122 is attached to pad 17. In contrast to busbar 15 as depicted in power module 30, busbar 122 is provided with any generic shape suitable for a power module, e.g. in a similar manner to the (AC and DC+) busbars 14, 16.

[0080] Also in contrast to power module 30, power module 120 comprises auxiliary substrates 12, 13 for the gate-source current loop, e.g. as shown in power module 50. It will be further understood that power module 120 may additionally or alternatively comprise the auxiliary substrate 52 (with busbar 122 provided on auxiliary substrate 122), wide busbars configuration, or any other features described in relation to other implementations of the disclosure.

[0081] Figure 13 depicts a flow diagram 1300 showing an example method for making a power module according to the present disclosure.

[0082] In step S1301 , one or more semiconductor dies are attached on the main substrates.

[0083] In step 1302, auxiliary substrates are attached to the main substrates.

[0084] In step 1303, wire bonding is provided for the power loop and the gate loop current paths.

[0085] In step 1304, gate resistor(s) are attached, while in step S1305 a signal pin is attached.

[0086] In step 1306, the AC and DC+ busbars are attached in their respective positions.

[0087] In step 1307, the main substrates are attached to a baseplate, if provided.

[0088] In step 1308, the DC- busbar is attached, e.g. to an auxiliary substrate.

[0089] In step 1309, a frame is attached to the substrate or baseplate, and the power module may be encapsulated and / or lidded for improved mechanical stability.

[0090] The skilled person will understand that in the preceding description and appended claims, positional terms such as ‘above’, ‘top’, ‘side’, ‘on’ etc. are made with reference to conceptual illustrations of an apparatus, such as those showing standard cross-sectional perspectives and those shown in the appended drawings. These terms are used for ease of reference but are not intended to be of limiting nature. These terms are therefore to be understood as referring to a device when in an orientation as shown in the accompanying drawings.

[0091] Although the disclosure has been described in terms of preferred embodiments as set forth above, it should be understood that these embodiments are illustrative only and that the claims are not limited to those embodiments. Those skilled in the art will be able to make modifications and alternatives in view of the disclosure, which are contemplated as falling within the scope of the appended claims. Each feature disclosed or illustrated in the present specification may be incorporated in the disclosure, whether alone or in any appropriate combination with any other feature disclosed or illustrated herein.

Claims

CLAIMS:1 . A power module comprising: a substrate one or more semiconductor devices positioned on the substrate; an auxiliary substrate positioned on the substrate; a first busbar located on the auxiliary substrate; and a second busbar electrically connected to the substrate such that, in use, a power loop current path extends between the first and second busbars via the substrate and the auxiliary substrate.

2. The power module of claim 1 , the power module comprising a second substrate electrically connected to the substrate, wherein second power bus bar is electrically connected to the second substrate.

3. The power module of claim 2, comprising a second auxiliary substrate positioned on and electrically connected to the second substrate, wherein the second busbar is located on the second auxiliary substrate.

4. The power module of any preceding claims, wherein the first busbar comprises: first, second and third sections, wherein: the first and third sections are parallel to one another; the second section is between the first section and the third section; and the second section is perpendicular to the first and third sections; and fourth and fifth section perpendicular to the first, second and third sections, wherein: the fourth section is between the first and second sections; and the fifth section is between the second and third sections.

5. The power module of claim 4, wherein: the second section extends from the fourth section towards the second busbar, optionally wherein the second section extends towards the second busbar such that the fifth section is separated from the second busbar by 10mm or less.

6. The power module of any preceding claim, wherein the substrate is a single contiguous element and extends beneath the auxiliary substrate.

7. The power module of claims 2 or 3, or any one of claims 4-6 when dependent upon claims 2 or 3, wherein the second substrate is a single contiguous element.

8. The power module of any preceding claim, comprising a further auxiliary substrate electrically connected to a gate terminal of the one or more semiconductor devices, wherein the further auxiliary substrate is located on the substrate, and wherein the substrate extends beneath of further auxiliary substrate.

9. The power module of claim 8, wherein further auxiliary substrate is perpendicular to the power loop current path extending between the first and second busbars.

10. The power module of any preceding claim, wherein the one or more semiconductor devices comprise a plurality of semiconductor devices arranged geometrically in a line and electrically connected in parallel, wherein a width of the first busbar is equal to or greater than a width of the line such that each semiconductor device is an equal distance from a base of the busbar.

11. The power module of any preceding claim, wherein the one or more semiconductor devices comprise silicon carbide (SiC) based semiconductor devices.

12. The power module of claim 11 , wherein the SiC based semiconductor devices comprise a SiC MOSFET.

13. The power module of claims 2 or 3, or any one of claims 4-12 when dependent upon claims 2 or 3, comprising a baseplate, wherein the substrate and second substrate are located on the baseplate.

14. The power module of any preceding claim arranged in a half bridge configuration.

15. The power module of any preceding claim, comprising a heat sink attached to the substrate.

16. A method for making a power module according to any preceding claim, the method comprising: attaching one or more semiconductor devices to a substrate; attaching an auxiliary substrate to the substrate such that the auxiliary substrate is positioned on and electrically connected to the substrate;attaching a first busbar on the auxiliary substrate; and electrically connecting a second busbar to the substrate such that, in use, a power loop current path extends between the first and second busbars via the substrate and the auxiliary substrate.

17. The method of claim 16, wherein electrically connecting second busbar to the substrate comprises: providing a second substrate; electrically connecting the second substrate to the substrate; and electrically connecting the second busbar to the second substrate.

18. A busbar for use in a power module, the busbar comprising: first, second and third sections, wherein: the first and third sections are parallel to one another; the second section is between the first section and the third section; and the second section is perpendicular to the first and third sections; and fourth and fifth section perpendicular to the first, second and third sections, wherein: the fourth section is between the first and second sections; and the fifth section is between the second and third sections.

19. A power module comprising: the busbar of claim 18 connected to a first substrate a second busbar connected to a second substrate, wherein the first and second substrates are spaced apart from one another; and wherein the second section extends from the first substrate towards the second substrate.

20. The power module of claim 19, wherein the second section extends from the first substrate towards the second substrate such that the fifth section is separated from the second busbar by 10mm or less.

21. The power module of claim 19 or 20, comprising an isolation layer between the fifth section and the second busbar.

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