High-frequency power supply system

Abstract

A high-frequency power supply system according to the present disclosure supplies high-frequency power to a load. The high-frequency power supply system comprises: a first high-frequency power supply that can supply first high-frequency power to the load by outputting a first high-frequency voltage having a first fundamental frequency from a first high-frequency voltage output unit toward the load; and a first slave device. The first high-frequency power supply has: a first high-frequency power supply setting value information output unit that outputs a first high-frequency power supply setting value corresponding to the elapsed time or a command signal corresponding to the first high-frequency power supply setting value on the basis of first high-frequency power supply setting value information indicating the relationship between the elapsed time from a starting point of a cycle within the time of one cycle of amplitude modulation and the first high-frequency power supply setting value; and a first slave device synchronization signal output unit that outputs a first slave device synchronization signal in accordance with the time at which the first slave device setting value should be changed on the basis of first slave device time information indicating the relationship between the elapsed time and the time at which the first slave device setting value used in the first slave device should be changed. The first slave device has a first slave device setting value information output unit that outputs the first slave device setting value corresponding to the elapsed time or a command signal corresponding to the first slave device setting value on the basis of the first slave device synchronization signal, and first slave device setting value information indicating the relationship between the elapsed time and the first slave device setting value.

Description

High-frequency power supply system

[0001] The present disclosure relates to a radio frequency power supply system.

[0002] For example, a high-frequency power supply system used in a plasma processing apparatus has two high-frequency power supply devices (a first high-frequency power supply and a second high-frequency power supply), each of which outputs high-frequency voltages (traveling wave voltages) with different fundamental frequencies (fundamental wave frequencies) to a load. For example, the first high-frequency power supply outputs a high-frequency voltage (traveling wave voltage VF1) having a fundamental frequency F1 suitable for generating plasma, thereby supplying high-frequency power (first traveling wave power) to the load. The second high-frequency power supply outputs a high-frequency voltage (traveling wave voltage VF2) having a fundamental frequency F2 suitable for ion acceleration (fundamental frequency F1 > fundamental frequency F2), thereby supplying high-frequency power (second traveling wave power) to the load (see Patent Document 1).

[0003] A first matching box is provided between the first high frequency power supply and the load, and impedance matching is performed by adjusting the value of an internal variable element (e.g., the capacitance value of a variable capacitor) so that the power value of the reflected wave power at the output end of the first high frequency power supply (the input end of the first matching box) is reduced. A second matching box is provided between the second high frequency power supply and the load, and impedance matching is performed by adjusting the value of an internal variable element (e.g., the capacitance value of a variable capacitor) so that the power value of the reflected wave power at the output end of the second high frequency power supply (the input end of the second matching box) is reduced.

[0004] In the high-frequency power supply system described above, when performing processes such as etching or CVD in a load (e.g., a plasma processing apparatus), the target power value of each power supply may be changed in multiple stages within one cycle of amplitude modulation.

[0005] For example, a high-frequency power supply device such as a first high-frequency power supply or a second high-frequency power supply may perform two-stage amplitude modulation, which alternates between an ON operation in which a high-frequency voltage (high-frequency power) is output and an OFF operation in which no high-frequency voltage (high-frequency power) is output. Alternatively, two-stage amplitude modulation may be performed, which alternates between a first level and a second level, rather than an ON operation and an OFF operation. Furthermore, amplitude modulation involving three or more levels of level change may be performed. Furthermore, various output controls may be performed, such as gradually increasing or decreasing the output level or gradually increasing the duty ratio (see Patent Document 2).

[0006] JP 2023-98298 A JP 2021-57929 A

[0007] In the above configuration, the first and second high frequency power supplies synchronize their control timings (for example, timings for changing the output level of the high frequency voltage).

[0008] Conventionally, each power supply is controlled independently, and a cycle start signal is provided to the first and second high frequency power supplies for each time period of amplitude modulation to synchronize the timing of changing the output levels of the first high frequency voltage output from the first high frequency power supply and the second high frequency voltage output from the second high frequency power supply.

[0009] Each conventional power supply has setting value information that determines its target power value, so that the desired power control can be performed while synchronizing the timing of changing the output level for each time period of the amplitude modulation based on the cycle start signal.

[0010] Each power supply has a built-in reference clock with the same frequency, and switches between target power values ​​determined by the setting value information according to the clock count of each power supply. However, individual differences in each reference clock cause errors in the control timing of each power supply, resulting in synchronization errors.

[0011] For example, if a frequency error of up to 20 ppm occurs between the frequency of the reference clock built into the first high-frequency power supply and the frequency of the reference clock built into the second high-frequency power supply, and if the time for one cycle of the setting value information is one second, then a synchronization error of about 20 μsec will occur at the end of one cycle.

[0012] The set value of the high frequency power set by the set value information may be set to change every tens of microseconds, for example, so the above-mentioned synchronization deviation cannot be ignored.

[0013] The above is not a problem that occurs only between the first high frequency power supply and the second high frequency power supply, but can also occur between the first high frequency power supply and other slave devices (e.g., the first matching box, the second matching box, and a DC power supply that supplies a DC voltage to a load).

[0014] The present invention has been made in view of the above, and has an object to provide a high frequency power supply system that can reduce synchronization deviation between a first high frequency power supply and a slave device (such as a second high frequency power supply).

[0015] A high frequency power supply system according to one aspect of the present invention is a high frequency power supply system that supplies high frequency power to a load, the high frequency power supply system including: a first high frequency power supply that can supply first high frequency power to the load by outputting a first high frequency voltage having a first fundamental frequency from a first high frequency voltage output unit to the load; and a first slave device, wherein the first high frequency power supply is a first high frequency power setting unit that outputs the first high frequency power setting value corresponding to the elapsed time from a start point of one cycle of amplitude modulation or a command signal corresponding to the first high frequency power setting value, based on first high frequency power setting value information indicating a relationship between the first high frequency power setting value and the elapsed time from the start point of the cycle within the time of one cycle of amplitude modulation. and a first slave device synchronization signal output section that outputs a first slave device synchronization signal in accordance with the time at which the first slave device setting value used in the first slave device should be changed, based on first slave device time information that indicates the relationship between the elapsed time and the time at which the first slave device setting value used in the first slave device should be changed, and the first slave device has a first slave device setting value information output section that outputs the first slave device setting value that corresponds to the elapsed time or a command signal that corresponds to the first slave device setting value, based on the first slave device synchronization signal and first slave device setting value information that indicates the relationship between the elapsed time and the first slave device setting value.

[0016] 1 is a diagram showing a configuration of a high frequency power supply system according to an embodiment. FIG. 2 is a diagram for explaining amplitude modulation and a cycle start signal according to an embodiment. FIG. 3 is a diagram for explaining an example of setting value information according to an embodiment. FIG. 4 is a diagram showing an example of the relationship between a first high frequency power supply and a slave device according to an embodiment. FIG. 5 is a diagram for explaining an example of setting value information according to an embodiment. FIG. 6 is a diagram for explaining an example of setting value information according to an embodiment. FIG. 7 is a diagram for explaining an example of setting value information according to an embodiment. FIG. 8 is a diagram showing another example of the relationship between a first high frequency power supply and a slave device according to an embodiment. FIG. 9 is a diagram for explaining an example of setting value information according to an embodiment. FIG. 10 is a diagram showing another example of the amplitude modulated waveform of the first high frequency power supply according to an embodiment. FIG. 11 is a diagram showing an example of set value information for the first high frequency power supply according to an embodiment. FIG. 12 is a diagram showing a configuration of a high frequency power supply system according to a first modified embodiment. FIG. 13 is a diagram showing the operation of a high frequency power supply system according to a first modified embodiment. FIG. 14 is a diagram showing the operation of a high frequency power supply system according to a second modified embodiment. FIG. 15 is a diagram showing the configuration of a high frequency power supply system according to a third modified embodiment. FIG. 16 is a diagram showing the operation of a high frequency power supply system according to the third modified embodiment. FIG. 1 is a diagram showing the configuration of a high-frequency power supply system according to a fourth modified embodiment. FIG. 2 is a diagram showing the operation of a high-frequency power supply system according to a fourth modified embodiment. FIG. 3 is a diagram showing the operation of a high-frequency power supply system according to a fourth modified embodiment. FIG. 4 is a diagram showing the configuration of a high-frequency power supply system according to a fifth modified embodiment. FIG. 5 is a diagram showing the operation of a high-frequency power supply system according to the fifth modified embodiment. FIG. 6 is a diagram explaining synchronization deviation when external noise is erroneously detected as a synchronization signal. FIG. 7 is a diagram explaining a countermeasure (part 1) against external noise in a sixth modified embodiment. FIG. 8 is a diagram explaining a countermeasure (part 2) against external noise in a seventh modified embodiment. FIG. 9 is a diagram explaining a countermeasure (part 3) against external noise in an eighth modified embodiment. FIG. 10 is a diagram explaining a countermeasure (part 4) against external noise in a ninth modified embodiment. FIG. 11 is a diagram showing an example of the configuration of a high-frequency power supply system according to a tenth modified embodiment. FIG. 12 is a diagram showing another example of the configuration of a high-frequency power supply system according to the tenth modified embodiment.

[0017] Hereinafter, embodiments of a high-frequency power supply system according to the present disclosure will be described with reference to the drawings.

[0018] (Embodiment) FIG. 1 is a diagram showing the configuration of a high-frequency power supply system 1. As shown in FIG.

[0019] The high frequency power supply system 1 is an apparatus that supplies high frequency power to a load (e.g., a plasma processing apparatus PA) by outputting a high frequency voltage having a fundamental frequency (frequency of a fundamental wave) in the RF band (RF: Radio Frequency) from a high frequency power supply device. Such a high frequency power supply system 1 includes, for example, a first high frequency power supply device (hereinafter referred to as the first high frequency power supply) 10, a second high frequency power supply device (hereinafter referred to as the second high frequency power supply) 20, and a superposition matching box 50.

[0020] The superposition matching box 50 includes a first impedance matching box (hereinafter referred to as the first matching box) 30, a second impedance matching box (hereinafter referred to as the second matching box) 40, and a superposition output unit 51. The first high frequency power supply 10 and the second high frequency power supply 20 output high frequency voltages having the same or different fundamental frequencies to the load 103. In this specification, the fundamental frequency of the first high frequency power supply 10 is referred to as fundamental frequency F1 (an example of a first fundamental frequency), and the fundamental frequency of the second high frequency power supply 20 is referred to as fundamental frequency F2 (an example of a second fundamental frequency).

[0021] The high frequency power supply system 1 may be configured without the second high frequency power supply 20 and the second matching box 40 as described above. That is, the high frequency power supply system 1 may have a single first high frequency power supply 10 as the high frequency power supply, and the superposition matching box 50 may have a single first matching box 30 as the matching box. The matching box may also be expressed as a matching device. Of course, it is also possible to use matching boxes corresponding to three or more high frequency power supply devices.

[0022] Furthermore, the high frequency power supply system 1 may include not only the high frequency power supplies 10 and 20 but also a DC power supply device (hereinafter referred to as a DC power supply) 60 that supplies a DC voltage to the load 103 .

[0023] Furthermore, the high frequency voltage output from the first high frequency power supply 10 and directed toward the load 103 is referred to as the forward wave voltage VF1, the high frequency voltage reflected from the load 103 side and returning to the first high frequency power supply 10 is referred to as the reflected wave voltage VR1, the high frequency power output from the first high frequency power supply 10 and directed toward the load 103 is referred to as the forward wave power PF1, and the high frequency power reflected from the load 103 side and returning to the first high frequency power supply 10 is referred to as the reflected wave power PR1.

[0024] Furthermore, the high frequency voltage output from the second high frequency power supply 20 and directed toward the load 103 is referred to as the forward wave voltage VF2, the high frequency voltage reflected from the load 103 side and returning to the second high frequency power supply 20 is referred to as the reflected wave voltage VR2, the high frequency power output from the second high frequency power supply 20 and directed toward the load 103 is referred to as the forward wave power PF2, and the high frequency power reflected from the load 103 side and returning to the second high frequency power supply 20 is referred to as the reflected wave power PR2.

[0025] In addition, the power value of the forward wave power PF1 is the forward wave power value pf1, the power value of the reflected wave power PR1 is the reflected wave power value pr1, the power value obtained by subtracting the reflected wave power value pr1 from the forward wave power value pf1 is the load side power value pL1, the power value of the forward wave power PF2 is the forward wave power value pf2, the power value of the reflected wave power PR2 is the reflected wave power value pr2, and the power value obtained by subtracting the reflected wave power value pr2 from the forward wave power value pf2 is the load side power value pL2.

[0026] In this specification, the reflection coefficient expressed as the ratio of the reflected wave voltage to the forward wave voltage (reflected wave voltage / forward wave voltage) is defined as ρ, and the absolute value (magnitude) of the reflection coefficient ρ is defined as Γ. Therefore, the reflection coefficient on the first high frequency power supply 10 side is defined as ρ1, the reflection coefficient on the second high frequency power supply 20 side is defined as ρ2, the absolute value of the reflection coefficient on the first high frequency power supply 10 side is defined as Γ1, and the absolute value of the reflection coefficient on the second high frequency power supply 20 side is defined as Γ2.

[0027] Furthermore, subscripts are used as necessary to indicate corresponding parts. For example, "1" is used for the system of the first high frequency power supply 10 and the first matching box 30, "2" is used for the system of the second high frequency power supply 20 and the second matching box 40, "g" is used for the first high frequency power supply 10 and the second high frequency power supply 20, and "m" is used for the first matching box 30 and the second matching box 40.

[0028] Furthermore, high frequency power supply devices such as the first high frequency power supply 10 and the second high frequency power supply 20 can reduce the power value of the reflected wave power by changing the frequency of the traveling wave voltage they output. Hereinafter, this function will be referred to as "frequency matching." When frequency matching is performed, the fundamental frequency of the traveling wave voltage is not constant but fluctuates. However, the expression "fundamental frequency" (in the above example, fundamental frequency F1 and fundamental frequency F2) will be used to include such cases where the fundamental frequency fluctuates.

[0029] Furthermore, high frequency power supply devices such as the first high frequency power supply 10 and the second high frequency power supply 20 may perform frequency modulation control in order to reduce the power value of reflected wave power caused by intermodulation distortion (hereinafter, IMD). Even when frequency modulation control is performed, the fundamental frequency of the traveling wave voltage is not constant but fluctuates, but is still referred to as the fundamental frequency (in the above example, the fundamental frequency F1 and the fundamental frequency F2).

[0030] The first high frequency power supply 10 outputs a forward voltage VF1 having a fundamental frequency F1 to supply forward power PF1 to the load 103. At this time, feedback control is performed so as to reduce the error between the forward power value pf1 and the target power value pt1. This type of power control is called constant forward power control (constant PF control).

[0031] It is also possible to perform feedback control so as to reduce the error between the load power value pL1 and the target power value pt1. This type of power control is called constant load power control (constant PL control). However, the following description will mainly focus on the case where forward wave constant power control is performed.

[0032] The traveling wave voltage VF1 has a relatively high fundamental frequency F1 suitable for generating plasma. The fundamental frequency F1 is, for example, 40.68 MHz. Of course, the fundamental frequency F1 is not limited to 40.68 MHz and may be, for example, a frequency in the industrial RF band, such as 13.56 MHz or 27.12 MHz.

[0033] The first high frequency power supply 10 not only outputs a continuous wave with a constant forward power value pf1 or a constant load power value pL1, but also can output a variable target power value during a predetermined period. Changing the target power value changes the amplitude of the output forward wave voltage VF1, so this type of output control is referred to as amplitude modulation control in this specification. For simplicity, the term "amplitude modulation" is used. The second high frequency power supply 20 can also perform amplitude modulation control.

[0034] For example, two-stage amplitude modulation may be performed by repeating an ON operation in which the forward power value pf1 is output and an OFF operation in which the forward power value pf1 is not output at a predetermined cycle.In addition, instead of the ON operation and the OFF operation, two-stage amplitude modulation may be performed by repeating a first level and a second level, or multi-stage amplitude modulation with three or more levels may be performed.

[0035] Furthermore, it is configured to be able to perform various output controls, such as output control to gradually decrease or increase the output level, output control to gradually decrease or increase the duty ratio, frequency modulation control to change the fundamental frequency F1, and frequency matching.

[0036] The second high frequency power supply 20 outputs a traveling wave voltage VF2 having a fundamental frequency F2 to supply traveling wave power PF2 to the load 103. The fundamental frequency F2 is the same as or different from the fundamental frequency F1.

[0037] At this time, the second high frequency power supply 20 is subjected to feedback control (constant forward power control) so as to reduce the error between the forward power value pf2 and the target power value pt2. As with the first high frequency power supply 10, feedback control (constant load power control) may be performed so as to reduce the error between the load side power value pL2 and the target power value pt2, but the following description will mainly focus on the case where constant forward power control is performed.

[0038] The traveling wave voltage VF2 has a relatively low fundamental frequency F2 suitable for accelerating ions, for example. The fundamental frequency F2 is, for example, 400 kHz. Of course, the fundamental frequency F2 is not limited to 400 kHz and may be another frequency. For example, it may be a frequency in the industrial RF band, such as 13.56 MHz or 27.12 MHz. Furthermore, the fundamental frequency F2 is not necessarily limited to a frequency lower than the fundamental frequency F1, and may be the same frequency as the fundamental frequency F1 or a frequency higher than the fundamental frequency F1.

[0039] Similar to the first high frequency power supply 10, the second high frequency power supply 20 is configured to be able to perform various output controls.

[0040] The superposition matching box 50 is electrically connected between the first and second high frequency power supplies 10 and 20 and the load 103, for example.

[0041] The load 103 may be, for example, a plasma processing apparatus PA. The plasma processing apparatus PA is, for example, a parallel plate type, and a lower electrode EL1 and an upper electrode EL2 face each other in a chamber CH. A substrate SB to be processed may be placed on the lower electrode EL1. The first and second high frequency power supplies are electrically connected to the lower electrode EL1 via a superposition matching box 50. The upper electrode EL2 is electrically connected to ground potential. The chamber CH is connected to a gas supply device (not shown) via an air supply pipe and to a vacuum device (not shown) via an exhaust pipe.

[0042] When the load 103 is a plasma processing apparatus PA, the superposition matching box 50 may be electrically connected between the first and second high frequency power supplies 10 and 20 and the lower electrode EL1 of the plasma processing apparatus PA.

[0043] The superposition matching device 50 includes a first matching device 30 , a second matching device 40 , and a superposition output section 51 .

[0044] The DC power supply 60 supplies power to the load 103. When the load 103 is a plasma processing apparatus PA, the DC power supply 60 may supply a DC voltage to a lower electrode EL1 of the plasma processing apparatus PA. Of course, the location to which the DC power supply 60 supplies the DC voltage is not limited to the lower electrode EL1.

[0045] The DC power supply 60 is configured to output a DC voltage based on predetermined set values ​​such as a voltage value, a cycle time, a duty ratio, etc. These set values ​​are changeable.

[0046] The external control device 101 is a device that provides, for example, various commands IS (such as a command to start outputting a traveling wave voltage) and various set values ​​ST (such as a target power value). It can also be used to acquire and analyze information (monitoring information) IF, such as the traveling wave power value pf1 calculated by the first high frequency power supply 10. It can also provide a set value ST, such as the duration of one cycle of amplitude modulation, to a cycle start signal generating device 102 (described later). This allows the duration of one cycle of amplitude modulation, etc., to be changed.

[0047] 1, the various commands IS and various setting values ​​ST output from the external control device 101 are transmitted to the first matching device 30 via a first high frequency power supply communication unit 11, which will be described later. Also, the various commands IS and various setting values ​​ST output from the external control device 101 are transmitted to the second matching device 40 via a second high frequency power supply communication unit 21, which will be described later. However, the various commands IS and various setting values ​​ST may be transmitted directly from the external control device 101 to each of the first matching device 30 and the second matching device 40.

[0048] The high-frequency power supply system 1 and the load 103 (e.g., plasma processing apparatus PA) are not limited to the configuration shown in Fig. 1. For example, various configurations are possible, such as a configuration in which the superposition output unit 51 for superposing the traveling wave voltages VF1 and VF2 in the superposition matching box 50 is not provided, and the traveling wave voltage VF1 output from the first high-frequency power supply 10 is supplied to the upper electrode EL2 (which is not electrically connected to ground potential, unlike in Fig. 1) via the first matching box 30, and the traveling wave voltage VF2 output from the second high-frequency power supply 20 is supplied to the lower electrode EL1 via the second matching box 40. The high-frequency power supply system of this embodiment can also be used in such other configurations.

[0049] The period start signal generator 102 outputs a period start signal PS for each period of amplitude modulation.

[0050] 2 is a diagram for explaining amplitude modulation and a cycle start signal. In the example of FIG. 2, the time for one cycle of amplitude modulation is 2,000 μs, and amplitude modulation of the same waveform is repeated.

[0051] Here, the time on the horizontal axis represents the elapsed time from the start point of one cycle of amplitude modulation, so when amplitude modulation is repeated, it represents the time from the start point of a new cycle within the time of one cycle of amplitude modulation. In other words, the time at the start point of the cycle is 0 (zero).

[0052] 2A shows an example of an amplitude modulation waveform of the first high frequency power supply 10, which shows that the forward wave power value pf1 changes over time within one period of the amplitude modulation. In this way, the first high frequency power supply 10 can change the output level in multiple stages.

[0053] In this embodiment, the fundamental frequency F1 of the forward wave voltage VF1 is, for example, 40.68 MHz, so it is not possible to show an accurate waveform in the figure. Therefore, in Fig. 2(a), the waveform of the forward wave voltage VF1 is omitted and only the magnitude of the forward wave power value pf1 is shown. This is true not only for Fig. 2(a) but also for other figures such as Fig. 2(b) and Fig. 4(a).

[0054] 2B shows an example of an amplitude modulation waveform of the second high frequency power supply 20, which shows that the forward wave power value pf2 changes over time within one period of amplitude modulation. In this way, the second high frequency power supply 20 can change its output level in multiple stages.

[0055] 2(c) is an example of the cycle start signal PS, which is a signal whose cycle time is set to match the time of one cycle of amplitude modulation. As can be seen from Fig. 2, the starting point (start time) of the cycle of amplitude modulation can be determined by the cycle start signal PS.

[0056] In the example of Fig. 2(c), the cycle start signal PS is a pulse signal that changes from low level to high level at the start point of the amplitude modulation cycle, but the magnitude relationship before and after the change is not limited to the example shown in Fig. 2(c). For example, it may be a pulse signal that changes from high level to low level. Furthermore, instead of a pulse signal, it may be a signal transmitted via serial communication (for example, a bit pattern of a predetermined length).

[0057] By using this cycle start signal PS, it is possible to synchronize control timing such as the timing at which high frequency voltage output starts between devices that receive the cycle start signal PS. In other words, the cycle start signal PS functions as a signal for controlling synchronization in the devices to which the cycle start signal PS is supplied.

[0058] For example, if the devices to be synchronized are the first high frequency power supply 10, the second high frequency power supply 20, the first matching box 30, the second matching box 40, and the DC power supply 60, then the cycle start signal PS can be supplied to these devices. Of course, if the devices to be synchronized are the first high frequency power supply 10 and the second high frequency power supply 20, then the cycle start signal PS can be supplied to both the first high frequency power supply 10 and the second high frequency power supply 20.

[0059] The duration of one cycle of amplitude modulation is not fixed but can be changed. Therefore, the cycle start signal generator 102 is configured to be able to set the duration of one cycle required to generate the cycle start signal PS. For example, information on the duration of one cycle can be output from the external control device 101, and this information can be stored in a memory unit (not shown) of the cycle start signal generator 102. Furthermore, the generation timing of the cycle start signal PS may be adjustable. For example, the cycle start signal PS may be output when a command ST is received from the external control device 101.

[0060] In the example of FIG. 1, the period start signal generating device 102 is disposed outside the first high frequency power supply 10, but it may be disposed in another location, for example, inside the first high frequency power supply 10.

[0061] <Outline of operation of high frequency power supply system 1> The traveling wave voltage VF1 (traveling wave power value pf1) output from the first high frequency power supply 10 can be supplied to a lower electrode EL1 of a load 103 (e.g., a plasma processing apparatus PA) via a first matching box 30 and a superimposed output unit 51. The traveling wave voltage VF2 (traveling wave power value pf2) output from the second high frequency power supply 20 can be supplied to a lower electrode EL1 of the plasma processing apparatus PA via a second matching box 40 and a superimposed output unit 51.

[0062] That is, in this embodiment, the superposition output unit 51 in the superposition matching box 50 superimposes the traveling wave voltage VF1 and the traveling wave voltage VF2 and supplies the superimposed voltage to the lower electrode EL1. As a result, the plasma processing apparatus PA generates plasma between the lower electrode EL1 and the upper electrode EL2. Furthermore, the superposition matching box 50 performs a first matching operation in the first matching box 30 to match the impedance on the first high frequency power supply 10 side with the impedance on the load 103 side, and also performs a second matching operation in the second matching box 40 to match the impedance on the second high frequency power supply 20 side with the impedance on the load 103 side. Furthermore, the DC power supply 60 supplies a DC voltage to the lower electrode EL1.

[0063] The first high frequency power supply 10 and the second high frequency power supply 20 each control their output power to a predetermined target power value. When the first high frequency power supply 10 performs amplitude modulation, the target power value is changed at a predetermined time. When the second high frequency power supply 20 performs amplitude modulation, the target power value is also changed at a predetermined time.

[0064] Here, the predetermined time corresponds to the elapsed time when the time at the start point of one cycle of amplitude modulation is set to 0.

[0065] In the high-frequency power supply system 1, when the output pattern of amplitude modulation becomes complicated, the setting of the target power value, etc. also becomes complicated, requiring a great deal of effort. Therefore, in this embodiment, the target power value, etc. is set based on the setting value information ST described later, thereby reducing the effort required for setting.

[0066] In this embodiment, the first high frequency power supply 10 is the master device, and the other devices (the second high frequency power supply 20, the first matching box 30, the second matching box 40, the DC power supply 60, etc.) are slave devices.

[0067] Therefore, unless otherwise specified, the first slave device in the present invention is any one of the second high frequency power supply 20, the first matching box 30, the second matching box 40, and the DC power supply 60. Furthermore, the second slave device is any one of the slave devices other than the first slave device.

[0068] In addition, in this embodiment, the set value information ST used in the first high frequency power supply 10 is set value information ST1 for the first high frequency power supply, the set value information ST used in the second high frequency power supply is set value information ST2 for the second high frequency power supply, the set value information ST used in the first matching box 30 is set value information ST3 for the first matching box, the set value information ST used in the second matching box 40 is set value information ST4 for the second matching box, and the set value information ST used in the DC power supply 60 is set value information ST5 for the DC power supply.

[0069] Below, the first high frequency power supply 10, the second high frequency power supply 20, the first matching box 30, the second matching box 40 and the DC power supply 60 will be described in detail, and then the set value information ST and related matters will be described.

[0070] <Details of First High Frequency Power Supply 10> The configuration of the first high frequency power supply 10 will be described below with reference to FIG.

[0071] The first high frequency power supply 10 has a first high frequency power supply communication unit 11, a first high frequency voltage output unit 12, a first high frequency power supply sensor 13, a first power information calculation unit 14, a first comparison unit 15, a first control target switching unit 16, a first power control unit 17, and a first high frequency power supply reference clock generation unit 18. The configuration including the first high frequency power supply sensor 13 and the first power information calculation unit 14 functions as a first power detection unit 10a.

[0072] The first high frequency power supply 10 also has a first high frequency power supply information storage unit 19 and a first high frequency power supply setting value information output unit 71. The first high frequency power supply information storage unit 19 stores first high frequency power supply setting value information ST1.

[0073] The first high frequency power supply setting value information ST1 is information indicating the relationship between the elapsed time from the start point of one cycle of amplitude modulation and the first high frequency power supply setting value.

[0074] The first high frequency power supply setting value information output unit 71 outputs a first high frequency power supply setting value corresponding to the elapsed time or a command signal corresponding to the first high frequency power supply setting value, based on the first high frequency power supply setting value information ST1.

[0075] In the first high frequency power supply 10, the parts that perform calculation processing and signal processing can be configured with, for example, circuits such as a CPU (Central Processing Unit) or FPGA (Field Programmable Gate Array), storage media such as memory, etc. Furthermore, the operation of each part can be controlled according to a control program pre-stored in a ROM (Read Only Memory), etc., and processing such as input / output, calculation, and time measurement can be performed. The first high frequency power supply 10 is equipped with a first high frequency power supply reference clock generation unit 18, and processing is performed for each control period based on a clock signal output from the first high frequency power supply reference clock generation unit 18. In this embodiment, the frequency of the reference clock of the first high frequency power supply reference clock generation unit 18 is 100 MHz, but is not limited to this frequency.

[0076] In the second high frequency power supply 20, the first matching box 30, the second matching box 40, and the DC power supply 60 described below, the parts that perform calculation processing and signal processing can also be configured with, for example, circuits such as a CPU or an FPGA, storage media such as a memory, etc. Also, a reference clock generating unit is provided. Since these are similar to those described above, description thereof will be omitted when describing the second high frequency power supply 20, the first matching box 30, the second matching box 40, and the DC power supply 60.

[0077] The first high frequency power communication unit 11 can communicate with other devices.

[0078] The first high frequency power supply communication unit 11 can, for example, output a signal generated inside the first high frequency power supply 10 to another device. The first high frequency power supply communication unit 11 can also input, for example, a command IS or a set value ST output from the external control device 101 and output it to each unit within the first high frequency power supply 10. The first high frequency power supply communication unit 11 can also input a cycle start signal PS output by the cycle start signal generating device 102 and output it to each unit within the first high frequency power supply 10.

[0079] In addition, the first high frequency power supply communication unit 11 is capable of communicating with an external control device 101, a period start signal generating device 102, a first matching device 30, a second matching device 40, a DC power supply 60, etc., but explanations thereof will be omitted.

[0080] First high frequency voltage output unit 12 outputs traveling wave voltage VF1. At this time, first high frequency voltage output unit 12 controls the output level based on command IS from first power control unit 17, so that it can output high frequency power of a desired power value.

[0081] As described above, high frequency power supply devices such as the first high frequency power supply 10 and the second high frequency power supply 20 are capable of performing frequency matching, frequency modulation control, etc. Therefore, the first high frequency power supply 10 sets necessary information when performing frequency matching, frequency modulation control, etc. The necessary information is, for example, information related to frequency such as the fundamental frequency, offset frequency, and frequency fluctuation range.

[0082] Furthermore, necessary information is set in first high frequency power supply setting value information ST1, and first high frequency power supply setting value information ST1 is stored in first high frequency power supply information storage unit 19. First high frequency power supply setting value information output unit 71 can read first high frequency power supply setting value information ST1 from first high frequency power supply information storage unit 19 and output it to first high frequency voltage output unit 12. First high frequency voltage output unit 12 can receive this information ST1 and use it for control.

[0083] The same is true for second high frequency power supply 20, where necessary information is set in second high frequency power supply setting value information ST2 and stored in second high frequency power supply information storage unit 29. Second high frequency power supply setting value information output unit 72 can read second high frequency power supply setting value information ST2 from second high frequency power supply information storage unit 29 and output it to second high frequency voltage output unit 22. Second high frequency voltage output unit 22 can input this information ST2 and use it for control.

[0084] The first high frequency power supply sensor 13 is provided at the output end of the first high frequency power supply 10, and passes the traveling wave voltage VF1 output from the first high frequency voltage output unit 12 and outputs it to the first matching box 30 of the superposition matching box 50. The first high frequency power supply sensor 13 also detects the traveling wave voltage VF1 output from the first high frequency voltage output unit 12 and outputs a detected signal, which is a traveling wave voltage detection signal vf1g, to the first power information calculation unit 14. The first high frequency power supply sensor 13 also detects a reflected wave voltage VR1 reflected from the load 103 side and returning to the first high frequency power supply 10, and outputs a detected signal, which is a reflected wave voltage detection signal vr1g, to the first power information calculation unit 14. The first high frequency power supply sensor 13 can be, for example, a directional coupler.

[0085] An A / D converter (not shown) may be provided between the first high frequency power sensor 13 and the first power information calculation unit 14 .

[0086] The first power information calculation unit 14 receives the forward wave voltage detection signal vf1g and the reflected wave voltage detection signal vr1g output from the first high frequency power supply sensor 13, and calculates and outputs the forward wave power value pf1, the reflected wave power value pr1, the load side power value pL1, and the reflection coefficient absolute value Γ1 based on the received signals. Since the calculation methods are well known, detailed explanations will be omitted, but for example, the calculations can be performed as follows. The calculated information IF can be output to the external control device 101 or the like as monitor information IF.

[0087] It is also possible to calculate the forward power value pf1 for each output level during amplitude modulation. Therefore, for example, a cycle start signal PS may be input to identify the start time of the amplitude modulation cycle. This allows the first power information calculation unit 14 to identify the output level during amplitude modulation. The same applies to the reflected power value pr1, the load power value pL1, and the reflection coefficient absolute value Γ1.

[0088] (1) Forward Wave Power Value pf1 The first power information calculation unit 14 calculates the forward wave power value pf1 based on the input forward wave voltage detection signal vf1g. For example, the first power information calculation unit 14 squares the input forward wave voltage detection signal vf1g, then uses a low-pass filter (e.g., an IIR filter) that extracts desired components to remove information about unnecessary frequency components, and further multiplies the squared signal by a constant for conversion to the forward wave power value pf1 to calculate the forward wave power value pf1. The forward wave power value pf1 can be calculated, for example, by the forward wave voltage detection signal vf1g^2 / R (R: gain corresponding to the resistance value).

[0089] (2) Reflected Wave Power Value pr1 The first power information calculator 14 calculates the reflected wave power value pr1 based on the input reflected wave voltage detection signal vr1g. For example, the first power information calculator 14 squares the input reflected wave voltage detection signal vr1g, then uses a low-pass filter (e.g., an IIR filter) that extracts desired components to remove information about unnecessary frequency components, and then multiplies the squared signal by a constant for conversion to the reflected wave power value pr1 to calculate the reflected wave power value pr1. The reflected wave power value pr1 can be calculated, for example, by the reflected wave voltage detection signal vr1g^2 / R (R: gain corresponding to the resistance value).

[0090] (3) Load-Side Power Value pL1 The first power information calculation unit 14 calculates the load-side power value pL1 based on the forward power value pf1 and the reflected power value pr1 calculated above. For example, the load-side power value pL1 can be calculated as forward power value pf1 - reflected power value pr1 (forward power value pf1 minus reflected power value pr1).

[0091] (4) Reflection Coefficient Absolute Value Γ1 The first power information calculator 14 calculates the reflection coefficient absolute value Γ1 based on the forward power value pf1 and the reflected power value pr1. The reflection coefficient absolute value Γ1 can be calculated, for example, by √(reflected power value pr1 / forward power value pf1).

[0092] The first control object switching unit 16 receives the forward power value pf1 and the load side power value pL1 as an input, and outputs either one of them as a control object to the first comparing unit 15. The control object is determined, for example, based on a command signal IS output from the external control device 101 or the first high frequency power supply set value information output unit 71. When the forward power value pf1 is the control object, forward power constant control is performed, and when the load side power value pL1 is the control object, load side power constant control is performed.

[0093] The first comparison unit 15 subtracts the power value to be controlled (forward wave power value pf1 or load side power value pL1) from the target power value pt1, and outputs the subtraction result as error information Δpf1 to the first power control unit 17. The target power value pt1 is output from the first high frequency power supply setting value information output unit 71.

[0094] The first power control unit 17 generates an amplitude adjustment signal IS for controlling the amplitude of the forward wave voltage VF1 in accordance with the error information Δpf1 and outputs the signal to the first high frequency voltage output unit 12. This makes it possible to adjust the amplitude of the forward wave voltage VF1, and thereby adjust the forward wave power value pf1.

[0095] For example, if the target power value pt1 is 1,000 [W] and the forward power value pf1 is 950 [W], this is 50 [W] short of the target power value pt1, so the first power control unit 17 determines and outputs the magnitude of the amplitude adjustment signal so as to increase the forward power value pf1 supplied to the load 103 by 50 [W]. For controlling the amplitude of the forward voltage initial signal VF1ini in this way, known techniques such as PI control and PID control can be used.

[0096] At this time, the first high frequency power supply setting value information output unit 71 outputs the corresponding target power value pt1 in accordance with the change in the output level during amplitude modulation, so that the forward wave power value pf1 can be changed in multiple stages.

[0097] <Details of second high frequency power supply 20> The second high frequency power supply 20 has a second high frequency power supply communication unit 21, a second high frequency voltage output unit 22, a second high frequency power supply sensor 23, a second power information calculation unit 24, a second comparison unit 25, a second control target switching unit 26, a second power control unit 27, and a second high frequency power supply reference clock generation unit 28. The configuration including the second high frequency power supply sensor 23 and the second power information calculation unit 24 functions as a second power detection unit.

[0098] Second high frequency power supply 20 also has second high frequency power supply information storage unit 29 and second high frequency power supply setting value information output unit 72. Second high frequency power supply information storage unit 29 also stores the above-mentioned second high frequency power supply setting value information ST2.

[0099] The second high frequency power supply setting value information output unit 29 outputs a second high frequency power supply setting value corresponding to the elapsed time or a command signal corresponding to the second high frequency power supply setting value, based on second high frequency power supply setting value information ST2 indicating the relationship between the elapsed time and the second high frequency power supply setting value.

[0100] The second high frequency power supply communication unit 21, the second high frequency voltage output unit 22, the second high frequency power supply sensor 23, the second power information calculation unit 24, the second controlled object switching unit 26, the second comparison unit 25, the second power control unit 27, and the second high frequency power supply reference clock generation unit 28 are similar to the first high frequency power supply communication unit 11, the first high frequency voltage output unit 12, the first high frequency power supply sensor 13, the first power information calculation unit 14, the first controlled object switching unit 16, the first comparison unit 15, the first power control unit 17, and the first high frequency power supply reference clock generation unit 18 of the first high frequency power supply 10, respectively, and therefore will not be described again.

[0101] The second high frequency power supply setting value information ST2 is information indicating the relationship between the elapsed time from the start point of one cycle of amplitude modulation and the second high frequency power supply setting value.

[0102] <Details of the Superposition Matching Device 50> The superposition matching device 50 has a first matching device 30, a second matching device 40, and a superposition output unit 51. The first matching device 30 is electrically connected, for example, between the first high frequency power supply 10 and the lower electrode EL1. The second matching device 40 is electrically connected, for example, between the second high frequency power supply 20 and the lower electrode EL1. The first matching device 30 performs a first matching operation, and the second matching device 40 performs a second matching operation.

[0103] <First matching device 30> The first matching device 30 has a first matching device communication unit 31, a first matching device sensor 32, a first matching device matching circuit 33, a first matching device calculation unit 34, a first matching device control unit 35, and a first matching device reference clock generation unit 36.

[0104] The first matching device 30 also includes a first matching device information storage unit 37 and a first matching device setting value information output unit 73. The first matching device information storage unit 37 stores first matching device setting value information ST3.

[0105] The first matching device communication unit 31 can communicate with other devices.

[0106] For example, the period start signal PS output by the period start signal generating device 102 is input and output to the first matching device setting value information output unit 73, the first matching device calculation unit 34, and the first matching device control unit 35.

[0107] In addition, the first high frequency power supply communication unit 31 is capable of communicating with an external control device 101, a period start signal generating device 102, the first high frequency power supply 10, the second high frequency power supply 20, the second matching box 40, and the DC power supply 60, etc., but a description thereof will be omitted.

[0108] The first matching box sensor 32 is provided at the input end of the first matching box 30, and detects information for calculating a load-side impedance Z1 when looking at the load 103 from the input end of the first matching box 30 (equivalent to the output end of the first high frequency power supply 10), or information for calculating a reflection coefficient ρ1 at the input end of the first matching box 30. The load-side impedance Z1 and the reflection coefficient ρ1 can be converted into each other, so either may be detected.

[0109] When calculating the load-side impedance Z1, for example, a voltage detector and a current detector are used as the first matching box sensor 32. In this case, the voltage detector detects the voltage at the input end of the first matching box 30 and outputs a voltage detection signal v1 as its detection signal. Also, the current detector detects the current at the input end of the first matching box 30 and outputs a current detection signal i1 as its detection signal. The voltage detection signal v1 and the current detection signal i1 are output to the first matching box calculation unit 34.

[0110] When calculating the reflection coefficient ρ1 at the input end of the first matching box 30, for example, a directional coupler is used as the first matching box sensor 32. In this case, the sensor 32 detects the traveling wave voltage VF1 output from the first high frequency power supply 10 and outputs a traveling wave voltage detection signal vf1m as its detection signal, and also detects the reflected wave voltage VR1 reflected back from the load 103 and outputs a reflected wave voltage detection signal vr1m as its detection signal. The traveling wave voltage detection signal vf1m and the reflected wave voltage detection signal vr1m are output to the first matching box calculator 34.

[0111] An A / D converter (not shown) may be provided between the first matching device sensor 32 and the first matching device calculation unit 34 .

[0112] The first matching circuit 33 is provided between the first matching circuit sensor 32 and the superposition output unit 51. This first matching circuit 33 includes a variable element such as a variable capacitor (also called a variable condenser) whose capacitance can be changed, and changes the variable value of the variable element (capacitance in the case of a variable capacitor, inductance in the case of a variable inductor) in response to a command from the first matching circuit control unit 35 (described later), thereby adjusting the load-side impedance Z1 as seen from the input end of the first matching circuit 30 to the load 103 side. A variable inductor may be provided as the variable element. The first matching circuit 33 also includes a drive circuit (not shown) for changing the capacitance of the variable element in response to a command from the first matching circuit control unit 35.

[0113] In addition to the variable element, there are many cases where an inductor with a fixed inductance is provided, and there are also cases where a capacitor with a fixed capacitance is provided.

[0114] Such a matching circuit 33 for the first matcher is often a so-called inverted L type (also called L type), π type, or other matching circuit.

[0115] There are various types of variable capacitors. For example, there is a type of variable capacitor that changes its capacitance by changing the distance between electrodes. There is also a type of variable capacitor that connects multiple capacitors in series with switches in parallel and changes the overall capacitance by changing the state (ON / OFF) of the switches. In this way, the type of variable capacitor is not limited.

[0116] The first matching device calculation unit 34 calculates the reflection coefficient ρ1 or the load-side impedance Z1 based on the information output from the first matching device sensor 32, and outputs the calculated value to the first matching device control unit 35 as load information IF on the first matching device 30 side. The reflection coefficient ρ1 and the load-side impedance Z1 are the load information IF representing the load state. The first matching device calculation unit 34 may include a filter on the input side for removing unnecessary signal components (e.g., harmonic components). In this case, the type of the filter may be selected appropriately.

[0117] The reflection coefficient ρ1 can be calculated, for example, from the reflected wave voltage detection signal vr1m / forward wave voltage detection signal vf1m. The load impedance Z1 can be calculated, for example, from the voltage detection signal v1 / current detection signal i1. The load impedance Z1 can be calculated, for example, based on the magnitude of the voltage detection signal v1, the magnitude of the current detection signal i1, and the phase difference θ between the voltage detection signal v1 and the current detection signal i1. Since the methods for calculating the reflection coefficient ρ1 and the load impedance Z1 are well known, a detailed description thereof will be omitted.

[0118] Furthermore, since the reflection coefficient ρ1 and the load side impedance Z1 can be converted into each other, in order to simplify the explanation, in the following, the first matching device calculation unit 34 may only explain either the reflection coefficient ρ1 or the load side impedance Z1.

[0119] The first matching device control unit 35 uses the load information IF2 on the first matching device 30 side output from the first matching device calculation unit 34 to output a command signal for controlling the variable value of the variable element in the matching circuit 33 for the first matching device so that the absolute value Γ1 of the reflection coefficient ρ1 approaches the target reflection coefficient absolute value Γ0 (normally 0). In other words, it outputs a command signal for controlling the variable value of the variable element in the matching circuit 33 for the first matching device so that the load side impedance Z1 becomes the complex conjugate of the output impedance Z0 of the first high frequency power supply 10. For example, if the variable element provided in the matching circuit 33 for the first matching device is a variable capacitor, it outputs a command signal for controlling the capacitance. More specifically, for example, it calculates the capacitance of the variable capacitor that is predicted to make the absolute value Γ1 of the reflection coefficient ρ1 closest to the target reflection coefficient absolute value Γ0, and outputs a command signal to a drive circuit that drives the variable capacitor so that the capacitance is reached.

[0120] When performing the above-described control, first matching device control unit 35 can use setting value ST3 for first matching device 30 or a command signal corresponding to setting value ST3 output from first matching device setting value information output unit 73. Furthermore, first matching device control unit 35 can synchronize with other devices using cycle start signal PS.

[0121] <Second matching device 40> The second matching device 40 has a second matching device communication unit 41, a second matching device sensor 42, a second matching device matching circuit 43, a second matching device calculation unit 44, a second matching device control unit 45, and a second matching device reference clock generation unit 46. These have the same functions as the first matching device communication unit 31, the first matching device sensor 32, the first matching device matching circuit 33, the first matching device calculation unit 34, the first matching device control unit 35, and the first matching device reference clock generation unit 36 ​​of the first matching device 30, and therefore description thereof will be omitted.

[0122] The second matching device 40 also has a second matching device information storage unit 47 and a second matching device setting value information output unit 74. The second matching device information storage unit 47 stores second matching device setting value information ST4.

[0123] The second matching device setting value information output unit 74 outputs a second matching device setting value corresponding to the elapsed time or a command signal corresponding to the second matching device setting value, based on second matching device setting value information ST4 that indicates the relationship between the elapsed time and the second matching device setting value.

[0124] In addition, like the first matching device calculation unit 34, the second matching device calculation unit 44 calculates the reflection coefficient ρ2 or the load side impedance Z2 based on the information output from the second matching device sensor 42 (the reflected wave voltage detection signal vr2m and the forward wave voltage detection signal vf2m, or the voltage detection signal v2 and the current detection signal i2), and outputs it to the second matching device control unit 45 as load information IF on the second matching device 40 side.

[0125] Similar to the first matching device 30, the second matching device control unit 45 can use the setting value ST4 for the second matching device 40 output from the second matching device setting value information output unit 74 or a command signal corresponding to the setting value ST4. In addition, the second matching device control unit 45 can synchronize with other devices using the cycle start signal PS.

[0126] <Details of DC power supply 60> The DC power supply 60 has a DC power supply setting value information output unit 76, a DC power supply communication unit 61, a DC-DC converter 62, a pulse voltage output unit 63, a DC power supply control unit 64, and a DC power supply reference clock generation unit 65.

[0127] The DC power supply 60 also has a DC power supply information storage unit 66 and a DC power supply setting value information output unit 76. The DC power supply information storage unit 66 also stores DC power supply setting value information ST5.

[0128] The DC power supply setting value information output unit 76 outputs a DC power supply setting value corresponding to the elapsed time or a command signal corresponding to the DC power supply setting value, based on DC power supply setting value information ST5 indicating the relationship between the elapsed time and the DC power supply setting value.

[0129] The DC power supply communication unit 61 receives the cycle start signal PS output by the cycle start signal generating device 102 and outputs it to the DC power supply setting value information output unit 76 and the DC power supply control unit 64. The DC power supply communication unit 61 can also communicate with the first high frequency power supply 10 and the like. For example, the reflection coefficient ρ1 calculated by the first matching box 30 and the like can be output to the first high frequency power supply 10.

[0130] The DC-DC converter 62 outputs a DC voltage of a predetermined voltage. The predetermined voltage is a relatively high voltage, such as -10 kV. The polarity is not limited to negative. The absolute value of the voltage is also not limited.

[0131] The pulse voltage output unit 63 intermittently outputs the DC voltage output from the DC-DC converter 62. As a result, a pulsed voltage is output and supplied to the load 103 (for example, the plasma processing apparatus PA).

[0132] The DC power supply control unit 64 controls the DC-DC converter 62 and the pulse voltage output unit 63 .

[0133] For example, the duty ratio of the switching elements in the DC-DC converter 62 is controlled so that the output voltage of the DC-DC converter 62 becomes a target voltage value.

[0134] Furthermore, by controlling the duty ratio of the switching element inside the pulse voltage output unit 63, the pulse width, duty ratio, etc. of the pulsed voltage are controlled.

[0135] When performing the above-described control, the DC power supply control unit 64 can use the setting value ST5 for the DC power supply 60 output from the DC power supply setting value information output unit 76 or a command signal corresponding to the setting value ST5. In addition, synchronization with other devices can be achieved by the cycle start signal PS.

[0136] <Regarding the setting value information ST> Various settings are possible for the setting value information ST. Below, the setting value information ST and related matters will be described using several setting examples.

[0137] (1) Setting Example of Set Value Information ST (Part 1) Fig. 3 is a diagram for explaining a setting example of set value information. Fig. 3(a) shows an example of set value information ST1 for the first high frequency power supply corresponding to Fig. 2(a). In the set value information ST1 for the first high frequency power supply, setting items include a "No." indicating the order, a duration [µs], and a target power value [W] for the first high frequency power supply.

[0138] Fig. 3(b) shows an example of the second high frequency power supply setting value information ST2 corresponding to Fig. 2(b). The second high frequency power supply setting value information ST2 has setting items such as a "No." indicating the order, a duration [µs], and a target power value [W] of the second high frequency power supply.

[0139] Fig. 3(c) shows another example of the first high frequency power supply setting value information ST1 corresponding to Fig. 2(a), in which the duration [µs] shown in Fig. 3(a) is converted into elapsed time [µs].

[0140] Fig. 3(d) shows another example of second high frequency power supply setting value information ST2 corresponding to Fig. 2(b), in which the duration [µs] shown in Fig. 3(b) is converted into elapsed time [µs].

[0141] 3(a) to 3(d), the order of the columns is random. Also, the information constituting the setting value information ST is read in order by the corresponding setting value information output units 71 and 72, so the "No." information is not essential. This concept applies hereinafter as well.

[0142] In this way, the setting value information ST can be expressed in a table format. The setting value information ST includes multiple sets of information, as shown by the dashed line in Fig. 3(a), for example, and one set of information shown by the dotted line in Fig. 3(a) includes information on elapsed time and information on at least one type of setting item (for example, target power value).

[0143] While Figures 3(a) and 3(b) use duration as the time element, it may also be expressed as elapsed time, as in Figures 3(c) and 3(d). For example, in Figure 3(a), the elapsed time of No. 1 is 100 μs, and the elapsed time of No. 2 is 100 μs, so the elapsed time at the start of execution of No. 3 is 200 μs. Also, as mentioned above, in the example of Figure 2, the time for one cycle of amplitude modulation is 2,000 μs, so the elapsed time at the start of execution of No. 20 in Figure 3(c) is 1,900 μs, and the duration of No. 20 is 100 μs.

[0144] As can be seen from the above, time may be expressed as a duration or as an elapsed time, but in either case, the setting value information ST shown in Figure 3 indicates the relationship between the elapsed time from the start point of one cycle of amplitude modulation and a target power value as an example of a setting value.

[0145] The setting values ​​stored as the setting value information ST are sequentially read by the corresponding setting value information output units 71, 72, which then perform the corresponding processing. In the example of Fig. 3, since the target power value is stored, the setting value information output unit (e.g., first high frequency power supply setting value information output unit 71) outputs the setting value of the target power value corresponding to the elapsed time to a comparison unit (e.g., first comparison unit 15). For example, information on 100 W, which is the setting value of the target power value of the first high frequency power supply 10 for period No. 2, is output to the first comparison unit 15 as the target power value pt1. This allows the high frequency power supply (e.g., first high frequency power supply 10) to control the power value to be output.

[0146] Therefore, by using the information of the set value information ST1, the first high frequency power supply 10 can perform the amplitude modulation shown in Fig. 2(a) , and by using the information of the set value information ST2, the second high frequency power supply 20 can perform the amplitude modulation shown in Fig. 2(b) .

[0147] In this way, even when performing complex amplitude modulation such as that shown in FIGS. 2(a) and 2(b), it is easy to set the set value (target power value, etc.) because it is only necessary to set a set value (target power value, etc.) corresponding to the elapsed time from the start point of one cycle of amplitude modulation, as shown in FIG. 3.

[0148] As shown in Fig. 2, the same waveform is often repeated in amplitude modulation. In this case, the setting value information ST shown in Fig. 3(a) to Fig. 3(d) can be used repeatedly. In other words, it is only necessary to set the setting value information ST for one cycle of amplitude modulation.

[0149] (2) Setting Example of Set Value Information ST (Part 2) FIG. 4 is a diagram showing an example of the relationship between the first high frequency power supply 10 and the slave device.

[0150] 4 is obtained by adding, to FIG. 2, an example of a period during which load information is acquired by the first matching box 30 and the second matching box 40, and an example of a period during which voltage is output by the DC power supply 60. Since FIG. 4(a) corresponds to FIG. 2(a) and FIG. 4(c) corresponds to FIG. 2(b), their explanations will be omitted. Furthermore, the cycle start signal PS shown in FIG. 2 is omitted in FIG. 4.

[0151] The first matching box 30 and the second matching box 40 may each acquire load information (reflection coefficient ρ or load-side impedance Z) IF for the entire period of one amplitude modulation cycle and perform matching operation using the acquired load information IF, or may acquire load information IF for a specific period and perform matching operation based on the acquired load information IF. In this case, matching operation may be performed during other periods assuming the same load information IF as during the specific period. The specific period is, for example, the period during which the target power value of the first high-frequency power supply 10 is highest.

[0152] 4(b) shows a case where the period during which the target power value of the first high frequency power supply 10 is the highest is set as a specific period, and the first matching box 30 acquires load information IF during this specific period. Also, FIG. 4(d) shows a case where the period during which the target power value of the second high frequency power supply 20 is the highest is set as a specific period, and the second matching box 40 acquires load information IF during this specific period.

[0153] It is not necessary to acquire the load information IF for the entire specific period. For example, since the state of the load 103 becomes unstable immediately after the target power value of the first high frequency power supply 10 is changed, the load information IF may be acquired after a predetermined time has elapsed since the target power value of the first high frequency power supply 10 was changed.

[0154] Furthermore, it is not necessary to change the variable value of the variable element in the first matching circuit 33 for the entire period. For example, the variable value of the variable element may be maintained immediately after the target power value of the first high frequency power supply 10 is changed.

[0155] 4( e) shows a case where the DC power supply 60 outputs a voltage during a period when the target power value of the first high frequency power supply 10 is high. Of course, the DC power supply 60 may output a voltage during other periods. For example, the DC power supply 60 may output a voltage during a period when the target power value of the second high frequency power supply 20 is high. The DC power supply may also output a voltage during a period when the target power value of the first high frequency power supply 10 and a period when the target power value of the second high frequency power supply 20 are relatively high. The DC power supply may also output a voltage during a period when the target power values ​​of the first high frequency power supply 10 and the second high frequency power supply 20 are relatively low.

[0156] FIG. 5 shows an example of the first matching device setting value information ST3, the second matching device setting value information ST4, and the DC power supply setting value information ST5.

[0157] 5A shows an example of the first matching device setting value information ST3 corresponding to FIG. 4B. The first matching device setting value information ST3 indicates the relationship between a "No." indicating the order, a duration [μs], and a period for acquiring the load information IF.

[0158] 5B shows an example of the second matching device setting value information ST4 corresponding to FIG. 4D. The second matching device setting value information ST4 indicates the relationship between a "No." indicating the order, a duration [μs], and a period for acquiring the load information IF.

[0159] Here, when the load information IF acquisition period is "1", it indicates a period during which the load information IF is acquired, and when it is "0", it indicates a period during which the load information IF is not acquired.

[0160] Fig. 5(c) shows an example of DC power supply setting value information ST5 corresponding to Fig. 4(e). The DC power supply setting value information ST5 shows the relationship between a "No." indicating the order, a duration [µs], and a voltage output period. Here, when the voltage output period is "1", it indicates a period during which voltage is output, and when the voltage output period is "0", it indicates a period during which voltage is not output.

[0161] The operation of each device will be described below assuming that the input of the cycle start signal PS is the start point of one cycle of amplitude modulation (elapsed time is 0).

[0162] 5 shows that the first matching device 30 acquires load information IF during periods No. 9 and No. 13. Therefore, the first matching device setting value information output unit 73 outputs a command signal (the control target switching signal in FIG. 1 ) to the first matching device control unit 34 during periods No. 9 and No. 13 to instruct the first matching device control unit 34 to adopt the load information IF output from the first matching device calculation unit 33. The first matching device control unit 34 performs a matching operation using the adopted load information IF so that the absolute value Γ1 of the reflection coefficient ρ1 approaches the target reflection coefficient absolute value Γ0 (normally 0).

[0163] That is, even during periods other than those No. 9 and No. 13, matching operations are performed using the load information IF acquired during those periods. Note that during the period No. 1, the output of first high frequency power supply 10 is 0 W, so matching operations are not performed. The output level of first high frequency power supply 10 can be calculated based on information from first matching device sensor 32.

[0164] 5 shows that the second matching device 40 acquires load information IF during period No. 1. Therefore, the second matching device 40 acquires load information IF during period No. 1 and performs matching operations during periods No. 1 and No. 2 using the acquired load information IF. This control is similar to that of the first matching device 30, and therefore a description thereof will be omitted.

[0165] 5 shows that DC power supply 60 outputs a voltage during Periods No. 9 and No. 13. Therefore, DC power supply setting value information output unit 76 instructs DC power supply control unit 64 that these are voltage output periods during Periods No. 9 and No. 13. DC power supply control unit 64 instructs pulse voltage output unit 63 to output a voltage.

[0166] By doing as described above, it is possible to perform control corresponding to FIG.

[0167] Here, the setting value information ST shown in Figures 5(a) to 5(c) can be simplified. For example, in Figure 5(a), the setting values ​​for the acquisition periods No. 1 to No. 8 are the same, so they can be combined into one. However, the setting value information ST shown in Figures 5(a) to 5(c) has not been simplified in order to clarify the correspondence with Figure 4.

[0168] That is, the first matching device setting value information ST3 shown in Fig. 5(a) is set with the same time intervals as the first high frequency power supply setting value information ST1 shown in Fig. 3(a). Similarly, the second matching device setting value information ST4 shown in Fig. 5(b) is set with the same time intervals as the second high frequency power supply setting value information ST2 shown in Fig. 3(b). Similarly, the DC power supply setting value information ST5 shown in Fig. 5(c) is set with the same time intervals as the first high frequency power supply setting value information ST1 shown in Fig. 3(a).

[0169] This is because, in the example of FIG. 5, the period during which the matching circuits 30 and 40 acquire the load information IF and the period during which the DC power supply 60 outputs voltage are related to the target power value.

[0170] 5, the time intervals of the set value information ST3, ST4, and ST5 may be set to be the same as the time intervals of the set value information ST1 and ST2 of the corresponding high frequency power supplies 10 and 20. By doing so, the period for acquiring the load information IF in the matching devices 30 and 40 and the period for outputting a voltage in the DC power supply 60 can be easily set.

[0171] (3) Setting Example of Set Value Information (Part 3) FIG. 6 shows another example of the first matching device set value information ST3, the second matching device set value information ST4, and the DC power supply set value information ST5.

[0172] Fig. 6(a) shows another example of the first matching device setting value information ST3 corresponding to Fig. 4(b). Fig. 6(b) shows another example of the second matching device setting value information ST4 corresponding to Fig. 4(d). Fig. 6(c) shows another example of the DC power supply setting value information ST5 corresponding to Fig. 4(e).

[0173] As described above, when the acquisition period of the load information IF is related to the target power value, the first high frequency power supply setting value information ST1 can be used as the first matching device setting value information ST3. Similarly, the second high frequency power supply setting value information ST2 can be used as the second matching device setting value information ST4.

[0174] Similarly, when the voltage output period of DC power supply 60 is related to the target power value, first high frequency power supply setting value information ST1 or second high frequency power supply setting value information ST2 can be used as DC power supply setting value information ST5. Fig. 6(c) shows an example in which first high frequency power supply setting value information ST1 is used as DC power supply setting value information ST5.

[0175] In such a case, the relationship between the target power value and the acquisition period of the load information IF may be stored separately for the first and second matching. For example, for the first matching, a target power value of 800 W of the first high frequency power supply 10 may be recognized as the acquisition period. Alternatively, the period with the highest target power value among the set value information may be automatically determined.

[0176] Similarly, the relationship between the target power value and the voltage output period may be stored separately in the DC power supply 60. For example, when the target power value of the first high frequency power supply 10 is 800 W, this may be recognized as an acquisition period. Alternatively, the period with the highest target power value may be automatically determined from the setting value information ST.

[0177] The control of each device is the same as in the case of FIG. 5, and therefore the explanation will be omitted.

[0178] 6, there is no need to determine the output levels of the high-frequency power sources 10 and 20. For example, in the example of FIG. 5, when the output level of the corresponding high-frequency power sources 10 and 20 is 0, the matching operation must be stopped, and therefore the output level must be determined based on the outputs of the sensors 32 and 42. However, in FIG. 6, whether or not to perform the matching operation can be determined based on the set value information ST, making control easier. Moreover, it is only necessary to copy the set value information ST1 and ST2 of the corresponding high-frequency power sources 10 and 20.

[0179] (4) Setting Example of Set Value Information (Part 4) FIG. 7 shows another example of the first high frequency power supply set value information ST1 and the second high frequency power supply set value information ST2.

[0180] FIG. 7A shows the first high frequency power supply setting value information ST1 shown in FIG. 3A, to which a fundamental frequency and a control method have been added as setting items.

[0181] FIG. 7B shows the second high frequency power supply setting value information ST2 shown in FIG. 3B, to which a fundamental frequency and a control method have been added as setting items.

[0182] In this way, the setting items other than the "No." and duration [μs] of the set value information ST can be set to multiple types rather than just one type. In the case of Figure 7, in both Figure 7(a) and Figure 7(b), the target power value, fundamental frequency, and control method are the three setting items other than the "No." and duration [μs]. In the control method, "PL" indicates load side constant power control, and "PF" indicates forward wave constant power control.

[0183] 7A, the target power value for Period No. 1 is 0 W, so that no high frequency power is output from first high frequency power supply 10.

[0184] Then, in Period No. 2, high frequency power is output from first high frequency power supply 10 under the conditions that the target power value is 100 W, the fundamental frequency is 40.68 MHz, and the control method is constant load power control. This constant load power control continues until Period No. 3. In Period No. 4, the control method changes to constant forward power control, and thereafter, constant forward power control continues until Period No. 20.

[0185] Then, in period No. 8, the fundamental frequency is changed from 40.68 MHz to 40.78 MHz. After that, the fundamental frequency remains at 40.78 MHz until period No. 14, but then returns to 40.68 MHz in period No. 15. After that, the fundamental frequency remains at 40.68 MHz until period No. 20.

[0186] After the period No. 20 ends, the process returns to No. 1, and the first high frequency power supply set value information is repeatedly used. Of course, this does not necessarily apply when the amplitude modulation control ends, the set value information is changed, or the like.

[0187] The information on the target power value in the first high frequency power supply setting value information ST1 shown in FIG. 7A is read from the first high frequency power supply information storage unit 19 as the target power value pt1 in FIG.

[0188] The information on the fundamental frequency in the first high frequency power supply setting value information ST1 shown in Fig. 7(a) is read out from the first high frequency power supply information storage unit 19 as information such as frequency information FR in Fig. 1. This information such as frequency information FR is output to, for example, the first high frequency voltage output unit 12.

[0189] The control method information in the first high frequency power supply setting value information ST1 shown in Fig. 7(a) is read from the first high frequency power supply information storage unit 19 as the control method information in Fig. 1. This control method information is output to the first control object switching unit 16, for example.

[0190] 7B , during Period No. 1, high frequency power is output from second high frequency power supply 20 under the conditions that the target power value is 800 W, the fundamental frequency is 400 kHz, and the control method is constant load power control.

[0191] Then, in period No. 2, the target power value is changed to 500 W, the fundamental frequency is changed to 410 kHz, and the control method is changed to constant forward power control.

[0192] Thereafter, in period No. 3, the target power value is set to 0 W, the fundamental frequency is set to 400 kHz, and the control method is changed to constant forward power control. However, since the target power value is 0 W, no high frequency power is output from second high frequency power supply 20.

[0193] After the end of the period No. 3, the process returns to No. 1, and the second high frequency power supply set value information ST2 is repeatedly used. Of course, this does not necessarily apply when the amplitude modulation control is ended, the set value information ST is changed, or the like.

[0194] The various pieces of information in the second high frequency power supply setting value information ST2 shown in Fig. 7(b) are read out from the first high frequency power supply information storage unit 29. This is the same as the case of the first high frequency power supply 10 shown in Fig. 7(a), and therefore a description thereof will be omitted.

[0195] In this way, by setting the setting items and setting values ​​that are suited to each device, it becomes possible to perform a variety of controls.

[0196] Of course, other setting items can be set in addition to those described above. For example, various setting items can be set, such as a command value for frequency matching, a command value for frequency modulation control for IMD suppression, and the like.

[0197] (5) Setting Example of Set Value Information (Part 5) FIG. 8 is a diagram showing another example of the relationship between the first high frequency power supply 10 and the slave device.

[0198] 8 shows an example in which, in contrast to FIG. 4 , the start time of one cycle of amplitude modulation of the second high frequency power supply 20 and the start time of one cycle of amplitude modulation of the second matching box 40 are set later than the start time of one cycle of amplitude modulation of the first high frequency power supply 10.

[0199] 8 shows an example in which a power ramp time is set when changing the target power value of the high frequency power in the second high frequency power supply 20. The power ramp time at the target power value is the time during which the target power value is slowly changed like a ramp function.

[0200] Fig. 9 shows another example of the first high frequency power supply set value information ST1, the second high frequency power supply set value information ST2, and the second matching device set value information ST4 corresponding to Fig. 8. Note that the first matching device set value information ST3 and the DC power supply set value information ST5 are omitted.

[0201] FIG. 9A shows an example of first high frequency power supply setting value information ST1, which is similar to FIG. 7A and will not be described further.

[0202] Fig. 9(b) shows an example of second high frequency power supply setting value information ST2, which is the same as the second high frequency power supply setting value information ST2 shown in Fig. 7(b) except that a power ramp time is added as a setting item and a delay time (200 µS) is set for the duration of period No. 1.

[0203] Therefore, the start time of one cycle of amplitude modulation of second high frequency power supply 20 is delayed by 200 μS from the start time of one cycle of amplitude modulation of first high frequency power supply 10. The amplitude modulation of second high frequency power supply 20 is performed based on the information from the periods No. 2 to No. 4. After No. 4, the process returns to No. 2, so from the second cycle of amplitude modulation, amplitude modulation is performed based on the information from the periods No. 2 to No. 4 without any delay.

[0204] Furthermore, since power ramp times are set in periods No. 2 and No. 3, the amplitude modulation waveform of second high frequency power supply 20 becomes as shown in FIG.

[0205] Fig. 9(c) is an example of second matching device setting value information ST4. In Fig. 9(c), a delay time is set in accordance with second high frequency power supply setting value information ST2 in Fig. 9(b), and a period for acquiring load information IF is set to correspond to the power ramp time.

[0206] If the delay time is a positive time, it indicates that the start time of the amplitude modulation in the first high frequency power supply 10 is earlier than the start time of the amplitude modulation in the second high frequency power supply 20. If the delay time is a negative time, it indicates the opposite.

[0207] 8 and 9, in the second high frequency power supply 20 and the second matching box 40 for which a delay time is set, the start point of the period within one period of amplitude modulation is delayed by the delay time. Therefore, the second high frequency power supply 20 and the second matching box 40 do not set the time when the period start signal is input as the start point of the period within one period of amplitude modulation, but set a time shifted by the delay time as the start point.

[0208] This applies not only to the slave device but also to the first high frequency power supply 10 .

[0209] That is, when a delay time is set in first high frequency power supply 10, the time shifted by the delay time from the time when the cycle start signal is input is set as the start time in first high frequency power supply 10. When a delay time is set in the slave device, the time shifted by the delay time from the time when the cycle start signal PS is input is set as the start time in the slave device.

[0210] In other words, the time when the period start signal PS generated every time period of one period of amplitude modulation is input or the time when the period start signal PS is input plus a delay time is considered to be the starting point of the period within the time period of one period of amplitude modulation.

[0211] (6) Example of Setting Value Information (No. 6) FIG. 10 shows another example of the amplitude modulation waveform of the first high frequency power supply 10. In FIG.

[0212] FIG. 11 shows an example of the first high frequency power supply setting value information ST1 corresponding to FIG.

[0213] FIG. 11 shows that the number of repetitions can be set for a set of consecutive information in the setting value information ST1.

[0214] In Fig. 10, in the initial period of one cycle of amplitude modulation, the target power value changes from 1000 W to 900 W to 1000 W to 900 W. That is, the change from 1000 W to 900 W is repeated twice. Therefore, as shown in Fig. 11, the number of repetitions for this period should be set to two. This makes it easier to set the target power value.

[0215] In contrast, there is no repetition in the subsequent period in which the target power value changes from 800 W to 700 W, so the number of repetitions is 1. Note that if the number of repetitions is 1, the repetition can be omitted.

[0216] 10, the waveform for the period from 0 to 1,400 μs elapsed from the start point of one cycle of amplitude modulation is also repeated for the period from 1,400 to 2,800 μs. Therefore, the number of repetitions for the information for the period from 0 to 1,400 μs elapsed is set to two.

[0217] Similarly, the number of repetitions for information on the period of elapsed time from 2,800 to 3,600 μs may be set to two.

[0218] In this way, the number of sets of information to be repeated is arbitrary. For example, the number of repetitions may be set for two sets of information, or for three sets of information.

[0219] The number of repetitions may also be set for information that includes information for which the number of repetitions is set and other information.

[0220] Furthermore, although not shown in FIGS. 10 and 11, the number of repetitions for the entire information may be set.

[0221] As can be seen from the above example, if the number of repetitions can be set for information with a set number of repetitions and other information, it is easy to create long-term set value information, which is very useful in plasma processing, where such repetitive patterns exist frequently.

[0222] Of course, the above concept is similarly applied to other set value information (set value information ST2 for the second high frequency power supply, set value information ST3 for the first matching device, set value information ST4 for the second matching device, and set value information ST5 for the DC power supply).

[0223] As described above, when amplitude modulation is performed, the settings can be easily made by using the setting value information ST for each device.

[0224] <Comparison with the Prior Art> When amplitude modulation is performed using the prior art, it is necessary to determine the following setting values ​​(1) to (3) for each predetermined period. Furthermore, these setting values ​​are transmitted from the external control device 101 to the high frequency power supply devices 10 and 20 in accordance with the progress of the plasma processing process.

[0225] (1) Information on the frequency (the reciprocal of the cycle time) or cycle time for a predetermined period; (2) Information on the target power value for each level; and (3) Information on the duty ratio.

[0226] For example, when performing the amplitude modulation described in Figures 10 and 11 using the conventional technology, the periods No. 1 and No. 2 are set as predetermined periods, and information on a total of five setting values ​​(A) to (C) below needs to be transmitted from external control device 101 to high frequency power supply devices 10 and 20 immediately before the start of period No. 1.

[0227] Although the periods No. 1 and No. 2 are repeated twice, the set value information for the next predetermined period is automatically repeated until it is transmitted from the external control device 101 to the high-frequency power supply devices 10 and 20, so there is no need to transmit it again for the second repetition. Therefore, the total time including the repetition of the predetermined periods (periods No. 1 and No. 2) is 400 μs.

[0228] (A) Frequency (reciprocal of cycle time) or cycle time for a specified period 5,000 Hz for frequency, 200 μs for cycle time (B) Target power value information Target power value for period No. 1: 1,000 W Target power value for period No. 2: 900 W (C) Duty ratio information Time for period No. 1 / (Time for period No. 1 + Time for period No. 2): 50% Time for period No. 2 / (Time for period No. 1 + Time for period No. 2): 50%

[0229] Next, with No. 3 and No. 4 being set as predetermined periods (repeated once), it is necessary to transmit information on a total of five setting values ​​from external control device 101 to high-frequency power supply devices 10 and 20 immediately before period No. 3 begins.

[0230] As described above, the total time of the previous predetermined periods (periods No. 1 and No. 2) is 400 μs, and so within this 400 μs, information on a total of five setting values ​​needs to be transmitted from external control device 101 to high frequency power supply devices 10 and 20. However, with the current state of the art, it is difficult to complete transmission within such a short time.

[0231] Next, the periods No. 5 and No. 6 are set as a predetermined period (repeated three times), and the setting value information (a total of five setting value information) must be transmitted from external control device 101 to high-frequency power supply devices 10 and 20 immediately before the start of period No. 5. However, because the total time of the previous predetermined period (periods No. 3 and No. 4) is 400 μs, it is difficult to complete transmission of the setting value information within this time.

[0232] Thereafter, the process proceeds in the following order: period No. 1 and No. 2 (repeated twice) → period No. 3 and No. 4 (repeated once) → period No. 5 and No. 6 (repeated three times) → period No. 7 and No. 8 (repeated twice) → period No. 9 and No. 10 (repeated twice) → period No. 7 and No. 8 (repeated twice) → period No. 9 and No. 10 (repeated twice)

[0233] However, since the total time for each period is short, it is difficult to complete the transmission of the setting value information.

[0234] Therefore, with the conventional technology, it is difficult to perform the amplitude modulation described with reference to FIGS.

[0235] In contrast, in the high frequency power supplies 10, 20 and the high frequency power supply system 1 of this embodiment, when amplitude modulation is performed in the high frequency power supplies 10, 20, the high frequency power supply setting value information ST1, ST2 required for amplitude modulation can be set in advance in the high frequency power supplies 10, 20. Therefore, it is possible to realize amplitude modulation that requires changing the setting value in a shorter time than the time required for transmitting the high frequency power supply setting value information ST1, ST2 from the external control device 101 to the high frequency power supply 10, 20. For example, it is possible to realize even the complex amplitude modulation described in FIGS. 10 and 11 .

[0236] In recent years, there has been a demand for complex amplitude modulation waveforms, and also for high-speed changes to set values ​​such as target power values, so the effects obtained by this embodiment are extremely useful.

[0237] Furthermore, when performing processing in accordance with the progress of a plasma processing process in a slave device such as a matching device, slave device setting value information required for the processing can be set in advance in the slave device, so that even processing that requires changing the setting value in a time shorter than the time required to transmit slave device setting value information ST from external control device 101 or high frequency power supply devices 10 and 20 to the slave device can be realized.

[0238] (First Modification of the Embodiment) Next, as a first modification of the embodiment, a configuration of a high frequency power supply system that reduces synchronization deviation between a first high frequency power supply serving as a master device and a slave device will be described.

[0239] FIG. 12 is a diagram showing the configuration of a high-frequency power supply system 1i according to a first modified example of the embodiment.

[0240] The following description will focus on the differences from the embodiment.

[0241] The above-mentioned cycle start signal PS (see FIG. 1) is not essential, and the cycle start signal PS may be used when necessary, for example, as in the example of FIG. 24 described later.

[0242] <Details of First High Frequency Power Supply 10i> The first high frequency power supply 10i has a first high frequency power supply communication unit 11, a first high frequency voltage output unit 12, a first high frequency power supply sensor 13, a first power information calculation unit 14, a first comparison unit 15, a first control target switching unit 16, a first power control unit 17, and a first high frequency power supply reference clock generation unit 18. The configuration including the first high frequency power supply sensor 13 and the first power information calculation unit 14 functions as a first power detection unit 10a. These are the same as those in FIG. 1 , and therefore description thereof will be omitted.

[0243] The first high frequency power supply 10i also has a first high frequency power supply information storage unit 19i, a first high frequency power supply setting value information output unit 71, and a slave device synchronization signal output unit 77i. The slave device synchronization signal output unit 77i includes a second high frequency power supply synchronization signal output unit 82, a first matching device synchronization signal output unit 83, a second matching device synchronization signal output unit 84, and a DC power supply synchronization signal output unit 86. The first high frequency power supply information storage unit 19i also stores first high frequency power supply setting value information ST1, second high frequency power supply time information TI2, first matching device time information Ti3, second matching device time information TI4, and DC power supply time information TI5.

[0244] The first high frequency power supply setting value information ST1 is information indicating the relationship between the elapsed time from the start point of one cycle of amplitude modulation and the first high frequency power supply setting value.

[0245] The first high frequency power supply setting value information output unit 71 outputs a first high frequency power supply setting value corresponding to the elapsed time or a command signal corresponding to the first high frequency power supply setting value, based on the first high frequency power supply setting value information ST1.

[0246] The second high frequency power supply time information TI2 is information indicating the relationship between the elapsed time and the time at which the second high frequency power supply setting value used in the second high frequency power supply 20 should be changed.

[0247] The first matching device time information TI3 is information indicating the relationship between the elapsed time and the time at which the first matching device setting value used in the first matching device 30 should be changed.

[0248] The second matching device time information TI4 is information indicating the relationship between the elapsed time and the time at which the second matching device setting value used in the second matching device 40 should be changed.

[0249] The DC power supply time information TI5 is information indicating the relationship between the elapsed time and the time at which the DC power supply setting value used in the DC power supply should be changed.

[0250] Each of these pieces of time information is an example of slave device time information TI.

[0251] Based on second high frequency power time information TI2, second high frequency power synchronization signal output section 82 outputs second high frequency power synchronization signal SS2 in accordance with the time at which the second high frequency power setting value should be changed.

[0252] Based on the first matching device time information TI3, the first matching device synchronization signal output section 83 outputs the first matching device synchronization signal SS3 in accordance with the time at which the first matching device setting value should be changed.

[0253] Based on the second matching device time information TI4, the second matching device synchronization signal output section 84 outputs the second matching device synchronization signal SS4 in accordance with the time at which the second matching device setting value should be changed.

[0254] The DC power supply synchronization signal output unit 86 outputs a DC power supply synchronization signal SS5 in accordance with the time at which the DC power supply setting value should be changed, based on the DC power supply time information TI5.

[0255] These synchronization signals SS are each an example of a slave device synchronization signal SS.

[0256] <Details of second high frequency power supply 20> The second high frequency power supply 20 has a second high frequency power supply communication unit 21, a second high frequency voltage output unit 22, a second high frequency power supply sensor 23, a second power information calculation unit 24, a second comparison unit 25, a second control target switching unit 26, a second power control unit 27, and a second high frequency power supply reference clock generation unit 28. The configuration including the second high frequency power supply sensor 23 and the second power information calculation unit 24 functions as a second power detection unit. These are the same as those in FIG. 1, so their description will be omitted.

[0257] The second high frequency power supply 20 also has a second high frequency power supply information storage unit 29 and a second high frequency power supply set value information output unit 72. The second high frequency power supply set value information output unit 72 can receive a second high frequency power supply synchronization signal SS2 from the first high frequency power supply 10i via the second high frequency power supply communication unit 21. The second high frequency power supply information storage unit 29 also stores the above-mentioned second high frequency power supply set value information ST2.

[0258] The second high frequency power supply setting value information ST2 is information indicating the relationship between the elapsed time from the start point of one cycle of amplitude modulation and the second high frequency power supply setting value.

[0259] 1, the superposition matching device 50 includes a first matching device 30, a second matching device 40, and a superposition output unit 51. The first matching device 30 performs a first matching operation, and the second matching device 40 performs a second matching operation.

[0260] <First matching device 30> The first matching device 30 has a first matching device communication unit 31, a first matching device sensor 32, a first matching device matching circuit 33, a first matching device calculation unit 34, a first matching device control unit 35, and a first matching device reference clock generation unit 36. These are the same as those in FIG. 1, so their description will be omitted.

[0261] The first matching device 30 also includes a first matching device information storage unit 37 and a first matching device setting value information output unit 73. The first matching device information storage unit 37 stores first matching device setting value information ST3.

[0262] The first matching device set value information output unit 73 can receive the first matching device synchronization signal SS3 from the first high frequency power supply 10i via the first matching device communication unit 31. The first matching device set value information output unit 73 outputs a first matching device set value corresponding to the elapsed time or a command signal corresponding to the first matching device set value, based on the first matching device synchronization signal SS3 and the first matching device set value information ST3 indicating the relationship between the elapsed time and the first matching device set value.

[0263] <Second matching device 40> The second matching device 40 has a second matching device communication unit 41, a second matching device sensor 42, a second matching device matching circuit 43, a second matching device calculation unit 44, a second matching device control unit 45, and a second matching device reference clock generation unit 46. These are the same as those in FIG. 1, so their description will be omitted.

[0264] The second matching device 40 also has a second matching device information storage unit 47 and a second matching device setting value information output unit 74. The second matching device information storage unit 47 stores second matching device setting value information ST4.

[0265] The first matching device set value information output unit 74 can receive the second matching device synchronization signal SS4 from the first high frequency power supply 10i via the second matching device communication unit 41. The second matching device set value information output unit 74 outputs a second matching device set value corresponding to the elapsed time or a command signal corresponding to the second matching device set value, based on the second matching device synchronization signal SS4 and second matching device set value information ST4 indicating the relationship between the elapsed time and the second matching device set value.

[0266] <Details of DC power supply 60> The DC power supply 60 has a DC power supply setting value information output unit 76, a DC power supply communication unit 61, a DC-DC converter 62, a pulse voltage output unit 63, a DC power supply control unit 64, and a DC power supply reference clock generation unit 65. These are the same as those in FIG. 1, so their description will be omitted.

[0267] The DC power supply 60 also has a DC power supply information storage unit 66 and a DC power supply setting value information output unit 76. The DC power supply information storage unit 66 also stores DC power supply setting value information ST6.

[0268] DC power supply setting value information output unit 76 can receive DC power supply synchronization signal SS5 from first high frequency power supply 10i via DC power supply communication unit 61. Based on DC power supply synchronization signal SS5 and DC power supply setting value information ST5 indicating the relationship between elapsed time and DC power supply setting value, DC power supply setting value information output unit 76 outputs a DC power supply setting value corresponding to the elapsed time or a command signal corresponding to the DC power supply setting value.

[0269] Next, a detailed description will be given of how the first high frequency power supply generates a synchronization signal and synchronizes with the slave device using the synchronization signal.

[0270] For example, in the high-frequency power supply system 1i shown in FIG. 12, the slave device may be at least one of the second high-frequency power supply 20, the first matching box 30, the second matching box 40, the DC power supply 60, etc., but here, the second high-frequency power supply 20 will be described as the slave device.

[0271] FIG. 13 is an explanatory diagram of the synchronization timing between the synchronization signals SS2 to SS5 generated in the first high frequency power supply 10i and the slave devices.

[0272] FIG. 13A shows an example of an amplitude modulation waveform of the first high frequency power supply 10i.

[0273] FIG. 13B shows an example of the second high frequency power supply synchronization signal SS2.

[0274] FIG. 13C shows an example of an amplitude modulation waveform of the second high frequency power supply 20.

[0275] FIG. 13D shows an example of first high frequency power supply setting value information ST1 corresponding to FIG. 13A.

[0276] FIG. 13E shows an example of second high frequency power source time information TI2 corresponding to FIG. 13B.

[0277] FIG. 13(f) shows an example of second high frequency power supply setting value information ST2 corresponding to FIG. 13(c).

[0278] The first high frequency power supply setting value information ST1 shown in Fig. 13(d) and the second high frequency power supply setting value information ST2 shown in Fig. 13(f) both have a setting value of the target power value set as a setting item, which allows the first high frequency power supply 10i and the second high frequency power supply 20 to perform amplitude modulation.

[0279] As indicated by the bold arrow, time information TI2 for the second high frequency power supply shown in Fig. 13(e) includes information corresponding to the elapsed time information of second high frequency power supply setting value information ST2 shown in Fig. 13(f). That is, time information TI2 for the second high frequency power supply includes information indicating the time at which the second high frequency power supply setting value should be changed, as indicated by the dotted line in Fig. 13(f).

[0280] Here, the time at which the set value should be changed corresponds to the elapsed time from the starting point of one cycle of amplitude modulation, where the starting point is set to time 0.

[0281] For example, since period No. 1 begins when the elapsed time from the starting point is 0 ms, the time at which the setting value should be changed during period No. 1 is the time 0 ms after the starting point (the same time as the starting point). Furthermore, period No. 2 begins when the elapsed time from the starting point is 300 ms, so the time at which the setting value should be changed during period No. 2 is the time 300 ms after the starting point. In this way, the time at which the setting value should be changed indicates the timing at which the setting value should be changed.

[0282] The time when the set value should be changed can also be said to be the time when the set value changes, and therefore the time when the set value should be changed also indicates the timing when the set value changes.

[0283] As described above, second high frequency power supply synchronization signal output unit 82 of first high frequency power supply 10i outputs second high frequency power supply synchronization signal SS2 in accordance with the time at which the second high frequency power supply set value should be changed, based on second high frequency power supply time information TI2. In other words, second high frequency power supply synchronization signal output unit 82 outputs second high frequency power supply synchronization signal SS2 at a timing corresponding to the time at which the target power value in second high frequency power supply 20 should be changed.

[0284] This second high frequency power supply synchronization signal SS2 is, for example, a pulse-like signal that changes from high level to low level, and the synchronization timing occurs when the signal changes from low level to high level. That is, in this example, the synchronization timing occurs at the rising edge timing of the second high frequency power supply synchronization signal SS2. Of course, the logic may be reversed. That is, the second high frequency power supply synchronization signal may be a pulse-like signal that changes from low level to high level, and the synchronization timing occurs when the signal changes from high level to low level. This concept will be applied hereinafter as well.

[0285] Furthermore, the second high frequency power supply setting value information output unit 72 of the second high frequency power supply 20 outputs a second high frequency power supply setting value corresponding to the elapsed time or a command signal corresponding to the high frequency power supply setting value, based on the second high frequency power supply synchronization signal SS2 and second high frequency power supply setting value information ST2 indicating the relationship between the elapsed time and the second high frequency power supply setting value.

[0286] Therefore, when second high frequency power supply synchronization signal SS2 is input (more precisely, at the above-mentioned synchronization timing), second high frequency power supply set value information output unit 72 outputs information on the target power value corresponding to the elapsed time to second high frequency voltage output unit 22. This allows second high frequency power supply 20 to perform amplitude modulation based on second high frequency power supply set value information ST2.

[0287] Furthermore, since the second high frequency power supply synchronization signal SS2 is input to the second high frequency power supply 20 each time the second high frequency power supply setting value corresponding to the elapsed time is changed, synchronization is achieved more frequently than when synchronization is achieved using the cycle start signal PS. Therefore, even if a frequency error occurs between the frequency of the reference clock built into the first high frequency power supply 10i and the frequency of the reference clock built into the second high frequency power supply 20, there is almost no loss of synchronization between the first high frequency power supply 10i and the second high frequency power supply 20. Similarly, there is almost no loss of synchronization between the first high frequency power supply 10i and other slave devices.

[0288] In the above, the second high-frequency power supply 20 has been described as a slave device, but the same effect can be obtained with other slave devices (e.g., the first matching box 30, the second matching box 40, the DC power supply 60, etc.).

[0289] Second Modification of the Embodiment Next, another configuration of the high frequency power supply system will be described as a second modification of the embodiment.

[0290] FIG. 14 is a diagram showing the configuration of a high-frequency power supply system 1j according to a second modification of the embodiment.

[0291] The following description will focus on the differences from the embodiment.

[0292] The above-mentioned cycle start signal PS (see FIG. 1) is not essential, and the cycle start signal PS may be used when necessary, for example, as in the example of FIG. 24 described later.

[0293] <Details of First High Frequency Power Supply 10j> The first high frequency power supply 10j has a first high frequency power supply communication unit 11, a first high frequency voltage output unit 12, a first high frequency power supply sensor 13, a first power information calculation unit 14, a first comparison unit 15, a first control target switching unit 16, a first power control unit 17, and a first high frequency power supply reference clock generation unit 18. The configuration including the first high frequency power supply sensor 13 and the first power information calculation unit 14 functions as a first power detection unit 10a. These are the same as those in FIG. 1 , and therefore description thereof will be omitted.

[0294] The first high frequency power supply 10j also has a first high frequency power supply information storage unit 19, a first high frequency power supply setting value information output unit 71, and a slave device synchronization signal output unit 77j. The slave device synchronization signal output unit 77j includes a common slave synchronization signal output unit 89. The first high frequency power supply information storage unit 19 also stores first high frequency power supply setting value information ST1.

[0295] The first high frequency power supply setting value information ST1 is information indicating the relationship between the elapsed time from the start point of one cycle of amplitude modulation and the first high frequency power supply setting value.

[0296] The first high frequency power supply setting value information output unit 71 outputs a first high frequency power supply setting value corresponding to the elapsed time or a command signal corresponding to the first high frequency power supply setting value, based on the first high frequency power supply setting value information ST1.

[0297] The common slave synchronization signal output unit 89 outputs a common slave synchronization signal SS6 in accordance with the time when the set value for each slave device should be changed, based on the first high frequency power supply set value information ST1.

[0298] <Details of second high frequency power supply 20> The second high frequency power supply 20 has a second high frequency power supply communication unit 21, a second high frequency voltage output unit 22, a second high frequency power supply sensor 23, a second power information calculation unit 24, a second comparison unit 25, a second control target switching unit 26, a second power control unit 27, and a second high frequency power supply reference clock generation unit 28. The configuration including the second high frequency power supply sensor 23 and the second power information calculation unit 24 functions as a second power detection unit 20a. These are the same as those in FIG. 1, so their description will be omitted.

[0299] Second high frequency power supply 20 also has second high frequency power supply information storage unit 29 and second high frequency power supply setting value information output unit 72. Second high frequency power supply information storage unit 29 also stores the above-mentioned second high frequency power supply setting value information ST2.

[0300] The second high frequency power supply setting value information ST2 is information indicating the relationship between the elapsed time from the start point of one cycle of amplitude modulation and the second high frequency power supply setting value.

[0301] The second high frequency power supply setting value information output unit 72 outputs a second high frequency power supply setting value corresponding to the elapsed time or a command signal corresponding to the high frequency power supply setting value, based on the common slave device synchronization signal SS6 and second high frequency power supply setting value information ST2 indicating the relationship between the elapsed time and the second high frequency power supply setting value.

[0302] 1, the superposition matching device 50 includes a first matching device 30, a second matching device 40, and a superposition output unit 51. The first matching device 30 performs a first matching operation, and the second matching device 40 performs a second matching operation.

[0303] <First matching device 30> The first matching device 30 has a first matching device communication unit 31, a first matching device sensor 32, a first matching device matching circuit 33, a first matching device calculation unit 34, a first matching device control unit 35, and a first matching device reference clock generation unit 36. These are the same as those in FIG. 1, so their description will be omitted.

[0304] The first matching device 30 also includes a first matching device information storage unit 37 and a first matching device setting value information output unit 73. The first matching device information storage unit 37 stores first matching device setting value information ST3.

[0305] The first matching device setting value information output unit 73 outputs a first matching device setting value corresponding to the elapsed time or a command signal corresponding to the first matching device setting value, based on the common slave device synchronization signal and first matching device setting value information ST3 indicating the relationship between the elapsed time and the first matching device setting value.

[0306] <Second matching device 40> The second matching device 40 has a second matching device communication unit 41, a second matching device sensor 42, a second matching device matching circuit 43, a second matching device calculation unit 44, a second matching device control unit 45, and a second matching device reference clock generation unit 46. These are the same as those in FIG. 1, so their description will be omitted.

[0307] The second matching device 40 also has a second matching device information storage unit 47 and a second matching device setting value information output unit 74. The second matching device information storage unit 47 stores second matching device setting value information ST4.

[0308] The second matching device setting value information output unit 74 outputs a second matching device setting value corresponding to the elapsed time or a command signal corresponding to the second matching device setting value, based on the common slave device synchronization signal and second matching device setting value information ST4 indicating the relationship between the elapsed time and the second matching device setting value.

[0309] <Details of DC power supply 60> The DC power supply 60 has a DC power supply setting value information output unit 76, a DC power supply communication unit 61, a DC-DC converter 62, a pulse voltage output unit 63, a DC power supply control unit 64, and a DC power supply reference clock generation unit 65. These are the same as those in FIG. 1, so their description will be omitted.

[0310] Furthermore, the DC power supply 60 has a DC power supply information storage unit 47 and a DC power supply setting value information output unit 76. Furthermore, the DC power supply information storage unit 47 stores DC power supply setting value information ST5.

[0311] The DC power supply setting value information output unit 76 outputs a DC power supply setting value corresponding to the elapsed time or a command signal corresponding to the DC power supply setting value, based on the common slave device synchronization signal SS6 and DC power supply setting value information ST5 indicating the relationship between the elapsed time and the DC power supply setting value.

[0312] Next, a detailed description will be given of how the first high frequency power supply generates a synchronization signal and synchronizes with the slave device using the synchronization signal.

[0313] For example, in the high-frequency power supply system 1j shown in FIG. 14, the slave device may be at least one of the second high-frequency power supply 20, the first matching box 30, the second matching box 40, the DC power supply 60, etc., but here, the second high-frequency power supply 20 will be described as the slave device.

[0314] FIG. 15 is an explanatory diagram of the synchronization timing between the synchronization signal SS6 generated by the first high frequency power supply 10j and the slave device.

[0315] 15(a) shows an example of the amplitude modulation waveform of the first high frequency power supply 10j, FIG. 15(b) shows an example of the common slave device synchronization signal SS6, and FIG. 15(c) shows an example of the amplitude modulation waveform of the second high frequency power supply 20.

[0316] Fig. 15(d) shows an example of first high frequency power supply setting value information ST1 corresponding to Fig. 13(a), and Fig. 15(e) shows an example of second high frequency power supply setting value information ST2 corresponding to Fig. 13(c).

[0317] The first high frequency power supply setting value information ST1 shown in Fig. 15(d) and the second high frequency power supply setting value information ST2 shown in Fig. 15(e) both have a setting value of the target power value set as a setting item, which allows the first high frequency power supply 10j and the second high frequency power supply 20 to perform amplitude modulation.

[0318] 15(d) and 15(e), the time at which the first high frequency power supply setting value should be changed and the time at which the second high frequency power supply setting value should be changed are the same in the example of Fig. 15. Therefore, as shown by the dotted line in Fig. 15(d), the first high frequency power supply setting value information ST1 can be used in place of the second high frequency power supply time information ST2 described in Fig. 13(e).

[0319] Therefore, the common slave device synchronization signal output unit 89 of the first high frequency power supply outputs a common slave device synchronization signal SS6 based on the setting value information ST1 for the first high frequency power supply, in accordance with the time at which the setting value for the first high frequency power supply should be changed.

[0320] This common slave device synchronization signal SS6 is, for example, a pulse signal that changes from high to low, and the synchronization timing occurs when the signal changes from low to high. That is, Figure 15 shows an example in which the synchronization timing occurs at the rising edge of the common slave device synchronization signal SS6.

[0321] Furthermore, the second high frequency power supply setting value information output unit 72 of the second high frequency power supply 20 outputs a second high frequency power supply setting value corresponding to the elapsed time or a command signal corresponding to the high frequency power supply setting value, based on the common slave device synchronization signal SS6 and the second high frequency power supply setting value information ST2 indicating the relationship between the elapsed time and the second high frequency power supply setting value.

[0322] Therefore, when common slave device synchronization signal SS6 is input (more precisely, at the above-mentioned synchronization timing), second high frequency power supply set value information output unit 72 outputs information on the target power value corresponding to the elapsed time to second high frequency voltage output unit 22. This allows second high frequency power supply 20 to perform amplitude modulation based on second high frequency power supply set value information ST2.

[0323] In this case, since the common slave device synchronization signal SS6 is input to the second high frequency power supply 20 each time the second high frequency power supply setting value corresponding to the elapsed time is changed, synchronization is achieved more frequently than when synchronization is achieved using the cycle start signal PS. Therefore, even if a frequency error occurs between the frequency of the reference clock built into the first high frequency power supply 10j and the frequency of the reference clock built into the second high frequency power supply 20, there is almost no synchronization error between the first high frequency power supply 10j and the second high frequency power supply 20. Similarly, there is almost no synchronization error between the first high frequency power supply 10j and the other slave devices.

[0324] In the above, the second high-frequency power supply 20 has been described as a slave device, but the same effect can be obtained with other slave devices (e.g., the first matching box 30, the second matching box 40, the DC power supply 60, etc.).

[0325] 15, only the second high frequency power supply 20 is described as a slave device, but multiple slave devices (e.g., the first matching box 30, the second matching box 40, the DC power supply 60, etc.) can be used. For example, the second high frequency power supply 20 and the first matching box 30 can be slave devices. Even in this case, only one type of common slave device synchronization signal SS6 is output as a synchronization signal.

[0326] However, when the common slave device synchronization signal SS6 is input, each slave device outputs a setting value corresponding to the elapsed time or a command signal corresponding to that setting value based on the setting value information for that device, so that the same effect as in the case of Figure 13 can be obtained.

[0327] (Third Modification of the Embodiment) Next, another configuration of the high frequency power supply system will be described as a third modification of the embodiment.

[0328] FIG. 16 is a diagram showing the configuration of a high-frequency power supply system 1k according to a third modification of the embodiment.

[0329] The following description will focus on the differences from the second modified example of the embodiment.

[0330] The above-mentioned cycle start signal PS (see FIG. 1) is not essential, and the cycle start signal PS may be used when necessary, for example, as in the example of FIG. 24 described later.

[0331] <Details of First High Frequency Power Supply 10k> The first high frequency power supply 10k has a first high frequency power supply communication unit 11, a first high frequency voltage output unit 12, a first high frequency power supply sensor 13, a first power information calculation unit 14, a first comparison unit 15, a first control target switching unit 16, a first power control unit 17, and a first high frequency power supply reference clock generation unit 18. The configuration including the first high frequency power supply sensor 13 and the first power information calculation unit 14 functions as a first power detection unit 10a. These are the same as those in FIG. 1 , and therefore description thereof will be omitted.

[0332] The first high frequency power supply 10k also has a first high frequency power supply information storage unit 19k, a first high frequency power supply setting value information output unit 71, and a slave device synchronization signal output unit 77j. The slave device synchronization signal output unit 77j includes a common slave synchronization signal output unit 89. The first high frequency power supply information storage unit 19k also stores first high frequency power supply setting value information ST1 and common slave time information TI6.

[0333] The first high frequency power supply setting value information ST1 is information indicating the relationship between the elapsed time from the start point of one cycle of amplitude modulation and the first high frequency power supply setting value.

[0334] The first high frequency power supply setting value information output unit 71 outputs a first high frequency power supply setting value corresponding to the elapsed time or a command signal corresponding to the first high frequency power supply setting value, based on the first high frequency power supply setting value information ST1.

[0335] The common slave time information TI6 is information indicating the relationship between the elapsed time and the time at which the setting value for each slave device should be changed.

[0336] The common slave synchronization signal output unit 89 outputs a common slave synchronization signal SS6 in accordance with the time when the set value for each slave device should be changed, based on the common slave time information TI6.

[0337] The common slave device time information TI6 is generated based on the time when the set value of the second high frequency power supply set value information ST2 should be changed, the time when the set value of the first matching device set value information ST3 should be changed, the time when the set value of the second matching device set value information ST4 should be changed, and the time when the set value of the DC power supply set value information ST5 should be changed. In other words, the common slave device time information TI6 is information that indicates the relationship between the elapsed time and the time when the slave device set values ​​used in the slave devices should be changed.

[0338] The common slave device synchronization signal output unit 89 outputs a common slave device synchronization signal SS6 based on the common slave device time information TI6, in accordance with the time at which either the second high frequency power supply setting value or the first matching device setting value is changed.

[0339] In this example, the second high frequency power supply 20, the first matching box 30, the second matching box 40, and the DC power supply 60 are targeted, but the targets may be limited. For example, the targets may be the second high frequency power supply 20 and the first matching box 30.

[0340] When the second high frequency power supply 20 and the first matching device 30 are targeted, the common slave device synchronization signal output unit 89 outputs a common slave device synchronization signal SS6 including identification information of the slave device (second high frequency power supply 20, first matching device 30) whose setting value is to be changed, in accordance with the time when the setting value for the second high frequency power supply should be changed or the time when the setting value for the first matching device should be changed.

[0341] <Details of second high frequency power supply 20> The second high frequency power supply 20 has a second high frequency power supply communication unit 21, a second high frequency voltage output unit 72, a second high frequency power supply sensor 23, a second power information calculation unit 24, a second comparison unit 25, a second control target switching unit 26, a second power control unit 27, and a second high frequency power supply reference clock generation unit 28. The configuration including the second high frequency power supply sensor 23 and the second power information calculation unit 24 functions as a second power detection unit 20a. These are the same as those in FIG. 1, and therefore description thereof will be omitted.

[0342] Second high frequency power supply 20 also has second high frequency power supply information storage unit 29 and second high frequency power supply setting value information output unit 72. Second high frequency power supply information storage unit 29 also stores the above-mentioned second high frequency power supply setting value information ST2.

[0343] The second high frequency power supply setting value information ST2 is information indicating the relationship between the elapsed time from the start point of one cycle of amplitude modulation and the second high frequency power supply setting value.

[0344] The second high frequency power supply setting value information output unit 72 outputs a second high frequency power supply setting value corresponding to the elapsed time or a command signal corresponding to the high frequency power supply setting value, based on the common slave device synchronization signal SS6 and second high frequency power supply setting value information ST2 indicating the relationship between the elapsed time and the second high frequency power supply setting value.

[0345] 1, the superposition matching device 50 includes a first matching device 30, a second matching device 40, and a superposition output unit 51. The first matching device 30 performs a first matching operation, and the second matching device 40 performs a second matching operation.

[0346] <First matching device 30> The first matching device 30 has a first matching device communication unit 31, a first matching device sensor 32, a first matching device matching circuit 33, a first matching device calculation unit 34, a first matching device control unit 35, and a first matching device reference clock generation unit 36. These are the same as those in FIG. 1, so their description will be omitted.

[0347] The first matching device 30 also includes a first matching device information storage unit 37 and a first matching device setting value information output unit 73. The first matching device information storage unit 37 stores first matching device setting value information ST3.

[0348] The first matching device setting value information output unit 73 outputs a first matching device setting value corresponding to the elapsed time or a command signal corresponding to the first matching device setting value, based on the common slave device synchronization signal SS6 and first matching device setting value information ST3 indicating the relationship between the elapsed time and the first matching device setting value.

[0349] <Second matching device 40> The second matching device 40 has a second matching device communication unit 41, a second matching device sensor 42, a second matching device matching circuit 43, a second matching device calculation unit 44, a second matching device control unit 45, and a second matching device reference clock generation unit 46. These are the same as those in FIG. 1, so their description will be omitted.

[0350] The second matching device 40 also has a second matching device information storage unit 47 and a second matching device setting value information output unit 74. The second matching device information storage unit 47 stores second matching device setting value information ST4.

[0351] The second matching device setting value information output unit 74 outputs a second matching device setting value corresponding to the elapsed time or a command signal corresponding to the second matching device setting value, based on the common slave device synchronization signal SS6 and second matching device setting value information ST4 indicating the relationship between the elapsed time and the second matching device setting value.

[0352] <Details of DC power supply 60> The DC power supply 60 has a DC power supply setting value information output unit 76, a DC power supply communication unit 61, a DC-DC converter 62, a pulse voltage output unit 63, a DC power supply control unit 64, and a DC power supply reference clock generation unit 65. These are the same as those in FIG. 1, so their description will be omitted.

[0353] Furthermore, the DC power supply 60 has a DC power supply information storage unit 66 and a DC power supply setting value information output unit 76. Furthermore, the DC power supply information storage unit 66 stores DC power supply setting value information ST5.

[0354] The DC power supply setting value information output unit 76 outputs a DC power supply setting value corresponding to the elapsed time or a command signal corresponding to the DC power supply setting value, based on the common slave device synchronization signal SS6 and DC power supply setting value information ST5 indicating the relationship between the elapsed time and the DC power supply setting value.

[0355] Next, a detailed description will be given of how the first high frequency power supply generates a synchronization signal and synchronizes with the slave device using the synchronization signal.

[0356] For example, in the high-frequency power supply system 1k shown in FIG. 16, the slave device may be at least one of the second high-frequency power supply 20, the first matching box 30, the second matching box 40, the DC power supply 60, etc., but here, the second high-frequency power supply 20 will be described as the first slave device and the first matching box 30 as the second slave device.

[0357] FIG. 17 is an explanatory diagram of the synchronization timing between the synchronization signal SS6 generated in the first high frequency power supply 10 and the slave device.

[0358] FIG. 17A shows an example of an amplitude modulation waveform of the first high frequency power supply 10k.

[0359] FIG. 17(b) shows an example of the common slave device synchronization signal SS6.

[0360] FIG. 17C shows an example of an amplitude modulation waveform of the second high frequency power supply 20.

[0361] FIG. 17D shows an example of a period during which the load information IF of the first matching device 30 is acquired.

[0362] FIG. 17(e) shows an example of first high frequency power supply setting value information ST1 corresponding to FIG. 17(a).

[0363] FIG. 17(f) shows an example of common slave device time information TI6 corresponding to FIG. 17(b).

[0364] FIG. 17G shows an example of second high frequency power supply setting value information ST2 corresponding to FIG. 17C.

[0365] FIG. 17(h) shows an example of the first matching device setting value information ST3 corresponding to FIG. 17(d).

[0366] FIG. 17(i) shows an example of converted second high frequency power supply set value information ST2 corresponding to FIG. 17(c).

[0367] FIG. 17(j) shows an example of the converted first matching device setting value information ST3 corresponding to FIG. 17(d).

[0368] In both the first high frequency power supply setting value information ST1 shown in Fig. 17(e) and the second high frequency power supply setting value information ST2 shown in Fig. 17(g), a setting value for the target power value is set as a setting item, thereby enabling the first high frequency power supply 10k and the second high frequency power supply 20 to perform amplitude modulation.

[0369] Furthermore, the load information IF can be acquired during a set period using the first matching device setting value information ST3 shown in FIG. 17(h).

[0370] As shown by the dotted line encircling the common slave device time information TI6 in FIG. 17( f), the common slave device time information TI6 includes time information of both the second high frequency power supply setting value information ST2 and the first matching device setting value information ST3, and therefore may be generated based on the second high frequency power supply setting value information ST2 in FIG. 17( g) and the first matching device setting value information ST3 in FIG. 17( h).

[0371] In this example, the second high frequency power supply setting value information ST2 and the first matching device setting value information ST3 have different time intervals. Specifically, the second high frequency power supply setting value information ST2 is made up of 10 periods (No. 1 to No. 10), while the first matching device setting value information ST3 is made up of 4 periods (No. 1 to No. 4). Therefore, the common slave device time information TI6 is as shown in Figure 17(f), and is made up of a total of 11 periods (No. 1 to No. 11).

[0372] Furthermore, common slave device synchronization signal SS6 is generated based on common slave device time information TI6. Therefore, common slave device synchronization signal SS6 is output to second high frequency power supply set value information output unit 72 and first matching device set value information output unit 73 in accordance with the time at which either the set value of second high frequency power supply set value information ST2 or the set value of first matching device set value information ST3 is changed.

[0373] However, since the common slave device synchronization signal SS6 is common to all slave devices, the second high frequency power supply setting value information ST2 and the first matching device setting value information ST3 must be converted to a configuration corresponding to the common slave device time information TI6.

[0374] Therefore, the second high frequency power supply setting value information ST2 shown in Fig. 17(g) is converted into the second high frequency power supply setting value information ST2 shown in Fig. 17(i). The first matching device setting value information ST3 shown in Fig. 17(h) is converted into the first matching device setting value information ST3 shown in Fig. 17(j).

[0375] In this way, second high frequency power supply setting value information output unit 72 can output the setting value set in second high frequency power supply setting value information ST2 or a command signal corresponding to the setting value while synchronizing with first high frequency power supply 10 based on common slave device synchronization signal SS6. The same applies to first matching box 30.

[0376] Therefore, second high frequency power supply 20 can be controlled in accordance with second high frequency power supply setting value information ST2. For example, if the second high frequency power supply setting value is a target power value of second high frequency power supply 20, output control can be performed so that the output high frequency power becomes the target power value.

[0377] Furthermore, the first matching device 30 can be controlled in accordance with the first matching device setting value information ST3. For example, if the first matching device setting value is the period for acquiring the load information IF of the first matching device 30, the load information IF can be acquired during the set period.

[0378] Because the common slave device synchronization signal SS6 is input to the second high frequency power supply 20 each time the second high frequency power supply setting value is changed in accordance with the elapsed time, synchronization is achieved more frequently than when synchronization is achieved using the cycle start signal PS. Therefore, even if a frequency error occurs between the frequency of the reference clock built into the first high frequency power supply 10k and the frequency of the reference clock built into the second high frequency power supply 20, there is almost no synchronization error between the first high frequency power supply 10k and the second high frequency power supply 20. Similarly, there is almost no synchronization error between the first high frequency power supply 10k and the first matching box 30.

[0379] In this example, the second high-frequency power supply 20 is described as the first slave device, and the first matching box 30 is described as the second slave device, but the configuration may also include other slave devices (for example, the second matching box 40, the DC power supply 60, etc.).

[0380] In this example, since the synchronization signal is common, if the synchronization signal SS6 for the common slave device is output as a voltage signal such as a pulse voltage, the synchronization signals of the multiple slave devices can be consolidated into one. However, to simplify the drawing, the number of output ports is not shown.

[0381] (Fourth Modification of the Embodiment) Next, another configuration of the high frequency power supply system will be described as a fourth modification of the embodiment.

[0382] FIG. 18 is a diagram showing another configuration of the high-frequency power supply system 1n according to the fourth modified example of the embodiment.

[0383] The following description will focus on the differences from the first modified example of the embodiment.

[0384] The above-mentioned cycle start signal PS (see FIG. 1) is not essential, and the cycle start signal PS may be used when necessary, for example, as in the example of FIG. 24 described later.

[0385] <Details of First High Frequency Power Supply 10n> The first high frequency power supply 10n has a first high frequency power supply communication unit 11, a first high frequency voltage output unit 12, a first high frequency power supply sensor 13, a first power information calculation unit 14, a first comparison unit 15, a first control target switching unit 16, a first power control unit 17, and a first high frequency power supply reference clock generation unit 18. The configuration including the first high frequency power supply sensor 13 and the first power information calculation unit 14 functions as a first power detection unit 10a. These are the same as those in FIG. 1, and therefore description thereof will be omitted.

[0386] The first high frequency power supply 10n also has a first high frequency power supply information storage unit 19n, a first high frequency power supply setting value information output unit 71, and a slave device synchronization signal output unit 77i. The slave device synchronization signal output unit 77i includes a second high frequency power supply synchronization signal output unit 82, a first matching device synchronization signal output unit 83, a second matching device synchronization signal output unit 84, and a DC power supply synchronization signal output unit 86. The first high frequency power supply information storage unit 19n also stores first high frequency power supply setting value information ST1, second high frequency power supply setting value information ST2, first matching device setting value information ST3, second matching device setting value information ST4, and DC power supply setting value information ST5.

[0387] The first high frequency power supply setting value information ST1 is information indicating the relationship between the elapsed time from the start point of one cycle of amplitude modulation and the first high frequency power supply setting value.

[0388] The first high frequency power supply setting value information output unit 71 outputs a first high frequency power supply setting value corresponding to the elapsed time or a command signal corresponding to the first high frequency power supply setting value, based on the first high frequency power supply setting value information ST1.

[0389] The second high frequency power supply setting value information ST2 includes information indicating the relationship between the elapsed time and the time at which the second high frequency power supply setting value used in the second high frequency power supply 20 should be changed, as well as information indicating the relationship between the elapsed time from the start point of one cycle of amplitude modulation and the second high frequency power supply setting value.

[0390] The setting value information ST3 for the first matcher includes information indicating the relationship between the elapsed time and the time at which the setting value for the first matcher used in the first matcher 30 should be changed, as well as information indicating the relationship between the elapsed time from the start point of one period of amplitude modulation and the setting value for the first matcher.

[0391] The setting value information ST4 for the second matcher includes information indicating the relationship between the elapsed time and the time at which the setting value for the second matcher used in the second matcher 40 should be changed, as well as information indicating the relationship between the elapsed time from the start point of one period of amplitude modulation and the setting value for the second matcher.

[0392] The DC power supply setting value information ST5 includes information indicating the relationship between the elapsed time and the time at which the DC power supply setting value used in the DC power supply 60 should be changed, as well as information indicating the relationship between the elapsed time from the start point of one cycle of amplitude modulation and the DC power supply setting value.

[0393] Based on the second high frequency power supply setting value information ST2, the second high frequency power supply synchronization signal output unit 82 outputs a second high frequency power supply synchronization signal SS2 including information equivalent to the second high frequency power supply setting value corresponding to the elapsed time, in accordance with the time at which the second high frequency power supply setting value should be changed.

[0394] The first matching device synchronization signal output unit 83 outputs a first matching device synchronization signal SS3 including information corresponding to the first matching device setting value corresponding to the elapsed time, in accordance with the time at which the first matching device setting value should be changed, based on the first matching device setting value information ST3.

[0395] The second matching device synchronization signal output unit 84 outputs a second matching device synchronization signal SS4 including information corresponding to the second matching device setting value corresponding to the elapsed time, in accordance with the time at which the second matching device setting value should be changed, based on the second matching device setting value information ST4.

[0396] The DC power supply synchronization signal output unit 86 outputs a DC power supply synchronization signal SS5 including information equivalent to the DC power supply setting value corresponding to the elapsed time, based on the DC power supply setting value information ST5, in accordance with the time at which the DC power supply setting value should be changed.

[0397] Each of these synchronization signals is an example of a slave device synchronization signal.

[0398] <Details of second high frequency power supply 20n> The second high frequency power supply 20n has a second high frequency power supply communication unit 21, a second high frequency voltage output unit 22, a second high frequency power supply sensor 23, a second power information calculation unit 24, a second comparison unit 25, a second control target switching unit 26, a second power control unit 27, and a second high frequency power supply reference clock generation unit 28. The configuration including the second high frequency power supply sensor 23 and the second power information calculation unit 24 functions as a second power detection unit 20a. These are the same as those in FIG. 1, so their description will be omitted.

[0399] The second high frequency power supply 20n also has a second high frequency power supply setting value information output unit 72n.

[0400] The second high frequency power supply 20 does not have a second high frequency power supply information storage unit 29 (see FIG. 12 ) but has a second high frequency power supply setting value information output unit 72n. The second high frequency power supply setting value information output unit 72n can receive a second high frequency power supply synchronization signal SS2 from the first high frequency power supply 10n via a second high frequency power supply communication unit 21. The second high frequency power supply setting value information output unit 72n acquires setting value information corresponding to a second high frequency power supply setting value corresponding to elapsed time based on the second high frequency power supply synchronization signal SS2. The second high frequency power supply setting value information output unit 72n may have conversion information CV2 between setting value information and second high frequency power supply setting values. The second high frequency power supply setting value information output unit 72n may convert the setting value information included in the second high frequency power supply synchronization signal SS2 into a second high frequency power supply setting value using the conversion information CV2. The second high frequency power supply setting value information output unit 72n outputs a command signal corresponding to the acquired setting value information. This allows the second high frequency power supply 20n to be controlled in accordance with the second high frequency power supply setting value included in the second high frequency power supply synchronization signal SS2.

[0401] 1, the superposition matching device 50n has a first matching device 30n, a second matching device 40n, and a superposition output unit 51. The first matching device 30n performs a first matching operation, and the second matching device 40n performs a second matching operation.

[0402] <First matching device 30n> The first matching device 30n has a first matching device communication unit 31, a first matching device sensor 32, a first matching device matching circuit 33, a first matching device calculation unit 34, a first matching device control unit 35, and a first matching device reference clock generation unit 36. These are the same as those in FIG. 1, so their description will be omitted.

[0403] The first matching device 30n does not have the first matching device information storage unit 37 (see FIG. 12 ), but has a first matching device set value information output unit 73n. The first matching device set value information output unit 73n can receive a first matching device synchronization signal SS3 from the first high frequency power source 10n via the first matching device communication unit 31. The first matching device set value information output unit 73n acquires set value information corresponding to a first matching device set value corresponding to elapsed time based on the first matching device synchronization signal SS3. The first matching device set value information output unit 73n may have conversion information CV3 between set value information and first matching device set value. The first matching device set value information output unit 73n may convert the set value information included in the first matching device synchronization signal SS3 into a first matching device set value using the conversion information CV3. The first matching device set value information output unit 73n outputs a command signal corresponding to the acquired set value information. This allows the first matching device 30n to perform control in accordance with the first matching device setting value included in the first matching device synchronization signal SS3.

[0404] <Second matching device 40n> The second matching device 40n has a second matching device communication unit 41, a second matching device sensor 43, a second matching device matching circuit 43, a second matching device calculation unit 44, a second matching device control unit 45, and a second matching device reference clock generation unit 46. These are the same as those in FIG. 1, so their description will be omitted.

[0405] The second matching device 40n does not have the second matching device information storage unit 47 (see FIG. 12 ), but has a second matching device set value information output unit 74n. The second matching device set value information output unit 74n can receive a second matching device synchronization signal SS4 from the first high frequency power source 10n via the second matching device communication unit 41. The second matching device set value information output unit 74n acquires set value information corresponding to a second matching device set value corresponding to elapsed time based on the second matching device synchronization signal SS4. The second matching device set value information output unit 74n may have conversion information CV4 between set value information and second matching device set values. The first matching device set value information output unit 74n may convert the set value information included in the second matching device synchronization signal SS4 into a second matching device set value using the conversion information CV4. The first matching device set value information output unit 74n outputs a command signal corresponding to the acquired set value information. This allows the second matching device 40n to perform control in accordance with the second matching device setting value included in the second matching device synchronization signal SS4.

[0406] <Details of DC power supply 60n> The DC power supply 60n has a DC power supply setting value information output unit 76, a DC power supply communication unit 61, a DC-DC converter 62, a pulse voltage output unit 63, a DC power supply control unit 64, and a DC power supply reference clock generation unit 65. These are the same as those in FIG. 1, so description thereof will be omitted.

[0407] Furthermore, the DC power supply 60n does not have the DC power supply information storage unit 67 (see FIG. 12 ), but has a DC power supply setting value information output unit 76n. The DC power supply setting value information output unit 76n can receive a DC power supply synchronization signal SS5 from the first high frequency power supply 10n via the DC power supply communication unit 61. The DC power supply setting value information output unit 76n acquires setting value information corresponding to a DC power supply setting value corresponding to an elapsed time, based on the DC power supply synchronization signal SS5. The DC power supply setting value information output unit 76n may have conversion information CV5 between setting value information and DC power supply setting values. The DC power supply setting value information output unit 76n may convert the setting value information into a DC power supply setting value using the conversion information CV5. The DC power supply setting value information output unit 76n outputs a command signal according to the acquired setting value information. This allows the DC power supply 60n to be controlled in accordance with the DC power supply setting value included in the DC power supply synchronization signal SS5.

[0408] Next, a detailed description will be given of how the first high frequency power supply generates a synchronization signal and synchronizes with the slave device using the synchronization signal.

[0409] For example, in the high-frequency power supply system 1n shown in FIG. 18, the slave device may be at least one of, for example, the second high-frequency power supply 20n, the first matching box 30n, the second matching box 40n, the DC power supply 60n, etc., but here, the second high-frequency power supply 20n will be described as the slave device.

[0410] FIG. 19 is an explanatory diagram of the synchronization timing between the synchronization signals SS2 to SS5 generated in the first high frequency power supply 10n and the slave device.

[0411] FIG. 19A shows an example of an amplitude modulation waveform of the first high frequency power supply 10n.

[0412] FIG. 19B shows an example of the second high frequency power supply synchronization signal SS2.

[0413] FIG. 19C shows an example of an amplitude modulation waveform of the second high frequency power supply 20n.

[0414] FIG. 19D shows an example of first high frequency power supply setting value information ST1 corresponding to FIG. 19A.

[0415] FIG. 19(e) shows an example of second high frequency power supply setting value information ST2 corresponding to FIG. 19(c).

[0416] FIG. 19(f) shows an example of the conversion information CV2, which is a correspondence table between pulse widths and target power values.

[0417] In both the first high frequency power supply setting value information ST1 shown in Fig. 19(d) and the second high frequency power supply setting value information ST2 shown in Fig. 19(e), a setting value for the target power value is set as a setting item, thereby enabling the first high frequency power supply 10n and the second high frequency power supply 20n to perform amplitude modulation.

[0418] However, second high frequency power supply synchronization signal output unit 82 is provided in first high frequency power supply 10 n, and therefore outputs second high frequency power supply synchronization signal SS2 including information corresponding to the second high frequency power supply setting value corresponding to the elapsed time, in accordance with the time at which the second high frequency power supply setting value corresponding to the elapsed time should be changed, based on second high frequency power supply setting value information ST2.

[0419] That is, the second high frequency power supply synchronization signal SS2 is characterized in that it contains information corresponding to the second high frequency power supply set value corresponding to the elapsed time. The second high frequency power supply synchronization signal SS2 contains set value information.

[0420] In this example, the target power value is set as the setting value for the second high frequency power supply, so if the synchronization signal SS2 for the second high frequency power supply is a voltage pulse signal, the target power value can be identified by changing the pulse width or voltage level according to the target power value.

[0421] Therefore, as shown in FIG. 19( e ), information on the pulse width corresponding to the target power value may be added to the second high frequency power supply setting value information ST2.

[0422] When generating the second high frequency power supply synchronization signal SS2, the second high frequency power supply synchronization signal output unit 82 reads pulse width information corresponding to the target power value in the second high frequency power supply setting value information ST2, and changes the pulse width of the second high frequency power supply synchronization signal SS2 based on that information. Figure 19(b) shows an example in which the first three pulse widths are modulated to 500 μs, 300 μs, and 200 μs in that order.

[0423] On the other hand, when the second high frequency power supply setting value information output unit 72n receives the second high frequency power supply synchronization signal SS2, it outputs the second high frequency power supply setting value included in the second high frequency power supply synchronization signal SS2 or a command signal corresponding to the second high frequency power supply setting value. In this case, the second high frequency power supply setting value information output unit 72n can convert the setting value information included in the second high frequency power supply synchronization signal SS2 into a setting value using conversion information CV2. For example, the target power value may be recognized based on a correspondence table between pulse widths and target power values, such as that shown in FIG. 19(f). In FIGS. 19(b) and 19(f), the target power value is controlled to 500 W, 300 W, or 200 W at the edge timing of each pulse, depending on the width of the first three pulses.

[0424] Since the second high frequency power supply synchronization signal SS2 is input to the second high frequency power supply 20n each time the second high frequency power supply setting value corresponding to the elapsed time is changed, synchronization is achieved more frequently than when synchronization is achieved using the cycle start signal PS. Therefore, even if a frequency error occurs between the frequency of the reference clock built into the first high frequency power supply 10n and the frequency of the reference clock built into the second high frequency power supply 20n, synchronization error hardly occurs between the first high frequency power supply 10n and the second high frequency power supply 20n. Similarly, synchronization error hardly occurs between the first high frequency power supply 10n and other slave devices.

[0425] Even if the second high frequency power supply 20n erroneously recognizes the external noise NZ as the synchronization signal SS2 for the second high frequency power supply, the normal setting value for the second high frequency power supply can be restored the next time the setting value for the second high frequency power supply is changed, so the influence of the external noise NZ can be minimized compared to a synchronization method using only the cycle start signal PS.

[0426] In the above, the second high frequency power supply 20n has been described as a slave device, but the same effect can be obtained with other slave devices (e.g., the first matching device 30n, the second matching device 40n, the DC power supply 60n, etc.).

[0427] Furthermore, although the target power value is set as the second high frequency power supply setting value information, other setting items can also be set.

[0428] Next, a detailed description will be given of how the first high frequency power supply generates a synchronization signal and synchronizes with the slave device using the synchronization signal.

[0429] For example, in the high-frequency power supply system 1n shown in FIG. 18, the slave device may be at least one of, for example, the second high-frequency power supply 20n, the first matching box 30n, the second matching box 40n, the DC power supply 60n, etc., but here, the second high-frequency power supply 20n will be described as the slave device.

[0430] FIG. 20 is an explanatory diagram of the synchronization timing between the synchronization signals SS2 to SS5 generated in the first high frequency power supply 10n and the slave device.

[0431] FIG. 20A shows an example of an amplitude modulation waveform of the first high frequency power supply 10n.

[0432] FIG. 20B shows an example of the second high frequency power supply synchronization signal SS2.

[0433] FIG. 20C shows an example of an amplitude modulation waveform of the second high frequency power supply 20n.

[0434] FIG. 20D shows an example of first high frequency power supply setting value information ST1 corresponding to FIG. 20A.

[0435] FIG. 20(e) shows an example of second high frequency power supply setting value information ST2 corresponding to FIG. 20(c).

[0436] This example is characterized in that, like the example in FIG. 19 , the synchronization signal SS2 for the second high frequency power supply contains information (setting value information) equivalent to the setting value for the second high frequency power supply corresponding to the elapsed time, but differs in that the setting value information is contained in the synchronization signal SS2 for the second high frequency power supply as a signal for serial communication (for example, a bit pattern).

[0437] As described above, the second high frequency power supply synchronization signal output unit 82 of the first high frequency power supply 10 n outputs a second high frequency power supply synchronization signal SS2 including information corresponding to the second high frequency power supply setting value corresponding to the elapsed time, in accordance with the time at which the second high frequency power supply setting value corresponding to the elapsed time should be changed, based on the second high frequency power supply setting value information ST2 (information on the target power value in this example).

[0438] In this case, since serial communication is used, the pulse width or the like of the second high frequency power supply synchronization signal SS2 is not changed (see FIG. 19(b)), but information equivalent to the second high frequency power supply setting value corresponding to the elapsed time (information indicating the target power value in this example) is included in the second high frequency power supply synchronization signal SS2 in a format suitable for serial communication, as shown in FIG. 20(b). The filled-in rectangular portions in FIG. 19(b) actually contain a plurality of waveforms indicating predetermined bit patterns. FIG. 19(b) illustrates an example in which bit pattern BP1, bit pattern BP2, and bit pattern BP3 are included in the first three rectangles in this order.

[0439] On the other hand, when the second high frequency power supply setting value information output unit 72n receives the second high frequency power supply synchronization signal SS2, it outputs the second high frequency power supply setting value included in the second high frequency power supply synchronization signal SS2 or a command signal corresponding to the second high frequency power supply setting value. In this case, the second high frequency power supply setting value information output unit 72n decodes the bit pattern BP to identify the setting value information included in the second high frequency power supply synchronization signal SS2. For example, the target power value can be recognized by decoding the bit pattern according to a predetermined decoding rule. Figure 20(b) illustrates an example in which the target power value is controlled to 500 W, 300 W, or 200 W at the edge timing of each pulse according to the three leading bit patterns BP1, BP2, and BP3.

[0440] Since the second high frequency power supply synchronization signal SS2 is input to the second high frequency power supply 20n each time the second high frequency power supply setting value corresponding to the elapsed time is changed, synchronization is achieved more frequently than when synchronization is achieved using the cycle start signal PS. Therefore, even if a frequency error occurs between the frequency of the reference clock built into the first high frequency power supply 10n and the frequency of the reference clock built into the second high frequency power supply 20n, synchronization error hardly occurs between the first high frequency power supply 10n and the second high frequency power supply 20n. Similarly, synchronization error hardly occurs between the first high frequency power supply 10n and other slave devices.

[0441] Furthermore, by using serial communication, more information can be sent in the bit pattern BP than in the example of Fig. 19. For example, information such as parity and checksum can be added to the bit pattern BP, making it possible to check and correct errors.

[0442] In the above, the second high frequency power supply 20n has been described as a slave device, but the same effect can be obtained with other slave devices (e.g., the first matching device 30n, the second matching device 40n, the DC power supply 60n, etc.).

[0443] Furthermore, although the second high frequency power supply setting value information ST2 is exemplified as information for setting a target power value, other setting items may also be set.

[0444] Fifth Modification of the Embodiment Next, another configuration of the high frequency power supply system will be described as a fifth modification of the embodiment.

[0445] FIG. 21 is a diagram showing the configuration of a high-frequency power supply system 1p according to a fifth modified example of the embodiment.

[0446] The following description will focus on the differences from the third modified example of the embodiment.

[0447] The above-mentioned cycle start signal PS (see FIG. 1) is not essential, and the cycle start signal PS may be used when necessary, for example, as in the example of FIG. 24 described later.

[0448] <Details of First High Frequency Power Supply 10p> The first high frequency power supply 10p has a first high frequency power supply communication unit 11, a first high frequency voltage output unit 12, a first high frequency power supply sensor 13, a first power information calculation unit 14, a first comparison unit 15, a first control target switching unit 16, a first power control unit 17, and a first high frequency power supply reference clock generation unit 18. The configuration including the first high frequency power supply sensor 13 and the first power information calculation unit 14 functions as a first power detection unit 10a. These are the same as those in FIG. 1 , and therefore description thereof will be omitted.

[0449] The first high frequency power supply 10p also has a first high frequency power supply information storage unit 19p, a first high frequency power supply setting value information output unit 71, and a slave device synchronization signal output unit 77j. The slave device synchronization signal output unit 77j includes a common slave synchronization signal output unit 89. The first high frequency power supply information storage unit 19p also stores first high frequency power supply setting value information ST1 and common slave setting value information ST6.

[0450] The first high frequency power supply setting value information ST1 is information indicating the relationship between the elapsed time from the start point of one cycle of amplitude modulation and the first high frequency power supply setting value.

[0451] The common slave setting value information ST6 is information indicating the relationship between the elapsed time from the start point of one cycle of amplitude modulation and the setting value for each slave device.

[0452] The first high frequency power supply setting value information output unit 71 outputs a first high frequency power supply setting value corresponding to the elapsed time or a command signal corresponding to the first high frequency power supply setting value, based on the first high frequency power supply setting value information ST1.

[0453] The common slave synchronization signal output unit 89 outputs a common slave synchronization signal SS6 in accordance with the time when the setting values ​​for each slave device should be changed, based on the common slave setting value information ST6.

[0454] The slave device setting value information ST6 is generated based on the second high frequency power supply setting value information ST2, the first matching device setting value information ST3, the second matching device setting value information ST4, and the DC power supply setting value information ST5.

[0455] The second high frequency power supply setting value information ST2 is information indicating the relationship between the elapsed time and the second high frequency power supply setting value.

[0456] The first matching device setting value information ST3 is information indicating the relationship between the elapsed time and the first matching device setting value.

[0457] The second matching device setting value information ST4 is information indicating the relationship between the elapsed time and the second matching device setting value.

[0458] The DC power supply setting value information ST5 is information indicating the relationship between the elapsed time and the DC power supply setting value.

[0459] These pieces of setting value information are examples of setting value information for a slave device.

[0460] The common slave device synchronization signal output unit 89 outputs a common slave device synchronization signal SS6 containing information corresponding to the slave device setting value based on the common slave setting value information ST6, in accordance with the time at which the slave device setting value should be changed.

[0461] In this example, the second high frequency power supply 20p, the first matching box 30p, the second matching box 40p, and the DC power supply 60p are targeted, but the targets may be limited to, for example, the second high frequency power supply 20p and the first matching box 30p.

[0462] When the second high frequency power supply 20p and the first matching device 30p are targeted, the common slave device synchronization signal output unit 89 outputs a common slave device synchronization signal SS6 including slave device identification information, information corresponding to the setting value for the second high frequency power supply, and information corresponding to the setting value for the first matching device, in accordance with the time at which either the setting value for the second high frequency power supply or the setting value for the first matching device is changed.

[0463] <Details of second high frequency power supply 20p> The second high frequency power supply 20p has a second high frequency power supply communication unit 21, a second high frequency voltage output unit 22, a second high frequency power supply sensor 23, a second power information calculation unit 24, a second comparison unit 25, a second control target switching unit 26, a second power control unit 27, and a second high frequency power supply reference clock generation unit 28. The configuration including the second high frequency power supply sensor 23 and the second power information calculation unit 24 functions as the second power detection unit 10b. These are the same as those in FIG. 1, and therefore description thereof will be omitted.

[0464] The second high frequency power supply 20p does not have a second high frequency power supply information storage unit 29 (see FIG. 14 ), but has a second high frequency power supply setting value information output unit 72p. The second high frequency power supply setting value information output unit 72p can receive a common slave synchronization signal SS6 from the first high frequency power supply 10p via the second high frequency power supply communication unit 21. The second high frequency power supply setting value information output unit 72p acquires setting value information corresponding to a second high frequency power supply setting value corresponding to elapsed time, based on the common slave synchronization signal SS6. The second high frequency power supply setting value information output unit 72n may have conversion information CV2 between setting value information and second high frequency power supply setting values. The second high frequency power supply setting value information output unit 72n may convert the setting value information included in the common slave synchronization signal SS6 into a second high frequency power supply setting value using the conversion information CV2. The second high frequency power supply setting value information output unit 72p outputs a command signal corresponding to the acquired setting value information. This allows the second high frequency power supply 20p to be controlled in accordance with the second high frequency power supply setting value included in the common slave synchronization signal SS6.

[0465] 1, the superposition matching device 50p includes a first matching device 30p, a second matching device 40p, and a superposition output unit 51. The first matching device 30p performs a first matching operation, and the second matching device 40p performs a second matching operation.

[0466] <First matching device 30p> The first matching device 30p has a first matching device communication unit 31, a first matching device sensor 32, a first matching device matching circuit 33, a first matching device calculation unit 34, a first matching device control unit 35, and a first matching device reference clock generation unit 36. These are the same as those in FIG. 1, so their description will be omitted.

[0467] The first matching device 30p does not have the first matching device information storage unit 37 (see FIG. 14 ), but has a first matching device set value information output unit 73p. The first matching device set value information output unit 73p can receive the common slave synchronization signal SS6 from the first high frequency power source 10p via the first matching device communication unit 31. The first matching device set value information output unit 73p acquires set value information corresponding to the first matching device set value corresponding to the elapsed time based on the common slave synchronization signal SS6. The first matching device set value information output unit 73p may have conversion information CV3 between set value information and the first matching device set value. The first matching device set value information output unit 73p may convert the set value information included in the common slave synchronization signal SS6 into the first matching device set value using the conversion information CV3. The first matching device set value information output unit 73p outputs a command signal corresponding to the acquired set value information. This allows the first matching device 30p to perform control in accordance with the first matching device setting value included in the common slave synchronization signal SS6.

[0468] <Second matching device 40p> The second matching device 40p has a second matching device communication unit 41, a second matching device sensor 43, a second matching device matching circuit 43, a second matching device calculation unit 44, a second matching device control unit 45, and a second matching device reference clock generation unit 46. These are the same as those in FIG. 1, so their description will be omitted.

[0469] The second matching device 40p does not have the second matching device information storage unit 47 (see FIG. 14 ), but has a second matching device set value information output unit 74p. The second matching device set value information output unit 74p can receive the common slave synchronization signal SS6 from the first high frequency power source 10p via the second matching device communication unit 41. The second matching device set value information output unit 74p acquires set value information corresponding to the second matching device set value corresponding to the elapsed time based on the common slave synchronization signal SS6. The second matching device set value information output unit 74p may have conversion information CV4 between set value information and second matching device set value. The first matching device set value information output unit 74p may convert the set value information included in the common slave synchronization signal SS6 into the second matching device set value using the conversion information CV4. The first matching device set value information output unit 74p outputs a command signal corresponding to the acquired set value information. This allows the second matching device 40p to perform control in accordance with the second matching device setting value included in the common slave synchronization signal SS6.

[0470] <Details of DC power supply 60p> The DC power supply 60p has a DC power supply setting value information output unit 76, a DC power supply communication unit 61, a DC-DC converter 62, a pulse voltage output unit 63, a DC power supply control unit 64, and a DC power supply reference clock generation unit 65. These are the same as those in FIG. 1, so description thereof will be omitted.

[0471] Furthermore, the DC power supply 60p does not have a DC power supply information storage unit 67 (see FIG. 14 ), but has a DC power supply setting value information output unit 76p. The DC power supply setting value information output unit 76p can receive a common slave synchronization signal SS6 from the first high frequency power supply 10p via the DC power supply communication unit 61. The DC power supply setting value information output unit 76p acquires setting value information corresponding to a DC power supply setting value corresponding to an elapsed time, based on the common slave synchronization signal SS6. The DC power supply setting value information output unit 76p may have conversion information CV5 between setting value information and DC power supply setting values. The DC power supply setting value information output unit 76p may convert the setting value information into a DC power supply setting value using the conversion information CV5. The DC power supply setting value information output unit 76p outputs a command signal according to the acquired setting value information. This allows the DC power supply 60p to be controlled in accordance with the DC power supply setting value included in the common slave synchronization signal SS6.

[0472] Next, a detailed description will be given of how the first high frequency power supply generates a synchronization signal and synchronizes with the slave device using the synchronization signal.

[0473] For example, in the high-frequency power supply system 1p shown in FIG. 21, the slave devices are, for example, a second high-frequency power supply 20p, a first matching box 30p, a second matching box 40p, a DC power supply 60p, etc., but here, the second high-frequency power supply 20p will be described as the first slave device and the first matching box 30p as the second slave device.

[0474] FIG. 22 is an explanatory diagram of the synchronization timing between the synchronization signal SS6 generated in the first high frequency power supply 10p and the slave device.

[0475] FIG. 22(a) shows an example of an amplitude modulation waveform of the first high frequency power supply 10p.

[0476] FIG. 22(b) shows an example of the common slave device synchronization signal SS6.

[0477] FIG. 22C shows an example of an amplitude modulation waveform of the second high frequency power supply 20p.

[0478] FIG. 22(d) shows an example of a period for acquiring the load information IF of the first matching device 30p.

[0479] FIG. 22(e) shows an example of first high frequency power supply setting value information ST1 corresponding to FIG. 22(a).

[0480] FIG. 22(f) shows an example of common slave device setting value information ST6 corresponding to FIG. 22(b).

[0481] FIG. 22(g) shows an example of second high frequency power supply setting value information ST2 corresponding to FIG. 22(c).

[0482] FIG. 22(h) shows an example of the first matching device setting value information ST3 corresponding to FIG. 22(d).

[0483] 22(e), a setting value for the target power value is set as a setting item, thereby enabling the first high frequency power supply 10p to perform amplitude modulation.

[0484] The first high frequency power supply setting value information ST1 shown in Fig. 22(e) and the second high frequency power supply setting value information ST2 shown in Fig. 22(g) both have a setting value of the target power value set as a setting item, which allows the first high frequency power supply 10p and the second high frequency power supply 20p to perform amplitude modulation.

[0485] Furthermore, the load information IF can be acquired during a set period using the first matching device setting value information ST3 shown in FIG. 22(h).

[0486] The setting value information ST2 for the second high frequency power supply and the setting value information ST3 for the first matching device, which are enclosed by dotted lines, are replaced by the setting value information ST6 for the common slave device, as indicated by the thick arrows, and are therefore not actually used.

[0487] The common slave device setting value information ST6 in FIG. 22(f) is setting value information that includes information from both the second high frequency power supply setting value information ST2 and the first matching device setting value information ST3, and therefore can be generated based on the second high frequency power supply setting value information ST2 in FIG. 22(g) and the first matching device setting value information ST3 in FIG. 22(h).

[0488] In this example, the second high frequency power supply setting value information ST2 and the first matching device setting value information ST3 have different time intervals. Specifically, the second high frequency power supply setting value information ST2 is made up of 10 periods (No. 1 to No. 10), while the first matching device setting value information ST3 is made up of 4 periods (No. 1 to No. 4). Therefore, the common slave device setting value information ST6 is as shown in Figure 22(f), and is made up of a total of 11 periods (No. 1 to No. 11).

[0489] Furthermore, common slave device synchronization signal SS6 is generated based on common slave device setting value information ST6, and is therefore output to second high frequency power supply setting value information output unit 72p and first matching device setting value information output unit 73p in accordance with the time when either the setting value of second high frequency power supply setting value information ST2 or the setting value of first matching device setting value information ST3 is changed.

[0490] Furthermore, the common slave device setting value information ST6 includes the setting value for the second high frequency power supply and the setting value for the first matching device, which correspond to the elapsed time, so that the common slave device synchronization signal SS6 can include information corresponding to the setting value for the second high frequency power supply and the setting value for the first matching device, which correspond to the elapsed time.

[0491] In this example, the common slave device setting value information ST6 includes a setting item, which is a target power value of the second high frequency power supply 20p, so that the second high frequency power supply 20p can perform amplitude modulation.

[0492] Furthermore, the common slave device setting value information ST6 includes a setting item for the period during which the first matching device 30p acquires the load information IF, which allows the first matching device 30p to acquire the load information IF within a predetermined period.

[0493] However, since the common slave device synchronization signal SS6 is common to each slave device, it is necessary to devise a way for each slave device to recognize information intended for itself.

[0494] For example, a rule may be established that the information is added to the common slave device synchronization signal in the order of "target power value of the second high frequency power supply" → "period for acquiring load information of the first matching device." Specifically, in period No. 1, the information "500 W, 0" is added to the common slave device synchronization signal, and in period No. 2, the information "500 W, 1" is added to the common slave device synchronization signal.

[0495] If each slave device is aware of such rules, each slave device can recognize its own information when it receives a common slave device synchronization signal.

[0496] For example, if the second high frequency power supply 20p receives the information "500 W, 0" during the period No. 1, the first information "500 W" is recognized as information about the target power value of the second high frequency power supply 20p, but the second information "0" is not recognized as information about the second high frequency power supply 20p.

[0497] Similarly, if the first matching box 30p receives the information "500 W, 0" during the period No. 1, the first information "500 W" is not recognized as information from the period during which the first matching box 30p acquired load information, but the second information "0" is recognized as information from the second high-frequency power supply.

[0498] Of course, other methods may be used to recognize the information for each slave device.

[0499] In this way, each slave device can perform processing based on information corresponding to the set value included in the common slave device synchronization signal SS6 while being synchronized with the first high frequency power supply 10p.

[0500] For this reason, it is preferable that the common slave device synchronization signal SS6 is transmitted using serial communication rather than as a voltage pulse signal, but a voltage pulse signal is also possible.

[0501] For example, in the case of the target power value of the second high frequency power supply 20p, a pulse signal with a pulse width of 100 μs may be output at 100 W, and a pulse signal with a pulse width of 500 μs may be output at 500 W.

[0502] In the case of the period for acquiring the load information IF of the first matching device 30p, a pulse signal with a pulse width of 100 μs is used when the value is 0 (not acquired), and a pulse signal with a pulse width of 200 μs is used when the value is 1 (acquired).

[0503] Then, the above-described pulse signals may be combined. That is, after transmitting a pulse signal indicating the target power value of the second high-frequency power supply 20p, a pulse signal indicating the acquisition period of the load information IF of the first matching box 30p may be transmitted.

[0504] This common slave device synchronization signal SS6 is input to the second high frequency power supply 20p each time the second high frequency power supply setting value is changed in accordance with the elapsed time, so synchronization is achieved more frequently than when synchronization is achieved using the cycle start signal PS. Therefore, even if a frequency error occurs between the frequency of the reference clock built into the first high frequency power supply 10p and the frequency of the reference clock built into the second high frequency power supply 20p, there is almost no synchronization error between the first high frequency power supply 10p and the second high frequency power supply 20p. Similarly, there is almost no synchronization error between the first high frequency power supply 10p and the first matching device 30p.

[0505] In this example, the second high-frequency power supply 20p is described as the first slave device, and the first matching device 30p is described as the second slave device, but the configuration may also include other slave devices (for example, the second matching device 40p, the DC power supply 60p, etc.).

[0506] In this example, since the synchronization signal is common, if the synchronization signal SS6 for the common slave device is output as a voltage signal such as a pulse voltage, the synchronization signals of the multiple slave devices can be consolidated into one. However, to simplify the drawing, the number of output ports is not shown.

[0507] (Sixth Modification of the Embodiment) Next, a description will be given of measures against external noise NZ.

[0508] In the following description, the second high frequency power supply synchronizing signal SS2 and the common slave device synchronizing signal SS6 will be referred to simply as the synchronizing signal SS without any distinction.

[0509] FIG. 23 is a diagram for explaining a synchronization error that occurs when external noise NZ is erroneously detected as a synchronization signal SS.

[0510] 23A shows an example of an amplitude modulation waveform of the first high frequency power supply 10. FIG.

[0511] FIG. 23(b) shows an example of the synchronization signal SS.

[0512] FIG. 23C shows an example of an amplitude modulation waveform of the second high frequency power supply 20.

[0513] As shown by the bold line in Fig. 23(b), if external noise NZ, which is not the actual synchronization signal SS, is erroneously detected as the synchronization signal SS, all subsequent change times of the target power value will be shifted, as shown by the bold line in Fig. 23(c). Below, we will explain measures to prevent such synchronization shifts due to external noise NZ.

[0514] As a sixth modification of the embodiment, the high frequency power supply system 1 may have a function that takes into consideration the following <Measure (1)>.

[0515] <Countermeasure (Part 1)> FIG. 24 is a diagram for explaining countermeasure (Part 1) against the external noise NZ.

[0516] 24A shows an example of an amplitude modulation waveform of the first high frequency power supply 10. FIG.

[0517] FIG. 24(b) shows an example of the synchronization signal SS.

[0518] FIG. 24(c) shows an example of the cycle start signal PS.

[0519] FIG. 24D shows an example of an amplitude modulation waveform of the second high frequency power supply 20.

[0520] As shown by the thick line in FIG. 24(b), consider a case where external noise NZ, which is not the original synchronization signal SS, is erroneously detected as the synchronization signal SS.

[0521] As described above, the first high frequency power supply 10 and the second high frequency power supply 20 can receive the cycle start signal PS (see FIG. 1) generated every time one cycle of amplitude modulation is performed.

[0522] This cycle start signal PS is, for example, a pulse-like signal that changes from high level to low level, and the synchronization timing occurs when it changes from low level to high level. That is, an example is shown in which the synchronization timing occurs at the rising edge timing of the cycle start signal PS. Of course, the logic can be reversed. That is, the cycle start signal PS can be a pulse-like signal that changes from low level to high level, and the synchronization timing occurs when it changes from high level to low level. This concept applies hereinafter as well.

[0523] Therefore, the time when the cycle start signal PS is input (when the cycle start signal is input) is set to be the starting point of one cycle of amplitude modulation (elapsed time is 0 (zero)). In this way, even if synchronization error occurs due to external noise NZ, it is possible to recover from the synchronization error when the next cycle start signal PS is input, as shown by the thick line in Figure 24(d).

[0524] (Seventh Modification of the Embodiment) As a seventh modification of the embodiment, the high frequency power supply system 1 may have a function that takes into consideration the following <Measure (No. 2)>.

[0525] <Countermeasure (Part 2)> FIG. 25 is a diagram for explaining countermeasure (Part 2) against the external noise NZ.

[0526] 25A shows an example of an amplitude modulation waveform of the first high frequency power supply 10. FIG.

[0527] FIG. 25(b) shows an example of the synchronization signal SS.

[0528] FIG. 25C shows an example of an amplitude modulation waveform of the second high frequency power supply 20.

[0529] As shown by the thick line in FIG. 25(b), consider a case where external noise NZ, which is not an actual synchronization signal, is erroneously detected as a synchronization signal SS.

[0530] In countermeasure (2), as shown by the diagonal hatching in Figure 25 (b), the synchronization signal SS output when the above-mentioned elapsed time is 0 is generated so as to include unique identification information that can be distinguished from synchronization signals SS output at other times.

[0531] For example, if the synchronization signal SS is a voltage pulse signal, the time width or voltage level of the pulse signal can be differentiated between the synchronization signal SS output when the elapsed time is 0 and the synchronization signal SS output at other times.

[0532] The second high frequency power supply 20 also determines that the time when the synchronization signal SS containing the unique identification information is input is the starting point of one period of amplitude modulation.

[0533] In this way, even if synchronization error occurs due to external noise NZ, the synchronization error can be recovered from when the next synchronization signal SS containing the unique identification information is input, as shown by the bold line in Figure 25 (c).

[0534] Eighth Modification of the Embodiment As an eighth modification of the embodiment, the high frequency power supply system 1 may have a function that takes into consideration the following <Measure (No. 3)>.

[0535] <Countermeasure (Part 3)> FIG. 26 is a diagram for explaining countermeasure (Part 3) against the external noise NZ.

[0536] 26A shows an example of an amplitude modulation waveform of the first high frequency power supply 10. FIG.

[0537] FIG. 26(b) shows an example of the synchronization signal SS.

[0538] FIG. 26C shows an example of an amplitude modulation waveform of the second high frequency power supply 20.

[0539] As shown by the thick line in FIG. 26(b), consider a case where external noise NZ, which is not the original synchronization signal SS, is erroneously detected as the synchronization signal SS.

[0540] In the third measure, the synchronization signals SS are generated so that each has unique identification information, as shown by the diagonal hatching in FIG. 26(b).

[0541] For example, if the synchronization signal SS is a voltage pulse signal, a pulse signal having a predetermined pulse width is generated a predetermined number of times (for example, three times) in succession. A set of such pulse signals can be used as the synchronization signal SS.

[0542] Furthermore, the synchronization signal SS may be a pulse signal having a pulse width that can be distinguished from external noise NZ.

[0543] In this way, the synchronization signal SS can be distinguished from the external noise NZ, and as shown by the absence of a thick line in FIG. 26(d), synchronization deviation can be prevented.

[0544] Ninth Modification of the Embodiment As a ninth modification of the embodiment, the high-frequency power supply system 1i (see FIG. 12) may have a function that takes into consideration the following <Measure (No. 4)>.

[0545] <Countermeasure (No. 4)> FIG. 27 is a diagram for explaining countermeasure (No. 4) against the external noise NZ.

[0546] FIG. 27( a ) shows an example of an amplitude modulation waveform of the first high frequency power supply 10 .

[0547] FIG. 27(b) shows an example of the synchronization signal SS.

[0548] FIG. 27C shows an example of an amplitude modulation waveform of the second high frequency power supply 20.

[0549] FIG. 27(d) shows an example of first high frequency power supply setting value information ST1 corresponding to FIG. 27(a).

[0550] FIG. 27(e) shows an example of second high frequency power source time information TI2 corresponding to FIG. 27(b).

[0551] FIG. 27(f) shows an example of second high frequency power supply setting value information ST2 corresponding to FIG. 27(c).

[0552] 27(d) shows the relationship between the elapsed time and the first high frequency power supply setting value. In this example, the first high frequency power supply setting value information ST1 has three types of information as setting items: a "No." indicating the order, the duration, and the target power value.

[0553] 27( e) shows the relationship between the elapsed time and the time to change the second high frequency power supply setting value used in second high frequency power supply 20. In this example, second high frequency power supply time information TI2 has three types of information as setting items: a “No.” indicating the order, a duration, and a pulse width as information corresponding to the order.

[0554] 27(f) shows the relationship between the elapsed time and the second high frequency power supply setting value. In this example, the second high frequency power supply setting value information ST2 has four types of information as setting items: a "No." indicating the order, a duration, a target power value, and a pulse width as information corresponding to the order.

[0555] As can be seen from the above, the second high frequency power supply time information TI2 and the second high frequency power supply set value information ST2 differ from FIG. 13 in that they include pulse widths as information corresponding to the order.

[0556] Since the pulse widths change in one-to-one correspondence with the order, the synchronization signal SS output from the synchronization signal output unit 82 has a pulse width that corresponds to the order, and therefore the second high frequency power supply setting value information output unit 72 can distinguish the order based on the pulse width.

[0557] Therefore, when the synchronization signal SS is input, the second high frequency power supply set value information output section 72 can output information on the corresponding target power value in order.

[0558] In this case, the synchronization signal SS has continuity because it contains information on the order, so even if external noise NZ is superimposed on the synchronization signal SS when it is transmitted or received, as shown by the thick line in Fig. 27(b), it is highly unlikely that the external noise NZ will be recognized as the synchronization signal SS, as shown by the absence of the thick line in Fig. 27(c).

[0559] Even if the external noise NZ is recognized as the synchronization signal SS, the synchronization error can be recovered at the time when the next synchronization signal is input.

[0560] Therefore, the influence of external noise NZ can be reduced.

[0561] (Tenth Modification of the Embodiment) As a tenth modification of the embodiment, the high frequency power supply system 1 may be improved to have a function that takes into consideration the following <Measure (No. 5)>.

[0562] <Countermeasure (5)> In the countermeasure (3) for external noise NZ described in FIG. 26 and the countermeasure (4) for external noise NZ described in FIG. 27, the synchronization signal SS is modified so that the external noise NZ is not recognized as the synchronization signal SS.

[0563] However, if the external noise NZ is superimposed on the normal synchronization signal SS, it is possible that the normal synchronization signal SS will not be recognized as the synchronization signal SS. In other words, it is possible that the normal synchronization signal SS will be erroneously recognized as the external noise NZ.

[0564] If such a situation occurs, the setting value will not be changed in the slave device even though it is the time when the setting value should be changed.

[0565] Therefore, if a signal that can be regarded as a synchronization signal SS for each slave device is not input within a predetermined time that takes into account the allowable error for the time at which the setting value for each slave device set in the setting value information for each slave device should be changed, the setting value information output unit for each slave device may output a setting value for each slave device corresponding to the elapsed time or a command signal corresponding to the setting value for each slave device based on the setting value information for each slave device ST.

[0566] The high frequency power supply system 1i described with reference to FIGS. 12 and 13 will be used as an example.

[0567] As described above, even if the first high frequency power supply 10i outputs a synchronization signal for the second high frequency power supply (hereinafter referred to as synchronization signal) SS2 in accordance with the time when the target power value should be changed in the second high frequency power supply 20, the second high frequency power supply 20 may recognize the synchronization signal SS2 as external noise NZ.

[0568] For example, even if the synchronization signal SS2 corresponding to the period No. 2 in the second high frequency power supply setting value information ST2 in Fig. 13(f) is output from first high frequency power supply 10i when the elapsed time from the start point of one cycle of amplitude modulation is 200 ms, if second high frequency power supply 20 recognizes the synchronization signal SS2 as external noise NZ, the target power value will not be changed to 300 W but will remain at 500 W.

[0569] Therefore, the second high frequency power supply setting value information output unit 72 measures the elapsed time from the start point of the cycle, and when it determines that the synchronization signal SS2 has not been input within a predetermined time, it changes the setting value to the setting value that should have been changed when the elapsed time has elapsed. The elapsed time from the start point of the cycle may be, for example, the elapsed time from the time when the cycle start signal was input. Alternatively, it may be the time elapsed from the time when the No. 1 period started.

[0570] However, as described above, there is a frequency error between the frequency of the reference clock built into the first high-frequency power supply 10i and the frequency of the reference clock built into the first slave device, so an allowable error α is set for the above-mentioned specified elapsed time.

[0571] For example, the period No. 2 in Figure 13(f) begins at a time when the elapsed time from the start of the cycle is 300 ms. However, taking into consideration the problem of error in the frequency of the reference clock, the elapsed time from the start of the cycle may be set within a range of 300 ms ± α within the above-mentioned predetermined time. The allowable error α may be determined based on the error that may occur. For example, it may be set to about 20 μs.

[0572] In this way, even if external noise NZ is superimposed on a normal synchronization signal SS2 and the signal is recognized as external noise NZ, the set value can be changed to the original set value. Although a deviation in the change time occurs due to an error in the frequency of the reference clock, the effect on the plasma processing process can be reduced compared to when the set value is not changed.

[0573] The same applies to the high-frequency power supply system 1j described in FIGS. 14 and 15 and the high-frequency power supply system 1k described in FIGS. 16 and 17.

[0574] However, in the high-frequency power supply system 1n described in Figures 18, 19, and 20, and the high-frequency power supply system 1p described in Figures 21 and 22, because the synchronization signal SS includes setting value information corresponding to the setting value, the setting value information output section of each slave device does not use slave device setting value information (e.g., second power supply setting value information ST2, etc.) that indicates the relationship between the elapsed time and the slave device setting value. In other words, each slave device cannot recognize the relationship between the elapsed time and the time at which the slave device setting value used by each slave device should be changed and the setting value.

[0575] Therefore, each slave device should be able to recognize the relationship between the elapsed time and the time at which each slave device setting value used in each slave device should be changed, and the setting value to be changed. Specifically, each slave device setting value information output unit should be able to read information from each slave device setting value information ST. Note that each slave device setting value information ST is the same as the setting value information ST described above. For example, the second high frequency power supply setting value information ST2 is the same as that shown in FIG. 13(f).

[0576] FIG. 28 shows the configuration of a high-frequency power supply system 1n′ that has been improved so that each of the slave device setting value information output units 72n, 73n, 74n, and 76n described in FIGS. 18, 19, and 20 can read the information of each of the slave device setting value information ST2, ST3, ST4, and ST5.

[0577] FIG. 29 shows the configuration of a high-frequency power supply system 1p′ that has been improved so that the slave device setting value information output units 72p, 73p, 74p, and 76p described in FIGS. 21 and 22 can read the information of the slave device setting value information ST2, ST3, ST4, and ST5.

[0578] 28 and 29 are different from FIGS. 18 and 21 in the following respects, but are otherwise similar, so detailed description will be omitted.

[0579] A second high frequency power supply information storage unit 29 is added to the second high frequency power supplies 20n′, 20p′, and the second high frequency power supply setting value information output units 72n, 72p are able to read the second high frequency power supply setting value information ST2 stored in the second high frequency power supply information storage unit 29.

[0580] The first matcher 30n', 30p' has an additional first matcher information storage unit 37, which enables the first matcher setting value information output units 73n, 73p to read the first matcher setting value information ST3 stored in the first matcher information storage unit 37.

[0581] The second matchers 40n' and 40p' are additionally provided with a second matcher information storage unit 47, so that the second matcher setting value information output units 74n and 74p can read the second matcher setting value information ST4 stored in the second matcher information storage unit 47.

[0582] A DC power supply information storage unit 66 is added to the DC power supply 60, and the DC power supply setting value information output units 76n, 76p are able to read the DC power supply setting value information ST5 stored in the DC power supply information storage unit 66.

[0583] In this way, the high-frequency power supply system 1n described in Figures 18, 19, and 20, and the high-frequency power supply system 1p described in Figures 21 and 22 can be improved to obtain the same effects as above.

[0584] That is, in the improved high-frequency power supply systems 1n' and 1p', even if an external noise NZ is superimposed on a normal synchronization signal SS and the normal synchronization signal SS is recognized as the external noise NZ, the set value can be changed to the original set value. Although a deviation occurs in the change time due to an error in the frequency of the reference clock, the effect on the plasma processing process can be reduced compared to when the set value is not changed.

[0585] (Eleventh Modification of the Embodiment) As an eleventh modification of the embodiment, the high frequency power supply system 1 may be improved to have a function that takes into consideration the following <Measure (No. 6)>.

[0586] <Countermeasure (6)> As can be seen from Countermeasure (5), each slave device setting value information output unit can determine whether the input synchronization signal was input within a predetermined time period or outside of the predetermined time period. Therefore, if the input synchronization signal was input outside of the predetermined time period, the synchronization signal can be determined to be external noise NZ and not be recognized as a synchronization signal.

[0587] In this way, the synchronization signal can be distinguished from the external noise NZ, and therefore synchronization deviation can be prevented.

[0588] However, the possibility that external noise NZ will be input within a predetermined time is extremely low.

[0589] [Supplementary Note 1] A high frequency power supply system for supplying high frequency power to a load, the high frequency power supply system comprising: a first high frequency power supply capable of supplying first high frequency power to the load by outputting a first high frequency voltage having a first fundamental frequency from a first high frequency voltage output unit to the load; and a first slave device, wherein the first high frequency power supply comprises: a first high frequency power supply setting value information output unit that outputs, based on first high frequency power supply setting value information indicating the relationship between an elapsed time from a starting point of one cycle of amplitude modulation and a first high frequency power supply setting value, the first high frequency power supply setting value corresponding to the elapsed time or a command signal corresponding to the first high frequency power supply setting value; and a first slave device synchronization signal output unit that outputs, based on first slave device time information indicating the relationship between the elapsed time and a time at which the first slave device setting value used in the first slave device should be changed, a first slave device synchronization signal in accordance with the time at which the first slave device setting value should be changed; A high-frequency power supply system including a first-slave-device setting value information output unit that outputs the first-slave-device setting value corresponding to the elapsed time or a command signal corresponding to the first-slave-device setting value based on the first-slave-device synchronization signal and first-slave-device setting value information indicating the relationship between the elapsed time and the first-slave-device setting value. <Effects> The first-slave-device synchronization signal of the present invention is output in accordance with the time at which the first-slave-device setting value is to be changed. Therefore, the first-slave device (e.g., a second high-frequency power supply) can be synchronized with the first high-frequency power supply based on the first-slave-device synchronization signal. Furthermore, the first-slave-device setting value information output unit of the first slave device outputs the first-slave-device setting value corresponding to the elapsed time or a command signal corresponding to the first-slave-device setting value, thereby enabling control according to the first-slave-device setting value. For example, if the first-slave-device setting value is a target power value for the second high-frequency power supply, output control can be performed so that the output high-frequency power becomes the target power value.In the high frequency power supply system according to claim 1, the first high frequency power supply and the first slave device each use a time delay added to the time when a period start signal is input to the first slave device, and therefore synchronization is achieved more frequently than when a period start signal is used for synchronization. Therefore, even if a frequency error occurs between the frequency of the reference clock built in the first high frequency power supply and the frequency of the reference clock built in the first slave device, synchronization is hardly lost between the first high frequency power supply and the first slave device. [Supplementary Note 2] The high frequency power supply system according to claim 1, wherein the first high frequency power supply and the first slave device each use a time delay added to the time when a period start signal generated every time one period of the amplitude modulation is input. [Supplementary Note 3] The high-frequency power supply system according to Supplementary Note 1, wherein the first high-frequency power supply includes unique identification information that enables the first slave device synchronization signal output at the start point to be distinguished from first slave device synchronization signals output at other times, and the first slave device defines the start point as a time when the first slave device synchronization signal including the unique identification information is input or a time when the cycle start signal is input plus a delay time. [Supplementary Note 4] The high-frequency power supply system according to Supplementary Note 1, wherein the first slave device synchronization signals each have unique identification information, and the first slave device recognizes only signals having the unique identification information as the first slave device synchronization signal. [Supplementary Note 5] The high-frequency power supply system according to Supplementary Note 1, wherein the first slave device time information includes information on an order within one cycle of the amplitude modulation, the first slave device synchronization signal output unit outputs the first slave device synchronization signal including the order information, and the first slave device recognizes only the first slave device synchronization signal including the order information as the first slave device synchronization signal.[Supplementary Note 6] The high-frequency power supply system according to Supplementary Note 1, wherein, when a signal regarded as the first-slave device synchronization signal is not input within a predetermined time considering an allowable error with respect to a time at which the first-slave device setting value set in the first-slave device setting value information should be changed, the first-slave device setting value information output unit outputs the first-slave device setting value corresponding to the elapsed time or a command signal corresponding to the first-slave device setting value based on the first-slave device setting value information. [Supplementary Note 7] The high-frequency power supply system according to Supplementary Note 1, wherein, even if external noise NZ that is mistakenly recognized as the first-slave device synchronization signal is input outside the predetermined time considering an allowable error with respect to a time at which the first-slave device setting value set in the first-slave device setting value information should be changed, the first-slave device setting value information output unit does not recognize it as the first-slave device synchronization signal.[Supplementary Note 8] The high frequency power supply system further includes a second slave device, wherein the first high frequency power supply further includes a second slave device synchronization signal output unit that outputs a second slave device synchronization signal in accordance with the time at which the second slave device setting value used in the second slave device should be changed, based on second slave device time information indicating the relationship between the elapsed time and the time at which the second slave device setting value used in the second slave device should be changed, and the second slave device further includes a second slave device setting value information output unit that outputs the second slave device setting value corresponding to the elapsed time or a command signal corresponding to the second slave device setting value, based on the second slave device synchronization signal and second slave device setting value information indicating the relationship between the elapsed time and the second slave device setting value, and the second slave device time information and the second slave device setting value information can each be used repeatedly, and the first slave device The high frequency power supply system according to Supplementary Note 1, comprising: a second high frequency power supply capable of supplying second high frequency power to the load by outputting a second high frequency voltage having a second fundamental frequency that is the same as or different from the first fundamental frequency from a second high frequency voltage output unit to the load, a first matching box provided between the first high frequency power supply and the load, a second matching box provided between the second high frequency power supply and the load, or a DC power supply that supplies a DC voltage to the load. [Supplementary Note 9] The high frequency power supply system according to any one of Supplementary Note 1 to Supplementary Note 8, wherein the first high frequency power supply setting value information, the first slave device time information, and the first slave device setting value information can each be used repeatedly.

[0590] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention described in the claims and their equivalents.

[0591] 1, 1i, 1j, 1k, 1n, 1p, 1n', 1p' High frequency power supply system 10, 10i, 10j, 10k, 10n, 10p First high frequency power supply 20, 20n, 20p Second high frequency power supply 30, 30n, 30p First matching box 40, 40n, 40p Second matching box 50, 50n, 50p Superposition matching box 60, 60n, 60p DC power supply

Claims

1. A high frequency power supply system for supplying high frequency power to a load, the high frequency power supply system comprising: a first high frequency power supply capable of supplying first high frequency power to the load by outputting a first high frequency voltage having a first fundamental frequency from a first high frequency voltage output unit toward the load; and a first slave device, wherein the first high frequency power supply comprises: a first high frequency power supply setting value information output unit that outputs, based on first high frequency power supply setting value information indicating the relationship between an elapsed time from a starting point of one cycle of amplitude modulation and a first high frequency power supply setting value, the first high frequency power supply setting value corresponding to the elapsed time or a command signal corresponding to the first high frequency power supply setting value; and a first slave device synchronization signal output unit that outputs a first slave device synchronization signal in accordance with the time at which the first slave device setting value should be changed, based on first slave device time information indicating the relationship between the elapsed time and a time at which the first slave device setting value used in the first slave device should be changed; a first slave device setting value information output unit that outputs the first slave device setting value corresponding to the elapsed time or a command signal corresponding to the first slave device setting value, based on the first slave device synchronization signal and first slave device setting value information that indicates the relationship between the elapsed time and the first slave device setting value.

2. The high frequency power supply system according to claim 1, wherein the first high frequency power supply and the first slave device respectively use the time when a cycle start signal generated every time period of the amplitude modulation is input or the time when the cycle start signal is input plus a delay time as the starting point.

3. The high frequency power supply system according to claim 1, wherein the first high frequency power supply includes unique identification information that enables the first slave device synchronization signal output at the start point to be distinguished from the first slave device synchronization signals output at other times, and the first slave device defines the start point as the time when the first slave device synchronization signal including the unique identification information is input or the time when a cycle start signal is input plus a delay time.

4. The high frequency power supply system according to claim 1, wherein each of the first slave device synchronization signals has unique identification information, and the first slave device recognizes only signals having the unique identification information as the first slave device synchronization signal.

5. The high frequency power supply system according to claim 1, wherein the first slave device time information includes information on the order within one cycle of the amplitude modulation, the first slave device synchronization signal output unit outputs the first slave device synchronization signal including the order information, and the first slave device recognizes only the first slave device synchronization signal including the order information as the first slave device synchronization signal.

6. The high-frequency power supply system of claim 1, wherein, when a signal that can be regarded as a synchronization signal for the first slave device is not input within a predetermined time that takes into account an allowable error from the time at which the setting value for the first slave device set in the setting value information for the first slave device should be changed, the first slave device setting value information output unit outputs the setting value for the first slave device that corresponds to the elapsed time or a command signal that corresponds to the setting value for the first slave device based on the setting value information for the first slave device.

7. The high frequency power supply system according to claim 1, wherein the first slave device setting value information output unit does not recognize external noise that is mistakenly recognized as the first slave device synchronization signal as the first slave device synchronization signal even if it is input outside of a predetermined time period that takes into account an allowable error with respect to the time at which the first slave device setting value set in the first slave device setting value information should be changed.

8. The high frequency power supply system further comprises a second slave device, wherein the first high frequency power supply further comprises a second slave device synchronization signal output section that outputs a second slave device synchronization signal in accordance with the time at which the second slave device setting value used in the second slave device should be changed, based on second slave device time information indicating the relationship between the elapsed time and the time at which the second slave device setting value used in the second slave device should be changed, and the second slave device further comprises a second slave device setting value information output section that outputs the second slave device setting value corresponding to the elapsed time or a command signal corresponding to the second slave device setting value, based on the second slave device synchronization signal and second slave device setting value information indicating the relationship between the elapsed time and the second slave device setting value, and the second slave device time information and the second slave device setting value information can each be used repeatedly, and the first slave device 2. The high frequency power supply system according to claim 1, comprising: a second high frequency power supply capable of supplying second high frequency power to the load by outputting a second high frequency voltage having a second fundamental frequency that is the same as or different from the first fundamental frequency from a second high frequency voltage output unit toward the load; a first matching box provided between the first high frequency power supply and the load; a second matching box provided between the second high frequency power supply and the load; or a DC power supply that supplies a DC voltage to the load.

9. A high frequency power supply system according to any one of claims 1 to 8, wherein the first high frequency power supply setting value information, the first slave device time information, and the first slave device setting value information can each be used repeatedly.

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