Multilayered metal-two-dimensional (2D) material insulator-metal (m-2dmat-m) capacitor for power delivery and heat dissipation

Abstract

An integrated circuit (IC) structure comprising a multilayered capacitor structure comprising a plurality of electrically conductive layers spaced apart from each other by respective ones of a plurality of electrically insulating layers, wherein the plurality of electrically conductive layers comprise alternating power delivery layers and ground layers, and the plurality of electrically insulating layers comprise two-dimensional (2D) crystalline semiconductor material.

Description

Multilayered Metal-Two-dimensional (2D) Material Insulator-Metal (M-2DMat-M) Capacitor for Power Delivery and Heat DissipationTECHNICAL FIELD

[0001] The present disclosure is generally related to semiconductor structures and electronics packages and, in particular embodiments, to metal-two-dimensional material insulator-metal (M-2DMat-M) capacitor structures and packaging methods.BACKGROUND

[0002] Many electrical components and devices, such as integrated circuits, generate heat while operating. Also, some devices in integrated circuits are susceptible to heat that interferes with electrical characteristics and operations negatively influenced by the heat. Heating effects can especially affect the precision of high-precision devices.

[0003] Printed Circuit Boards (PCBs) are utilized in most electrical devices in use today. PCBs are used to mechanically support and electronically connect electronic components. PCBs typically contain a plurality of electronic devices, such as transistors and resistors, which are physically attached to the substrate. The metal circuitry printed (etched) on the PCBs provides the electrical connections between the components and provides electrical power for them to operate. The substrate material of typical PCBs is not thermally conductive. One challenge in the design of electronics is effectively removing the heat that is generated by the electrical components attached on or integrated within the substrate materials of PCBs that have poor thermal conductivity.SUMMARY

[0004] The disclosed aspects / embodiments of the present disclosure provide techniques, methods and devices or systems that have thin and low-thermal-resistance multilayered metalinsulator-metal (MIM) capacitors that are to be used for power delivery and heat dissipation within an integrated circuit (IC) device and / or outside of an IC device (e.g., on a printed circuit board (PCB)). More specifically, a thin and low-thermal-resistance multilayered MIM capacitor may include electrically conductive layers spaced apart from each other by electrically insulating layers that include 2D material(s) (e.g., gadolinium pentoxide (Gd2O5)). Thus, the thin and low-thermal- resistance multilayered MIM capacitors may also be referred to as multilayered metal-two- dimensional (2D) material insulator-metal (M-2DMat-M) capacitors. The 2D material(s) allow fora thin insulator layer (e.g., a thickness between about 2 nm and 100 nm) with a high dielectric constant and a high breakdown voltage. The thin insulator layers can reduce the distance between the electrically conductive layers, thereby improving thermal heat dissipation. The high dielectric constant and the high breakdown voltage enable the multilayered M-2DMat-M capacitors to maintain power integrity and stability when used in a power delivery network despite the insulating layers being thin. In an embodiment, a multilayered M-2DMat-M capacitors may be provided by stacking a ground layer (e.g., an electrically conductive layer), an electrically insulating layer, and a power delivery layer (e.g., an electrically conductive layer) sequentially (e.g., in a vertical direction, in a horizontal direction, or in any suitable stacking direction) and repeating the stacking. The ground layer, the electrically insulating layer, and the power delivery layer are shaped and arranged such that the power delivery layers are in electrical contact with one another and the ground layers are in electrical contact with one another to provide current paths and thermal conductive paths across the capacitor structure.

[0005] A first aspect of the embodiments of the present disclosure relates to an integrated circuit (IC) structure comprising a multilayered capacitor structure comprising a plurality of electrically conductive layers spaced apart from each other by respective ones of a plurality of electrically insulating layers, wherein the plurality of electrically conductive layers comprise alternating power delivery layers and ground layers, and the plurality of electrically insulating layers comprise two- dimensional (2D) crystalline semiconductor material.

[0006] Optionally, in any of the preceding aspects, another implementation of the aspect provides that the 2D crystalline semiconductor material in an individual layer of the plurality of electrically insulating layers has a thickness between about 1 and 100 nanometers (nm).

[0007] Optionally, in any of the preceding aspects, another implementation of the aspect provides that the 2D crystalline semiconductor material has a dielectric constant greater than 5 at a frequency between about 45 and 55 kilohertz (kHz) and a thickness between about 1 and 50 nanometers.

[0008] Optionally, in any of the preceding aspects, another implementation of the aspect provides that the 2D crystalline semiconductor material has a breakdown field strength greater than 6 megavolts per centimeter (MV / cm).

[0009] Optionally, in any of the preceding aspects, another implementation of the aspect provides that the 2D crystalline semiconductor material comprises at least one of gadolinium (Gd),lanthanum (La), gadolinium pentoxide (Gd20s), lanthanum oxybromide (LaOBr), lanthanum oxychloride (LaOCl), bismuth chloride (BiOCl), calcium hydrogen iodine (CaHI), strontium hydrogen bromide (SrHBr), or strontium Iodide (Srh).

[0010] Optionally, in any of the preceding aspects, another implementation of the aspect provides that an individual layer of the plurality of electrically insulating layers comprises two buffer layers comprising second 2D crystalline semiconductor material different than the 2D crystalline semiconductor material; and a core electrically insulating layer comprising the 2D crystalline semiconductor material between the buffer layers.

[0011] Optionally, in any of the preceding aspects, another implementation of the aspect provides that the second 2D crystalline semiconductor material in the buffer layers comprises crystalline barium nitride (BN).

[0012] Optionally, in any of the preceding aspects, another implementation of the aspect provides that an individual layer of the plurality of electrically insulating layers comprises two buffer layers comprising the 2D crystalline semiconductor material; and a core electrically insulating layer comprising amorphous material between the buffer layers.

[0013] Optionally, in any of the preceding aspects, another implementation of the aspect provides that the amorphous material in the core electrically insulating layer comprises hafnium oxide (HK ).

[0014] Optionally, in any of the preceding aspects, another implementation of the aspect provides that the multilayered capacitor structure further comprises a first electrically insulating material disposed along sidewalls of an individual layer of the electrically conductive layers, and a second electrically insulating material disposed along sidewalls of an individual layer of the ground layers.

[0015] Optionally, in any of the preceding aspects, another implementation of the aspect provides that the first electrically insulating material and the second electrically insulating material comprise at least one of hafnium oxide (HK ) or aluminum oxide (AI2O3).

[0016] Optionally, in any of the preceding aspects, another implementation of the aspect provides that the power delivery layers are configured to be coupled to one of a positive power voltage or a negative power voltage.

[0017] Optionally, in any of the preceding aspects, another implementation of the aspect provides that at least one of the power delivery layers that are configured to be coupled to the positivepower voltage are in electrical contact with each other or the power delivery layers that are configured to be couple to the negative power voltage are in electrical contact with each other, and electrically insulated from the power delivery layers.

[0018] Optionally, in any of the preceding aspects, another implementation of the aspect provides that a first power delivery layer of the power delivery layers is between a second power delivery layer of the power delivery layers and a third power delivery layer of the power delivery layers, the first power delivery comprises a first corner portion and a second, diagonally opposite corner portion respectively in electrical contact with a third corner portion of the second power delivery layer and a fourth corner portion of the third power delivery layer, a first ground layer of the ground layers is between a second ground layer of the ground layers and a third ground layer of the ground layers, and the first ground layer comprises a fifth corner portion and a sixth, diagonally opposite corner portion respectively in electrical contact with a seventh corner portion of the second ground layer and an eighth corner portion of the third ground layer.

[0019] Optionally, in any of the preceding aspects, another implementation of the aspect provides that the first ground layer is between the first and second power delivery layers or the first and third power delivery layers and comprises a cutout corner portion aligned respectively to the first corner portion or the second, diagonally opposite corner portion of the first power delivery layer.

[0020] Optionally, in any of the preceding aspects, another implementation of the aspect provides that the first power delivery layer is between the first and second ground layers or the first and third ground layers and comprises a cutout corner portion aligned respectively to the fifth corner portion or the sixth, diagonally opposite corner portion of the first ground layer.

[0021] Optionally, in any of the preceding aspects, another implementation of the aspect provides that an individual layer of the electrically insulating layers between a respective one of the power delivery layers and a respective one of the ground layers comprises a first cutout corner portion aligned to a cutout corner portion of the respective power delivery layer, and a second cutout corner portion aligned to a cutout corner portion of the respective ground layer.

[0022] Optionally, in any of the preceding aspects, another implementation of the aspect provides that the multilayered capacitor structure is part of a power delivery network of the IC structure.

[0023] A second aspect of the embodiments of the present disclosure relates to an electronics package comprising a die of an electrical chip; a printed circuit board having an opening; and acapacitor structure positioned within the opening, wherein the capacitor structure comprises a plurality of electrically conductive layers spaced apart from each other by respective ones of a plurality of electrically insulating layers, the plurality of electrically conductive layers comprise alternating ground layers and one of positive electrically conductive layers or negative electrically conductive layers, and the plurality of electrically insulating layers comprise two-dimensional (2D) crystalline semiconductor material.

[0024] Optionally, in any of the preceding aspects, another implementation of the aspect provides that the electronics package further comprises a backside heat sink in contact with the capacitor structure.

[0025] Optionally, in any of the preceding aspects, another implementation of the aspect provides that the one of the positive electrically conductive layers or the negative electrically conductive layers of the capacitor structure are configured to respectively provide a positive electrical current path or a negative electrical current path for a supply voltage extending from the printed circuit board across the capacitor structure to the die of the electrical chip.

[0026] Optionally, in any of the preceding aspects, another implementation of the aspect provides that the ground layers of the capacitor structure are configured to provide an electrical current return path to ground extending from the printed circuit board across the capacitor structure to the die of the electrical chip.

[0027] Optionally, in any of the preceding aspects, another implementation of the aspect provides that the capacitor structure further comprises a first electrically insulating material disposed along sidewalls of an individual layer of the one of the positive electrically conductive layers or the negative electrically conductive layers, and a second electrically insulating material disposed along sidewalls of an individual layer of the ground layers.

[0028] Optionally, in any of the preceding aspects, another implementation of the aspect provides that the 2D crystalline semiconductor material in an individual layer of the plurality of electrically insulating layers has a thickness between about 1 and 100 nanometers.

[0029] Optionally, in any of the preceding aspects, another implementation of the aspect provides that the 2D crystalline semiconductor material has a dielectric constant greater than 5 at a frequency between about 45 and 55 kilohertz (kHz) and a thickness between about 1 and 55 nanometers.

[0030] Optionally, in any of the preceding aspects, another implementation of the aspect provides that the 2D crystalline semiconductor material has a breakdown field strength greater than 6 megavolts per centimeter (MV / cm).

[0031] Optionally, in any of the preceding aspects, another implementation of the aspect provides that the 2D crystalline semiconductor material comprises at least one of gadolinium (Gd), lanthanum (La), gadolinium pentoxide (Gd20s), lanthanum oxybromide (LaOBr), lanthanum oxychloride (LaOCl), bismuth chloride (BiOCl), calcium hydrogen iodine (CaHI), strontium hydrogen bromide (SrHBr), or strontium Iodide (Srh).

[0032] Optionally, in any of the preceding aspects, another implementation of the aspect provides that the electronics package further includes a frontside heat sink in contact with an upper surface of the die of the electrical chip.

[0033] A third aspect of the embodiments of the present disclosure relates to a method of forming a capacitor structure, the method comprising providing a ground layer; providing an electrically insulating layer comprising two-dimensional (2D) crystalline semiconductor material; stacking the electrically insulating layer on a surface of the ground layer to provide a stacked structure; providing a power delivery layer; and stacking the power delivery layer on a surface of the stacked structure such that the electrically insulating layer is between the ground layer and the power delivery layer.

[0034] Optionally, in any of the preceding aspects, another implementation of the aspect provides that the power delivery layer comprises a first corner portion and a second corner portion diagonally opposite the first corner portion along a first axis, and a first cutout corner portion and a second cutout corner portion diagonally opposite the first cutout corner portion along a second axis different than the first axis, the ground layer comprises a third corner portion and a fourth corner portion diagonally opposite the third corner portion along the second axis, and a third cutout corner portion and a fourth cutout corner portion diagonally opposite the third cutout corner portion along the first axis, and the electrically insulating layer comprises a fifth cutout corner portion and a sixth cutout corner portion adjacent to the fifth cutout comer portion.

[0035] Optionally, in any of the preceding aspects, another implementation of the aspect provides that the stacking the electrically insulating layer on the surface of the ground layer comprises aligning the fifth cutout corner portion of the electrically insulating layer to expose a surface of the third corner portion of the ground layer, the stacking the power delivery layer on thesurface of the stacked structure comprises aligning the fifth cutout corner portion of the electrically insulating layer to expose a surface of the first corner portion of the power delivery layer; and aligning the first cutout corner portion of the power delivery layer to the sixth cutout corner portion of the of the electrically insulating layer so that the exposed surface of the third corner portion of the ground layer remains exposed.

[0036] Optionally, in any of the preceding aspects, another implementation of the aspect provides that the method further comprises providing a power pad and a ground pad at adjacent corners on a substrate plane; providing a second electrically insulating layer comprising second 2D crystalline semiconductor material, wherein the second electrically insulating layer comprises a seventh cutout corner portion and an eighth cutout corner portion adjacent to the seventh cutout corner portion; and stacking the second electrically insulating layer over the substrate plane to provide a second stacked structure by aligning the seventh cutout corner portion to expose a surface of the power pad and aligning the eighth cutout corner portion to expose a surface of the ground pad.

[0037] Optionally, in any of the preceding aspects, another implementation of the aspect provides that the method further comprises stacking the ground layer on a surface of the second stacked structure such that the fourth corner portion of the ground layer is in electrical contact with the exposed surface of the ground pad to provide a third stacked structure, wherein the stacking the electrically insulating layer on the surface of the ground layer comprises stacking the electrically insulating layer on the third stacked structure, and an electrically insulating material is disposed along a sidewall of the third cutout corner portion of the ground layer adjacent to the power pad to prevent the ground layer from being in electrical contact with the power pad.

[0038] Optionally, in any of the preceding aspects, another implementation of the aspect provides that the stacking the power delivery layer on the surface of the stacked structure comprises aligning the exposed surface of the first corner portion of the power delivery layer to be in electrical contact with the exposed surface of the power pad.

[0039] Optionally, in any of the preceding aspects, another implementation of the aspect provides that the 2D crystalline semiconductor material in the electrically insulating layer has a thickness between about 1 and 100 nanometers.

[0040] Optionally, in any of the preceding aspects, another implementation of the aspect provides that the 2D crystalline semiconductor material has a dielectric constant greater than 5 at afrequency between about 45 and 55 kilohertz (kHz) and a thickness between about 1 and 50 nanometers.

[0041] Optionally, in any of the preceding aspects, another implementation of the aspect provides that the 2D crystalline semiconductor material has a breakdown field strength greater than 6 megavolts per centimeter (MV / cm).

[0042] Optionally, in any of the preceding aspects, another implementation of the aspect provides that the 2D crystalline semiconductor material comprises at least one of gadolinium (Gd), lanthanum (La), gadolinium pentoxide (Gd20s), lanthanum oxybromide (LaOBr), lanthanum oxychloride (LaOCl), bismuth chloride (BiOCl), calcium hydrogen iodine (CaHI), strontium hydrogen bromide (SrHBr), or strontium Iodide (Srh).

[0043] For the purpose of clarity, any one of the foregoing embodiments may be combined with any one or more of the other foregoing embodiments to create a new embodiment within the scope of the present disclosure.

[0044] These and other features will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings and claims.BRIEF DESCRIPTION OF THE DRAWINGS

[0045] For a more complete understanding of this disclosure, reference is now made to the following brief description, taken in connection with the accompanying drawings and detailed description, wherein like reference numerals represent like parts.

[0046] FIG. 1 illustrates a side cross-sectional view of a multilayered metal-two-dimensional material insulator-metal (M-2DMat-M) capacitor structure according to an embodiment of the present disclosure.

[0047] FIG. 2 illustrates top views of a portion of a multilayered M-2DMat-M capacitor structure according to an embodiment of the present disclosure.

[0048] FIGS. 3A-3H illustrate an example method of providing a multilayered M-2DMat-M capacitor structure according to an embodiment of the present disclosure.

[0049] FIGS. 4A-4B illustrate example current paths in a multilayered M-2DMat-M capacitor structure according to an embodiment of the present disclosure.

[0050] FIG. 5 illustrates a side cross-sectional view of another multilayered M-2DMat-M capacitor structure according to an embodiment of the present disclosure.

[0051] FIG. 6 illustrates a side cross-sectional view of an integrated circuit (IC) structure including a multilayered M-2DMat-M capacitor structure for backside power delivery according to an embodiment of the present disclosure.

[0052] FIG. 7 illustrates a side cross-sectional view of an electronics package including a multilayered M-2DMat-M capacitor structure according to an embodiment of the present disclosure.

[0053] FIG. 8 is a flowchart of an example method of providing a multilayered M-2DMat-M capacitor structure according to an embodiment of the present disclosure.

[0054] FIG. 9 is a block diagram of an example computer apparatus according to an embodiment of the present disclosure.DETAILED DESCRIPTION

[0055] It should be understood at the outset that although an illustrative implementation of one or more embodiments are provided below, the disclosed systems and / or methods may be implemented using any number of techniques, whether currently known or in existence. The disclosure should in no way be limited to the illustrative implementations, drawings, and techniques illustrated below, including the exemplary designs and implementations illustrated and described herein, but may be modified within the scope of the appended claims along with their full scope of equivalents.

[0056] The following terms are defined as follows unless used in a contrary context herein. Specifically, the following definitions are intended to provide additional clarity to the present disclosure. However, terms may be described differently in different contexts. Accordingly, the following definitions should be considered as a supplement and should not be considered to limit any other definitions of descriptions provided for such terms herein.

[0057] A data center may include various information technology (IT) equipment and computing devices. In an example, a data center may consume about 40 % of its total electrical power consumption on computing, 20 % of its total electrical power consumption on the IT equipment, and 40 % of its total electrical power consumption on cooling. IT equipment and computing devices may include various integrated circuit (IC) devices and / or electronic packages (e.g., including IC devices and electrical components on printed circuit boards (PCBs)). Thus, heat dissipation is an important aspect in the design of IC devices and / or electronic packages.

[0058] Backside power delivery (BSPD) is an advanced technique in semiconductor design that delivers power to components (e.g., transistors) through the backside of a silicon wafer. BSPD can provide various benefits compared to traditional top or frontside power delivery (e.g., on the same side as the signals). For instance, BSPD can reduce resistance and voltage (IR) drop, increase routing area for signals, improve performance and power efficiency, and / or enable continued transistor scaling.

[0059] As advanced semiconductor nodes continue to scale (e.g., to below 14 nanometers (nm) processes), maintaining power integrity becomes critically important. Metal-insulator-metal (MIM) capacitors are being increasingly explored for BSPD and heat dissipation due to their abilities to maintain high power quality, suppress voltage noise and transients caused by high switching activities, and ensure stable performance and reliability of transistors at advanced processes below 14 nm. A MIM capacitor may include an electrically insulating layer between two metal layers (e.g., electrically conductive layers). The capacitance of a capacitor (e.g., a MIM capacitor) may be computed as shown below:C=A X SeffX So / tox, ( 1 ) where A represents the area of overlap between the metal layers (in square meters), £ represents the effective dielectric constant of the electrically insulating layer, so represents the vacuum permittivity, and toxrepresents the thickness of the electrically insulating layer. As can be observed from equation (1), the electrically insulating layer can have an important role in determining the capacitance of a MIM capacitor. For instance, to achieve a high capacitance for a given area A, the electrically insulating layer should be thin (e.g., toxhaving a small value) and the effective dielectric constant should be high (e.g., £ having a high value). Currently, a high dielectric constant and large bandgap material of choice for the electrically insulating layer in a MIM capacitor is hafnium oxide (HfCh). For instance, HfCh may have a dielectric constant of about 25 and a bandgap voltage of about 5.5 electron Volt (eV).

[0060] While MIM capacitors are primarily used for power integrity and decoupling, MIM capacitors can also assist in heat dissipation. For instance, a BSPD network including MIM capacitors may be placed near power vias and power rails at the backside of a silicon wafer and disposed between the back of a silicon wafer and a heat sink, where the MIM capacitors can assist in transferring heat towards the heat sink. To that end, the metal layers of a MIM capacitor are often composed of copper or aluminum, which are good thermal conductors. While the electricallyinsulating layer between the metal layers is not thermally conductive, a thinner electrically insulating layer can reduce the distance between the metal layers and thus improve heat transfer. While HfCh is a good choice for electrically insulating layers in MIM capacitors, HfO; is amorphous and has a high leakage when the HfCh is in a thin layer (e.g., at a thickness of about 50 nm or less). The high leakage can have various adverse effects on the power integrity of a power delivery network, such as causing power loss and instability.

[0061] Disclosed herein are techniques for providing thin and low-thermal-resistance multilayered MIM capacitors to be used for power delivery and heat dissipation within an integrated circuit (IC) device and / or outside of an IC device (e.g., on a printed circuit board (PCB)). More specifically, a thin and low-thermal-resistance multilayered MIM capacitor may include electrically conductive layers spaced apart from each other by electrically insulating layers that include 2D material(s) (e.g., gadolinium pentoxide (Gd2O5)). Thus, the thin and low-thermal- resistance multilayered MIM capacitors may also be referred to as multilayered metal-two- dimensional (2D) material insulator-metal (M-2DMat-M) capacitors. 2D materials are crystalline solids including a single layer of atoms. 2D materials have strong in-plane covalent bonds and weak out-of-plane van der Waals (vdW) bonds. 2D materials may also refer to vdW dielectrics with dangling-bond-free and atomically flat surfaces. The 2D material(s) allow for a thin insulator layer (e.g., a thickness between about 2 nm and 100 nm) with a high dielectric constant and a high breakdown voltage without the aforementioned adverse effects. The thin insulator layers can reduce the distance between the electrically conductive layers, thereby improving thermal heat dissipation. The high dielectric constant and the high breakdown voltage enable the multilayered M-2DMat-M capacitors to maintain power integrity and stability when used in a power delivery network despite the insulators being thin.

[0062] In one embodiment, the multilayered M-2DMat-M capacitors are part of a power delivery network positioned at the backside of a silicon wafer in an IC device. In another embodiment, the multilayered M-2DMat-M capacitors are part of a power delivery network positioned within a PCB and in contact with a heat sink. In an embodiment, a multilayered M-2DMat-M capacitors may be provided by stacking a ground layer (e.g., an electrically conductive layer), an electrically insulating layer, and a power delivery layer (e.g., an electrically conductive layer) in order or sequentially (e g., in a vertical direction, in a horizontal direction, or generally, in any suitable stacking direction) and repeating the stacking. The ground layer, theelectrically insulating layer, and the power delivery layer are shaped and arranged such that the power delivery layers are in electrical contact with one another and the ground layers are in electrical contact with one another to provide return current paths and thermal conductive paths across the capacitor structure.

[0063] FIG. 1 illustrates a side cross-sectional view of a multilayered M-2DMat-M capacitor structure 100 (hereinafter “capacitor structure”) according to an embodiment of the present disclosure. The side cross-sectional view may be in a y-z plane along line A-A of FIG. 2. In an embodiment, the capacitor structure 100 is part of a power delivery network positioned at the backside of a silicon wafer in an IC device (e.g., as shown in FIG. 6). In another embodiment, the capacitor structure 100 is part of a power delivery network positioned within a PCB and in contact with a heat sink (e.g., as shown in FIG. 7).

[0064] The capacitor structure 100 may include a plurality of electrically conductive layers 101 spaced apart from each other in a direction of the z-axis by respective ones of a plurality of electrically insulating layers 106 formed on a substrate 110 (e.g., including silicon or any suitable flat insulating layer materials). Generally, the alternating electrically conductive layers 101 and electrically insulating layers 106 may be formed or stacked along a direction about perpendicular to a surface of the substrate 110. The plurality of electrically conductive layers 101 may include alternating power delivery layers 102 and ground layers 104. In some instances, the power delivery layers 102 may be positive electrically conductive layers (e.g., when a positive power supply voltage, denoted as Vdd, is connected to the power delivery layers 102). Stated differently, the power delivery layers 102 may be configured to have a positive electrical polarity. Alternatively, the power delivery layers 102 may be negative electrically conductive layers (e.g., when a negative power supply voltage, denoted as Vss, is connected to the power delivery layers 102). Stated differently, the power delivery layers 102 may be configured to have a negative electrical polarity.

[0065] The plurality of electrically conductive layers 101 may be metal layers or metal sheets. In some examples, the plurality of electrically conductive layers 101 may include copper and / or aluminum, which are good thermal conductors. In some examples, an individual electrically conductive layer 101 may have a thickness 112 between about 1, 2, or 3 micrometers (pm). According to embodiments of the present disclosure, the plurality of electrically insulating layers 106 may include one or more 2D crystalline semiconductor materials. In some examples, the 2D crystalline semiconductor material in an electrically insulating layer 106 may have a thickness 114between about 1 and 100 nanometers. In certain examples, the 2D crystalline semiconductor material in an electrically insulating layer 106 may have a thickness 114 of about 5 nm, 10 nm, or any value less than 50 nm. In an example, when the electrically conductive layer 101 are copper layers, each having a thickness 112 of about 1 pm and each electrically insulating layer 106 has a thickness between about 1 and 100 nm, the capacitor structure 100 may have 98.5 % copper in volume, thereby providing good thermal dissipation.

[0066] Generally, the thinner the electrically insulating layers 106, the higher the thermal conductivity of the capacitor structure 100. As discussed above, the capacitor structure 100 may be used in a power delivery network to provide power integrity and / or decoupling. To maintain power integrity, a thin electrically insulating layer 106 is to have a high dielectric constant and a high bandgap or breakdown field strength. Generally, there are two contributors to a dielectric constant, an optical component and an ionic or ferro component. The optical component contributes to the high-frequency dielectric constant (e.g., denoted as &>), and the ionic or ferro component contributes to the static dielectric constant (e.g., denoted as £o - £«>) at a slower frequency. Further, power switching activities (e.g., at a power delivery network) may generally occur at a significantly slower frequency than control signal switching activities (e.g., with transistors). Thus, generally 2D crystalline semiconductor material with a dielectric constant greater than 5 at a frequency between about 45 and 55 kilohertz (kHz) and a thickness between about 1 and 50 nm and a breakdown field strength greater than 6 megavolts per centimeter (MV / cm) may be used for the electrically insulating layers 106. In certain examples, the 2D crystalline semiconductor material in the electrically insulating layers 106 may have a dielectric constant greater than 25 at a frequency between about 45 and 55 kHz and a thickness between about 2 and 50 nm and a breakdown field strength between about 6 and 16 MV / cm).

[0067] The 2D crystalline semiconductor material in the electrically insulating layers 106 may generally include rare earth elements such as lanthanum (La) and / or gadolinium (Gd). In some examples, the 2D crystalline semiconductor material in the electrically insulating layers 106 may include at least one of gadolinium pentoxide (Gd20s), lanthanum oxybromide (LaOBr), lanthanum oxychloride (LaOCl), bismuth chloride (BiOCl), calcium hydrogen iodine (CaHI), strontium hydrogen bromide (SrHBr), or strontium Iodide (SrL). In a certain example, the 2D crystalline semiconductor material in the electrically insulating layers 106 may include Gd20s, which may have a high breakdown bandwidth strength in the range of 6.9 to 15.7 MV / cm and an effective dielectricconstant (e.g., denoted as eeff) of about 25.5 at a frequency of about 50 kHz and a thickness 114 of about 32 nm. Generally, the 2D crystalline semiconductor material in the electrically insulating layers 106 may have a dielectric constant greater than 5. Dielectric constant has two components: optical and static-optical. Dielectric constant can drop when the modulation frequency increases.

[0068] In an example, the capacitor structure 100 may have an area A of about a 1 millimeter (mm) by 1 mm in the x-y plane (or more specifically, an overlap of about 1 mm by 1 mm between the electrically conductive layers 101) and the 2D crystalline semiconductor material in the electrically insulating layers 106 may be Gd2Os (e.g., having an effective dielectric constant eeff of about 25.5 at a frequency of 50 kHz and a thickness 114 of about 32 nm). That is, each electrically insulating layer and corresponding adjacent power delivery layer 102 and adjacent ground layer 104 may provide a capacitance of about 0.007 microfarad (pF). Thus, tor the capacitor structure 100 to provide 1 pF capacitance, the capacitor structure 100 may have a total of 142 electrically insulating layers 106 and corresponding adjacent power delivery layers 102 and adjacent ground layers 104. Assuming the thickness 112 of each of the power delivery layers 102 and each of the ground layers 104 is about 1 pm, the total thickness of the capacitor structure may be about 300 pm. Assuming Gd20s at the above specified conditions and having a breakdown voltage greater than 10 MV / cm, an applied voltage of 1 volt (V) at 32 nm corresponding to 0.3 MV / cm is well below the 10 MV / cm breakdown voltage.

[0069] As will be discussed more fully below with reference to FIGS. 2, 3 A-3H, and 4A-4B, the power delivery layers 102, the ground layers 104, and the electrically insulating layers 106 are shaped and arranged such that the power delivery layers 102 are in electrical contact with each other via certain corner portions of the power delivery layers 102 (e.g., as indicated by the arrow 120) and the ground layers 104 are in electrical contact with each other via certain corner portions of the ground layers 104 (e.g., as indicated by the arrows 122). Further, electrically insulating material 108 is disposed on the edges or sidewalls of the power delivery layers 102 and the ground layers 104. In an example, the electrically insulating material 108 may include at least one of HfO2 or aluminum oxide (AI2O3).

[0070] FIG. 2 illustrates top views of a portion 118 of the capacitor structure 100 of FIG. 1 according to an embodiment of the present disclosure. The top views are in an x-y plane. The leftside of FIG. 2 illustrates the top views of a power delivery layer 102, an electrically insulating layer 106, and a ground layer 104 separately. The right-side of FIG. 2 illustrates the portion 118after the power delivery layer 102, the electrically insulating layer 106, and the ground layer 104 are stacked sequentially in a direction along the z-axis. That is, the electrically insulating layer 106 is a middle layer between the power delivery layer 102 and the ground layer 104.

[0071] As shown in the left-side of FIG. 2, the edges or sidewalls 206a-206f of the power delivery layer 102 and edges or sidewalls 208a-208f of the ground layer 104 may be coated with the electrically insulating material 108. Further, the power delivery layer 102 may have a cutout corner portion 210 and a diagonally, opposite cutout corner portion 212 along an axis 202 (e.g., a diagonal axis). The ground layer 104 may also have a cutout corner portion 214 and a diagonally, opposite cutout corner portion 216 along an axis 204 (e.g., a diagonal axis) different than the axis 202. For instance, the axis 204 may intercept the axis 202 as shown. Stated differently, the power delivery layer 102 and the ground layer 104 may have different pairs of diagonally, opposite cutout corner portions. Further, the electrically insulating layer 106 may also include a cutout corner portion 218 and a cutout corner portion 220 adjacent to the cutout corner portion 218.

[0072] As shown in the right-side of FIG. 2, the power delivery layer 102, the electrically insulating layer 106, and the ground layer 104 are stacked sequentially (in the direction along the z-axis) such that the cutout corner portion 212 of the power delivery layer 102 is in alignment with the cutout corner portion 220 of the electrically insulating layer 106 to expose a surface (e.g., a top surface in the direction of the z-axis) of a corner portion 222 of the ground layer 104. As will be discussed more fully below with reference to FIGS. 3A-3H, the exposed corner potion 222 allows the ground layer 104 to be in electrical contact with the next, upper ground layer 104 in the capacitor structure 100. Further, all the power delivery layers 102 in the capacitor structure 100 may have cutout corner portions at the same locations (e.g., the bottom-left and the top-right corners) as the power delivery layer 102 shown in FIG. 2 and all the ground layers 104 in the capacitor structure 100 may have cutout corner portions at the same locations (e.g., the top-left and the bottom-right corners) as the ground layer 104 shown in FIG. 2. However, the cutout corner portions of the electrically insulating layers 106 in the capacitor structure 100 may rotate from one electrically insulating layer 106 to the next electrically insulating layer 106 (e.g., shown in FIGS. 3A and 3C). Such an arrangement may allow respective uncut corner portions (e.g., the top-left corner and the bottom-right corner) of each power delivery layer 102 to be connected to (in electrical contact with) adjacent power delivery layers 102 on opposite sides of the respective power delivery layer 102 (e.g., above and below the respective power delivery layer 102 in thedirection of the z-axis). Similarly, such an arrangement may allow each ground layer 104 to be connected to (in electrical contact with) adjacent ground layers 104 on opposite sides of the respective ground layer 104 (e.g., above and below the respective ground layer 104 in the direction of the z-axis). In some instances, because adjacent power delivery layers 102 are separated by a ground layer 104 and an electrically insulating layer 106, the uncut corner portions of a power delivery layer 102 may have a greater height (in the direction along the z-axis) than the rest of the plane to enable contact with a next upper power delivery layer 102 or a next lower power delivery layer 102. Similarly, because adjacent ground layers 104 are separated by a power delivery layer 102 and an electrically insulating layer 106, the uncut corner portions of a ground layer 104 may have a greater height (in the direction along the z-axis) than the rest of the plane to enable contact with a next upper ground layer 104 or a next lower ground layer 104.

[0073] FIGS. 3A-3H illustrate an example method 300 of providing the capacitor structure 100 according to an embodiment of the present disclosure. At a high level, the method 300 may provide the capacitor structure 100 by stacking a ground layer 104, an electrically insulating layer 106, and a power delivery layer 102 sequentially (e.g., in a direction along the z-axis) or in a reverse order and repeating the stacking. FIGS. 3A-3H illustrate the stacking using top views of the power delivery layers 102, the ground layers 104, and the electrically insulating layers 106 in the x-y plane. Generally, the power delivery layers 102 with the electrically insulating material 108 along the sidewalls 206a-206f, the ground layers 104 with the electrically insulating material 108 along the sidewalls 208a-208f, and the electrically insulating layers 106 may be prefabricated using any suitable semiconductor fabrication processes (e.g., wafer preparation, atomic layer deposition (ALD), pulsed laser deposition (PLD), chemical vapor deposition (CVD), sputtering, patterning, dry etching, wet etching, reactive ion etching, doping, oxidization, planarization, annealing, etc.). The following discussions may use the terms “a top surface” or “a bottom surface” to refer to the orientations or sides when viewing along a direction of the z-axis.

[0074] Turning now to FIG. 3 A, the method 300 may begin with providing two electrically conductive pads 301 (individually shown as 301a and 301b). The electrically conductive pads 301 may be formed on a substrate 110 using any suitable semiconductor fabrication processes. The electrically conductive pads 301a and 301b may respectively be referred to as a power pad and a ground pad and may respectively be illustrated using the same pattern as the power delivery layer 102 and the ground layer 104. In one embodiment, the power pad 301a may be configured to beconnected to a positive supply voltage Vdd (e.g., via a bond wire) and the ground pad 301b may be configured to be connected to ground, denoted as Vgnd (e.g., via a bond wire). In another embodiment, the power pad 301a may be configured to be connected to a negative supply voltage Vss (e.g., via a bond wire) and the ground pad 301b may be configured to be connected to ground Vgnd (e.g., via a bond wire). Next, the electrically insulating layer 106a with a top-left cutout corner portion and a bottom-left cutout corner portion may be stacked on a surface of the power pad 301a and the ground pad 301b to form a stacked structure 302. The electrically insulating layer 106a may have a top-left cutout corner portion and a bottom-left cutout corner portion. The stacking may include aligning the top-left cutout corner portion and the botom-left cutout corner portion of the electrically insulating layer 106a respectively to the power pad 301a and the ground pad 301b so that a surface (e g., a top surface) of a corner portion 330 of the power pad 301a and a surface (e.g., a top surface) of a corner portion 340 of the ground pad 301b may be exposed.

[0075] Turning now to FIG. 3B, after forming the stacked structure 302, a ground layer 104a may be stacked on a surface of the stacked structure 302 such that the ground layer 104a is adjacent to the electrically insulating layer 106a to form a stacked structure 304. The stacking may include aligning the top-left cutout corner portion and the bottom-right cutout corner portion of the ground layer 104a respectively to the top-left cutout corner portion and the botom-left cutout corner portion of the electrically insulating layer 106a so that the previously exposed surface (e.g., the top surface) of the corner portion 330 of the power pad 301a may remain exposed and a surface (e.g., the top surface) of the bottom-right corner portion of the electrically insulating layer 106a may be exposed. The electrically insulating material 108 along the sidewall of the top-left corner of the ground layer 104a may prevent the ground layer 104a from being in electrical contact with the exposed portion of the power pad 301a. The stacking may further include aligning the corner portion 342 of the ground layer 104a to the exposed corner portion 340 of the ground pad 301b so that a surface (e.g., the bottom surface) of the corner portion 342 of ground layer 104a facing the exposed corner portion 340 of the ground pad 301b may be in electrical contact with the exposed corner portion 340.

[0076] Turning now to FIG. 3C, after forming the stacked structure 304, an electrically insulating layer 106b may be stacked on a surface of the stacked structure 304 such that the electrically insulating layer 106b is adjacent to the ground layer 104a to form a stacked structure 306. The electrically insulating layer 106b may have a top-left cutout corner portion and a top-right cutout corner portion. As can be seen, the cutout comer portions of electrically insulating layer 106b 1are rotated clockwise by 90 degrees from the previous electrically insulating layer 106a. The stacking may include aligning the top-left cutout corner portion and the top-right cutout corner portion of the electrically insulating layer 106b respectively to the top-left cutout corner portion and the top-right corner portion 344 of the ground layer 104a so that the previously exposed surface (e.g., the top surface) of the corner portion 330 of the power pad 301a may remain exposed and a surface (e.g., the top surface) of the top-right corner portion 344 of the ground layer 104a may be exposed.

[0077] Turning now to FIG. 3D, after forming the stacked structure 306, a power delivery layer 102a may be stacked on a surface of the stacked structure 306 such that the power delivery layer 102a is adjacent to the electrically insulating layer 106b to form a stacked structure 308. The stacking may include aligning the top-right cutout corner portion and the bottom-left cutout corner portion of the power delivery layer 102a respectively to the top-right cutout corner portion and the bottom-left corner portion of the electrically insulating layer 106b so that the previously exposed surface (e.g., the top surface) of corner portion 344 of the ground layer 104a may remain exposed and the bottomleft corner portion of the electrically insulating layer 106b may be exposed. The electrical insulating material 108 along the sidewall of the top-right corner of the power delivery layer 102a may prevent the power delivery layer 102a from being in electrical contact with the exposed portion 344 of the ground layer 104a.The stacking may further include aligning the top-left corner portion 332 of the power delivery layer 102a to the exposed corner portion 330 of the power pad 301a so that a surface (e.g., the bottom surface) of the corner portion 332 of the power delivery layer 102a facing the exposed corner portion 330 of the power pad 301a may be in electrical contact with the exposed corner portion 330.

[0078] Turning now to FIG. 3E, after forming the stacked structure 308, an electrically insulating layer 106c may be stacked on a surface of the stacked structure 308 such that the electrically insulating layer 106c is adjacent to the power delivery layer 102a to form a stacked structure 310. The electrically insulating layer 106c may have a top-right cutout corner portion and a bottom-right cutout corner portion. As can be seen, the cutout comer portions of electrically insulating layer 106c are rotated clockwise by 90 degrees from the previous electrically insulating layer 106b. The stacking may include aligning the top-right cutout corner portion and the bottom-right cutout corner portion of the electrically insulating layer 106c respectively to the top-right cutout corner portion and the bottom-right corner portion 334 of the power delivery layer 102a so that the previously exposed surface (e.g., the top surface) of the corner portion 344 of the ground layer 104a may remain exposedand a surface (e g., the top surface) of the bottom-right corner portion 334 of power delivery layer 102a may be exposed.

[0079] Turning now to FIG. 3F, after forming the stacked structure 310, a ground layer 104b may be stacked on a surface of the stacked structure 306 such that the ground layer 104b is adjacent to the electrically insulating layer 106c to form a stacked structure 312. The stacking may include aligning the bottom-right cutout corner portion and the top-left cutout corner portion of the ground layer 104b to the bottom-right cutout corner portion and the top-left corner portion of the electrically insulating layer 106c so that the previously exposed surface (e.g., the top surface) of the bottomright corner portion 334 of the power delivery layer 102a may remain exposed and a surface (e.g., the top surface) of the top-left corner portion of the electrically insulating layer 106c may be exposed. The electrical insulating material 108 along the sidewall of the bottom-right cutout corner portion of the ground layer 104b may prevent the ground layer 104b from being in electrical contact with the exposed portion 334 of the power delivery layer 102a. The stacking may further include aligning the top-right corner portion 346 of the ground layer 104b to the exposed corner portion 344 of the ground layer 104a so that a surface (e.g., the bottom surface) of the corner portion 346 of the ground layer 104b facing the exposed corner portion 344 of the lower ground layer 104a may be in electrical contact with the exposed corner portion 344.

[0080] Turning now to FIG. 3G, after forming the stacked structure 312, an electrically insulating layer 106d may be stacked on a surface of the stacked structure 312 such that the electrically insulating layer 106d is adjacent to the ground layer 104b to form a stacked structure 314. The electrically insulating layer 106d may have a bottom-left cutout corner portion and a bottom-right cutout corner portion. As can be seen, the cutout corner portions of electrically insulating layer 106d are rotated clockwise by 90 degrees from the previous electrically insulating layer 106c. The stacking may include aligning the bottom-right cutout corner portion and the bottomleft cutout corner portion of the electrically insulating layer 106d respectively to the bottom-right cutout corner portion and the bottom-left corner portion 348 of the ground layer 104b so that the previously exposed surface (e.g., the top surface) of the bottom-right corner portion 334 of the power delivery layer 102a may remain exposed and a surface (e.g., the top surface) of the bottom-left corner portion 348 of the ground layer 104b may be exposed.

[0081] Turning now to FIG. 3H, after forming the stacked structure 314, a power delivery layer 102b may be stacked on a surface of the stacked structure 314 such that the power delivery layer102b is adjacent to the electrically insulating layer 106d to form a stacked structure 316. The stacking may include aligning the bottom-left cutout corner portion and the top-right cutout corner portion of the power delivery layer 102b respectively to the bottom-left cutout corner portion and the top-right corner portion of the electrically insulating layer 106c so that the previously exposed surface (e.g., the top surface) of the botom-left corner portion 348 of the ground layer 104b may remain exposed and a surface (e.g., the top surface) of the top-right corner portion of the electrically insulating layer 106b may be exposed. The electrical insulating material 108 along the sidewall of the botom-left corner of the power delivery layer 102b may prevent the power delivery layer 102b from being in electrical contact with the exposed portion 348 of the ground layer 104b. The stacking may further include aligning the bottom-right corner portion 336 of the power delivery layer 102b to the exposed corner portion 334 of the power delivery layer 102a so that a surface (e.g., the bottom surface) of the corner portion 336 of the power delivery layer 102b facing the exposed corner portion 334 of the power delivery layer 102a may be in electrical contact with the exposed corner portion 334.

[0082] Subsequently, an electrically insulating layer 106, a ground layer 104, and a power delivery layer 102 may be stacked in a sequential order on a surface of the stacked structure 316 along the direction of the z-axis and so on using similar mechanisms discussed above with reference to FIGS. 3A-3H. That is, the stacking operations may be repeated until the desired number of layers are achieved (e.g., for a certain target capacitance to be provided by the capacitor structure 100).

[0083] As can be observed from FIGS. 3A-3H, an individual power delivery layer 102 in the capacitor structure 100 may be connected to adjacent power delivery layers 102 on opposite sides of the individual power delivery layer 102 (e.g., above and below the individual power delivery layer 102 in the direction of the z-axis) via different ones of the top-left corner portion or the bottom-right corner portion of the individual power delivery layer 102. Similarly, an individual ground layer 104 in the capacitor structure 100 may be connected to adjacent ground layers 104 on opposite sides of the individual ground layer 104(e.g., above and below the individual ground layer 104 in the direction of the z-axis) via different ones of the bottom-left corner portion or the top-right corner portion of the individual power delivery layer 102. Stated differently, the power delivery layers 102 in the capacitor structure 100 are continuous and in electrical contact with one another, and the ground layers 104 in the capacitor structure 100 may be continuous and in electrical contact with one another to provide thermal conductive paths across the capacitor structure 100.

[0084] In some instances, a corner portion of a power delivery layer 102 may extend towards a corresponding corner portion of a next upper power delivery layer 102 or a next lower power delivery layer 102 (e.g., at the location of the arrow 120 shown in FIG. 1). Similarly, a corner portion of a ground layer 104 may extend towards a corresponding corner portion of a next upper ground layer 104 or a next lower ground layer 104 (e.g., at the locations of the arrows 122 shown in FIG. 1). As discussed above, the thickness 112 of a power delivery layer 102 or a ground layer 104 may be about 1, 2, or 3 pm, whereas the thickness 114 of an electrically insulating layer 106 may be between about 1 and 100 nm. Thus, the corner portions of the power delivery layers 102 and the ground layers 104 may extend by a fraction of the thickness 112 of the respective power delivery layers 102 and ground layers 104. In such instances, the electrically insulating material 108 disposed along the sidewalls (e.g., the sidewalls 206c and 2061) of the bottom-left cutout corner portions (e.g., the cutout corner portion 210) and the top-right cutout corner portions (e.g., the cutout corner portion 212) of the power delivery layers 102 may electrically insulate (or separate) the power delivery layer 102 from respective ground layers 104. Similarly, the electrically insulating material 108 disposed along the sidewalls (e.g., the sidewalls 208b and 208e) of the top-left cutout corner portions (e.g., the cutout corner portion 214) and the bottom-right cutout comer portions (e.g., the cutout corner portion 216) of the ground layers 104 may electrically insulate (or separate) the ground layers 102 from respective power delivery layers 102.

[0085] Accordingly, in an embodiment, a first power delivery layer 102 of the power delivery layers 102 comprises a first corner portion and a second, diagonally opposite corner portion (e.g., the corner portions 332 and 334) respectively in electrical contact with a third corner portion (e.g., the corner portion 332) of a second power delivery layer 102 of the power delivery layers 102and a fourth corner portion (e.g., the corner portion 334) of a third power delivery layer 102 of the power delivery layers 102, where the first power delivery layer 102 is between the second and third power deliver layers 102. Similarly, a first ground layer 104 of the ground layers 104 comprises a fifth corner portion and a sixth, diagonally opposite corner portion (e.g., the corner portions 344 and 342) respectively in electrical contact with a seventh corner portion (e.g., the corner portion 342) of a second ground layer 104 of the ground layers 104 and an eighth corner portion (e.g., the corner portion 344) of a third ground layer 104 of the ground layers 104, where the first ground layer 104 is between the second and third ground layers 104. In some embodiments, the first ground layer 104 is between the first and second power delivery layers 102 or the first and third power delivery layers102 and comprises a cutout corner portion (e.g., the cutout corner portions 210 and 212) aligned respectively to the first corner portion or the second, diagonally opposite corner portion of the first power delivery layer 102. In some embodiments, the first power delivery layer 102 is between the first and second ground layers 104 or the first and third ground layers 104 and comprises a cutout corner portion (e g., the cutout corner portions 214 and 216) aligned respectively to the fifth corner portion or the sixth, diagonally opposite corner portion of the first ground layer. In some embodiments, an individual layer of the electrically insulating layers 106 between a respective one of the power delivery layer 102 and a respective one of the ground layer 104 comprises a first cutout corner portion (e.g., the cutout corner portion 220) aligned to a cutout corner portion of the respective power delivery layer and a second cutout corner portion (e.g., the cutout corner portion 218) aligned to a cutout corner portion of the respective ground layer 104.

[0086] As will be discussed more fully below with reference to FIGS. 4A-4B, the continuity of the power delivery layers 102 and the continuity of the ground layers 104 in the capacitor structure 100 may allow for current paths and thermal conduction paths across the capacitor structure 100 in the direction along the z-axis. In some embodiments, the locations of the cutout corner portions of the power delivery layers 102 may be switched with the locations of the cutout corner portions of the ground layer 104. That is, all the power delivery layers 102 in a capacitor structure 100 may have cutout corner portion in the top-left corners and the bottom-right corners, and all the ground layer 104 in a capacitor structure 100 may have cutout corner portion at the bottom-left corners and the top-right corners.

[0087] FIGS. 4A-4B are discussed in relation to FIGS. 3A-3H. FIGS. 4A-4B illustrate example current paths 402 and 404 in the capacitor structure 100 according to an embodiment of the present disclosure. For ease of illustration, FIG. 4A only shows the power delivery layers 102a and 102b without the electrically insulating layers 106a, 106b, and 106c and the ground layers 104a and 104b. Similarly, FIG. 4B illustrates the ground layer 104a and 104b without the electrically insulating layers 106a, 106b, and 106c and the power delivery layers 102a and 102b.

[0088] As shown in FIG. 4 A, the current path 402 may traverse from the power pad 301a to the power delivery layer 102a via the top-left corner portion 332 of the power delivery layer 102a in electrical contact with the power pad 301a. The current path 402 may further traverse to the power delivery layer 102b via the bottom-right corner portion 334 of the power delivery layer 102a that is in electrical contact with the bottom-right corner portion 336 of the power delivery layer102b, and so on. As can be seen, the current path 402 may traverse across the capacitor structure 100 in a zig-zag pattern following the corner portions of the power delivery layer 102 that are in electrical contact with each other. In some instances, the power pad 301a may be connected to a positive supply voltage Vdd, and thus the power delivery layers 102 may be positive electrically conductive layers and the current path 402 may be a positive current path. In other instances, the power pad 301a is connected to a negative supply voltage Vss, and thus the power delivery layers 102 may be negative electrically conductive layers and the current path 402 may be a negative current path.

[0089] As shown in FIG. 4B, the current path 404 may traverse from the ground pad 301b to the ground layer 104a via the bottom-left corner portion 342 of ground layer 104a in electrical contact with the ground pad 301b. The current path 402 may further traverse to the ground layer 104b via the top-right corner portion 344 of the ground layer 104a that is in electrical contact with the top-right corner portion 346 of the ground layer 104b, and so on. As can be seen, the current path 404 may traverse across the capacitor structure 100 in a zig-zag pattern following the corner portions of the ground layer 104 that are in electrical contact with each other. The ground pad 301b may be connected to ground Vgnd.

[0090] FIG. 5 illustrates a side cross-sectional view of another multilayered M-2DMat-M capacitor structure 500 according to an embodiment of the present disclosure. The side cross- sectional view is in a y-z plane. The capacitor structure 500 may be substantially similar to the capacitor structure 100. However, the electrically insulating layers 106 interleaving with the electrically conductive layers 101 may include multiple layers. As shown, an electrically insulating layer 106 may include two buffer layers 502 and a core electrically insulating layer 504 between the buffer layers 502. The core electrically insulating layer may include 2D crystalline semiconductor material (e.g., La, Gd, Gd2Os, Bi2SeOs, LaOBr, LaOCl, BiOCl, CaFU, SrHBr, and / or SrL). In one embodiment, the buffer layers 502 may also include 2D crystalline semiconductor material but different than the 2D crystalline semiconductor material in the core electrically insulating layer 504. In some instances, the 2D crystalline semiconductor material in the buffer layers 502 may include at least one of hexagonal boron nitride (hBN) or Bi2SeO_5. In another embodiment, the core electrically insulating layer 504 may include amorphous material (e.g., HfO2) and the buffer layers 502 may include 2D crystalline semiconductor material.

[0091] Generally, different combinations of 2D crystalline materials or different combinations of 2D crystalline material and amorphous material can be used to achieve a desired capacitance for the capacitor structure 500 and / or a desired thickness for the electrically insulating layer 106. For instance, using different combinations of 2D crystalline materials or different combinations of 2D crystalline material and amorphous material can provide thinner electrically insulating layers 106. In an embodiment, each of the buffer layers 502 may have a thickness 506 of about 2.5 and 3.5 nm and the core electrically insulating layer 504 may have a thickness 508 of about 2.5 and 3.5 nm. In a certain example, the buffer layers 502 may include Gd^Os may each have a thickness 506 of about 3 nm and above, and the core electrically insulating layer 504 may include hafnium oxides (Hf'Ch) with a thickness 508 of about 3 nm, resulting in an individual electrically insulating layer 106 having a total thickness of about 9 nm. In a certain example, the buffer layers 502 may include crystalline barium nitride (BN) and may each have a thickness 506 of about 1.2 nm and the core electrically insulating layer 504 may include Gd2O5 with a thickness 508 of about 1.2 nm, resulting in an individual electrically insulating layer 106 having a total thickness of about 3.6 nm.

[0092] FIG. 6 illustrates a side cross-sectional view of an IC structure 600 including a capacitor structure 100 for backside power delivery according to an embodiment of the present disclosure. The side cross-sectional view is in a y-z plane. As shown in FIG. 6, the IC structure 600 may include frontside signal metallization 602, backside power delivery metallization 606, and a transistor layer 604 between the frontside signal metallization 602 and the backside signal metallization 606. The transistor layer 604 may include transistors for logics and / or switches. The frontside signal metallization 602 may include conductive vias and conductive lines for routing signals (e.g., input / output signals, clock signals, etc.) between the transistors in the transistor layer 604 and logic blocks and / or memory blocks (e.g., on a surface of the frontside signal metallization 602). The backside power delivery metallization 606 may include conductive vias and conductive lines for supplying power and ground from the backside of the IC structure to the transistors in the transistor layer 604. The capacitor structure 100 discussed herein may be integrated as part of the backside power delivery metallization 606. The capacitor structure 100 may improve power integrity (e.g., providing better IR drop handling, stabilize voltage rails, suppress power noise, etc.) for the power and / or ground signals that are supplied to the transistor layer 604. The capacitor structure 100 may also assist in transferring heat out of the IC structure 600. For instance, the thinner electrically insulating layers 106 can improve the total capacitance (e.g., provide a highertotal capacitance). As such, the M-2DM-M capacitor structure 100 may achieve 1 pF total capacitance with fewer layers. With fewer layers, the capacitor structure 100 may have a thinner configuration, thereby improving the conductivity of the total package. While FIG. 6 is illustrated with the capacitor structure 100 as part of the backside power delivery metallization 606, in some embodiments, the IC structure 600 may include the multilayered M-2DMat-M capacitor structure 500 of FIG. 5.

[0093] FIG. 7 illustrates a side cross-sectional view of an electronics package 700 including a capacitor structure 100 according to an embodiment of the present disclosure. The side cross- sectional view is in a y-z plane. As shown in FIG. 7, the electronics package 700 includes a die of an electrical chip 708 (e.g., an unpackaged semiconductor chip including the integrated circuity), a PCB 702 having an opening 710, and the capacitor structure 100 positioned within the opening 710. The electrical chip 708 may be an active device that generates heat. The electrical chip 708 may be located on top of the PCB 702 and electrically coupled to the PCB 702 and the capacitor structure 100 via solder bonds 712. In some instances, the electrical chip 708 may be a logic device. In some instances, the electrical chip 708 may be a high-bandwidth memory (HBM) device. In some instances, the electrical chip 708 may include an HBM device and a logic device.

[0094] To facilitate cooling, the electronics package 700 may include a backside heat sink 714. The backside heat sink 714 may be positioned within the opening 710 below the capacitor structure 100 and in contact with a bottom side surface of the capacitor structure 100. Thus, the continuous power delivery layers 102 and the continuous ground layers 104 in the capacitor structure 100 may provide thermal conduction paths to transfer heat from the die of the electrical chip 708 to the backside heat sink 714. The backside heat sink 714 may be made of any suitable thermally conductive materials (e.g., aluminum and / or copper). The backside heat sink 714 may have a base 715 that is in direct contact with the bottom side surface of the capacitor structure 100 and slots or fins 716 to provide further cooling channels (e.g., filled with air or coolants) to improve heat dissipation. In an embodiment, the electronics package 700 may provide dual cooling (e.g., frontside and backside cooling) by including an additional frontside heat sink 704. The frontside heat sink 704 may be positioned above the die of the electrical chip 708 and in contact with a top side surface of the die of the electrical chip 708 to transfer heat from the die of the electrical chip 708 to the frontside heat sink 704. The frontside heat sink 704 may be substantially similar to thebackside heat sink 714. Generally, the backside heat sink 714 and the frontside heat sink 704 may have any suitable structures to facilitate cooling of the electronics package 700.

[0095] FIG. 8 is a flowchart of an example method 800 of providing a multilayered M-2DMat-M capacitor structure (e.g., the capacitor structures 100 and / or 500) according to an embodiment of the present disclosure. The method 800 may use substantially similar mechanisms as discussed above with reference to FIGS. 2, 3A-3H, and 5-7. As illustrated, FIG. 8 includes a number of enumerated operations, but embodiments of the operations in FIG. 8 may include additional operations before, after, and in between the enumerated operations. In some embodiments, one or more of the enumerated operations may be omitted or performed in a different order.

[0096] At operation 802, the method 800 includes providing a ground layer (e.g., the ground layers 104). At operation 804, the method 800 includes providing an electrically insulating layer (e.g., the electrically insulating layers 106) including 2D crystalline semiconductor material. At operation 806, the method 800 includes stacking the electrically insulating layer on a surface of the ground layer to provide a stacked structure (e.g., the stacked structures 306, 308, 310, 312, 314, and / or 316). At operation 808, the method 800 includes providing a power delivery layer (e.g., the power delivery layers 102). At operation 810, the method 800 includes stacking the power delivery layer on a surface of the stacked structure such that the power delivery layer is adjacent to the electrically insulating layer.

[0097] In an embodiment, the power delivery layer includes a first comer portion and a second corner portion diagonally opposite the first corner portion along a first axis (e.g., the axis 202). The power delivery layer further includes a first corner cutout portion and a second corner cutout portion diagonally opposite the first corner cutout portion along a second axis (e.g., the axis 202) different than the first axis. The ground layer includes a third corner portion and a fourth corner portion diagonally opposite the third corner portion along the second axis. The ground layer further includes a third corner cutout portion and a fourth corner cutout portion diagonally opposite the third corner cutout portion along the first axis. The electrically insulating layer includes a fifth corner cutout portion and a sixth corner cutout portion adjacent to the fifth corner cutout portion.

[0098] In an example, the power delivery layer may correspond to the power delivery layer 102a, the ground layer may correspond to the ground layer 104a, and the electrically insulating layer may correspond to the electrically insulating layer 106b as discussed above with reference to FIGS. 3C-3D. For instance, the first cutout corner portion, the second cutout corner portion, the first corner portion, and the second corner portion of the power delivery layer may be located respectively at the botom-left, top-right, top-left, and bottom-right corners of the power delivery layer. Further, the third cutout corner portion, the fourth cutout corner portion, the fifth corner portion, and the sixth corner portion of the ground layer may be located respectively at the top-left, bottom-right, bottomleft, and top-right, and corners of the ground layer. Further, the fifth cutout corner portion and the sixth cutout corner portion of the electrically insulating layer may be located respectively at the topleft and top-right corners of the electrically insulating layer.

[0099] In another example, the power delivery layer may correspond to the power delivery layer 102b, the ground layer may correspond to the ground layer 104b, and the electrically insulating layer may correspond to the electrically insulating layer 106c as discussed above with reference to FIGS. 3G-3H. The first cutout corner portion, the second cutout corner portion, the first corner portion, and the second corner portion of the power delivery layer may be at the locations discussed in the previous example. Similarly, the third cutout corner portion, the fourth cutout corner portion, the fifth corner portion, and the sixth corner portion of the ground layer may be at the locations discussed in the previous example. However, the fifth cutout corner portion and the sixth cutout corner portion of the electrically insulating layer may be located respectively at the bottom-left and bottom-right corners of the electrically insulating layer.

[0100] In an embodiment, the stacking the electrically insulating layer on the surface of the ground layer at operation 806 includes aligning the fifth corner cutout portion of the electrically insulating layer to expose a surface of the third corner portion of the ground layer. The stacking the power delivery layer on the surface of the stacked structure at operation 810 includes aligning the fifth corner cutout portion of the electrically insulating layer to expose a surface of the first corner portion of the power delivery layer. The stacking the power delivery layer on the surface of the stacked structure at operation 810 further includes aligning the first corner cutout portion of the power delivery layer to the sixth corner cutout portion of the of the electrically insulating layer so that the exposed surface of the third corner portion of the ground layer remains exposed.

[0101] In an embodiment, the method 800 further includes providing a power pad (e.g., the power pad 301a) and a ground pad (e.g., the ground pad 301b) at adjacent corners on a substrate plane (e.g., the substrate 110). The method 800 further includes providing a second electrically insulating layer comprising second 2D crystalline semiconductor material. The second electrically 1insulating layer (e.g., the electrically insulating layer 106a shown in FIGS. 3A-3B) includes a seventh corner cutout portion and an eighth corner cutout portion adjacent to the seventh corner cutout portion. The method 800 further includes stacking the second electrically insulating layer on a surface of the substrate plane to provide a second stacked structure (e.g., the stacked structure 302 shown in FIG. 3 A) by aligning the seventh corner cutout portion to expose a surface of the power pad and aligning the eighth corner cutout portion to expose a surface of the ground pad. In an embodiment, the method 800 further includes stacking the ground layer (e.g., the ground layer 104a) on a surface of the second stacked structure such that the fourth corner portion (e.g., the corner portion 342) of the ground layer is in electrical contact with the exposed surface of the ground pad to provide a third stacked structure (e.g., the stacked structure 304). The stacking the electrically insulating layer (e.g., the electrically insulating layer 106b) on the surface of the ground layer at operation 806 further includes stacking the electrically insulating layer on a surface of the third stacked structure. Further, an electrically insulating material (e.g., the electrically insulating material 108) is disposed along a sidewall (e.g., the sidewall 205) of the third corner cutout portion of the ground layer adjacent to the power pad to prevent the ground layer from being in electrical contact with the power pad. In an embodiment, the stacking the power delivery layer on the surface of the stacked structure at operation 810 further includes aligning the exposed surface of the first corner portion of the power delivery layer to be in electrical contact with the exposed surface of the power pad.

[0102] FIG. 9 is a schematic diagram of a computer apparatus 900 (e.g., part of the computer system 130). The computer apparatus 900 is suitable for implementing the disclosed embodiments as described herein. The computer apparatus 900 comprises ingress ports / ingress means 910 (a.k.a., upstream ports) and receiver units (Rx)Zreceiving means 920 for receiving data; a processor, logic unit, or central processing unit (CPU)Zprocessing means 930 to process the data; transmitter units (Tx)Ztransmitting means 940 and egress portsZegress means 950 (a.k.a., downstream ports) for transmitting the data; and a memoryZmemory means 960 for storing the data. The computer apparatus 900 may also comprise optical-to-electrical (OE) components and electrical -to-optical (EO) components coupled to the ingress portsZingress means 910, the receiver unitsZreceiving means 920, the transmitter unitsZtransmitting means 940, and the egress portsZegress means 950 for egress or ingress of optical or electrical signals.

[0103] The processor / processing means 930 is implemented by hardware and software. The processor / processing means 930 may be implemented as one or more CPU chips, cores (e.g., as a multi-core processor), field-programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), and digital signal processors (DSPs). The processor / processing means 930 is in communication with the ingress ports / ingress means 910, receiver units / receiving means 920, transmitter units / transmitting means 940, egress ports / egress means 950, and memory / memory means 960.

[0104] The computer apparatus 900 may also include input and / or output (I / O) devices or I / O means 980 for communicating data to and from a user. The I / O devices or I / O means 980 may include output devices such as a display for displaying video data, speakers for outputting audio data, etc. The I / O devices or I / O means 980 may also include input devices, such as a keyboard, mouse, trackball, etc., and / or corresponding interfaces for interacting with such output devices.

[0105] The memory / memory means 960 comprises one or more disks, tape drives, and solid- state drives and may be used as an over-flow data storage device, to store programs when such programs are selected for execution, and to store instructions and data that are read during program execution. The memory / memory means 960 may be volatile and / or non-volatile and may be readonly memory (ROM), random access memory (RAM), ternary content-addressable memory (TCAM), and / or static random-access memory (SRAM).

[0106] In an embodiment, one or more of the components (e.g., the ingress ports / ingress means 910, the receiver units / receiving means 920, the processor / processing means 930, the transmitter units / transmitting means 940, the egress ports / egress means 950, and memory / memory means 960) of the network apparatus 900 may include an IC die packaged within the component, where the IC die may include one or more structures similar to the capacitor structures 100 and / or 500 discussed herein. In an embodiment, one or more of the components (e.g., the ingress ports / ingress means 910, the receiver units / receiving means 920, the processor / processing means 930, the transmitter units / transmitting means 940, the egress ports / egress means 950, and memory / memory means 960) of the network apparatus 900 may include an electronics package packaged within the component, where the electronics package may include one or more structures similar to the capacitor structures 100 and / or 500 and / or configured similar to the electronics package 700 discussed herein.

[0107] It should also be understood that the steps of the exemplary methods set forth herein are not necessarily required to be performed in the order described, and the order of the steps of such methods should be understood to be merely exemplary. Likewise, additional steps may be included in such methods, and certain steps may be omitted or combined, in methods consistent with various embodiments of the present disclosure.

[0108] While several embodiments have been provided in the present disclosure, it should be understood that the disclosed systems and methods might be embodied in many other specific forms without departing from the spirit or scope of the present disclosure. The present examples are to be considered as illustrative and not restrictive, and the intention is not to be limited to the details given herein. For example, the various elements or components may be combined or integrated in another system or certain features may be omitted, or not implemented.

[0109] In addition, techniques, systems, subsystems, and methods described and illustrated in the various embodiments as discrete or separate may be combined or integrated with other systems, modules, techniques, or methods without departing from the scope of the present disclosure. Other items shown or discussed as coupled or directly coupled or communicating with each other may be indirectly coupled or communicating through some interface, device, or intermediate component whether electrically, mechanically, or otherwise. Other examples of changes, substitutions, and alterations are ascertainable by one skilled in the art and could be made without departing from the spirit and scope disclosed herein.

Claims

CLAIMSWhat is claimed is:

1. An integrated circuit (IC) structure comprising: a multilayered capacitor structure comprising a plurality of electrically conductive layers spaced apart from each other by respective ones of a plurality of electrically insulating layers, wherein: the plurality of electrically conductive layers comprise alternating power delivery layers and ground layers, and the plurality of electrically insulating layers comprise two-dimensional (2D) crystalline semiconductor material.

2. The IC structure of claim 1, wherein the 2D crystalline semiconductor material in an individual layer of the plurality of electrically insulating layers has a thickness between about 1 and 100 nanometers.

3. The IC structure of any of claims 1-2, wherein the 2D crystalline semiconductor material has a dielectric constant greater than 5 at a frequency between about 45 and 55 kilohertz (kHz) and a thickness between about 1 and 50 nanometers.

4. The IC structure of any of claims 1-3, wherein the 2D crystalline semiconductor material has a breakdown field strength greater than 6 megavolts per centimeter (MV / cm).

5. The IC structure of any of claims 1-4, wherein the 2D crystalline semiconductor material comprises at least one of gadolinium (Gd), lanthanum (La), gadolinium pentoxide (Gd20s), lanthanum oxybromide (LaOBr), lanthanum oxychloride (LaOCl), bismuth chloride (BiOCl), calcium hydrogen iodine (CaHI), strontium hydrogen bromide (SrHBr), or strontium Iodide (Srh).

6. The IC structure of any of claims 1-5, wherein an individual layer of the plurality of electrically insulating layers comprises: two buffer layers comprising second 2D crystalline semiconductor material different than the 2D crystalline semiconductor material; anda core electrically insulating layer comprising the 2D crystalline semiconductor material between the buffer layers.

7. The IC structure of claim 6, wherein the second 2D crystalline semiconductor material in the buffer layers comprises crystalline barium nitride (BN).

8. The IC structure of any of claims 1-5, wherein an individual layer of the plurality of electrically insulating layers comprises: two buffer layers comprising the 2D crystalline semiconductor material; and a core electrically insulating layer comprising amorphous material between the buffer layers.

9. The IC structure of claim 8, wherein the amorphous material in the core electrically insulating layer comprises hafnium oxide (HfCh).

10. The IC structure of any of claims 1-9, wherein the multilayered capacitor structure further comprises: a first electrically insulating material disposed along sidewalls of an individual layer of the electrically conductive layers, and a second electrically insulating material disposed along sidewalls of an individual layer of the ground layers.

11. The IC structure of claim 10, wherein the first electrically insulating material and the second electrically insulating material comprise at least one of hafnium oxide (HfO ) or aluminum oxide (AI2O3).

12. The IC structure of claim 1, wherein the power delivery layers are configured to be coupled to one of a positive power voltage or a negative power voltage.

13. The IC structure of claim 12, wherein:at least one of the power delivery layers that are configured to be coupled to the positive power voltage are in electrical contact with each other or the power delivery layers that are configured to be couple to the negative power voltage are in electrical contact with each other, and the ground layers are in electrical contact with each other and electrically insulated from the power delivery layers.

14. The IC structure of any of claims 1-13, wherein: a first power delivery layer of the power delivery layers is between a second power delivery layer of the power delivery layers and a third power delivery layer of the power delivery layers, the first power delivery layer comprises a first corner portion and a second, diagonally opposite corner portion respectively in electrical contact with a third corner portion of the second power delivery layer and a fourth corner portion of the third power delivery layer, a first ground layer of the ground layers is between a second ground layer of the ground layers and a third ground layer of the ground layers, and the first ground layer comprises a fifth corner portion and a sixth, diagonally opposite corner portion respectively in electrical contact with a seventh corner portion of the second ground layer and an eighth corner portion of the third ground layer.

15. The IC structure of any of claims 1-14, wherein the first ground layer is between the first and second power delivery layers or the first and third power delivery layers and comprises a cutout corner portion aligned respectively to the first comer portion or the second, diagonally opposite corner portion of the first power delivery layer.

16. The IC structure of claim 14, wherein the first power delivery layer is between the first and second ground layers or the first and third ground layers and comprises a cutout corner portion aligned respectively to the fifth corner portion or the sixth, diagonally opposite corner portion of the first ground layer.

17. The IC structure of any of claims 1-16, wherein an individual layer of the electrically insulating layers between a respective one of the power delivery layers and a respective one of the ground layers comprises:a first cutout corner portion aligned to a cutout corner portion of the respective power delivery layer, and a second cutout corner portion aligned to a cutout corner portion of the respective ground layer.

18. The IC structure of any of claims 1-17, wherein the multilayered capacitor structure is part of a power delivery network of the IC structure.

19. An electronics package, comprising: a die of an electrical chip; a printed circuit board having an opening; and a capacitor structure positioned within the opening, wherein: the capacitor structure comprises a plurality of electrically conductive layers spaced apart from each other by respective ones of a plurality of electrically insulating layers, the plurality of electrically conductive layers comprise alternating ground layers and one of positive electrically conductive layers or negative electrically conductive layers, and the plurality of electrically insulating layers comprise two-dimensional (2D) crystalline semiconductor material.

20. The electronics package of claim 19, further comprising a backside heat sink in contact with the capacitor structure.

21. The electronics package of any of claims 19-20, wherein the one of the positive electrically conductive layers or the negative electrically conductive layers of the capacitor structure are configured to respectively provide a positive electrical current path or a negative electrical current path for a supply voltage extending from the printed circuit board across the capacitor structure to the die of the electrical chip.

22. The electronics package of any of claims 19-21, wherein the ground layers of the capacitor structure are configured to provide an electrical current return path to ground extending from the printed circuit board across the capacitor structure to the die of the electrical chip.

23. The electronics package of any of claims 19-22, wherein the capacitor structure further comprises: a first electrically insulating material disposed along sidewalls of an individual layer of the one of the positive electrically conductive layers or the negative electrically conductive layers, and a second electrically insulating material disposed along sidewalls of an individual layer of the ground layers.

24. The electronics package of any of claims 19-23, wherein the 2D crystalline semiconductor material in an individual layer of the plurality of electrically insulating layers has a thickness between about 1 and 100 nanometers.

25. The electronics package of any of claims 19-24, wherein the 2D crystalline semiconductor material has a dielectric constant greater than 5 at a frequency between about 45 and 55 kilohertz (kHz) and a thickness between about 1 and 55 nanometers.

26. The electronics package of any of claims 19-25, wherein the 2D crystalline semiconductor material has a breakdown field strength greater than 6 megavolts per centimeter (MV / cm).

27. The electronics package of any of claims 19-26, wherein the 2D crystalline semiconductor material comprises at least one of gadolinium (Gd), lanthanum (La), gadolinium pentoxide (Gd20s), lanthanum oxybromide (LaOBr), lanthanum oxychloride (LaOCl), bismuth chloride (BiOCl), calcium hydrogen iodine (CaHI), strontium hydrogen bromide (SrHBr), or strontium Iodide (Srh).

28. The electronics package of any of claims 19-27, further comprising a frontside heat sink in contact with an upper surface of the die of the electrical chip.

29. A method of forming a capacitor structure, the method comprising: providing a ground layer; providing an electrically insulating layer comprising two-dimensional (2D) crystalline semiconductor material;stacking the electrically insulating layer on a surface of the ground layer to provide a stacked structure; providing a power delivery layer; and stacking the power delivery layer on a surface of the stacked structure such that the electrically insulating layer is between the ground layer and the power delivery layer.

30. The method of claim 29, wherein: the power delivery layer comprises: a first corner portion and a second corner portion diagonally opposite the first corner portion along a first axis, and a first cutout corner portion and a second cutout corner portion diagonally opposite the first cutout corner portion along a second axis different than the first axis, the ground layer comprises: a third corner portion and a fourth corner portion diagonally opposite the third corner portion along the second axis, and a third cutout corner portion and a fourth cutout corner portion diagonally opposite the third cutout corner portion along the first axis, and the electrically insulating layer comprises a fifth cutout corner portion and a sixth cutout corner portion adjacent to the fifth cutout corner portion.

31. The method of claim 30, wherein: the stacking the electrically insulating layer on the surface of the ground layer comprises aligning the fifth cutout corner portion of the electrically insulating layer to expose a surface of the third corner portion of the ground layer, the stacking the power delivery layer on the surface of the stacked structure comprises: aligning the fifth cutout corner portion of the electrically insulating layer to expose a surface of the first corner portion of the power delivery layer; and aligning the first cutout corner portion of the power delivery layer to the sixth cutout corner portion of the of the electrically insulating layer so that the exposed surface of the third corner portion of the ground layer remains exposed.

32. The method of claim 31 , further comprising: providing a power pad and a ground pad at adjacent corners on a substrate plane; providing a second electrically insulating layer comprising second 2D crystalline semiconductor material, wherein the second electrically insulating layer comprises a seventh cutout corner portion and an eighth cutout corner portion adjacent to the seventh cutout corner portion; and stacking the second electrically insulating layer over the substrate plane to provide a second stacked structure by aligning the seventh cutout comer portion to expose a surface of the power pad and aligning the eighth cutout corner portion to expose a surface of the ground pad.

33. The method of claim 32, further comprising: stacking the ground layer on a surface of the second stacked structure such that the fourth corner portion of the ground layer is in electrical contact with the exposed surface of the ground pad to provide a third stacked structure, wherein: the stacking the electrically insulating layer on the surface of the ground layer comprises stacking the electrically insulating layer on the third stacked structure, and an electrically insulating material is disposed along a sidewall of the third cutout corner portion of the ground layer adjacent to the power pad to prevent the ground layer from being in electrical contact with the power pad.

34. The method of claim 33, wherein the stacking the power delivery layer on the surface of the stacked structure comprises aligning the exposed surface of the first corner portion of the power delivery layer to be in electrical contact with the exposed surface of the power pad.

35. The method of any of claims 29-34, wherein the 2D crystalline semiconductor material in the electrically insulating layer has a thickness between about 1 and 100 nanometers.

36. The method of any of claims 29-35, wherein the 2D crystalline semiconductor material has a dielectric constant greater than 5 at a frequency between about 45 and 55 kilohertz (kHz) and a thickness between about 1 and 50 nanometers.

37. The method of any of claims 29-36, wherein the 2D crystalline semiconductor material has a breakdown field strength greater than 6 megavolts per centimeter (MV / cm).

38. The method of any of claims 29-37, wherein the 2D crystalline semiconductor material comprises at least one of gadolinium (Gd), lanthanum (La), gadolinium pentoxide (Gd20s), bismuth lanthanum oxybromide (LaOBr), lanthanum oxychloride (LaOCl), bismuth chloride (BiOCl), calcium hydrogen iodine (CaHI), strontium hydrogen bromide (SrHBr), or strontium Iodide (SrE).

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