Bandwidth allocation method, apparatus, device and system, and medium and program product

Abstract

The present application relates to the technical field of computers. Disclosed are a bandwidth allocation method, apparatus, device and system, and a medium and a program product. The method comprises: controlling a general-purpose input / output interface of a first interface expansion device to output a high level for a preset duration, wherein a first presence signal pin of each slot is connected to the general-purpose input / output interface of the first interface expansion device; during the general-purpose input / output interface of the first interface expansion device outputting the high level for the preset duration, reading the level of a general-purpose input / output interface of a second interface expansion device corresponding to a root port, wherein a second presence signal pin of each slot is connected to the general-purpose input / output interface of the second interface expansion device, and the general-purpose input / output interface of the second interface expansion device connected to the second presence signal pin of the slot is related to the bandwidth of the slot; and determining, on the basis of the read level, the bandwidth of a slot connected to the root port, and performing bandwidth allocation accordingly. The method can improve the bandwidth allocation efficiency and accuracy.

Description

A bandwidth allocation method, apparatus, device, system, medium, and program product

[0001] Cross-references to related applications

[0002] This application claims priority to Chinese Patent Application No. 202411481633.9, filed on October 23, 2024, entitled "A Bandwidth Allocation Method, Apparatus, Device, System, Medium and Program Product", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of computer technology, and in particular to a bandwidth allocation method, apparatus, device, system, medium, and computer program product. Background Technology

[0004] PCIe (Peripheral Component Interconnect Express) is a high-speed serial computer expansion card standard, primarily used to connect the central processing unit (CPU) and various expansion cards. PCIe bandwidth is closely related to its version and the number of lanes. For example, a PCIe x1 slot has a theoretical maximum bandwidth of 1GB / s, while a PCIe x4 slot has a theoretical maximum bandwidth of 4GB / s. Server motherboards typically use PCIe x8 and PCIe x16 slots to facilitate the installation of different types of expansion cards. To reduce PCIe resource waste, automatic identification and allocation of PCIe bandwidth is necessary. However, current methods for PCIe bandwidth identification and allocation suffer from low efficiency and accuracy. Summary of the Invention

[0005] The purpose of this application is to provide a bandwidth allocation method, apparatus, device, system, medium, and computer program product that can improve bandwidth allocation efficiency and accuracy.

[0006] To address the aforementioned technical problems, this application provides a bandwidth allocation method, comprising:

[0007] The general-purpose input / output interface of the first interface expansion device outputs a high level for a preset duration; the first in-situ signal pin of each slot is connected to the general-purpose input / output interface of the first interface expansion device.

[0008] During the high-level period of a preset duration of the general-purpose input / output interface of the first interface expansion device, the level of the general-purpose input / output interface of the second interface expansion device corresponding to the root port is read; the second in-situ signal pin of each slot is connected to the general-purpose input / output interface of the second interface expansion device, and the general-purpose input / output interface of the second interface expansion device connected to the second in-situ signal pin of the slot is related to the bandwidth of the slot;

[0009] The bandwidth of the slot to which the root port is connected is identified based on the level of the general input / output interface of the second interface extension device, and the bandwidth of the root port is allocated according to the bandwidth of the slot to which the root port is connected.

[0010] In some embodiments, the second presence signal pins of different slots connected to the root port are all connected to the general-purpose input / output interface of the same second interface expansion device corresponding to the root port, and the general-purpose input / output interfaces connected to the second presence signal pins of each slot connected to the same root port are different.

[0011] In some embodiments, the root port includes sixteen channels, and the second in-situ signal pins of the sixteen channels connected to different slots are all connected to the general-purpose input / output interface of the same second interface expansion device corresponding to the root port.

[0012] In some embodiments, the second interface expansion device includes sixteen general purpose input / output interfaces, and the general purpose input / output interfaces of the second interface expansion device correspond one-to-one with the channels of the root port.

[0013] In some embodiments, the second in-situ signal pin of the slot is connected to the general-purpose input / output interface corresponding to the channel with the largest sequence number among the channels used by the slot.

[0014] In some embodiments, identifying the bandwidth of the slot accessed by the root port based on the level of the general-purpose input / output interface of the second interface extension device includes:

[0015] Based on the level of the general input / output interface of the second interface expansion device corresponding to the root port, the bandwidth of the slot connected to the root port is identified by querying the level truth table; the level truth table includes the correspondence between the level of the general input / output interface of the second interface expansion device and the bandwidth of the slot.

[0016] In some embodiments, the first interface expansion device includes a sixteen-channel general purpose input / output interface.

[0017] In some embodiments, the level truth table also includes the correspondence between the root port channels and the general-purpose input / output interfaces of the second interface extension device.

[0018] In some embodiments, controlling the general-purpose input / output interface of the first interface expansion device to output a high level for a preset duration includes:

[0019] The control panel of the first interface expansion device outputs high-level signals of a preset duration sequentially through each of its general-purpose input / output interfaces.

[0020] In some embodiments, before the general-purpose input / output interface of the first interface expansion device outputs a high level for a preset duration, the method further includes:

[0021] Set the first interface expansion device to output mode, and set each general-purpose input / output interface of the first interface expansion device to output a low level.

[0022] In some embodiments, it also includes:

[0023] Set the second interface expansion device to input mode.

[0024] In some embodiments, the second in-situ signal pin of each slot is also connected to hot-plug monitoring logic circuitry.

[0025] In some embodiments, it also includes:

[0026] If, during the period when the general input / output interface of the first interface expansion device outputs a high level, the second in-situ signal pin of the slot to which the corresponding first in-situ signal pin belongs remains at a low level, an error is reported.

[0027] In some embodiments, it also includes:

[0028] If, during the period when the general-purpose input / output interface of the first interface expansion device outputs a high level, the second in-situ signal pin of the slot to which the corresponding first in-situ signal pin belongs remains at a low level, the general-purpose input / output interface of the first interface expansion device will no longer output a high level.

[0029] In some embodiments, controlling the general-purpose input / output interface of the first interface expansion device to output a high level for a preset duration includes:

[0030] The system management bus controls the general input / output interface of the first interface expansion device to output a high level for a preset duration.

[0031] In some embodiments, reading the level of the general-purpose input / output interface of the second interface extension device corresponding to the root port includes:

[0032] The system management bus reads the level of the general input / output interface of the second interface expansion device.

[0033] To address the aforementioned technical problems, this application also provides a bandwidth allocation device, comprising:

[0034] The control module is used to control the general-purpose input / output interface of the first interface expansion device to output a high level for a preset duration; the first in-situ signal pin of each slot is connected to the general-purpose input / output interface of the first interface expansion device.

[0035] The reading module is used to read the level of the general input / output interface of the second interface expansion device corresponding to the root port during a high-level period of a preset duration output by the general input / output interface of the first interface expansion device; the second in-situ signal pin of each slot is connected to the general input / output interface of the second interface expansion device, and the general input / output interface of the second interface expansion device connected to the second in-situ signal pin of the slot is related to the bandwidth of the slot;

[0036] The allocation module is used to identify the bandwidth of the slot to which the root port is connected based on the level of the general input / output interface of the second interface extension device, and to allocate bandwidth to the root port according to the bandwidth of the slot to which the root port is connected.

[0037] To address the aforementioned technical problems, this application also provides a bandwidth allocation device, comprising:

[0038] Memory, used to store computer programs;

[0039] The processor is used to implement the bandwidth allocation method described above when executing computer programs.

[0040] To address the aforementioned technical problems, this application also provides a computer program product, including a computer program / instructions, wherein the computer program / instructions, when executed by a processor, implement the bandwidth allocation method described above.

[0041] To address the aforementioned technical problems, this application also provides a computer non-volatile readable storage medium storing a computer program, which, when executed by a processor, implements the steps of the bandwidth allocation method described above.

[0042] To address the aforementioned technical problems, this application also provides a bandwidth allocation system, comprising:

[0043] Processor, first interface expansion device, second interface expansion device;

[0044] The processor controls the general-purpose input / output interface of the first interface expansion device to output a high level for a preset duration; the first presence signal pin of each slot is connected to the general-purpose input / output interface of the first interface expansion device; during the preset duration of the high level output by the general-purpose input / output interface of the first interface expansion device, the processor reads the level of the general-purpose input / output interface of the second interface expansion device corresponding to the root port; the second presence signal pin of each slot is connected to the general-purpose input / output interface of the second interface expansion device, and the general-purpose input / output interface of the second interface expansion device connected to the second presence signal pin of the slot is related to the bandwidth of the slot; the processor identifies the bandwidth of the slot connected to the root port based on the level of the general-purpose input / output interface of the second interface expansion device, and allocates bandwidth to the root port based on the bandwidth of the slot connected to the root port.

[0045] The bandwidth allocation method provided in this application includes: controlling the general-purpose input / output interface of a first interface expansion device to output a high level for a preset duration; connecting the first presence signal pin of each slot to the general-purpose input / output interface of the first interface expansion device; reading the level of the general-purpose input / output interface of the second interface expansion device corresponding to the root port during the period when the general-purpose input / output interface of the first interface expansion device outputs a high level for a preset duration; connecting the second presence signal pin of each slot to the general-purpose input / output interface of the second interface expansion device, and the general-purpose input / output interface of the second interface expansion device connected to the second presence signal pin of the slot is related to the bandwidth of the slot; identifying the bandwidth of the slot connected to the root port according to the level of the general-purpose input / output interface of the second interface expansion device, and allocating bandwidth to the root port according to the bandwidth of the slot connected to the root port.

[0046] As can be seen, in the bandwidth allocation method provided in this application, the first presence signal pin of the slot is not directly grounded, but connected to the general-purpose input / output interface of the first interface expansion device. The second presence signal pin of the slot is connected to the general-purpose input / output interface of the second interface expansion device. By controlling the output of a high level from the general-purpose input / output interface of the first interface expansion device, the level of the first presence signal pin connected to the general-purpose input / output interface of the first interface expansion device can be pulled high. By reading the level of the general-purpose input / output interface of the second interface expansion device, the level of the second presence signal pin of the slot can be obtained. Based on the level of the second presence signal pin of the slot, the bandwidth of the slot connected to the root port can be identified, and bandwidth allocation can be performed accordingly for the root port. With a single firmware development, a standard PCIe bandwidth resource adaptive allocation function module can be formed. In the server motherboard design, the first presence signal pin of the PCIe slot is connected to the general-purpose input / output interface of the first interface expansion device, and the second presence signal pin of the PCIe slot is connected to the general-purpose input / output interface of the second interface expansion device. By running the firmware, efficient and accurate allocation of PCIe bandwidth resources for various platforms, models, and configurations can be achieved. This method does not require the use of the southbridge's general-purpose input / output interface resources, nor does it require the involvement of the board management controller, and can achieve the allocation of arbitrary bandwidth combinations. Furthermore, this method can be used not only for PCIe root port bandwidth allocation on the CPU side, but also for PCIe root port bandwidth allocation on the PCIe switch side.

[0047] The bandwidth allocation device, equipment, system, media, and computer program products provided in this application all have the aforementioned technical effects. Attached Figure Description

[0048] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the prior art and embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0049] Figure 1 is a schematic flowchart of a bandwidth allocation method provided in an embodiment of this application;

[0050] Figure 2 is a schematic diagram of a PCIe device and a PCIe slot provided in an embodiment of this application;

[0051] Figure 3 is a schematic diagram of a first interface expansion device provided in an embodiment of this application;

[0052] Figure 4 is a schematic diagram of a second interface expansion device provided in an embodiment of this application;

[0053] Figure 5 is a circuit connection diagram provided in an embodiment of this application;

[0054] Figure 6 is a schematic diagram of a bandwidth allocation device provided in an embodiment of this application;

[0055] Figure 7 is a schematic diagram of a bandwidth allocation device provided in an embodiment of this application. Detailed Implementation

[0056] The core of this application is to provide a bandwidth allocation method, apparatus, device, system, medium, and computer program product that can improve bandwidth allocation efficiency and accuracy.

[0057] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0058] Please refer to Figure 1, which is a flowchart illustrating a bandwidth allocation method provided in an embodiment of this application. As shown in Figure 1, the method includes:

[0059] S101: Controls the general-purpose input / output interface of the first interface expansion device to output a high level for a preset duration; the first in-place signal pin of each slot is connected to the general-purpose input / output interface of the first interface expansion device.

[0060] S102: During the high-level period of a preset duration output by the general-purpose input / output interface of the first interface expansion device, read the level of the general-purpose input / output interface of the second interface expansion device corresponding to the root port; the second in-situ signal pin of each slot is connected to the general-purpose input / output interface of the second interface expansion device, and the general-purpose input / output interface of the second interface expansion device connected to the second in-situ signal pin of the slot is related to the bandwidth of the slot;

[0061] S103: Identify the bandwidth of the slot to which the root port is connected based on the level of the general input / output interface of the second interface extension device, and allocate bandwidth to the root port according to the bandwidth of the slot to which the root port is connected.

[0062] The first presence signal pin is the PRSNT1 signal pin, and the second presence signal pin is the PRSNT2 signal pin. On the PCIe device, pin 1 on pin A is the PRSNT1 signal pin; on the X1 bandwidth device, pin 17 on pin B is the PRSNT2 signal pin; on the X4 bandwidth device, pin 31 on pin B is the PRSNT2 signal pin; on the X8 bandwidth device, pin 48 on pin B is the PRSNT2 signal pin; and on the X16 bandwidth device, pin 81 on pin B is the PRSNT2 signal pin. The PRSNT1 and PRSNT2 signal pins on the PCIe device side are connected together. Referring to Figure 2, normally the PRSNT1 signal pin of the PCIe slot is grounded, and the PRSNT2 signal pin is pulled high by a pull-up resistor. After the PCIe device is inserted into the PCIe slot, the PRSNT2 signal pin of the PCIe slot is connected to the PRSNT1 signal pin, therefore the PRSNT2 signal pin is pulled low by ground, and the level of the PRSNT2 signal pin changes from high to low, indicating that the PCIe device has been inserted.

[0063] In this embodiment, the PRSNT1 signal pin of the PCIe slot (including the standard slots on the system motherboard and the standard slots on the Riser card) is not directly grounded, but is connected to the GPIO (General-purpose input / output) interface of the first interface expansion device. In some embodiments, the first interface expansion device includes sixteen general-purpose input / output interfaces. If the number of PCIe slots in the server exceeds 16, the number of first interface expansion devices is increased accordingly. For example, the first interface expansion device can be a PCA9555 device. The PCA9555 device includes 16 GPIO interfaces (P00~P07, P10~P17), denoted as GPIO1~GPIO16. As shown in Figure 3, the 16 GPIO interfaces of the PCA9555 device are each connected to the PRSNT1 signal pin of one slot. In Figure 3, Device1_PRSNT1# to Device16_PRSNT1# represent the PRSNT1 signal pins of different slots. If the number of PCIe slots in the server exceeds 16, the number of PCA9555 devices should be increased accordingly.

[0064] The PRSNT2 signal pin of the PCIe slot is connected to the GPIO pin of the second interface expansion device. The GPIO pin of the second interface expansion device to which the PRSNT2 signal pin of the PCIe slot is connected is related to the bandwidth of the PCIe slot, so that the bandwidth of the PCIe slot can be identified based on the level of the GPIO pin of the second interface expansion device to which the PRSNT2 signal pin of the PCIe slot is connected. In some embodiments, the second presence signal pin of each slot is also connected to a hot-plug monitoring logic circuit. Hot-plug control can be performed by monitoring the second presence signal pin of the slot. The circuit structure of the hot-plug monitoring logic circuit can be found in existing technology and will not be described in detail here.

[0065] In some embodiments, the second presence signal pins of different slots connected to the root port are all connected to the general-purpose input / output interface of the same second interface expansion device corresponding to the root port, and the general-purpose input / output interfaces connected to the second presence signal pins of each slot connected to the same root port are different.

[0066] In this embodiment, each root port corresponds to one second interface expansion device. The PRSNT2 signal pins of each PCIe slot connected to the same root port are all connected to the GPIO interface of the second interface expansion device corresponding to that root port. Furthermore, the GPIO interfaces connected to the PRSNT2 signal pins of each PCIe slot connected to the same root port are different.

[0067] The root port corresponds to a second interface expansion device. The second in-situ signal pins of different slots connected to the root port are all connected to the general input / output interface of the same second interface expansion device corresponding to the root port. This can reduce the number of second interface expansion devices.

[0068] In some embodiments, the root port includes sixteen channels, and the second in-situ signal pins of the sixteen channels connected to different slots are all connected to the general-purpose input / output interface of the same second interface expansion device corresponding to the root port.

[0069] The root port comprises 16 lanes, and slots use some or all of these 16 lanes. For example, if a slot is an x4 slot, it uses 4 lanes of the root port. If a slot is an x8 slot, it uses 8 lanes of the root port. It's clear that different slots do not use overlapping lanes. Additionally, it can be agreed that slots prioritize using lanes with smaller serial numbers. For example, if two slots connect to the same root port, one x4 and one x8, the x4 slot uses lanes 1 through 4, and the x8 slot uses lanes 5 through 12. Alternatively, the x8 slot uses lanes 1 through 8, and the x4 slot uses lanes 9 through 12.

[0070] In some embodiments, the second interface expansion device includes sixteen general purpose input / output interfaces, and the general purpose input / output interfaces of the second interface expansion device correspond one-to-one with the channels of the root port.

[0071] The 16 lanes of the root port correspond one-to-one with the general-purpose input / output interfaces of the corresponding second interface expansion device. The second interface expansion device can be a PCA9555 device. The serial number of the general-purpose input / output interface of the second interface expansion device can be the same as the serial number of the corresponding channel. The lane corresponding to GPIO1 is lane1, the lane corresponding to GPIO2 is lane2, and so on, with the lane corresponding to GPIO16 being lane16.

[0072] In some embodiments, the second in-situ signal pin of the slot is connected to the general-purpose input / output interface corresponding to the channel with the largest sequence number among the channels used by the slot.

[0073] For example, referring to Figure 4, the x8 slot uses lanes 1 to 8 (maximum number 8), and its PRSNT2 signal pin is connected to GPIO8. The x4 slot uses lanes 9 to 12 (maximum number 12), and its PRSNT2 signal pin is connected to GPIO12. The x4 slot uses lanes 13 to 16 (maximum number 16), and its PRSNT2 signal pin is connected to GPIO16.

[0074] The bandwidth allocation method provided in this embodiment can be used not only for PCIe root port bandwidth allocation on the CPU side, but also for PCIe root port bandwidth allocation on the PCIe switch side. The following description uses CPU-side PCIe root port bandwidth allocation as an example. The connection relationship between the CPU, the first interface expansion device, the second interface expansion device, etc., is shown in Figure 5. The CPU is connected to the Southbridge, and the Southbridge connects the first interface expansion device and the second interface expansion device. The PRSNT1 signal pin of the PCIe slot is connected to the general purpose input / output interface of the first interface expansion device, and the PRSNT2 signal pin of the PCIe slot is connected to the general purpose input / output interface of the second interface expansion device.

[0075] After the server powers on, before PCIe device enumeration, the BIOS (Basic Input Output System) controls each GPIO interface of the first interface expansion device to output a high level for a preset duration. For example, a high level of 10ms. During the preset duration of the high level output by the GPIO interface of the first interface expansion device, the BIOS reads the level of the GPIO interface of the second interface expansion device and records it in the bandwidth truth array corresponding to the root port. Then, based on the level of the GPIO interface of the second interface expansion device, it identifies the bandwidth of the slot connected to the root port and allocates bandwidth to the root port accordingly.

[0076] When the first interface expansion device and the second interface expansion device are PCA9555 devices, the BIOS can set the mode of the first interface expansion device and the second interface expansion device by sending control bytes.

[0077] Each PCA9555 device has a corresponding address. After the address is correctly acknowledged, the BIOS sends a control byte, which will be stored in the PCA9555 device's control register. Bits B0, B1, and B2 will define the operation and internal registers (input, output, polarity inversion, or configuration).

[0078] The PCA9555 device has four internal registers:

[0079] Input registers: Input port registers (registers 0 and 1) reflect the incoming logic level of the pin, regardless of whether the pin is defined as input or output by the configuration register. Input registers only function for read operations; writing to these registers has no effect. Before performing a read operation, a write transfer with a control byte is sent to indicate that the I2C device will access the input port register next.

[0080] Output Registers: The output port registers (registers 2 and 3) display the output logic configuration registers of the pins defined as outputs. The bit values ​​in this register have no effect on the pins defined as inputs. Reading the register from here reflects the value in the flip-flop that controls the output selection, not the actual pin value.

[0081] Polarity Inversion Register: The polarity inversion register (registers 4 and 5) allows the pin polarity to be reversed when the input is in the configuration register. Writing 1 to a bit in this register indicates that the pin is in the input polarity inversion state, while writing 0 has no effect.

[0082] Configuration Registers: The configuration registers (registers 6 and 7) configure the direction of the I / O pins. If the bit in this register is set to 1, the corresponding port pin is enabled as an input of the high-impedance output driver. If this register is cleared to 0, the corresponding port pin is enabled as an output.

[0083] In some embodiments, identifying the bandwidth of the slot accessed by the root port based on the level of the general-purpose input / output interface of the second interface extension device includes:

[0084] Based on the level of the general input / output interface of the second interface expansion device corresponding to the root port, the bandwidth of the slot connected to the root port is identified by querying the level truth table; the level truth table includes the correspondence between the level of the general input / output interface of the second interface expansion device and the bandwidth of the slot.

[0085] A pre-built truth table is constructed, which includes the correspondence between the levels of the general-purpose input / output interfaces of the second interface expansion device and the bandwidth of the slot. Based on reading the level of the GPIO interface of the second interface expansion device corresponding to the root port, the bandwidth of the PCIe slot connected to the root port can be identified by looking up the table, and then the corresponding bandwidth allocation can be performed on the root port accordingly.

[0086] For example, referring to Table 1, when GPIO16 is high, the true value of GPIO16 is 1; when other GPIOs are low, the true value of other GPIOs is 0; indicating that the PCIe slot connected to the PRSNT2 signal pin uses lanes 1 to 16, the bandwidth of the PCIe slot is x16, and the corresponding bandwidth is allocated to the root port accordingly.

[0087] When GPIO8 and GPIO16 are high, the true value of GPIO8 and GPIO16 is 1; when other GPIOs are low, the true value of other GPIOs is 0. This indicates that the PCIe slot connected to the PRSNT2 signal pin uses lanes 1 to 8, and the bandwidth of this PCIe slot is x8; the PCIe slot connected to the PRSNT2 signal pin uses lanes 9 to 16, and the bandwidth of this PCIe slot is x8. Based on this, the corresponding bandwidth is allocated to the root port.

[0088] When GPIO4, GPIO8, and GPIO16 are high, the truth value of GPIO4, GPIO8, and GPIO16 is 1; when other GPIOs are low, the truth value of other GPIOs is 0. This indicates that the PCIe slot connected to the PRSNT2 signal pin uses lanes 1 to 4, and the bandwidth of that PCIe slot is x4. It also indicates that the PCIe slot connected to the PRSNT2 signal pin uses lanes 5 to 8, and the bandwidth of that PCIe slot is x4. The PCIe slot connected to the PRSNT2 signal pin uses lanes 9 to 16, and the bandwidth of that PCIe slot is x8. The corresponding bandwidth is allocated to the root port accordingly.

[0089] When GPIO8, GPIO12, and GPIO16 are high, the true value of GPIO8, GPIO12, and GPIO16 is 1; when other GPIOs are low, the true value of other GPIOs is 0. This indicates that the PCIe slot connected to the PRSNT2 signal pin uses lanes 1 to 8, and the bandwidth of that PCIe slot is x8; the PCIe slot connected to the PRSNT2 signal pin uses lanes 9 to 12, and the bandwidth of that PCIe slot is x4; the PCIe slot connected to the PRSNT2 signal pin uses lanes 13 to 16, and the bandwidth of that PCIe slot is x4. Based on this, the corresponding bandwidth is allocated to the root port.

[0090] When GPIO4, GPIO8, GPIO12, and GPIO16 are high, the truth value of GPIO4, GPIO8, GPIO12, and GPIO16 is 1; when other GPIOs are low, the truth value of other GPIOs is 0. This indicates that the PCIe slot connected to the PRSNT2 signal pin uses lanes 1 to 4, and the bandwidth of that PCIe slot is x4. It also indicates that the PCIe slot connected to the PRSNT2 signal pin uses lanes 5 to 8, and the bandwidth of that PCIe slot is x4. The PCIe slot connected to the PRSNT2 signal pin uses lanes 9 to 12, and the bandwidth of that PCIe slot is x4. The PCIe slot connected to the PRSNT2 signal pin uses lanes 13 to 16, and the bandwidth of that PCIe slot is x4. Based on this, the corresponding bandwidth is allocated to the root port.

[0091] When GPIO8, GPIO12, GPIO14, and GPIO16 are high, the truth value of GPIO8, GPIO12, GPIO14, and GPIO16 is 1; when other GPIOs are low, the truth value of other GPIOs is 0. This indicates that the PCIe slot connected to the PRSNT2 signal pin uses lanes 1 to 8, and the bandwidth of that PCIe slot is x8; the PCIe slot connected to the PRSNT2 signal pin uses lanes 9 to 12, and the bandwidth of that PCIe slot is x4; the PCIe slot connected to the PRSNT2 signal pin uses lanes 13 to 14, and the bandwidth of that PCIe slot is x2; the PCIe slot connected to the PRSNT2 signal pin uses lanes 15 to 16, and the bandwidth of that PCIe slot is x2. The corresponding bandwidth is then allocated to the root port accordingly.

[0092] When GPIO8, GPIO10, GPIO12, and GPIO16 are high, the truth value of GPIO8, GPIO10, GPIO12, and GPIO16 is 1; when other GPIOs are low, the truth value of other GPIOs is 0. This indicates that the PCIe slot connected to the PRSNT2 signal pin uses lanes 1 to 8, and the bandwidth of that PCIe slot is x8; the PCIe slot connected to the PRSNT2 signal pin uses lanes 9 to 10, and the bandwidth of that PCIe slot is x2; the PCIe slot connected to the PRSNT2 signal pin uses lanes 11 to 12, and the bandwidth of that PCIe slot is x2; the PCIe slot connected to the PRSNT2 signal pin uses lanes 13 to 16, and the bandwidth of that PCIe slot is x4; and the corresponding bandwidth is allocated to the root port accordingly.

[0093] When GPIO4, GPIO6, GPIO8, and GPIO16 are high, the truth value of GPIO4, GPIO6, GPIO8, and GPIO16 is 1; when other GPIOs are low, the truth value of other GPIOs is 0. This indicates that the PCIe slot using the PRSNT2 signal pin connected to GPIO4 uses lanes 1 to 4, and the bandwidth of that PCIe slot is x4; the PCIe slot using the PRSNT2 signal pin connected to GPIO6 uses lanes 5 to 6, and the bandwidth of that PCIe slot is x2; the PCIe slot using the PRSNT2 signal pin connected to GPIO8 uses lanes 7 to 8, and the bandwidth of that PCIe slot is x2; the PCIe slot using the PRSNT2 signal pin connected to GPIO16 uses lanes 9 to 16, and the bandwidth of that PCIe slot is x8. The corresponding bandwidth is then allocated to the root port accordingly.

[0094] When GPIO2, GPIO4, GPIO8, and GPIO16 are high, the truth value of GPIO2, GPIO4, GPIO8, and GPIO16 is 1; when other GPIOs are low, the truth value of other GPIOs is 0. This indicates that the PCIe slot connected to the PRSNT2 signal pin uses lanes 1 to 2, and the bandwidth of that PCIe slot is x2. It also indicates that the PCIe slot connected to the PRSNT2 signal pin uses lanes 3 to 4, and the bandwidth of that PCIe slot is x2. The PCIe slot connected to the PRSNT2 signal pin uses lanes 5 to 8, and the bandwidth of that PCIe slot is x4. The PCIe slot connected to the PRSNT2 signal pin uses lanes 9 to 16, and the bandwidth of that PCIe slot is x8. The corresponding bandwidth is allocated to the root port accordingly.

[0095] Table 1

[0096] In some embodiments, the level truth table also includes the correspondence between channels and general-purpose input / output interfaces.

[0097] Referring to Table 1 above, the level truth table includes not only the correspondence between level and bandwidth, but also the correspondence between channels and general-purpose input / output interfaces. Lane 1 corresponds to GPIO 1, and lane 16 corresponds to GPIO 16. By consulting the level truth table, not only can the bandwidth of the slot be identified, but also the channel used by the slot can be determined. For example, if the level truth value of GPIO 8 is 1, the level truth value of GPIO 16 is 1, and the level truth values ​​of other GPIOs are 0, it indicates that the bandwidth of one slot connected to the root port is x8, the bandwidth of another slot is also x8, and one slot uses lanes 1 to 8, while the other slot uses lanes 9 to 16.

[0098] In some embodiments, controlling the general-purpose input / output interface of the first interface expansion device to output a high level for a preset duration includes:

[0099] The control panel of the first interface expansion device outputs high-level signals of a preset duration sequentially through each of its general-purpose input / output interfaces.

[0100] In this embodiment, each general-purpose input / output interface of the first interface expansion device outputs a high level for a preset duration in sequence, and no two general-purpose input / output interfaces output a high level at the same time.

[0101] In some embodiments, before the general-purpose input / output interface of the first interface expansion device outputs a high level for a preset duration, the method further includes:

[0102] Set the first interface expansion device to output mode, and set each general-purpose input / output interface of the first interface expansion device to output a low level.

[0103] In some embodiments, it also includes:

[0104] Set the second interface expansion device to input mode.

[0105] After the server powers on, before PCIe device enumeration, the BIOS sets the first interface expansion device to output mode and configures each general-purpose input / output (GPIO) port of the first interface expansion device to output a low level. The BIOS sets the second interface expansion device to input mode and configures pull-down resistors. The BIOS controls each GPIO port of the first interface expansion device to output a high level for a preset duration. During the preset duration of the high-level output of the GPIO ports of the first interface expansion device, the BIOS reads the level of the GPIO ports of the second interface expansion device.

[0106] In some embodiments, it also includes:

[0107] If, during the period when the general input / output interface of the first interface expansion device outputs a high level, the second in-situ signal pin of the slot to which the corresponding first in-situ signal pin belongs remains at a low level, an error is reported.

[0108] When a certain general-purpose input / output (GPIO) interface of the first interface expansion device outputs a high level, the level of the second presence signal pin of the slot to which the first presence signal pin belongs should be high. If, during the period when a certain GPIO interface of the first interface expansion device outputs a high level, the level of the second presence signal pin of the slot to which the first presence signal pin belongs remains low, it indicates an abnormality, and the BIOS will report an abnormality.

[0109] In some embodiments, it also includes:

[0110] If, during the period when the general-purpose input / output interface of the first interface expansion device outputs a high level, the second in-situ signal pin of the slot to which the corresponding first in-situ signal pin belongs remains at a low level, the general-purpose input / output interface of the first interface expansion device will no longer output a high level.

[0111] When a certain general-purpose input / output (GPIO) interface of the first interface expansion device outputs a high level, the level of the second presence signal pin of the slot to which the first presence signal pin belongs should be high. If, during the period when a certain GPIO interface of the first interface expansion device outputs a high level, the level of the second presence signal pin of the slot to which the first presence signal pin belongs remains low, it indicates an abnormality. In addition to reporting the abnormality, the BIOS can also control the GPIO interface of the first interface expansion device to stop outputting a high level, and the BIOS will no longer read the level of the GPIO interface of the second interface expansion device.

[0112] In some embodiments, controlling the general-purpose input / output interface of the first interface expansion device to output a high level for a preset duration includes:

[0113] The system management bus controls the general input / output interface of the first interface expansion device to output a high level for a preset duration.

[0114] In some embodiments, reading the level of the general-purpose input / output interface of the second interface extension device corresponding to the root port includes:

[0115] The system management bus reads the level of the general input / output interface of the second interface expansion device corresponding to the root port.

[0116] In this embodiment, the first interface expansion device and the second interface expansion device are connected to the SMBUS (System Management Bus). The BIOS controls the general-purpose input / output interface of the first interface expansion device to output a high level for a preset duration through the system management bus, and reads the level of the general-purpose input / output interface of the second interface expansion device corresponding to the root port through the system management bus.

[0117] To save on the use of interface expansion devices, if the root port is allocated x16 bandwidth, a second interface expansion device can be omitted. For root ports without a corresponding second interface expansion device, the BIOS will allocate x16 bandwidth by default.

[0118] In summary, the bandwidth allocation method provided in this application involves connecting the first presence signal pin of the slot to the general-purpose input / output (GPIO) interface of the first interface expansion device, rather than directly grounding it. The second presence signal pin of the slot is connected to the GPIO interface of the second interface expansion device. By controlling the GPIO interface of the first interface expansion device to output a high level, the level of the first presence signal pin connected to the GPIO interface of the first interface expansion device can be pulled high. By reading the level of the GPIO interface of the second interface expansion device, the level of the second presence signal pin of the slot can be obtained. Based on the level of the second presence signal pin of the slot, the bandwidth of the slot connected to the root port can be identified, and bandwidth allocation can be performed accordingly for the root port. With a single firmware development, a standard PCIe bandwidth resource adaptive allocation function module can be formed. During server motherboard design, the first presence signal pin of the PCIe slot is connected to the GPIO interface of the first interface expansion device, and the second presence signal pin of the PCIe slot is connected to the GPIO interface of the second interface expansion device. By running the firmware, efficient and accurate allocation of PCIe bandwidth resources for various platforms, models, and configurations can be achieved. This method does not require the use of the southbridge's general-purpose input / output interface resources, nor does it require the involvement of the board management controller, and can achieve the allocation of arbitrary bandwidth combinations. Furthermore, this method can be used not only for PCIe root port bandwidth allocation on the CPU side, but also for PCIe root port bandwidth allocation on the PCIe switch side.

[0119] This application also provides a bandwidth allocation device, which can be referred to in conjunction with the method described above. Please refer to FIG6, which is a schematic diagram of a bandwidth allocation device provided in an embodiment of this application. As shown in FIG6, the device includes:

[0120] Control module 10 is used to control the general input / output interface of the first interface expansion device to output a high level for a preset duration; the first in-situ signal pin of each slot is connected to the general input / output interface of the first interface expansion device.

[0121] The reading module 20 is used to read the level of the general input / output interface of the second interface expansion device corresponding to the root port during a high-level period of a preset duration output by the general input / output interface of the first interface expansion device; the second in-situ signal pin of each slot is connected to the general input / output interface of the second interface expansion device, and the general input / output interface of the second interface expansion device connected to the second in-situ signal pin of the slot is related to the bandwidth of the slot;

[0122] The allocation module 30 is used to identify the bandwidth of the slot to which the root port is connected based on the level of the general input / output interface of the second interface extension device, and to allocate bandwidth to the root port based on the bandwidth of the slot to which the root port is connected.

[0123] Based on the above embodiments, as a specific implementation method, the second presence signal pins of different slots connected to the root port are all connected to the general input / output interface of the same second interface expansion device corresponding to the root port, and the general input / output interfaces connected to the second presence signal pins of each slot connected to the same root port are different.

[0124] Based on the above embodiments, as a specific implementation method, the root port includes sixteen channels, and the second in-situ signal pins of the sixteen channels connected to different slots are all connected to the general input / output interface of the same second interface expansion device corresponding to the root port.

[0125] Based on the above embodiments, as a specific implementation method, the second interface expansion device includes sixteen general-purpose input / output interfaces, and the general-purpose input / output interfaces of the second interface expansion device correspond one-to-one with the channels of the root port.

[0126] Based on the above embodiments, as a specific implementation method, the second in-situ signal pin of the slot is connected to the general-purpose input / output interface corresponding to the channel with the largest sequence number among the channels used by the slot.

[0127] Based on the above embodiments, as a specific implementation method, the bandwidth of the slot accessed by the root port is identified according to the level of the general input / output interface of the second interface expansion device, including:

[0128] Based on the level of the general input / output interface of the second interface expansion device corresponding to the root port, the bandwidth of the slot connected to the root port is identified by querying the level truth table; the level truth table includes the correspondence between the level of the general input / output interface of the second interface expansion device and the bandwidth of the slot.

[0129] Based on the above embodiments, as a specific implementation method, the first interface expansion device includes sixteen general-purpose input / output interfaces.

[0130] Based on the above embodiments, as a specific implementation method, the level truth table also includes the correspondence between the root port channel and the general input / output interface of the second interface expansion device.

[0131] Based on the above embodiments, as a specific implementation method, the control module 10 is specifically used for:

[0132] The control panel of the first interface expansion device outputs high-level signals of a preset duration sequentially through each of its general-purpose input / output interfaces.

[0133] Based on the above embodiments, as a specific implementation method, it further includes:

[0134] The first setting module is used to set the first interface expansion device to output mode before the control module 10 controls the general input / output interface of the first interface expansion device to output a high level for a preset duration, and to set each general input / output interface of the first interface expansion device to output a low level.

[0135] Based on the above embodiments, as a specific implementation method, it further includes:

[0136] The second setting module is used to set the second interface extension device to input mode.

[0137] In some embodiments, the second in-situ signal pin of each slot is also connected to hot-plug monitoring logic circuitry.

[0138] Based on the above embodiments, as a specific implementation method, it further includes:

[0139] The error reporting module is used to report an error if, during the period when the general input / output interface of the first interface expansion device outputs a high level, the second in-situ signal pin of the slot to which the corresponding first in-situ signal pin belongs remains at a low level.

[0140] Based on the above embodiments, as a specific implementation method, it further includes:

[0141] The second control module is configured to control the general input / output interface of the first interface expansion device to stop outputting a high level if the second in-situ signal pin of the slot to which the corresponding first in-situ signal pin belongs remains at a low level during the period when the general input / output interface of the first interface expansion device outputs a high level.

[0142] Based on the above embodiments, as a specific implementation method, the control module 10 is specifically used for:

[0143] The system management bus controls the general input / output interface of the first interface expansion device to output a high level for a preset duration.

[0144] Based on the above embodiments, as a specific implementation method, the reading module 20 is specifically used for:

[0145] The system management bus reads the level of the general input / output interface of the second interface expansion device.

[0146] The bandwidth allocation device provided in this application has a slot whose first presence signal pin is not directly grounded, but connected to the general-purpose input / output interface of a first interface expansion device. The slot's second presence signal pin is connected to the general-purpose input / output interface of a second interface expansion device. By controlling the output of a high level from the general-purpose input / output interface of the first interface expansion device, the level of the first presence signal pin connected to the general-purpose input / output interface of the first interface expansion device can be pulled high. By reading the level of the general-purpose input / output interface of the second interface expansion device, the level of the slot's second presence signal pin can be obtained. Based on the level of the slot's second presence signal pin, the bandwidth of the slot connected to the root port can be identified, and bandwidth allocation can be performed accordingly. With a single firmware development, a standard PCIe bandwidth resource adaptive allocation function module can be formed. In the server motherboard design, the first presence signal pin of the PCIe slot is connected to the general-purpose input / output interface of the first interface expansion device, and the second presence signal pin of the PCIe slot is connected to the general-purpose input / output interface of the second interface expansion device. By running the firmware, efficient and accurate allocation of PCIe bandwidth resources for various platforms, models, and configurations can be achieved. This method does not require the use of the southbridge's general-purpose input / output interface resources, nor does it require the involvement of the board management controller, and can achieve the allocation of arbitrary bandwidth combinations. Furthermore, this method can be used not only for PCIe root port bandwidth allocation on the CPU side, but also for PCIe root port bandwidth allocation on the PCIe switch side.

[0147] This application also provides a bandwidth allocation device, as shown in FIG7, which includes a memory 1 and a processor 2.

[0148] Memory 1 is used to store computer programs;

[0149] Processor 2 is used to execute computer programs to perform the following steps:

[0150] The system controls the general-purpose input / output interface of the first interface expansion device to output a high level for a preset duration; the first presence signal pin of each slot is connected to the general-purpose input / output interface of the first interface expansion device; during the preset duration of the high level output by the general-purpose input / output interface of the first interface expansion device, the level of the general-purpose input / output interface of the second interface expansion device corresponding to the root port is read; the second presence signal pin of each slot is connected to the general-purpose input / output interface of the second interface expansion device, and the general-purpose input / output interface of the second interface expansion device connected to the second presence signal pin of the slot is related to the bandwidth of the slot; the bandwidth of the slot connected to the root port is identified according to the level of the general-purpose input / output interface of the second interface expansion device, and bandwidth allocation is performed on the root port according to the bandwidth of the slot connected to the root port.

[0151] For a description of the equipment provided in this application, please refer to the above method embodiments; further details will not be provided here.

[0152] In some embodiments, the memory 1 may include a program storage area and a data storage area, wherein the program storage area may store the operating system and applications required for at least one function; and the data storage area may store data created during use.

[0153] Furthermore, memory 1 may include read-only memory and random access memory, and provide instructions and data to processor 2. A portion of memory 1 may also include NVRAM. Memory 1 stores operating system and operation instructions, executable modules or data structures, or subsets thereof, or extended sets thereof, wherein the operation instructions may include various operation instructions for implementing various operations. The operating system may include various system programs for implementing various basic tasks and handling hardware-based tasks.

[0154] Processor 2 can be a central processing unit (CPU), an application-specific integrated circuit, a digital signal processor, a field-programmable gate array, or other programmable logic device. Processor 2 can be a microprocessor or any conventional processor. Processor 2 can call programs stored in memory 1.

[0155] The communication interface is used to connect with other devices or systems. It is understood that the structure shown in Figure 7 does not constitute a limitation on the bandwidth allocation device in the embodiments of this application. In practical applications, the bandwidth allocation device may include more or fewer components than those shown in Figure 7, or a combination of certain components.

[0156] The bandwidth allocation device provided in this application has a slot whose first presence signal pin is not directly grounded, but connected to the general-purpose input / output (GPIO) interface of a first interface expansion device. The slot's second presence signal pin is connected to the GPIO interface of a second interface expansion device. By controlling the GPIO interface of the first interface expansion device to output a high level, the level of the first presence signal pin connected to the GPIO interface of the first interface expansion device can be pulled high. By reading the level of the GPIO interface of the second interface expansion device, the level of the slot's second presence signal pin can be obtained. Based on the level of the slot's second presence signal pin, the bandwidth of the slot connected to the root port can be identified, and bandwidth allocation can be performed accordingly. With a single firmware development, a standard PCIe bandwidth resource adaptive allocation function module can be formed. In the server motherboard design, the first presence signal pin of the PCIe slot is connected to the GPIO interface of the first interface expansion device, and the second presence signal pin of the PCIe slot is connected to the GPIO interface of the second interface expansion device. By running the firmware, efficient and accurate allocation of PCIe bandwidth resources for various platforms, models, and configurations can be achieved. This method does not require the use of the southbridge's general-purpose input / output interface resources, nor does it require the involvement of the board management controller, and can achieve the allocation of arbitrary bandwidth combinations. Furthermore, this method can be used not only for PCIe root port bandwidth allocation on the CPU side, but also for PCIe root port bandwidth allocation on the PCIe switch side.

[0157] This application also provides a computer program product, including a computer program / instructions, which, when executed by a processor, performs the following steps:

[0158] The system controls the general-purpose input / output interface of the first interface expansion device to output a high level for a preset duration; the first presence signal pin of each slot is connected to the general-purpose input / output interface of the first interface expansion device; during the preset duration of the high level output by the general-purpose input / output interface of the first interface expansion device, the level of the general-purpose input / output interface of the second interface expansion device corresponding to the root port is read; the second presence signal pin of each slot is connected to the general-purpose input / output interface of the second interface expansion device, and the general-purpose input / output interface of the second interface expansion device connected to the second presence signal pin of the slot is related to the bandwidth of the slot; the bandwidth of the slot connected to the root port is identified according to the level of the general-purpose input / output interface of the second interface expansion device, and bandwidth allocation is performed on the root port according to the bandwidth of the slot connected to the root port.

[0159] The computer program product provided in this application has a slot whose first presence signal pin is not directly grounded, but connected to the general-purpose input / output (GPIO) interface of a first interface expansion device. The slot's second presence signal pin is connected to the GPIO interface of a second interface expansion device. By controlling the GPIO interface of the first interface expansion device to output a high level, the level of the first presence signal pin connected to the GPIO interface of the first interface expansion device can be pulled high. By reading the level of the GPIO interface of the second interface expansion device, the level of the slot's second presence signal pin can be obtained. Based on the level of the slot's second presence signal pin, the bandwidth of the slot connected to the root port can be identified, and bandwidth allocation can be performed accordingly. With a single firmware development, a standard PCIe bandwidth resource adaptive allocation function module can be formed. In the server motherboard design, the first presence signal pin of the PCIe slot is connected to the GPIO interface of the first interface expansion device, and the second presence signal pin of the PCIe slot is connected to the GPIO interface of the second interface expansion device. By running the firmware, efficient and accurate allocation of PCIe bandwidth resources for various platforms, models, and configurations can be achieved. This method does not require the use of the southbridge's general-purpose input / output interface resources, nor does it require the involvement of the board management controller, and can achieve the allocation of arbitrary bandwidth combinations. Furthermore, this method can be used not only for PCIe root port bandwidth allocation on the CPU side, but also for PCIe root port bandwidth allocation on the PCIe switch side.

[0160] This application also provides a computer non-volatile readable storage medium storing a computer program, which, when executed by a processor, can perform the following steps:

[0161] The system controls the general-purpose input / output interface of the first interface expansion device to output a high level for a preset duration; the first presence signal pin of each slot is connected to the general-purpose input / output interface of the first interface expansion device; during the preset duration of the high level output by the general-purpose input / output interface of the first interface expansion device, the level of the general-purpose input / output interface of the second interface expansion device corresponding to the root port is read; the second presence signal pin of each slot is connected to the general-purpose input / output interface of the second interface expansion device, and the general-purpose input / output interface of the second interface expansion device connected to the second presence signal pin of the slot is related to the bandwidth of the slot; the bandwidth of the slot connected to the root port is identified according to the level of the general-purpose input / output interface of the second interface expansion device, and bandwidth allocation is performed on the root port according to the bandwidth of the slot connected to the root port.

[0162] The non-volatile readable storage medium for this computer may include: USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks or optical disks, and other media capable of storing program code.

[0163] For a description of the non-volatile readable storage medium provided in this application, please refer to the above method embodiments; further details will not be repeated here.

[0164] This application also provides a bandwidth allocation system, including:

[0165] Processor, first interface expansion device, second interface expansion device;

[0166] The processor controls the general-purpose input / output interface of the first interface expansion device to output a high level for a preset duration; the first presence signal pin of each slot is connected to the general-purpose input / output interface of the first interface expansion device; during the preset duration of the high level output by the general-purpose input / output interface of the first interface expansion device, the processor reads the level of the general-purpose input / output interface of the second interface expansion device corresponding to the root port; the second presence signal pin of each slot is connected to the general-purpose input / output interface of the second interface expansion device, and the general-purpose input / output interface of the second interface expansion device connected to the second presence signal pin of the slot is related to the bandwidth of the slot; the processor identifies the bandwidth of the slot connected to the root port based on the level of the general-purpose input / output interface of the second interface expansion device, and allocates bandwidth to the root port based on the bandwidth of the slot connected to the root port.

[0167] For a description of the bandwidth allocation system provided in this application, please refer to the above method embodiments; further details will not be provided here.

[0168] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatuses, devices, and computer non-volatile readable storage media disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple, and relevant parts can be referred to the method section.

[0169] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0170] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented directly by hardware, a software module executed by a processor, or a combination of both. The software module can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.

[0171] The bandwidth allocation method, apparatus, device, system, medium, and program products provided in this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only for the purpose of helping to understand the method and core ideas of this application. It should be noted that those skilled in the art can make several improvements and modifications to this application without departing from the principles of this application, and these improvements and modifications also fall within the protection scope of this application.

Claims

1. A bandwidth allocation method, characterized in that, include: The general-purpose input / output interface of the first interface expansion device outputs a high level for a preset duration; the first in-situ signal pin of each slot is connected to the general-purpose input / output interface of the first interface expansion device. During the period when the general-purpose input / output interface of the first interface expansion device outputs a high level for a preset duration, the level of the general-purpose input / output interface of the second interface expansion device corresponding to the root port is read; the second in-situ signal pin of each slot is connected to the general-purpose input / output interface of the second interface expansion device, and the general-purpose input / output interface of the second interface expansion device connected to the second in-situ signal pin of the slot is related to the bandwidth of the slot; The bandwidth of the slot to which the root port is connected is identified based on the level of the general input / output interface of the second interface expansion device, and the bandwidth of the root port is allocated according to the bandwidth of the slot to which the root port is connected.

2. The bandwidth allocation method according to claim 1, characterized in that, The second presence signal pins of the different slots connected to the root port are all connected to the general-purpose input / output interface of the same second interface expansion device corresponding to the root port, and the general-purpose input / output interfaces connected to the second presence signal pins of the slots connected to the same root port are different.

3. The bandwidth allocation method according to claim 2, characterized in that, The root port includes sixteen channels, and the second in-situ signal pins of the different slots to which the sixteen channels are connected are all connected to the general input / output interface of the same second interface expansion device corresponding to the root port.

4. The bandwidth allocation method according to claim 3, characterized in that, The second interface expansion device includes sixteen general-purpose input / output interfaces, and each of the general-purpose input / output interfaces of the second interface expansion device corresponds one-to-one with the channel of the root port.

5. The bandwidth allocation method according to claim 4, characterized in that, The second in-situ signal pin of the slot is connected to the general-purpose input / output interface corresponding to the channel with the largest sequence number among the channels used by the slot.

6. The bandwidth allocation method according to claim 5, characterized in that, The bandwidth of the slot connected to the root port is identified based on the level of the general-purpose input / output interface of the second interface expansion device, including: Based on the level of the general input / output interface of the second interface expansion device corresponding to the root port, the bandwidth of the slot to which the root port is connected is identified by querying the level truth table; the level truth table includes the correspondence between the level of the general input / output interface of the second interface expansion device and the bandwidth of the slot.

7. The bandwidth allocation method according to claim 6, characterized in that, The level truth table also includes the correspondence between the root port channel and the general input / output interface of the second interface expansion device.

8. The bandwidth allocation method according to claim 1, characterized in that, The first interface expansion device includes sixteen general purpose input / output interfaces.

9. The bandwidth allocation method according to claim 1, characterized in that, The control of the general-purpose input / output interface of the first interface expansion device to output a high level for a preset duration includes: The control panel of the first interface expansion device outputs high-level signals of a preset duration sequentially through each of its general-purpose input / output interfaces.

10. The bandwidth allocation method according to claim 1, characterized in that, Before the general-purpose input / output interface of the first interface expansion device outputs a high level for a preset duration, it also includes: Set the first interface expansion device to output mode, and set each general-purpose input / output interface of the first interface expansion device to output a low level.

11. The bandwidth allocation method according to claim 1, characterized in that, Also includes: Set the second interface extension device to input mode.

12. The bandwidth allocation method according to claim 1, characterized in that, The second in-situ signal pin of each slot is also connected to the hot-plug monitoring logic circuit.

13. The bandwidth allocation method according to claim 1, characterized in that, Also includes: If the second in-slot of the corresponding slot to which the first in-slot signal pin belongs remains at a low level during the period when the general input / output interface of the first interface expansion device outputs a high level, an error is reported.

14. The bandwidth allocation method according to claim 1, characterized in that, Also includes: If the second in-slot signal pin of the slot to which the corresponding first in-slot signal pin belongs remains at a low level during the period when the general input / output interface of the first interface expansion device outputs a high level, the general input / output interface of the first interface expansion device will no longer output a high level.

15. The bandwidth allocation method according to claim 1, characterized in that, The control of the general-purpose input / output interface of the first interface expansion device to output a high level for a preset duration includes: The system management bus controls the general input / output interface of the first interface expansion device to output a high level for a preset duration.

16. The bandwidth allocation method according to claim 1, characterized in that, The levels of the general-purpose input / output interfaces of the second interface extension device corresponding to the root port include: The system management bus reads the level of the general input / output interface of the second interface expansion device.

17. A bandwidth allocation device, characterized in that, include: The control module is configured to control the general-purpose input / output interface of the first interface expansion device to output a high level for a preset duration; the first in-situ signal pin of each slot is connected to the general-purpose input / output interface of the first interface expansion device. The reading module is configured to read the level of the general input / output interface of the second interface expansion device corresponding to the root port during a high-level period of a preset duration output by the general input / output interface of the first interface expansion device; the second in-situ signal pin of each slot is connected to the general input / output interface of the second interface expansion device, and the general input / output interface of the second interface expansion device to which the second in-situ signal pin of the slot is connected is related to the bandwidth of the slot; The allocation module is configured to identify the bandwidth of the slot to which the root port is connected based on the level of the general input / output interface of the second interface extension device, and to allocate bandwidth to the root port based on the bandwidth of the slot to which the root port is connected.

18. A bandwidth allocation device, characterized in that, include: Memory, configured to store computer programs; The processor is configured to implement the steps of the bandwidth allocation method as described in any one of claims 1 to 16 when executing the computer program.

19. A computer program product comprising a computer program / instructions, characterized in that, When the computer program / instructions are executed by the processor, they implement the steps of the bandwidth allocation method as described in any one of claims 1 to 16.

20. A computer-defined non-volatile readable storage medium, characterized in that, The computer non-volatile readable storage medium stores a computer program that, when executed by a processor, implements the steps of the bandwidth allocation method as described in any one of claims 1 to 17.

21. A bandwidth allocation system, characterized in that, include: Processor, first interface expansion device, second interface expansion device; The processor is configured to control the general-purpose input / output interface of the first interface expansion device to output a high level for a preset duration; the first in-situ signal pin of each slot is connected to the general-purpose input / output interface of the first interface expansion device; During the period when the general-purpose input / output interface of the first interface expansion device outputs a high level for a preset duration, the level of the general-purpose input / output interface of the second interface expansion device corresponding to the root port is read; the second presence signal pin of each slot is connected to the general-purpose input / output interface of the second interface expansion device, and the general-purpose input / output interface of the second interface expansion device connected to the second presence signal pin of the slot is related to the bandwidth of the slot; the bandwidth of the slot connected to the root port is identified according to the level of the general-purpose input / output interface of the second interface expansion device, and bandwidth allocation is performed on the root port according to the bandwidth of the slot connected to the root port.

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